Method for preparing bonded wafer

Abstract

The present invention provides a method for preparing a bonded wafer, comprising: providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer; performing an ion implantation process on the device wafer; bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer; performing a flattening process on the bonded wafer, wherein the flattening process comprises a rapid thermal annealing process, a thinning process, and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are first performed sequentially at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of executions of the rapid thermal annealing process and the thinning process. The present invention can reduce deformation and slip lines generated in the bonded wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a bonded wafer. Background Art

[0002] Silicon on insulator (SOI) technology has now become one of the mainstream products in most electronic materials fields. With the rapid development of new energy vehicles, the integration of automotive-grade SOI wafers and on-board chips has gradually increased, so the market demand for high-uniformity SOI wafers is getting higher and higher.

[0003] In the process of preparing SOI wafers, the SOI wafer is placed in a furnace tube for non-contact planarization treatment. Due to the high temperature during the non-contact planarization process, the SOI wafer often contacts the supporting points in the furnace tube, resulting in uneven deformation of the SOI wafer due to heat and producing slip lines. In back-end applications, the slip lines will extend when the SOI wafer is oxidized again, causing the SOI wafer to even have the risk of fragmentation. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a bonded wafer, which can reduce deformation and slip lines generated in the bonded wafer.

[0005] In order to achieve the above object, the present invention provides a method for preparing a bonded wafer, comprising:

[0006] Providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer;

[0007] performing an ion implantation process on the device wafer;

[0008] Bonding the ion-implanted side of the device wafer to the support wafer to form a bonded wafer;

[0009] The bonded wafer is planarized, and the planarization process includes a rapid thermal annealing process, a thinning process and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are sequentially performed at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of times the rapid thermal annealing process and the thinning process are performed.

[0010] Optionally, the rapid thermal annealing process and the thinning process are performed less than three times.

[0011] Optionally, when the rapid thermal annealing process and the thinning process are performed sequentially once, the temperature of the argon annealing process is 1200° C.~1250° C.

[0012] Optionally, when the rapid thermal annealing process and the thinning process are performed twice in sequence, the temperature of the argon annealing process is 1120° C. to 1170° C.

[0013] Optionally, the argon annealing process lasts for 5 min to 120 min.

[0014] Optionally, after performing the rapid thermal annealing process and the thinning process in sequence at least once, and before performing the argon annealing process, a pre-annealing process is further performed on the bonded wafer.

[0015] Optionally, the temperature of the pre-annealing process is 700° C. to 800° C., and the time of the pre-annealing process is 10 min to 300 min.

[0016] Optionally, the temperature of the rapid thermal annealing process is 1150° C. to 1250° C., and the time of the rapid thermal annealing process is 10s to 60s.

[0017] Optionally, the thinning process includes an oxidation process and an etching process performed sequentially, the temperature of the oxidation process is 800°C~1000°C, the oxidation thickness of the oxidation process is 50nm~200nm, and the oxidation process includes a dry oxygen oxidation process and / or a wet oxygen oxidation process.

[0018] Optionally, after performing the argon annealing process, the method further includes performing a step-by-step cooling process on the bonded wafer.

[0019] In the preparation method of the bonded wafer provided by the present invention, it includes: providing a device wafer and a support wafer, and an oxide layer is formed on the surface of the device wafer and / or the support wafer; performing an ion implantation process on the device wafer; bonding the side of the device wafer after ion implantation with the support wafer to form a bonded wafer; performing a flattening process on the bonded wafer, and the flattening process includes a rapid thermal annealing process, a thinning process, and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are first performed in sequence at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of executions of the rapid thermal annealing process and the thinning process. Before performing the argon annealing process, the present invention performs the rapid thermal annealing process and the thinning process in sequence at least once, and then adjusts the temperature of the argon annealing process according to the number of executions of the rapid thermal annealing process and the thinning process, which can prevent insufficient thermal repair, resulting in particle aggregation on the surface of the bonded wafer, or prevent excessive thermal repair, resulting in more serious deformation and slip lines in the bonded wafer, thereby reducing the deformation and slip lines generated in the bonded wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a method for preparing a bonded wafer provided in one embodiment of the present invention.

[0021] Figure 2 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 1 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0022] Figure 3 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 2 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0023] Figure 4 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 3 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0024] Figure 5 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 4 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0025] Figure 6 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 5 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0026] Figure 7 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 6 of a method for preparing a bonded wafer provided in an embodiment of the present invention.

[0027] Figure 8 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 7 of a method for preparing a bonded wafer provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0029] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0030] Figure 1 This is a flow chart of the method for preparing a bonded wafer provided in this embodiment. Please refer to Figure 1 , this embodiment provides a method for preparing a bonded wafer, comprising:

[0031] Step S1: providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer;

[0032] Step S2: performing an ion implantation process on the device wafer;

[0033] Step S3: bonding the ion-implanted side of the device wafer to the support wafer to form a bonded wafer;

[0034] Step S4: performing a planarization process on the bonded wafer, the planarization process includes a rapid thermal annealing process, a thinning process and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are performed in sequence at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of times the rapid thermal annealing process and the thinning process are performed.

[0035] The following is a detailed description of the method for preparing the bonded wafer provided in this embodiment.

[0036] Execute step S1: provide a device wafer and a support wafer, the device wafer and the support wafer are silicon wafers, the thickness of the device wafer and the support wafer can be 500µm~800µm, for example, 775µm, the thickness difference between the device wafer and the support wafer can be less than 0.5µm, and the thickness difference is the difference between the maximum thickness and the minimum thickness, but is not limited thereto. Clean and oxidize the device wafer and / or the support wafer in sequence to form an oxide layer on the surface of the device wafer and / or the support wafer, the thickness of the oxide layer can be greater than 20nm and less than 300nm, but is not limited thereto; specifically, the oxide layer can be formed on the surface of the device wafer, or on the surface of the support wafer, or on the surface of the device wafer and the support wafer.

[0037] Execute step S2: perform an ion implantation process on the device wafer to form an ion implantation layer in the device wafer. The ion implantation layer mainly plays a role in stripping and splitting. The implanted ions in the ion implantation process may include hydrogen ions (single hydrogen ion implantation may be used), but are not limited thereto, and may also be other inert ions. In this embodiment, the implantation beam current of the ion implantation process may be 10mA~20mA, the implantation energy of the ion implantation process may be 45keV~65keV, and the implantation dose of the ion implantation process may be 1×10 16 atom / cm 2 ~6×10 16 atom / cm 2 .

[0038] Execute step S3: bond the ion-implanted side of the device wafer to the support wafer to form a bonded wafer. Specifically, the side of the device wafer with the ion implantation layer is bonded to the support wafer. The bonding method includes, but is not limited to, hydrophilic bonding.

[0039] Furthermore, after bonding, the device wafer of a part of the thickness is peeled off from the ion implantation layer of the device wafer, and a part of the device wafer is retained on the support wafer; after peeling, the retained part of the device wafer is used as the top silicon layer, the support wafer is used as the substrate layer, and the oxide layer between the device wafer and the support wafer is used as the insulating buried oxide layer. In this embodiment, after peeling, the thickness of the top silicon layer can be 200nm~500nm, but is not limited thereto. After peeling, the bonded wafer is double-sided cleaned by a single-wafer cleaning machine.

[0040] Execute step S4: perform a planarization process (non-contact planarization process) on the bonded wafer, the planarization process includes a rapid thermal annealing process, a thinning process and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are first performed sequentially at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of executions of the rapid thermal annealing process and the thinning process. In this embodiment, performing the rapid thermal annealing process and the thinning process sequentially means that the rapid thermal annealing process is first performed and then the thinning process is performed, and the number of executions of the rapid thermal annealing process and the thinning process is less than 3 times, that is, the number of executions of the rapid thermal annealing process and the thinning process is one or two times. After executing the rapid thermal annealing process and the thinning process, an argon annealing process is performed. Specifically, when the rapid thermal annealing process and the thinning process are performed once, the process steps of the planarization treatment are, in sequence, the rapid thermal annealing process, the thinning process, and the argon annealing process; when the rapid thermal annealing process and the thinning process are performed twice, the process steps of the planarization treatment are, in sequence, the rapid thermal annealing process, the thinning process, the rapid thermal annealing process, the thinning process, and the argon annealing process.

[0041] In this embodiment, the bonded wafer is loaded into a single-chip annealing chamber, and the initial temperature of the annealing chamber can be 500°C~800°C; then the bonded wafer is planarized, and the initial temperature of the annealing chamber is rapidly heated to the temperature of the rapid thermal annealing process. At this time, the heating rate is 30°C / s~70°C / s, and the temperature of the rapid thermal annealing process can be 1150°C~1250°C, preferably 1200°C~1230°C, and the time of the rapid thermal annealing process can be 10s~60s, not limited to the above process conditions. After performing a rapid thermal annealing process, a thinning process is performed. The thinning process includes an oxidation process and an etching process performed in sequence. The oxidation process includes a dry oxygen oxidation process and / or a wet oxygen oxidation process. The oxidation process is performed in a vertical furnace tube. The oxidation process is to oxidize the top silicon layer in the bonded wafer, thereby forming an oxide layer on the surface of the top silicon layer. Subsequently, a wet etching process can be used to remove the formed oxide layer to achieve thinning of the top silicon layer. The temperature of the oxidation process can be 800°C~1000°C, and the oxidation thickness of the oxidation process (each oxidation thickness) can be 50nm~200nm.

[0042] In this embodiment, after the rapid thermal annealing process and the thinning process are performed at least once in sequence, and before the argon annealing process is performed, a pre-annealing process is also performed on the bonded wafer, and the pre-annealing process can improve the mechanical strength of the bonded wafer. Specifically, the pre-annealing process is performed in a vertical furnace tube, and the initial temperature of the vertical furnace tube can be 500°C~800°C. The pre-annealing process is performed after the temperature is increased from the initial temperature of the vertical furnace tube to the temperature of the pre-annealing process. At this time, the heating rate can be 5°C / min~10°C / min, and the process gas atmosphere of the pre-annealing process is a mixed gas of argon and hydrogen. The temperature of the pre-annealing process can be 700°C~800°C, and the time of the pre-annealing process can be 10min~300min. Preferably, the temperature of the pre-annealing process is 780°C, and the time of the pre-annealing process is 40min, which is not limited to the above process conditions.

[0043] In this embodiment, the temperature of the argon annealing process is adjusted according to the number of times the rapid thermal annealing process and the thinning process are executed, which can prevent insufficient thermal repair from causing particle aggregation on the surface of the bonded wafer, or prevent excessive thermal repair from causing more serious deformation and slip lines in the bonded wafer, thereby reducing the deformation and slip lines generated in the bonded wafer. Specifically, the argon annealing process is carried out in a vertical furnace tube. After the pre-annealing process is performed, the temperature can be continued to be raised to the temperature of the argon annealing process and then the argon annealing process can be performed. At this time, the heating rate can be 3°C / min~5°C / min, and the process gas atmosphere of the argon annealing process is a mixed gas of argon and hydrogen; when the rapid thermal annealing process and the thinning process are performed once in sequence, the temperature of the argon annealing process is preferably 1200°C~1250°C, and the time of the argon annealing process can be 5min~120min; when the rapid thermal annealing process and the thinning process are performed twice in sequence, the temperature of the argon annealing process is preferably 1120°C~1170°C, and the time of the argon annealing process can be 5min~120min.

[0044] Furthermore, after performing the argon annealing process, it also includes performing a step-by-step cooling process on the bonded wafer. The step-by-step cooling process can release the thermal stress caused by long-term high temperature, which is conducive to reducing the deformation and slip line generation in the bonded wafer. The step-by-step cooling process includes a first cooling process and a second cooling process performed in sequence. The first cooling process is to cool down the temperature from the argon annealing process to a set temperature value in the vertical furnace tube, and the second cooling process is to cool down the temperature from the set temperature value to the initial temperature of the vertical furnace tube in the vertical furnace tube, wherein the set temperature value can be 1050°C, and the initial temperature of the vertical furnace tube can be 500°C~800°C; and the cooling rate of the first cooling process can be 3°C / min~5°C / min, and the cooling rate of the second cooling process can be 5°C / min~10°C / min, not limited to the above process conditions.

[0045] Seven comparative examples are provided below to further illustrate the method for preparing the bonded wafer provided in this embodiment.

[0046] In Comparative Examples 1 to 7, the steps before the planarization process are the same, and the specific steps are as follows: providing a device wafer and a support wafer, an oxide layer is formed on the surface of the device wafer, the thickness of the oxide layer is 200 nm, and the thickness of the device wafer and the support wafer can be 773 μm~775 μm; performing an ion implantation process on the device wafer, the implanted ions of the ion implantation process are hydrogen ions, the implantation energy of the ion implantation process can be 55 keV, and the implantation dose of the ion implantation process can be 5.5×10 16 atom / cm 2; Bonding the ion-implanted side of the device wafer to the support wafer to form a bonded wafer; performing a stripping process on the bonded wafer to strip off part of the device wafer, and retaining part of the device wafer as the top silicon layer, the thickness of the top silicon layer is 350nm, and then double-sided cleaning of the bonded wafer.

[0047] In Comparative Examples 1 to 7, the steps of performing the planarization process on the bonded wafer are different. The planarization process in Comparative Examples 1 to 7 is described in detail below.

[0048] In Comparative Example 1, a rapid thermal annealing process and a thinning process are performed sequentially once, the temperature of the rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after thinning is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1260°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0049] In comparative example 2, a rapid thermal annealing process and a thinning process are performed sequentially once, the temperature of the rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after thinning is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1200°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0050] In comparative example three, a rapid thermal annealing process and a thinning process are performed sequentially once, the temperature of the rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after thinning is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1150°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0051] In comparative example 4, a rapid thermal annealing process and a thinning process are sequentially performed twice, the temperature of each rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after two thinnings is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1200°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0052] In comparative example five, a rapid thermal annealing process and a thinning process are sequentially performed twice, the temperature of each rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after two thinnings is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1150°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0053] In Comparative Example 6, a rapid thermal annealing process and a thinning process are performed twice in sequence, the temperature of each rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after two thinnings is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1100°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process.

[0054] In comparative example seven, a rapid thermal annealing process and a thinning process are performed three times in sequence, the temperature of each rapid thermal annealing process is 1200°C, the time of the rapid thermal annealing process is 30s, and the thickness of the top silicon layer after three thinnings is 180nm; then an argon annealing process is performed, the temperature of the argon annealing process is 1150°C, the time of the argon annealing process is 30min, and a step-by-step cooling process is performed after the argon annealing process is performed.

[0055] Table 1. Comparative Example 1 to Comparative Example 7 Results Comparative Table

[0056]

[0057] Table 1 is a comparison table of the results of Comparative Examples 1 to 7. Figure 2 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 1 of the method for preparing a bonded wafer provided in this embodiment, Figure 3 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 2 in the method for preparing a bonded wafer provided in this embodiment, Figure 4 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 3 in the method for preparing a bonded wafer provided in this embodiment, Figure 5 A schematic diagram of particles on the surface of a bonded wafer in Comparative Example 4 of the method for preparing a bonded wafer provided in this embodiment, Figure 6 This is a schematic diagram of particles on the surface of a bonded wafer in Comparative Example 5 in the method for preparing a bonded wafer provided in this embodiment. Figure 7 This is a schematic diagram of particles on the surface of a bonded wafer in Comparative Example 6 of the method for preparing a bonded wafer provided in this embodiment. Figure 8 Schematic diagram of particles on the surface of the bonded wafer in Comparative Example 7 of the preparation method of the bonded wafer provided in this embodiment. Please refer to Table 1, and the bonded wafers finally obtained from Comparative Examples 1 to 7 were tested to obtain the above results. In Comparative Example 1, the temperature of the argon annealing process is too high and does not match the process conditions of sequentially performing the rapid thermal annealing process and the thinning process once. There are a large number of slip lines, and deformation occurs in the bonded wafer. The deformation refers to the warpage of the entire wafer. When there are slip lines, the deformation is relatively large, and there are fewer particles on the surface of the bonded wafer (reference Figure 2In comparative example 2, the temperature of the argon annealing process matches the process conditions of sequentially performing the rapid thermal annealing process and the thinning process once, there is no slip line, and the deformation generated in the bonded wafer is lighter, and there are fewer particles on the surface of the bonded wafer (reference Figure 3 In comparative example 3, the temperature of the argon annealing process is too low and does not match the process conditions of sequentially performing the rapid thermal annealing process and the thinning process once. The thermal repair ability is insufficient, and there are many particles on the surface of the bonded wafer, resulting in particle aggregation (reference Figure 4 In comparative example 4, the temperature of the argon annealing process is too high and does not match the process conditions of performing the rapid thermal annealing process and the thinning process twice in sequence. The number of slip lines is large, deformation occurs in the bonded wafer, and there are few particles on the surface of the bonded wafer (reference Figure 5 In comparative example 5, the temperature of the argon annealing process matches the process conditions of performing the rapid thermal annealing process and the thinning process twice in sequence, there is no slip line, and the deformation generated in the bonded wafer is lighter, and there are fewer particles on the surface of the bonded wafer (reference Figure 6 In comparative example 6, the temperature of the argon annealing process is too low and does not match the process conditions of performing the rapid thermal annealing process and the thinning process twice in sequence. The thermal repair ability is insufficient, and there are many particles on the surface of the bonded wafer, resulting in particle aggregation (reference Figure 7 In comparative example 7, the rapid thermal annealing process and the thinning process are performed too many times in sequence, although there are fewer particles on the surface of the bonded wafer (reference Figure 8 ), but the number of slip lines is too large, and a large deformation is generated in the bonded wafer. Therefore, it can be seen that the results of Comparative Examples 2 and 5 are better, without slip lines, and there are fewer particles on the surface of the bonded wafer, and the deformation generated in the bonded wafer is lighter. This embodiment needs to reasonably set the temperature of the argon annealing process according to the number of times the rapid thermal annealing process and the thinning process are performed in sequence, so as to reduce the particles generated on the surface of the bonded wafer and reduce the deformation and slip lines generated in the bonded wafer.

[0058] In summary, the preparation method of the bonded wafer provided by the present invention includes: providing a device wafer and a support wafer, an oxide layer is formed on the surface of the device wafer and / or the support wafer; performing an ion implantation process on the device wafer; bonding the side of the device wafer after ion implantation to the support wafer to form a bonded wafer; performing a planarization process on the bonded wafer, the planarization process includes a rapid thermal annealing process, a thinning process and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are first performed in sequence at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of times the rapid thermal annealing process and the thinning process are performed. The present invention sequentially performs a rapid thermal annealing process and a thinning process at least once before performing an argon annealing process, and then adjusts the temperature of the argon annealing process according to the number of executions of the rapid thermal annealing process and the thinning process, thereby preventing insufficient thermal repair from causing particle aggregation on the surface of the bonded wafer, or preventing excessive thermal repair from causing more serious deformation and slip lines in the bonded wafer, thereby reducing the deformation and slip lines generated in the bonded wafer.

[0059] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for preparing a bonded wafer, characterized in that: include: Providing a device wafer and a support wafer, wherein an oxide layer is formed on the surface of the device wafer and / or the support wafer; performing an ion implantation process on the device wafer; Bonding the ion-implanted side of the device wafer to the support wafer to form a bonded wafer; The bonded wafer is planarized, and the planarization process includes a rapid thermal annealing process, a thinning process and an argon annealing process, wherein the rapid thermal annealing process and the thinning process are sequentially performed at least once, and then the argon annealing process is performed, and the temperature of the argon annealing process is adjusted according to the number of times the rapid thermal annealing process and the thinning process are performed.

2. The method for preparing a bonded wafer according to claim 1, wherein: The rapid thermal annealing process and the thinning process are performed less than three times.

3. The method for preparing a bonded wafer according to claim 2, wherein: When the rapid thermal annealing process and the thinning process are performed sequentially once, the temperature of the argon annealing process is 1200° C. to 1250° C.

4. The method for preparing a bonded wafer according to claim 2, wherein: When the rapid thermal annealing process and the thinning process are sequentially performed twice, the temperature of the argon annealing process is 1120° C. to 1170° C.

5. The method for preparing a bonded wafer according to claim 3 or 4, characterized in that: The argon annealing process lasts for 5 minutes to 120 minutes.

6. The method for preparing a bonded wafer according to claim 1, wherein: After the rapid thermal annealing process and the thinning process are sequentially performed at least once, and before the argon annealing process is performed, a pre-annealing process is further performed on the bonded wafer.

7. The method for preparing a bonded wafer according to claim 6, wherein: The temperature of the pre-annealing process is 700° C. to 800° C., and the time of the pre-annealing process is 10 min to 300 min.

8. The method for preparing a bonded wafer according to claim 1, wherein: The temperature of the rapid thermal annealing process is 1150° C. to 1250° C., and the time of the rapid thermal annealing process is 10s to 60s.

9. The method for preparing a bonded wafer according to claim 1, wherein: The thinning process includes an oxidation process and an etching process performed sequentially, the temperature of the oxidation process is 800° C. to 1000° C., the oxidation thickness of the oxidation process is 50 nm to 200 nm, and the oxidation process includes a dry oxygen oxidation process and / or a wet oxygen oxidation process.

10. The method for preparing a bonded wafer according to claim 1, wherein: After performing the argon annealing process, the method further includes performing a step-by-step temperature reduction process on the bonded wafer.

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