Packaging structure and preparation method thereof

Abstract

The embodiment of the invention relates to a packaging structure and a preparation method thereof. The packaging structure comprises a packaging substrate; a buffer chip located on the package substrate; the chip structure comprises a first chip and a second chip which are symmetrically arranged on the buffer chip; the packaging layer covers the chip structure, the buffer chip and the packaging substrate. According to the packaging structure and the preparation method thereof provided by the embodiment of the invention, the first chip and the second chip are symmetrically arranged on the buffer chip, and then the chip structure, the buffer chip and the packaging layer of the packaging substrate are formed, so that the packaging structure is formed. Therefore, the chip structure and the buffer chip do not need to be packaged independently, the packaging steps are saved, and the packaging efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a packaging structure and a preparation method thereof. Background Art

[0002] The chip structure often needs to be connected to a buffer chip, which can temporarily store data sent from external devices or temporarily store data sent from the chip structure to external devices.

[0003] In conventional technology, when packaging a buffer chip and a chip structure, the buffer chip and the chip structure often need to be packaged separately, which reduces the efficiency of packaging the buffer chip and the chip structure. Summary of the invention

[0004] Based on this, it is necessary to provide a packaging structure and a preparation method thereof to address the problem of low packaging efficiency in the prior art.

[0005] In order to achieve the above objectives, on the one hand, an embodiment of the present application provides a packaging structure, including:

[0006] Package substrate;

[0007] A buffer chip, located on the packaging substrate;

[0008] A chip structure, comprising a first chip and a second chip symmetrically arranged on the buffer chip;

[0009] The packaging layer covers the chip structure, the buffer chip and the packaging substrate.

[0010] In one embodiment, the packaging structure further includes:

[0011] A support structure is located on the packaging substrate, the support structure includes a first support substructure and a second support substructure, the first chip is overlapped on the first support substructure and the buffer chip, and the second chip is overlapped on the second support substructure and the buffer chip.

[0012] In one embodiment, the adhesive layer is located between the first supporting substructure and the packaging substrate, and / or between the second supporting substructure and the packaging substrate.

[0013] In one embodiment, the packaging substrate is provided with a first solder ball area and a second solder ball area having the same packaging solder ball distribution on a side away from the buffer chip, the first solder ball area and the second solder ball area are symmetrically arranged on both sides of the buffer chip, the first chip is electrically connected to the packaging solder balls in the first solder ball area through the buffer chip, and the second chip is electrically connected to the packaging solder balls in the second solder ball area through the buffer chip.

[0014] In one embodiment, the packaging substrate includes a packaging pad, and buffer solder balls and buffer pads are respectively provided on opposite sides of the buffer chip. The first chip and the second chip include chip solder balls, and the buffer solder balls are welded to the packaging pads, and the chip solder balls are welded to the buffer pads.

[0015] In one embodiment, the first chip and the second chip include DRAM chips.

[0016] In one embodiment, the first chip and the second chip are memory chips.

[0017] The present application also provides a method for preparing a packaging structure, comprising the following steps:

[0018] Providing a packaging substrate;

[0019] forming a buffer chip on the packaging substrate;

[0020] forming a chip structure on the buffer chip, wherein the chip structure includes a first chip and a second chip symmetrically arranged on the buffer chip;

[0021] A packaging layer is formed to cover the chip structure, the buffer chip and the packaging substrate.

[0022] In one embodiment,

[0023] Before forming a chip structure above the buffer chip, the method includes:

[0024] A support structure is formed on the packaging substrate, wherein the support structure includes a first support substructure and a second support substructure, and the first support substructure and the second support substructure are symmetrically arranged on both sides of the buffer chip;

[0025] The forming of a chip structure on the buffer chip comprises:

[0026] The first chip is mounted on the first supporting substructure and the buffer chip, and the second chip is mounted on the second supporting substructure and the buffer chip.

[0027] In one embodiment, the packaging substrate includes a packaging pad, two opposite sides of the buffer chip are respectively provided with a buffer solder ball and a buffer solder pad, and the first chip and the second chip include chip solder balls;

[0028] The step of forming a buffer chip on the packaging substrate comprises:

[0029] Soldering the buffer chip to the packaging substrate through the buffer solder balls and the packaging pads;

[0030] The step of forming a chip structure on the buffer chip comprises:

[0031] The first chip and the second chip are soldered to the buffer chip through the chip solder balls and the buffer pads.

[0032] In the packaging structure and preparation method of the embodiment of the present application, the packaging structure is formed by symmetrically arranging the first chip and the second chip on the buffer chip, and then forming the chip structure, the buffer chip and the packaging layer of the packaging substrate. Therefore, there is no need to separately package the chip structure and the buffer chip, which saves packaging steps and improves packaging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 is a flow chart of a method for preparing a packaging structure provided in an embodiment;

[0035] Figure 2 is a schematic diagram of a packaging substrate provided in an embodiment;

[0036] Figure 3 A schematic diagram of a chip structure provided in an embodiment;

[0037] Figure 4 is a schematic diagram of an encapsulation layer provided in an embodiment;

[0038] Figure 5 FIG. 4 is a schematic diagram of a solder ball area provided in an embodiment.

[0039] Explanation of the accompanying drawings: packaging structure-100; packaging substrate-110; dielectric layer-111; first wiring layer-112; second wiring layer-113; interlayer dielectric layer-114; through-hole structure-115; buffer chip-120; buffer solder ball-121; buffer pad-122; chip structure-130; first chip-131; second chip-132; chip solder ball-133; packaging layer-140; supporting structure-150; first supporting substructure-151; second supporting substructure-152; first solder ball area-160; second solder ball area-161; packaging solder ball-170. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to" another element or layer, it may be directly on, adjacent to, or connected to another element or layer, or there may be an intervening element or layer. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to" another element or layer, there may be no intervening element or layer. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, and layers, these elements, components, regions, and layers should not be limited by these terms. These terms are merely used to distinguish one element, component, region, or layer from another element, component, region, or layer. Therefore, without departing from the teachings of the embodiments of the present application, the first element, component, region, or layer discussed below may be represented as a second element, component, region, or layer.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of embodiments of the present application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing techniques. The zones shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the zones of the device, and do not limit the scope of the embodiments of the present application.

[0046] As shown in the background technology, when encapsulating the buffer chip and the chip structure, it is often necessary to encapsulate the buffer chip and the chip structure separately. For example, when encapsulating the buffer chip and the chip structure, one of the buffer chip or the chip structure is usually formed on the encapsulation substrate first, and then a packaging sublayer covering the buffer chip or the chip structure is formed. Then, another buffer chip or chip structure is formed on the encapsulation substrate, and the above packaging process is repeated again. In this way, multiple layers of packaging sublayers will be formed during the multiple packaging processes. Delamination will occur between the multiple layers of packaging sublayers, affecting the overall packaging effect.

[0047] In one embodiment, see Figure 1 The present invention provides a method for preparing a packaging structure 100, comprising the following steps:

[0048] Step S100: providing a packaging substrate 110 .

[0049] Step S200 : forming a buffer chip 120 on the packaging substrate 110 .

[0050] Step S400 : forming a chip structure 130 on the buffer chip 120 . The chip structure 130 includes a first chip 131 and a second chip 132 symmetrically disposed on the buffer chip 120 .

[0051] Step S500 : forming a packaging layer 140 covering the chip structure 130 , the buffer chip 120 and the packaging substrate 110 .

[0052] In step S100, refer to Figure 2The package substrate 110 includes a dielectric layer 111, a first wiring layer 112, and a second wiring layer 113. As an example, the first wiring layer 112 is located on a side of the package substrate 110 facing the buffer chip 120 and the chip structure 130. The second wiring layer 113 is located on a side of the package substrate 110 facing away from the buffer chip 120 and the chip structure 130.

[0053] The dielectric layer 111 , the first wiring layer 112 , and the second wiring layer 113 may all include multiple layers. At this time, as an example, the multiple layers of first wiring layers 112 are connected by plugs, and a dielectric layer 111 is provided between adjacent first wiring layers 112 .

[0054] As an example, the material of the dielectric layer 111 includes silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride. The materials of the first wiring layer 112 and the second wiring layer 113 include metal materials such as cobalt, nickel, titanium, tungsten, tantalum, tantalum titanium, tungsten nitride, copper and aluminum.

[0055] The package substrate 110 may further include an interlayer dielectric layer 114. As an example, the interlayer dielectric layer 114 may be a silicon layer. In this case, the interlayer dielectric layer 114 is provided with a through-hole structure 115, and the through-hole structure 115 connects the first wiring layer 11 and the second wiring layer.

[0056] In step S200 , a buffer chip 120 is disposed on the package substrate 110 . As an example, the buffer chip 120 is located on the dielectric layer 111 and connected to the first wiring layer 112 .

[0057] The buffer chip 120 can be used to control data transmission, and is manufactured using a process different from that of the chip structure 130. The response speed of the buffer chip 120 is higher than that of the chip structure 130, so as to increase the data transmission speed.

[0058] Meanwhile, the buffer chip 120 can be used to temporarily store data sent from an external device, and can also temporarily store data sent from the chip structure 130 to an external device.

[0059] There may be a plurality of buffer chips 120 . The plurality of buffer chips 120 may be arranged at intervals on the package substrate 110 . As an example, the buffer chip 120 may be flip-chip mounted on the package substrate 110 .

[0060] In step S400, refer to Figure 3 , a chip structure 130 is disposed above the buffer chip 120 .

[0061] The chip structure 130 includes a first chip 131 and a second chip 132 symmetrically arranged on the buffer chip 120 based on the buffer chip 120. The first chip 131 and the second chip 132 are chips of the same type. As an example, the first chip 131 and the second chip 132 can be dynamic random access memory (DRAM) chips. Of course, the first chip 131 and the second chip 132 can also be other types of chips.

[0062] It can be understood that when the first chip 131 is connected to the buffer chip 120 , the second chip 132 is also connected to the buffer chip 120 .

[0063] In step S500, refer to Figure 4 , forming a packaging layer 140 covering the chip structure 130, the buffer chip 120 and the packaging substrate 110. As an example, the material of the packaging layer 140 may include epoxy molding compound (EMC) and the like.

[0064] In this embodiment, by first forming the buffer chip 120 on the packaging substrate 110, then forming the chip structure 130 above the buffer chip 120, and finally forming the packaging layer 140 covering the chip structure 130, the buffer chip 120 and the packaging substrate 110, the packaging structure 100 can be obtained through a one-time packaging process. Compared with the related art, the number of packaging times is saved and the packaging efficiency is improved.

[0065] Moreover, in this embodiment, the first chip 131 and the second chip 132 are symmetrically arranged based on the buffer chip 120, and the distance from the first chip 131 to the buffer chip 120 is the same as the distance from the second chip 132 to the buffer chip 120, thereby reducing the probability of access differences between the first chip 131 and the second chip 132 to the buffer chip 120.

[0066] Of course, in this embodiment, the chip structure 130 may also include more chips. The multiple chip structures 130 may be symmetrically arranged. As an example, the multiple chip structures 130 may surround the buffer chip 120.

[0067] In one embodiment, before step S400, the following steps are included:

[0068] Step S300 : forming a support structure 150 on the packaging substrate 110 , wherein the support structure 150 includes a first support substructure 151 and a second support substructure 152 , and the first support substructure 151 and the second support substructure 152 are symmetrically disposed on two sides of the buffer chip 120 .

[0069] At this time, step S400 includes:

[0070] Step S410 : mounting the first chip 131 on the first supporting substructure 151 and the buffer chip 120 , and mounting the second chip 132 on the second supporting substructure 152 and the buffer chip 120 .

[0071] In step S300, refer to Figure 2 The support structure 150 may be an insulating structure. At this time, a die attach film (DAF) may be formed on the side of the support structure 150 facing the package substrate 110 , and then the support structure 150 may be attached to the dielectric layer 111 of the package substrate 110 .

[0072] At this time, the adhesive layer is located between the first supporting substructure 151 and the packaging substrate 110. Alternatively, the adhesive layer is located between the second supporting substructure 152 and the packaging substrate 110. Of course, the adhesive layer can also be located between each supporting structure 150 and the packaging substrate 110 at the same time.

[0073] Of course, the support structure 150 may also be a chip. For example, the support structure 150 is a third chip. At this time, the support structure 150 may be connected to the first wiring layer 112 of the package substrate 110. As an example, the support structure 150 may also be a DRAM chip.

[0074] The supporting structure 150 includes a first supporting substructure 151 and a second supporting substructure 152 . The first supporting substructure 151 and the second supporting substructure 152 are symmetrically disposed on two sides of the buffer chip 120 .

[0075] A gap is provided between the first supporting substructure 151, the second supporting substructure 152 and the buffer chip 120. At this time, the subsequently formed encapsulation layer 140 is located in the gap.

[0076] Of course, there may be no gaps between the first supporting substructure 151, the second supporting substructure 152 and the buffer chip 120. In this case, the first supporting substructure 151, the second supporting substructure 152 and the buffer chip 120 are closely arranged.

[0077] In step S410, refer to Figure 3 The first chip 131 is located above the first supporting substructure 151 and the buffer chip 120 . The second chip 132 is located above the second supporting substructure 152 and the buffer chip 120 .

[0078] See also Figure 4 When the encapsulation layer 140 is subsequently formed, the encapsulation layer 140 covers the chip structure 130 , the buffer chip 120 and the encapsulation substrate 110 , and also covers the first supporting substructure 151 and the second supporting substructure 152 .

[0079] In this embodiment, the support structure 150 is provided, and the chip structure 130 is overlapped with the buffer chip 120 and the support structure 150 , so that the chip structure 130 can be more stable.

[0080] Similarly, in this embodiment, the support structure 150 may also include more support substructures. The multiple support substructures may be symmetrically arranged based on the buffer chip 120 .

[0081] In addition, the present embodiment does not limit the order of forming the buffer chip 120 and the support structure 150 on the packaging substrate 110. For example, the present embodiment may first form the buffer chip 120, and then form the first support substructure 151 and the second support substructure 152 on both sides of the buffer chip 120. In another example, the present embodiment may first form the first support substructure 151 and the second support substructure 152, and then form the buffer chip 120 between the first support substructure 151 and the second support substructure 152.

[0082] In one embodiment, see Figure 5 The package substrate 110 includes a package pad, which is located on the side of the package substrate 110 facing the buffer chip 120. The buffer chip 120 includes a buffer solder ball 121 and a buffer pad 122, which are respectively located on two opposite sides of the buffer chip 120. The first chip 131 and the second chip 132 both include a chip solder ball 133.

[0083] At this time, step S200 includes:

[0084] Step S210 : soldering the buffer chip 120 to the packaging substrate 110 via the buffer solder balls 121 and the packaging pads.

[0085] Step S400 includes:

[0086] Step S420 : soldering the first chip 131 and the second chip 132 to the buffer chip 120 via the chip solder balls 133 and the buffer pads 122 .

[0087] In step S210 , the buffer solder balls 121 and the package pads are aligned and soldered to connect the buffer chip 120 to the package substrate 110 .

[0088] In step S420 , the method of welding the chip solder balls 133 and the buffer pads 122 may be the same as the welding method in step S210 .

[0089] While the chip solder balls 133 of the chip structure 130 are soldered to the buffer pads 122, they can also be overlapped on the support structure 150. At this time, the chip solder balls 133 are located at positions corresponding to the chip structure 130 and the buffer chip 120. At the same time, the support structure 150 can be higher than the buffer chip 120 to obtain a more stable structure.

[0090] Of course, the chip structure 130 may also be welded to the support structure 150. For example, a support pad may also be provided on the side of the support structure 150 facing the chip structure 130. At this time, the chip solder balls 133 of the chip structure 130 may be welded to the buffer pads 122 and the support structure 150 at the same time.

[0091] In this embodiment, the chip structure 130 is welded to the buffer chip 120, and the first chip 131 and the second chip 132 are symmetrically arranged based on the buffer chip 120, so that the first chip 131 and the second chip 132 are equidistant from the buffer chip 120. When the chip structure 130 and the buffer chip 120 perform information exchange, no timing difference occurs.

[0092] In another example, the buffer chip 120 may also be bonded to the package substrate 110 via a through silicon via (TSV) technology, a bump, or other structures.

[0093] At the same time, the chip structure 130 and the buffer chip 120 may also be bonded via a through silicon via (TSV) technology, a bump or other structure.

[0094] In one embodiment, after step S500, a chemical mechanical polishing process may be used to planarize the upper surface of the encapsulation layer 140. Alternatively, processes such as marking, ball mounting, and singulation may also be performed.

[0095] For example, the coding process is to form letters or logos on the top surface of the package structure 100. The letters or logos may include information such as device codes or product specifications.

[0096] For example, the ball planting process may be to plant a copper or gold ball at a corresponding position on the side of the package substrate 110 away from the buffer chip 120 using a metal ball planting process. Alternatively, tin is applied to the side of the package substrate 110 away from the buffer chip 120. Figure 5The first solder ball area 160 and the second solder ball area 161 form a package solder ball 170. The first solder ball area 160 and the second solder ball area 161 are symmetrically arranged on both sides of the buffer chip 120. Moreover, the first solder ball area 160 and the second solder ball area 161 have the same distribution of package solder balls 170. At this time, the distance from each chip structure 130 to the corresponding pad solder ball 170 is equal, and there will be no timing difference when the chip structure 130 and the buffer chip 120 perform information exchange.

[0097] For example, the cutting process may be to use a blade to cut or a laser ablation process to separate a plurality of simultaneously packaged package structures 100 formed based on the same package substrate to form separate package structures 100 .

[0098] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0099] In one embodiment, a packaging structure 100 is provided. The packaging structure 100 includes a packaging substrate 110 , a buffer chip 120 , a chip structure 130 and a packaging layer 140 .

[0100] See also Figure 4 The package substrate 110 includes a dielectric layer 111, a first wiring layer 112, and a second wiring layer 113. As an example, the first wiring layer 112 is located on a side of the package substrate 110 facing the buffer chip 120 and the chip structure 130. The second wiring layer 113 is located on a side of the package substrate 110 facing away from the buffer chip 120 and the chip structure 130.

[0101] The dielectric layer 111 , the first wiring layer 112 , and the second wiring layer 113 may all include multiple layers. At this time, as an example, the multiple layers of first wiring layers 112 are connected by plugs, and a dielectric layer 111 is provided between adjacent first wiring layers 112 .

[0102] As an example, the material of the dielectric layer 111 includes silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride. The materials of the first wiring layer 112 and the second wiring layer 113 include metal materials such as cobalt, nickel, titanium, tungsten, tantalum, tantalum titanium, tungsten nitride, copper and aluminum.

[0103] The package substrate 110 may further include an interlayer dielectric layer 114. As an example, the interlayer dielectric layer 114 may be a silicon layer. In this case, the interlayer dielectric layer 114 is provided with a through-hole structure 115, and the through-hole structure 115 connects the first wiring layer 11 and the second wiring layer.

[0104] The buffer chip 120 is located on the package substrate 110 . As an example, the buffer chip 120 is located on the dielectric layer 111 and is connected to the first wiring layer 112 .

[0105] The buffer chip 120 can temporarily store data sent from an external device, and can also temporarily store data sent from the chip structure 130 to an external device.

[0106] There may be a plurality of buffer chips 120 . The plurality of buffer chips 120 may be arranged at intervals on the package substrate 110 . As an example, the buffer chip 120 may be flip-chip mounted on the package substrate 110 .

[0107] The chip structure 130 includes a first chip 131 and a second chip 132 symmetrically arranged on the buffer chip 120 based on the buffer chip 120. The first chip 131 and the second chip 132 are the same type of chips. As an example, the first chip 131 and the second chip 132 can be DRAM chips. Of course, the first chip 131 and the second chip 132 can also be other types of chips.

[0108] While the first chip 131 is connected to the buffer chip 120 , the second chip 132 is also connected to the buffer chip 120 .

[0109] The encapsulation layer 140 covers the chip structure 130, the buffer chip 120, and the encapsulation substrate 110. As an example, the material of the encapsulation layer 140 may include EMC and the like.

[0110] In this embodiment, the chip structure 130 is arranged above the buffer chip 120, and the first chip 131 and the second chip 132 are symmetrically arranged based on the buffer chip 120, so that the first chip 131 and the second chip 132 are at equal distances from the buffer chip 120. When the chip structure 130 and the buffer chip 120 perform information exchange, no timing difference will occur.

[0111] Of course, in this embodiment, the chip structure 130 may also include more chips. The multiple chip structures 130 may be symmetrically arranged.

[0112] In one embodiment, the package structure 100 further includes a support structure 150 .

[0113] See also Figure 4, the support structure 150 is located on the package substrate 110. The support structure 150 includes a first support substructure 151 and a second support substructure 152. At this time, the first chip 131 is overlapped on the first support substructure 151 and the buffer chip 120, and the second chip 132 is overlapped on the second support substructure 152 and the buffer chip 120. The first support substructure 151 and the second support substructure 152 are symmetrically arranged on both sides of the buffer chip 120.

[0114] The support structure 150 may be an insulating structure. In this case, the package structure 100 further includes an adhesive layer. The adhesive layer is located between the support structure 150 and the package substrate 110 .

[0115] At this time, the adhesive layer is located between the first supporting substructure 151 and the packaging substrate 110. Alternatively, the adhesive layer is located between the second supporting substructure 152 and the packaging substrate 110. Of course, the adhesive layer can also be located between each supporting structure 150 and the packaging substrate 110 at the same time.

[0116] The support structure 150 may also be a chip. For example, the support structure 150 is a third chip. At this time, the support structure 150 may be connected to the first wiring layer 112 of the package substrate 110. As an example, the support structure 150 may also be a DRAM chip.

[0117] A gap is provided between the first supporting substructure 151, the second supporting substructure 152 and the buffer chip 120. At this time, the encapsulation layer 140 is located in the gap.

[0118] Of course, the first supporting substructure 151 , the second supporting substructure 152 and the buffer chip 120 may also have no gaps.

[0119] The packaging layer 140 covers the chip structure 130 , the buffer chip 120 and the packaging substrate 110 , and also covers the first supporting substructure 151 and the second supporting substructure 152 .

[0120] In this embodiment, the support structure 150 is provided, and the chip structure 130 is overlapped with the buffer chip 120 and the support structure 150 , so that the chip structure 130 can be more stable.

[0121] Similarly, in this embodiment, the support structure 150 may also include more support substructures. The multiple support substructures may be symmetrically arranged based on the buffer chip 120 .

[0122] In one embodiment, see Figure 5 The package substrate 110 is provided with a solder ball pad on a side away from the buffer chip 120 . The solder ball pad is provided with a first solder ball area 160 and a second solder ball area 161 having the same distribution of package solder balls 170 .

[0123] The first solder ball area 160 and the second solder ball area 161 are symmetrically arranged on both sides of the buffer chip 120. A plurality of package solder balls 170 are arranged in the first solder ball area 160 and the second solder ball area 161. As an example, the plurality of package solder balls 170 can be connected to pads of other devices.

[0124] The first chip 131 is electrically connected to the package solder balls 170 of the first solder ball area 160 through the buffer chip 120 , and the second chip 132 is electrically connected to the package solder balls 170 of the second solder ball area 161 through the buffer chip 120 .

[0125] In this embodiment, by symmetrically setting the first solder ball area 160 and the second solder ball area 161, and symmetrically setting the first chip 131 and the second chip 132, the distance from each chip structure 130 to the corresponding package solder ball 170 is equal, and there will be no timing difference when the chip structure 130 and the buffer chip 120 exchange information.

[0126] Of course, in this embodiment, the package substrate 110 may also be provided with a plurality of solder ball regions, and each solder ball region and the corresponding chip structure 130 may be arranged opposite to each other.

[0127] Furthermore, in this embodiment, the packaging solder balls 170 may not be provided on the portion of the packaging substrate 110 corresponding to the buffer chip 120 on the side away from the buffer chip 120 .

[0128] Of course, solder balls 170 may also be provided on a portion of the packaging substrate 110 that is away from the buffer chip 120 and that corresponds to the buffer chip 120 .

[0129] In one embodiment, see Figure 4 The packaging substrate 110 includes a packaging pad, the buffer chip 120 includes a buffer solder ball 121 and a buffer pad 122, the chip structure 130 includes a chip solder ball 133, the buffer solder ball 121 is welded to the packaging pad, and the chip solder ball 133 is welded to the buffer pad 122.

[0130] In this embodiment, the chip structure 130 is welded to the buffer chip 120, and the first chip 131 and the second chip 132 are symmetrically arranged based on the buffer chip 120, so that the first chip 131 and the second chip 132 are equidistant from the buffer chip 120. When the chip structure 130 and the buffer chip 120 perform information exchange, no timing difference occurs.

[0131] The chip solder balls 133 of the chip structure 130 can be soldered to the buffer pads 122 and can also be overlapped on the support structure 150 . At this time, the support structure 150 can be higher than the buffer chip 120 .

[0132] Of course, a support pad may also be provided on the side of the support structure 150 facing the chip structure 130 . At this time, the chip solder balls 133 of the chip structure 130 may be welded to the buffer pads 122 and the support structure 150 at the same time.

[0133] In another embodiment, the chip structure 130 and the buffer chip 120 may be connected via a wire. In this case, since the distances from the first chip 131 and the second chip 132 to the buffer chip 120 are equal, the lengths of the wires connecting the first chip 131 and the second chip 132 to the buffer chip 120 are also the same. When the chip structure 130 and the buffer chip 120 perform information exchange, no timing difference will occur.

[0134] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A packaging structure, characterized in that: include: Package substrate; A buffer chip, located on the packaging substrate; A chip structure, comprising a first chip and a second chip symmetrically arranged on the buffer chip; The packaging layer covers the chip structure, the buffer chip and the packaging substrate.

2. The packaging structure according to claim 1, characterized in that: The packaging structure further includes: A support structure is located on the packaging substrate, the support structure includes a first support substructure and a second support substructure, the first chip is overlapped on the first support substructure and the buffer chip, and the second chip is overlapped on the second support substructure and the buffer chip.

3. The packaging structure according to claim 2, characterized in that: The first supporting substructure and / or the second supporting substructure comprises a third chip.

4. The packaging structure according to claim 2, characterized in that: The packaging structure comprises: The adhesive layer is located between the first supporting substructure and the packaging substrate, and / or between the second supporting substructure and the packaging substrate.

5. The packaging structure according to claim 1, characterized in that: The packaging substrate is provided with a first solder ball area and a second solder ball area having the same packaging solder ball distribution on a side away from the buffer chip. The first solder ball area and the second solder ball area are symmetrically arranged on both sides of the buffer chip. The first chip is electrically connected to the packaging solder balls in the first solder ball area through the buffer chip, and the second chip is electrically connected to the packaging solder balls in the second solder ball area through the buffer chip.

6. The packaging structure according to claim 1, characterized in that: The packaging substrate includes a packaging pad, and buffer solder balls and buffer pads are respectively provided on opposite sides of the buffer chip. The first chip and the second chip include chip solder balls, and the buffer solder balls are welded to the packaging pads, and the chip solder balls are welded to the buffer pads.

7. The packaging structure according to claim 1, characterized in that: The first chip and the second chip include DRAM chips.

8. A method for preparing a packaging structure, characterized in that: The steps include: Providing a packaging substrate; forming a buffer chip on the packaging substrate; forming a chip structure on the buffer chip, wherein the chip structure includes a first chip and a second chip symmetrically arranged on the buffer chip; A packaging layer is formed to cover the chip structure, the buffer chip and the packaging substrate.

9. The method for preparing a packaging structure according to claim 8, characterized in that: Before forming a chip structure above the buffer chip, the method includes: A support structure is formed on the packaging substrate, wherein the support structure includes a first support substructure and a second support substructure, and the first support substructure and the second support substructure are symmetrically arranged on both sides of the buffer chip; The forming of a chip structure on the buffer chip comprises: The first chip is mounted on the first supporting substructure and the buffer chip, and the second chip is mounted on the second supporting substructure and the buffer chip.

10. The method for preparing a packaging structure according to claim 8, characterized in that: The packaging substrate includes a packaging pad, two opposite sides of the buffer chip are respectively provided with a buffer solder ball and a buffer solder pad, and the first chip and the second chip include chip solder balls; The step of forming a buffer chip on the packaging substrate comprises: Soldering the buffer chip to the packaging substrate through the buffer solder balls and the packaging pads; The step of forming a chip structure on the buffer chip comprises: The first chip and the second chip are soldered to the buffer chip through the chip solder balls and the buffer pads.

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