Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A semiconductor device (1) is provided with a semiconductor substrate and a convex pattern structure (6) provided on a first main surface (2a) of the semiconductor substrate. The pattern structure (6) within a first predetermined distance (D1) from the first side surface (3a) along the first direction and the pattern structure (6) within the first predetermined distance (D1) from the second side surface (3b) along the first direction are symmetrical with respect to a line extending in the second direction. The pattern structure (6) within a second predetermined distance (D2) from the third side surface (3c) in the second direction and the pattern structure (6) within a second predetermined distance (D2) from the fourth side surface (3d) in the second direction are symmetrical with respect to a line extending in the first direction.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The manufacturing method of a semiconductor device includes a process of singulating a semiconductor wafer having a plurality of element regions arranged in a matrix for each element region. In such a singulation process, a scribe and break process is sometimes used. The scribe and break process is a process of dividing a semiconductor wafer by pushing a dividing component along a boundary after forming a fragile portion along the boundary of adjacent element regions. The scribe and break process is also practical for relatively hard materials because it divides the semiconductor wafer by cleavage starting from the fragile portion. In addition, the scribe and break process can increase the number of semiconductor wafers obtained, thereby reducing manufacturing costs, because the scribe line can be made narrower. In Patent Document 1, an example of a manufacturing method for a semiconductor device using a scribe and break process is disclosed.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2016-104578 Summary of the invention

[0006] In the dicing and breaking process, when the semiconductor wafer is divided by pushing the dividing member, a phenomenon called chipping may occur in which a part of the chip is missing. In this specification, a semiconductor device having a structure that is not prone to chipping and a method for manufacturing a semiconductor device that suppresses the occurrence of chipping are provided.

[0007] A semiconductor device according to a technical solution disclosed in this specification comprises: a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and side surfaces extending between the first main surface and the second main surface, the side surfaces including a first side surface and a second side surface opposite to each other in a first direction parallel to the first main surface and the second main surface, and a third side surface and a fourth side surface opposite to each other in a second direction parallel to the first main surface and the second main surface and orthogonal to the first direction, the side surfaces being cleavage surfaces; and a convex pattern structure provided on the first main surface of the semiconductor substrate. The pattern structure within a first predetermined distance from the first side surface along the first direction and the pattern structure within the first predetermined distance from the second side surface along the first direction are symmetrical with respect to a line extending in the second direction. The pattern structure within the second predetermined distance from the third side surface along the second direction and the pattern structure within the second predetermined distance from the fourth side surface along the second direction are symmetrical with respect to a line extending in the first direction. The semiconductor device has a structure that is unlikely to be damaged when the semiconductor wafer is divided into individual pieces.

[0008] Another technical solution disclosed in the present specification is a method for manufacturing a semiconductor device, comprising: a pattern structure forming step, which is a step of forming a convex pattern structure on the first main surface of a semiconductor chip having a first main surface and a second main surface, and the pattern structure is formed for each of a plurality of element regions arranged in a matrix in the semiconductor chip; and a dividing step, which is a step of dividing the semiconductor chip along a plurality of first scribing lines extending in a first direction parallel to the first main surface and the second main surface and a plurality of second scribing lines extending in a second direction parallel to the first main surface and the second main surface and orthogonal to the first direction, and a plurality of semiconductor devices are formed by pushing a dividing component against the plurality of first scribing lines and the plurality of second scribing lines and dividing the semiconductor chip. The plurality of semiconductor devices singulated above each have a semiconductor substrate having a side surface, the side surface extending between the first main surface and the second main surface, and the side surface including a first side surface and a second side surface opposing each other in the first direction, and a third side surface and a fourth side surface opposing each other in the second direction. The pattern structure within a first prescribed distance from the first side surface along the first direction and the pattern structure within a first prescribed distance from the second side surface along the first direction are symmetrical with respect to a line extending in the second direction. The pattern structure within a second prescribed distance from the third side surface along the second direction and the pattern structure within a second prescribed distance from the fourth side surface along the second direction are symmetrical with respect to a line extending in the first direction. According to the method for manufacturing a semiconductor device, in the above-mentioned segmentation step, since equal loads are applied to each of adjacent element regions, the occurrence of collapse is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a top view schematically showing the layout of a semiconductor wafer.

[0010] Fig. 2(A) is a cross-sectional view schematically showing element regions adjacent to each other in the x-axis direction and a cross-sectional view schematically showing a pattern structure. Fig. 2(B) is a cross-sectional view schematically showing element regions adjacent to each other in the y-axis direction and a cross-sectional view schematically showing a pattern structure.

[0011] Figure 3 It is an enlarged plan view schematically showing the layout of four device regions.

[0012] Figure 4 FIG. 1 is a plan view schematically showing the layout of a semiconductor device after being singulated.

[0013] Figure 5 FIG. 1 is a plan view schematically showing the layout of a semiconductor device after being singulated.

[0014] Figure 6 This is a diagram for explaining the protective tape attaching process.

[0015] Figure 7 This is a diagram for explaining the crack formation process.

[0016] Figure 8 This is a diagram for explaining the segmentation process.

[0017] Fig. 9 This is a diagram for explaining the segmentation process.

[0018] Fig.10 This is a diagram for explaining the segmentation process.

[0019] Fig.11 It is a diagram for explaining the dividing step of a comparative example. DETAILED DESCRIPTION

[0020] The technology disclosed in this specification is described below with reference to the accompanying drawings. For the purpose of clarifying the illustration, only a portion of the repeated structures in the drawings are marked. The structure of the semiconductor wafer and the semiconductor device is described below using mutually orthogonal xyz coordinates. The x-axis and the y-axis extend parallel to the main surface of the semiconductor substrate of the semiconductor wafer and the semiconductor device, and the z-axis extends parallel to the thickness direction of the semiconductor substrate of the semiconductor wafer and the semiconductor device.

[0021] exist Figure 1 A top view showing the layout of a semiconductor wafer 2 is schematically shown in FIG. The material of the semiconductor wafer 2 is not particularly limited, and may be, for example, silicon carbide, a nitride semiconductor, or silicon. In this example, the material of the semiconductor wafer 2 is silicon carbide. A plurality of element regions 3 are arranged in a matrix in the semiconductor wafer 2. The plurality of element regions 3 include a plurality of effective element regions 3A that are not shaded and a plurality of inspection element regions 3B (also referred to as "TEG (Test Element Group) regions") that are shaded.

[0022] The effective element region 3A is a region where an element structure is formed, and is a region that becomes a semiconductor device after being monolithicized. The element structure formed in the effective element region 3A is not particularly limited, and may be, for example, a MOSFET, an IGBT, or a diode. In this example, the element structure formed in the effective element region 3A is a MOSFET.

[0023] The inspection element region 3B is a region where a test pattern is formed. The test pattern of the inspection element region 3B is not particularly limited, and may be, for example, a test pattern used to evaluate the process of forming the element structure of the effective element region 3A, or a test pattern used to evaluate the electrical characteristics of the element structure of the effective element region 3A. The inspection element region 3B is appropriately formed in the semiconductor wafer 2 according to its purpose.

[0024] The plurality of element regions 3 are divided by scribe lines 12. The scribe lines 12 include a plurality of first scribe lines 12x extending in the x-axis direction and a plurality of second scribe lines 12y extending in the y-axis direction. The plurality of first scribe lines 12x extend at intervals from each other in the y-axis direction. The plurality of second scribe lines 12y extend at intervals from each other in the x-axis direction. The scribe lines 12 include predetermined division lines 4 for dividing the semiconductor wafer 2. The predetermined division lines 4 are not lines actually marked on the semiconductor wafer 2 but are imaginary lines.

[0025] In FIG. 2(A) and FIG. 2(B), a cross-sectional view including adjacent element regions 3 is schematically shown. FIG. 2(A) is a cross-sectional view including element regions 3 adjacent in the x-axis direction, and FIG. 2(B) is a cross-sectional view including element regions 3 adjacent in the y-axis direction. In addition, the element region 3 shown in the figure may be either the effective element region 3A or the inspection element region 3B. That is, the cross-sectional view of FIG. 2(A) represents a cross-sectional view of an arbitrary element region 3 adjacent in the x-axis direction in the semiconductor wafer 2, and the cross-sectional view of FIG. 2(B) represents a cross-sectional view of an arbitrary element region 3 adjacent in the y-axis direction in the semiconductor wafer 2. As shown in FIG. 2(A) and FIG. 2(B), the semiconductor wafer 2 includes a first main surface 2a and a second main surface 2b extending parallel to the xy plane and opposite to each other in the z-axis direction. On the first main surface 2a of the semiconductor wafer 2, a convex pattern structure 6 protruding from the first main surface 2a is provided in each of the plurality of element regions 3. When the element region 3 is the effective element region 3A, the pattern structure 6 provided in the effective element region 3A is a pattern of a protective film of an insulator (in this example, polyimide), a metal electrode, etc. constituting the element structure. In addition, the pattern structure 6 provided in the effective element region 3A is a common shape among a plurality of effective element regions 3A. When the element region 3 is the inspection element region 3B, the pattern structure 6 provided in the inspection element region 3B is a pattern of a protective film of an insulator (in this example, polyimide), a metal electrode, etc. formed as a test pattern.

[0026] The scribing line 12 is defined as an area between adjacent element regions 3 where the pattern structure 6 is not provided. As shown in FIG2(A), the width of the second scribing line 12y is 2×W2, and the width of the second scribing line 12 of each element region 3 is W2. As shown in FIG2(B), the width of the first scribing line 12x is 2×W1, and the width of the first scribing line 12x of each element region 3 is W1. In addition, the width W1 of the first scribing line 12x and the width W2 of the second scribing line 12y may be the same size or different sizes.

[0027] exist Figure 3 Schematically shows an enlarged top view of four element regions 3 (four effective element regions 3A in this example) in the first main surface 2a of the semiconductor wafer 2. In each of the four element regions 3, a protective film 7 of polyimide shown in grayscale and a plurality of electrode portions 8 of aluminum surrounded by the protective film 7 are provided. The plurality of electrode portions 8 include a pair of main electrodes and a plurality of signal electrodes for inputting and outputting gate signals and sensor signals. These protective films 7 and electrode portions 8 constitute a pattern structure 6.

[0028] Here, the relationship between the scribe line 12 and the pattern structure 6 will be described. Figure 4 and Figure 5 1 represents the semiconductor device 1 after being singulated. In addition, the semiconductor wafer 2 divided along the scribe line 12 is respectively referred to as a semiconductor substrate. As described in the manufacturing method described later, the semiconductor substrate of the semiconductor device 1 divided by the scribe-splitting process has four cleavage planes. The first side surface 3a and the second side surface 3b extend between the first main surface 2a and the second main surface 2b along the z-axis direction, and are opposite to each other in the x-axis direction parallel to the first main surface 2a and the second main surface 2b. The third side surface 3c and the fourth side surface 3d extend between the first main surface 2a and the second main surface 2b along the z-axis direction, and are opposite to each other in the y-axis direction parallel to the first main surface 2a and the second main surface 2b.

[0029] like Figure 4As shown, the pattern structure within the first prescribed distance D1 from the first side surface 3a along the x-axis direction and the pattern structure within the first prescribed distance D1 from the second side surface 3b along the x-axis direction are symmetrical with respect to the line extending in the y-axis direction. In this example, the pattern structure within the first prescribed distance D1 is only the protective film 7 of polyimide. Therefore, the structure of the protective film 7 within the first prescribed distance D1 from the first side surface 3a along the x-axis direction and the structure of the protective film 7 within the first prescribed distance D1 from the second side surface 3b along the x-axis direction are symmetrical with respect to the line extending in the y-axis direction. That is, the height of the protective film 7 within the first prescribed distance D1 in a symmetrical positional relationship with respect to the line extending in the y-axis direction is the same. In addition, as shown in FIG. 2(A), the first prescribed distance D1 is defined as twice the width W2 of the second scribe line 12y of the semiconductor device 1 after singulation.

[0030] like Figure 5 As shown, the pattern structure within the second prescribed distance D2 from the third side surface 3c along the y-axis direction and the pattern structure within the second prescribed distance D2 from the fourth side surface 3d along the y-axis direction are symmetrical with respect to the line extending in the x-axis direction. In this example, the pattern structure within the second prescribed distance D2 is only the protective film 7 of polyimide. Therefore, the structure of the protective film 7 within the second prescribed distance D2 from the third side surface 3c along the y-axis direction and the structure of the protective film 7 within the second prescribed distance D2 from the fourth side surface 3d along the y-axis direction are symmetrical with respect to the line extending in the x-axis direction. That is, the height of the protective film 7 within the second prescribed distance D2 in a symmetrical positional relationship with respect to the line extending in the x-axis direction is the same. In addition, as shown in FIG. 2(B), the second prescribed distance D2 is defined as twice the width W1 of the first scribing line 12x.

[0031] The pattern structures 6 of the plurality of effective element regions 3A in the semiconductor wafer 2 are of a common shape. Therefore, if the above relationship holds, the pattern structures 6 facing each other across the scribe line 12 between adjacent effective element regions 3A in the semiconductor wafer 2 are symmetrical with respect to the predetermined division line 4. In addition, the pattern structure of the inspection element region 3B may also be of a shape common to the pattern structure of the effective element region 3A within the specified distances D1 and D2. In this case, if the above relationship holds, the pattern structures 6 facing each other across the scribe line 12 between adjacent effective element regions 3A and inspection element regions 3B in the semiconductor wafer 2 are symmetrical with respect to the predetermined division line 4. As described below, if the above relationship holds, the effect of suppressing collapse can be obtained when the semiconductor wafer 2 is singulated.

[0032] (Method for manufacturing semiconductor device)

[0033] According to the method for manufacturing a semiconductor device disclosed in this specification, after forming a device structure including a pattern structure 6 in each device region 3 in a semiconductor wafer 2, the semiconductor wafer 2 is singulated by a scribing-breaking process to manufacture a semiconductor device 1. The scribing-breaking process is described below with reference to the drawings.

[0034] (Protective tape attaching step and crack forming step)

[0035] like Figure 6 As shown, in the protective tape pasting step, a protective tape 14 is pasted on the first main surface 2a side of the semiconductor wafer 2. The protective tape 14 is pasted in a manner that straddles the surface of the pattern structure 6 formed in each element region 3 in the semiconductor wafer 2. The material of the protective tape 14 is not particularly limited, and it can be, for example, a resin. Next, the semiconductor wafer 2 is placed on a workbench 16 with the surface of the semiconductor wafer 2 pasted with the protective tape 14 facing downward. The workbench 16 has a vacuum adsorption device (not shown), so that the semiconductor wafer 2 can be adsorbed and fixed to the workbench 16.

[0036] Then, if Figure 7 As shown, in the crack forming process, the scribing wheel 18 is pushed against the second main surface 2b of the semiconductor wafer 2, thereby forming a groove accompanied by a crack 5 on the semiconductor wafer 2. In addition, a metal electrode (not shown) can also be formed on the entire surface of the second main surface 2b of the semiconductor wafer 2. In this case, the scribing wheel 18 is pushed against the second main surface 2b of the semiconductor wafer 2 across the metal electrode. The scribing wheel 18 is a disc-shaped component, which is rotatably supported by a supporting device (not shown). In the crack forming process, the scribing wheel 18 is pushed against the second main surface 2b of the semiconductor wafer 2 while being moved along the predetermined dividing line 4. The scribing wheel 18 rolls on the second main surface 2b of the semiconductor wafer 2 like a tire rolling on the road. The scribing wheel 18 is an example of a "pushing component".

[0037] When the second main surface 2b of the semiconductor wafer 2 is pushed by the scribing wheel 18, compressive stress is generated in the surface area of ​​the second main surface 2b of the semiconductor wafer 2. A groove is formed at the pushed portion by the scribing wheel 18, and a tensile stress is generated inside the semiconductor wafer 2 just below the area where the compressive stress is generated. The tensile stress is generated in the direction away from the planned dividing line 4 along the second main surface 2b of the semiconductor wafer 2 just below the area where the compressive stress is generated. Due to the tensile stress, a crack 5 extending in the thickness direction of the semiconductor wafer 2 is formed inside the semiconductor wafer 2. The crack 5 is formed near the surface of the second main surface 2b of the semiconductor wafer 2.

[0038] (Separation process)

[0039] Next, implement Figure 8 to Figure 10The segmentation process shown in Figure 8 to Figure 10 In the splitting step, the semiconductor wafer 2 is again drawn with the first main surface 2a side facing upward. In the splitting step, the break bar 22 is pushed along the splitting predetermined line 4 to split the semiconductor wafer 2 along the splitting predetermined line 4. Here, first, as shown in FIG. Figure 8 As shown in FIG. 1 , the semiconductor wafer 2 is placed on two support tables 24. The two support tables 24 are arranged at a distance. When the semiconductor wafer 2 is placed on the support tables 24, the semiconductor wafer 2 is placed in such a manner that the distance is located below the position to be split (the position to be pushed against the splitting rod 22). Then, as shown in FIG. Fig. 9 As shown, the splitting bar 22 is pressed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14. The splitting bar 22 is an example of a "dividing member".

[0040] Since there is no support platform 24 below the split rod 22, when the split rod 22 is pushed against the first main surface 2a of the semiconductor wafer 2 through the protective tape 14, the semiconductor wafer 2 bends and enters the gap between the two support platforms 24. Here, the crack 5 is formed on the second main surface 2b side of the semiconductor wafer 2. Therefore, when the split rod 22 is pushed against the semiconductor wafer 2 from the first main surface 2a side, the semiconductor wafer 2 bends with the pushed portion (line) as the axis, and a force is applied to the crack 5 in the direction of pulling apart the two adjacent element regions 3 at the division position on the second main surface 2b side of the semiconductor wafer 2. In addition, as described above, tensile stress is applied around the crack 5. Therefore, when the split rod 22 is pushed against the first main surface 2a, the crack 5 extends in the thickness direction of the semiconductor wafer 2, and the semiconductor wafer 2 is cleaved along the crystal plane with the crack 5 as the starting point. As a result, the semiconductor wafer 2 is divided. In the dividing step, the above-mentioned step of pushing the splitting rod 22 against the first main surface 2a of the semiconductor wafer 2 is repeatedly performed along each planned dividing line 4. In this way, the semiconductor wafer 2 can be divided along the boundaries of each device region 3. As a result, Fig.10 As shown, a semiconductor wafer 2 is singulated into a plurality of semiconductor devices 1 .

[0041] As described above, the semiconductor device 1 is manufactured by forming the crack 5 with the dicing wheel 18 and dividing it with the splitting bar 22. Since the semiconductor wafer 2 is divided by cleavage starting from the crack 5 rather than cutting (cutting), it is also practical for relatively hard silicon carbide. In addition, the dicing-splitting process can increase the number of semiconductor wafers 2 obtained per semiconductor wafer 2, thereby reducing the manufacturing cost.

[0042] Here, refer to Fig.11The segmentation process of the comparative example is described. This comparative example is an example in which the pattern structure 6 formed on the first main surface 2a of the adjacent element regions 3 is asymmetrical. Specifically, the maximum height of the pattern structure 6 within a specified distance from the predetermined segmentation line 4 (refer to D1 and D2 in Figures 2(A) and 2(B)) is lower in the element region 3 on the right side of the figure than in the element region 3 on the left side of the figure (in this example, in the element region 3 on the right side of the figure, no pattern structure is formed within the specified distance from the predetermined segmentation line 4, and the height of the pattern structure 6 is "0"). Fig.11 As shown, in the comparative example in which the pattern structure 6 is asymmetric, when the splitting rod 22 is pushed against the first main surface 2a of the semiconductor wafer 2 via the protective tape 14, a difference occurs in the loads acting on the adjacent device regions 3. A relatively large load acts on the device region 3 with a high maximum height of the pattern structure 6 within a predetermined distance from the planned dividing line 4. Such a load difference may cause the device region 3 with a high maximum height of the pattern structure 6 to collapse.

[0043] As shown in FIG. 2(A) and FIG. 2(B), in the present embodiment, in the adjacent element regions 3, the pattern structures 6 within the predetermined distances D1 and D2 from the predetermined dividing line 4 are symmetrically formed with respect to the predetermined dividing line 4. Fig. 9 As shown, when the split rod 22 is pushed against the first main surface 2a of the semiconductor wafer 2 through the protective tape 14, an equal load is applied to each of the adjacent element regions 3. As a result, the segmentation process of the present embodiment can suppress the occurrence of breakage. In addition, in the present embodiment, the size of the prescribed distance D1 is twice the width W2 of the corresponding second scribing line 12y, and the size of the prescribed distance D2 is twice the width W1 of the corresponding first scribing line 12x. If the pattern structure 6 within the prescribed distances D1 and D2, which are twice the scribing line widths W1 and W2, is symmetrical, the load difference is sufficiently reduced, and the occurrence of breakage can be suppressed. In addition, the range of the load applied by the split rod 22 in the element region 3 depends on the radius of curvature of the front end of the split rod 22, the thickness of the protective tape 14, and the amount of the split rod 22 pressed into the protective tape 14. Therefore, the predetermined distances D1 and D2 may be set to “the radius of curvature of the tip of the split rod 22 ”+“the thickness of the protective tape 14 ”−“the amount of the split rod 22 pressed into the protective tape 14 ”.

[0044] Other features of the technology disclosed in this specification are summarized below.

[0045] In the manufacturing method disclosed in this specification, before the dividing step, a crack forming step is performed to form grooves and cracks 5 in the semiconductor wafer 2 by pushing the dicing wheel 18 against the second main surface 2b of the semiconductor wafer 2. The stress generated inside the semiconductor wafer 2 when the grooves and cracks 5 are formed in the semiconductor wafer 2 also exists as residual stress after the semiconductor wafer 2 is divided. Therefore, in the semiconductor device 1 manufactured by the manufacturing method disclosed in this specification, the residual stress of the second main surface 2b of the semiconductor substrate is higher than the residual stress of the first main surface 2a. In addition, even if such residual stress exists on the second main surface 2b of the semiconductor substrate, the influence on the electrical characteristics of the semiconductor device 1 is small. In addition, instead of forming the fragile portion including the grooves and cracks 5 using the dicing wheel 18, the fragile portion can be formed by, for example, laser irradiation.

[0046] The pattern structure 6 of the effective element region 3A is different from the pattern structure 6 of the inspection element region 3B. Therefore, in the conventional structure, the pattern structure 6 within the prescribed distance D1 and D2 in the effective element region 3A is different from the pattern structure 6 within the prescribed distance D1 and D2 in the inspection element region 3B, and the pattern structure 6 within the prescribed distance D1 and D2 between the adjacent effective element region 3A and the inspection element region 3B is asymmetric. In the technology disclosed in this specification, it is designed so that the pattern structure 6 within the prescribed distance D1 and D2 of the inspection element region 3B is the same as the pattern structure 6 within the prescribed distance D1 and D2 of the effective element region 3A. As a result, the pattern structure 6 within the prescribed distance D1 and D2 between the adjacent effective element region 3A and the inspection element region 3B is symmetrical, which suppresses the occurrence of collapse. In addition, it is also possible that the maximum height of the pattern structure 6 within the prescribed distance D1 and D2 of the inspection element region 3B is higher than the maximum height of the pattern structure 6 within the prescribed distance D1 and D2 of the effective element region 3A adjacent to the inspection element region 3B. In this case, since the chipping occurs preferentially in the inspection element region 3B, the chipping occurring in the effective element region 3A can be suppressed.

[0047] The above detailed description of the implementation methods is provided, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and alterations of the specific examples described above. The technical elements described in this specification or the drawings exert technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and side surfaces extending between the first main surface and the second main surface, the side surfaces including a first side surface and a second side surface opposite to each other in a first direction parallel to the first main surface and the second main surface, and a third side surface and a fourth side surface opposite to each other in a second direction parallel to the first main surface and the second main surface and orthogonal to the first direction, the side surfaces being cleavage planes; and A convex pattern structure is provided on the first main surface of the semiconductor substrate; The pattern structure within the first predetermined distance from the first side surface along the first direction and the pattern structure within the first predetermined distance from the second side surface along the first direction are symmetrical with respect to a line extending in the second direction; The pattern structure within the second predetermined distance from the third side surface along the second direction and the pattern structure within the second predetermined distance from the fourth side surface along the second direction are symmetrical with respect to a line extending in the first direction.

2. The semiconductor device according to claim 1, wherein The first predetermined distance is twice the width of a scribe line measured from each of the first side surface and the second side surface to the pattern structure along the first direction; The second predetermined distance is twice a scribe line width measured from each of the third side surface and the fourth side surface to the pattern structure along the second direction.

3. The semiconductor device according to claim 1, wherein The residual stress of the second main surface of the semiconductor substrate is higher than the residual stress of the first main surface.

4. The semiconductor device according to claim 1, wherein: The pattern structure within the first prescribed distance from the first side along the first direction, the pattern structure within the first prescribed distance from the second side along the first direction, the pattern structure within the second prescribed distance from the third side along the second direction, and the pattern structure within the second prescribed distance from the fourth side along the second direction are respectively protective films.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The material of the semiconductor substrate is silicon carbide.

6. A method for manufacturing a semiconductor device, characterized in that: have: a pattern structure forming step of forming a convex pattern structure on the first main surface of a semiconductor wafer having a first main surface and a second main surface, wherein the pattern structure is formed for each of a plurality of element regions arranged in a matrix in the semiconductor wafer; and a dividing step, which is a step of dividing the semiconductor wafer along a plurality of first scribing lines extending in a first direction parallel to the first main surface and the second main surface and a plurality of second scribing lines extending in a second direction parallel to the first main surface and the second main surface and orthogonal to the first direction, and forming a plurality of singulated semiconductor devices by dividing the semiconductor wafer by pushing a dividing member against the plurality of first scribing lines and the plurality of second scribing lines; The plurality of semiconductor devices singulated as a single chip each include a semiconductor substrate having side surfaces, the side surfaces extending between the first main surface and the second main surface, the side surfaces including a first side surface and a second side surface opposing each other in the first direction, and a third side surface and a fourth side surface opposing each other in the second direction; The pattern structure within the first predetermined distance from the first side surface along the first direction and the pattern structure within the first predetermined distance from the second side surface along the first direction are symmetrical with respect to a line extending in the second direction; The pattern structure within the second predetermined distance from the third side surface along the second direction and the pattern structure within the second predetermined distance from the fourth side surface along the second direction are symmetrical with respect to a line extending in the first direction.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The first predetermined distance is twice the width of a scribe line measured from each of the first side surface and the second side surface to the pattern structure along the first direction; The second predetermined distance is twice a scribe line width measured from each of the third side surface and the fourth side surface to the pattern structure along the second direction.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: A crack forming step is further provided before the dividing step. In the crack forming step, a pressing member is pressed against each of the plurality of first scribe lines and the plurality of second scribe lines on the second main surface of the semiconductor wafer to form cracks in the semiconductor wafer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: Prior to the dividing step, a step of sticking a protective tape to the first main surface side of the semiconductor wafer is further included.

10. The method for manufacturing a semiconductor device according to claim 6, wherein: The pattern structure within the first prescribed distance from the first side along the first direction, the pattern structure within the first prescribed distance from the second side along the first direction, the pattern structure within the second prescribed distance from the third side along the second direction, and the pattern structure within the second prescribed distance from the fourth side along the second direction are respectively protective films.

11. The method for manufacturing a semiconductor device according to claim 6, wherein: The material of the semiconductor wafer is silicon carbide.

12. The method for manufacturing a semiconductor device according to any one of claims 6 to 11, wherein: The plurality of device regions in the semiconductor wafer include an effective device region and an inspection device region; The height of the pattern structure of the inspection element region along the first direction within the first prescribed distance from the first side face and the second side face, and the height of the pattern structure along the second direction within the second prescribed distance from the third side face and the fourth side face, are respectively the same as or higher than the height of the pattern structure of the effective element region adjacent to the inspection element region along the first direction within the first prescribed distance from the first side face and the second side face, and the height of the pattern structure along the second direction within the second prescribed distance from the third side face and the fourth side face.

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