Semiconductor device and method of manufacturing semiconductor device

Abstract

In one example, a semiconductor device includes: a first dielectric including a first side and a second side; a first conductive horizon in the first dielectric and including a first conductive path integral with a first conductive via, where the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric comprising a first side and a second side; and a first barrier covering the first conductive horizon and covering the first dielectric, where the first barrier is between the second side of the first dielectric and the first side of the second dielectric. The first conductive horizon includes a trench barrier coupled with the first dielectric structure. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0002] Previous semiconductor packages and methods of forming semiconductor packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Additional limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the accompanying drawings. Summary of the invention

[0003] One aspect of the present disclosure is a semiconductor device, comprising a first dielectric including a first side and a second side; a first conductive layer in the first dielectric and including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; and a first barrier covering the first conductive layer and covering the first dielectric, wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric; wherein: the first conductive layer includes a trench barrier coupled to the first dielectric. In the semiconductor device, the first dielectric and the second dielectric include an organic dielectric material; and the first barrier includes an inorganic dielectric material. In the semiconductor device, the first barrier is configured to restrict ions of the first conductive layer from migrating into the second dielectric. In the semiconductor device, the trench barrier includes titanium. In the semiconductor device, the first dielectric includes a single layer of dielectric material; and the first conductive path and the first conductive via are in the single layer of dielectric material. The semiconductor device includes: a second conductive layer in the second dielectric and including a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; wherein the second conductive layer is coupled to the first conductive layer through an opening in the first barrier. In the semiconductor device, the second conductive layer includes: a first arcuate vertex between a lateral side of the second conductive path and a horizontal side of the second conductive path; and a second arcuate vertex between the horizontal side of the second conductive path and a lateral side of the second conductive via. In the semiconductor device, the first barrier completely covers the first dielectric and partially covers the first conductive layer. The semiconductor device includes: a first substrate including an inward terminal; wherein the inward terminal is coupled to the first conductive layer. The semiconductor device includes: an encapsulant coupled to a lateral side of the first substrate and to the first side of the first dielectric. In the semiconductor device, the encapsulant covers a side of the first substrate opposite to the inward terminal. The semiconductor device comprises: a first substrate comprising a semiconductor die having a component interconnection; wherein the component interconnection is coupled to the first conductive layer.

[0004] One aspect of the present disclosure is a semiconductor device, comprising: a first dielectric including a first side and a second side; a first conductive layer including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; a second conductive layer including a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; a first barrier between the second side of the first conductive layer and the first side of the second dielectric; a first electronic component coupled to the second conductive layer; and a first encapsulant coupled to the second dielectric and covering a lateral side of the first electronic component; wherein the second conductive layer is coupled to the first conductive layer through an opening in the first barrier. The semiconductor device comprises: a base substrate including a base dielectric structure and a base conductive structure; wherein the base conductive structure is coupled to the first conductive layer through a substrate-inward terminal. The semiconductor device comprises: a cover covering the first electronic component and coupled to the base substrate. The semiconductor device includes: a third dielectric, which is between the base substrate and the first dielectric; an external interconnection, which extends through the third dielectric; and a second barrier structure, which is between the first conductive layer and the third dielectric; wherein: the external interconnection is coupled to the first conductive layer through an opening in the second barrier structure; and the external interconnection is coupled to the base conductive structure through the substrate-facing internal terminal.

[0005] One aspect of the present disclosure is a method of manufacturing a semiconductor device, comprising: providing a substrate including a first side and a second side; providing a first dielectric including a first side and a second side, wherein the first side of the first dielectric is coupled to the second side of the substrate; providing a first conductive layer in the first dielectric and including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side of the first dielectric and the second side of the first dielectric; providing a first barrier covering the first conductive layer and covering the second side of the first dielectric; and providing a second dielectric including a first side and a second side, wherein the first side of the second dielectric is coupled to the second side of the first dielectric; wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric. The method includes providing the first conductive layer including: providing a trench barrier into the first dielectric; and providing the first conductive via and the first conductive path above the trench barrier; wherein the trench barrier is between the first dielectric and each of the first conductive path and the first conductive via. The method includes providing a second conductive layer in the second dielectric and including a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side of the second dielectric and the second side of the second dielectric; wherein the second conductive via is coupled to the first conductive layer through an opening in the first barrier. In the method, the first dielectric includes a single layer of dielectric material; and the first conductive path and the first conductive via are in the single layer of dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an exemplary electronic assembly is shown.

[0007] Figures 2A to 2S A cross-sectional view showing an exemplary method of manufacturing an exemplary electronic assembly.

[0008] Figure 3 A cross-sectional view of an exemplary electronic assembly is shown.

[0009] Figure 4 A cross-sectional view of an exemplary electronic device is shown.

[0010] Figure 5 A cross-sectional view of an exemplary electronic device is shown.

[0011] Figure 6 A cross-sectional view of an exemplary electronic device is shown.

[0012] Figure 7A cross-sectional view of an exemplary electronic device is shown.

[0013] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0014] The figures illustrate general construction methods, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures represent the same elements.

[0015] The term "or" means any one or more items in a list connected by "or". For example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0016] The terms "comprises," "comprising," "includes," and "including" are "open" terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features. The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure could be referred to as a second element without departing from the teachings of the present disclosure.

[0017] Unless otherwise specified, the term "coupled" may be used to describe that two elements are in direct contact with each other, or that two elements are indirectly connected through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly connected to element B through an intervening element C. Similarly, the terms "over" or "on" may be used to describe that two elements are in direct contact with each other, or that two elements are indirectly connected through one or more other elements. DETAILED DESCRIPTION

[0018] In one example, a semiconductor device includes: a first dielectric including a first side and a second side; a first conductive tier in the first dielectric and including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; and a first barrier covering the first conductive tier and covering the first dielectric, wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric. The first conductive tier includes a trench barrier coupled to the first dielectric.

[0019] In another example, a semiconductor device includes: a first dielectric including a first side and a second side; a first conductive layer including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; a second conductive layer including a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; a first barrier between the second side of the first conductive layer and the first side of the second dielectric; a first electronic component coupled to the second conductive layer; and a first encapsulant coupled to the second dielectric and covering a lateral side of the first electronic component. The second conductive layer is coupled to the first conductive layer through an opening in the first barrier.

[0020] In another example, a method of manufacturing a semiconductor device includes: providing a substrate including a first side and a second side; providing a first dielectric including a first side and a second side, wherein the first side of the first dielectric is coupled to the second side of the substrate; providing a first conductive layer in the first dielectric and including a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side of the first dielectric and the second side of the first dielectric; providing a first barrier covering the first conductive layer and covering the second side of the first dielectric; and providing a second dielectric including a first side and a second side, wherein the first side of the second dielectric is coupled to the second side of the first dielectric. The first barrier is between the second side of the first dielectric and the first side of the second dielectric.

[0021] Other examples are included in the present disclosure. These examples can be found in the figures, claims, or description of the present disclosure.

[0022] Figure 1 A cross-sectional view of an exemplary electronic assembly 100 is shown. Figure 1 In the example shown in , electronic component 100 may include substrate 110, dielectric structure 120', conductive structure 130', external interconnect 140, and barrier structure 150'. Dielectric structure 120' may include one or more dielectrics 120 that may be stacked vertically. Conductive structure 130' may include one or more conductive layers 130 that may be stacked vertically. Barrier structure 150' may include one or more barriers 150 that may extend between adjacent dielectrics 120. Barrier 150 may cover portions of conductive layers 130 and may extend between these portions and adjacent dielectrics 120.

[0023] The conductive layer 130 may be located in the dielectric 120 between the top side of the dielectric 120 and the bottom side of the dielectric 120. The conductive layer 130 may include a seed 130a including one or more seed layers, a conductive path 130b, a conductive via 130c, an inward terminal 130d, or an outward terminal 130e. In some examples, the seed 130a may include or may be referred to as a trench barrier 130a. The trench barrier 130a may be coupled to the surrounding dielectric 120. In some examples, the conductive path 130b may include or refer to a trace, pad, or other conductive pattern. The conductive path 130b may be integral with the conductive via 130c. In some examples, the conductive layer 130 may include an arcuate vertex 130x between a lateral side of the conductive path 130b and a horizontal side of the conductive path 130b, or an arcuate vertex 130y between a horizontal side of the conductive path 130b and a vertical side of the conductive via 130c. The external interconnect 140 may include a contact pad 140 a and a terminal tip 140 b .

[0024] The dielectric structure 120', the conductive structure 130', the external interconnect 140, and the barrier structure 150' may be referred to as a semiconductor package, and the package may protect the substrate 110 from external elements or environmental exposure. The semiconductor package may provide electrical coupling between an external electrical component and the external interconnect 140 or the substrate 110. In some examples, the electronic device 100 may include an electronic component 170C. In some examples, the electronic component 170C may include a component interconnect 171C.

[0025] Figures 2A to 2S A cross-sectional view of an exemplary method of manufacturing electronic assembly 100 is shown. Figure 2A A cross-sectional view of electronic assembly 100 is shown at an early stage of manufacture.

[0026] exist Figure 2A In the example shown in , dielectric 120 can be disposed on substrate 110. In some examples, substrate 110 can include or be referred to as a wafer, a reconstituted wafer, or a removable carrier.

[0027] In some examples, the wafer can be used in the manufacture of a wafer level package (WLP) or wafer level chip scale package (WLCSP) package, the reconstituted wafer can be used in the manufacture of a wafer level fan-out (WLFO) package, and the reconstituted wafer can be used in the manufacture of a high density fan-out (HDFO) or silicon wafer fan-out technology. or redistribution layer (RDL) insert or substrate A removable carrier is used for packaging.

[0028] In some examples, the wafer may include a plurality of semiconductor dies, which may include good or bad dies. In some examples, the reconstructed wafer may be a configuration in which good semiconductor dies are gathered. In some examples, the removable carrier may include or be referred to as glass, ceramic, or metal. Substrate 110 may be optional or application dependent. The thickness of substrate 110 may be in the range of about 20 microns (μm) to about 1000 μm. Substrate 110 may support dielectric 120, conductive layer 130, external interconnect 140, and barrier 150 until or after the manufacturing process is completed.

[0029] The dielectric 120 may be configured by providing a dielectric material on the substrate 110. In some examples, the dielectric 120 may include an organic material. In some examples, the dielectric material may include or be referred to as a photoimageable organic passivation material, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), phenolic resin, or ajinomoto deposited film (ABF). Such dielectric materials may be applied or spin-coated in liquid form, or attached to the substrate 110 in the form of a preformed film. The thickness of the dielectric structure 120 may be in the range of about 3 μm to about 100 μm. The dielectric 120 may support a conductive layer 130 to be provided in a later process.

[0030] Figure 2B A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2B In the example shown in FIG. 1 , the dielectric 120 may be patterned. In some examples, the path pattern 121 and the via pattern 122 may be disposed on the dielectric 120 by a patterning process. The patterning process may include coating, exposure, development, and curing processes.

[0031] In some examples, a photoresist layer may be disposed on dielectric 120, for example, by spin coating, spray coating, dip coating, or rod coating. In some examples, the photoresist layer may be provided by laminating a dry film. In some examples, a mask having a pattern may be disposed on the photoresist layer, and ultraviolet (UV) light may be exposed to the mask to transfer the pattern to the photoresist layer. The transferred portion or the non-transferred portion of the photoresist layer may be developed and cured, and the photoresist layer may include a pattern. A portion of dielectric 120 may be exposed by the pattern. The photoresist pattern may be used as a mask to etch a first portion of dielectric 120. In some examples, the etching of dielectric 120 may be processed by wet etching such as immersion or spraying or dry etching such as plasma etching, reactive ion etching (RIE), or sputter etching. In some examples, this first etching may only partially etch through dielectric 120 to define a substrate for path pattern 121. The patterning process may be repeated so that a second portion of the dielectric 120 may be etched using the second photoresist pattern as a mask to define a via pattern 122 through the dielectric 120. Due to the double patterning process, the depth of the via pattern 122 may be greater than the depth of the path pattern 121, and a portion of the substrate 110 may be exposed through the via pattern 122. In some examples, similar to Figure 1 The vertices of the arcuate vertices 130x or 130y may be produced by such corresponding sequential etching processes. In some examples, the portion of the substrate 110 corresponding to the through hole pattern 122 may include an input / output terminal. The input / output terminal may include or be referred to as a pad, a pad, an under-bump metal (UBM), or a pillar.

[0032] Figure 2C A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2CIn the example shown in , the seed 130a may be disposed on the dielectric 120. The seed 130a may be disposed on the path pattern 121 and the via pattern 122. The seed 130a may also be disposed on a portion of the substrate 110 exposed by the via pattern 122. In some examples, the dielectric 120 and the seed 130a on the substrate 110 may be electrically short-circuited. In some examples, the seed 130a may include or may be referred to as a barrier structure. In some examples, the seed 130a or the trench barrier 130a may include titanium / copper (Ti / Cu), thallium / copper (Ta / Cu), titanium tungsten / copper (TiW / Cu), or titanium / titanium nitride / copper (Ti / TiN / Cu). In some examples, the seed 130a or trench barrier 130a may include a barrier metal, such as titanium (Ti), tantalum (Ta), titanium tungsten (TiW), or titanium nitride (TiN), disposed on the dielectric 120, because copper (Cu) tends to diffuse into the dielectric 120. Next, Cu may be disposed on the barrier metal. The barrier metal comprising Ti, Ta, TiW, or TiN may be provided by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The seed 130a comprising Cu may be provided by PVD, ALD, CVD, LPCVD, or PECVD. The thickness of the seed 130a may be in the range of about 0.05 μm to about 1 μm. The seed 130a may provide a current supply path when the conductive layer 130 is later electroplated.

[0033] Figure 2D A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2D In the example shown in , the conductive structure 1300 may be disposed on the seed 130a. In some examples, the conductive structure 1300 may be disposed above the substrate 110 and the dielectric 120 including the path pattern 121 and the through-hole pattern 122. In some examples, the conductive structure 1300 may include or be referred to as an electrodeposition layer or an electrode plating layer. In some examples, the conductive structure 1300 may include copper (Cu), nickel (Ni), palladium (Pd), silver (Ag) or gold (Au). In some examples, the conductive structure 1300 may be provided by electrodeposition on the seed 130a. In some examples, electrodeposition may be a method of producing an in-situ metal coating by acting on a conductive material immersed in a solution containing a salt of the metal to be deposited by an electric current. The thickness of the conductive structure 1300 may be provided to be thicker than the thickness of the RDL pattern and the through-hole pattern to be provided later. The thickness of the conductive structure 1300 may be in the range of about 3 μm to about 200 μm. The conductive structure 1300 may provide conductive layers 130 that are separated from each other after later processing.

[0034] Figure 2EA cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2E In the example shown in , the top side of the conductive structure 1300 can be planarized. In some examples, the chemical mechanical polishing pad can grind the top side of the conductive structure 1300. The chemical mechanical polishing can be performed until the top side of the dielectric 120 is exposed. In some examples, a portion of the seed 130a on the top side of the dielectric 120 can also be grinded or removed. In some examples, after the chemical mechanical polishing process, the top side of the conductive structure 1300 and the top side of the dielectric 120 can be coplanar. In some examples, the conductive layer 130 can be electrically and mechanically isolated from each other. The conductive layer 130 having a conductive path 130b and a conductive via 130c can be disposed on the dielectric 120. In some examples, the conductive via 130c corresponding to the input / output terminal of the substrate 110 can be defined as an inward terminal 130d. In some examples, the conductive layer 130 may include or be referred to as a trace, a through hole, a pad, or a conductive path. The thickness of the conductive layer 130 may be in the range of about 3 μm to about 100 μm. The conductive layer 130 may provide a horizontal or vertical current path between the electronic component 100 and an external device. In some examples, the dielectric 120 includes a single layer of dielectric material, wherein the conductive layer 130 is in the single layer of dielectric material. In some examples, the conductive layer 130 includes a conductive path 130b coupled to the conductive via 130c, so that the conductive path 130b and the conductive via 130c are in the single layer of dielectric material. In some examples, the conductive layer 120 extends from one side of the dielectric 120 to the other side of the dielectric 120. In other examples, the conductive layer 120 only partially extends from one side of the dielectric 120 without reaching the other side of the dielectric 120.

[0035] Figure 2F A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2F, a barrier 150 or barrier layer 150 may be disposed on dielectric 120 and conductive layer 130. In some examples, barrier 150 may contact seed 130a. Thus, conductive layer 130 may be covered by barrier 150 and seed 130a. The top side of conductive layer 130 may be covered by barrier 150, and the bottom side and lateral sides of conductive layer 130 may be covered by seed 130a. In some examples, barrier 150 or barrier structure 150' may include an inorganic material. In some examples, barrier 150 or barrier structure 150' may include or be referred to as a non-conductive or dielectric inorganic material, or an inorganic passivation deposit. In some examples, barrier layer 150 may include SiO2 or Si3N4. In some examples, the barrier 150 may be deposited by supplying silicon (Si) and oxygen (O) or nitrogen (N) over the dielectric 120 and the conductive layer 130 at a high temperature, for example, about 300° C. to about 500° C. The thickness of the barrier 150 may be in a range of about 0.01 μm to about 10 μm. The barrier 150 may reduce or prevent the migration of copper ions of the conductive layer 130 to the dielectric 120.

[0036] Figure 2G A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2G In the example shown in , another dielectric 120 may be disposed on the barrier 150 . Figure 2G The process shown in can be roughly similar to Figure 2A . The dielectric 120 may be configured by providing a dielectric material on the barrier 150. In some examples, the dielectric material may include or be referred to as a photoimageable organic passivation material, PI, BCB, PBO, phenolic resin, or ABF. Such dielectric materials may be applied or spin-coated in liquid form, or attached to the barrier 150 in the form of a preformed film. The dielectric 120 may support a conductive layer 130 to be provided in a later process.

[0037] Figure 2H A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2H In the example shown in FIG. 1 , the dielectric 120 may be patterned. In some examples, the path pattern 121 and the via pattern 122 may be disposed on the dielectric 120 by a patterning process. Figure 2H The process shown in can be roughly similar to Figure 2B Through the patterning process, a portion of the barrier 150 may be exposed through the through-hole pattern 122.

[0038] Fig.2I A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Fig.2I, a portion of barrier 150 may be removed. In some examples, dielectric 120 on barrier 150 may be used as a mask, and the portion of barrier 150 may be etched. In some examples, the portion of barrier 150 may be removed using a wet etching process or a dry etching process. In some examples, nitric acid (HNO3), hydrofluoric acid (HF), or phosphoric acid (H3PO3) may be used to etch and remove the portion of barrier 150. A portion of conductive layer 130 may be exposed through barrier 150 by etching or removing the portion of barrier 150.

[0039] Figure 2J A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2J In the example shown in FIG. 1 , a seed 130a may be disposed on the dielectric 120 and the conductive layer 130. In some examples, the seed 130a may cover an exposed portion of the conductive layer 130. In some examples, the seed 130a may be coupled to the barrier 150. In some examples, a portion of the top side of the conductive layer 130 may be covered by the barrier 150, and another portion of the top side of the conductive structure 130 may be covered by the seed 130a. Figure 2J The process shown in can be roughly similar to Figure 2C The craftsmanship shown in.

[0040] Figure 2K A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2K In the example shown in FIG. 1 , the conductive structure 1300 may be disposed on the seed crystal 130a. In some examples, the conductive structure 1300 may be disposed above the dielectric 120 including the path pattern 121 and the via pattern 122. In some examples, the conductive structure 1300 may include or be referred to as an electrodeposition layer or an electrode plating layer. In some examples, the conductive structure 1300 may include copper (Cu), nickel (Ni), palladium (Pd), silver (Ag), or gold (Au). Figure 2K The process shown in can be roughly similar to Figure 2D The craftsmanship shown in.

[0041] Figure 2L A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2LIn the example shown in , the top side of the conductive structure 1300 can be planarized. In some examples, the chemical mechanical polishing pad can grind the top side of the conductive structure 1300. The chemical mechanical polishing can be performed until the top side of the dielectric 120 is exposed. In some examples, a portion of the seed 130a on the top side of the dielectric 120 can also be grinded and removed. In some examples, after the chemical mechanical polishing process, the top side of the conductive layer 130 and the top side of the dielectric 120 can be coplanar. In some examples, the conductive layer 130 can be electrically and mechanically isolated from each other. The conductive layer 130 having the conductive path 130b and the conductive via 130c can be disposed on the dielectric 120. Figure 2L The process shown in can be roughly similar to Figure 2E In some examples, one conductive layer 130 of one dielectric 120 can be coupled to another conductive layer 130 of another dielectric 120 through an opening in a barrier 150 or barrier structure 150'. In some examples, the barrier 150 or barrier structure 150' can completely cover the dielectric 120 and can partially cover the conductive layer 130 to accommodate the opening.

[0042] Figure 2M A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2M In the example shown in FIG. 1 , the barrier 150 may be disposed on the dielectric 120 and the conductive layer 130. In some examples, the barrier 150 may contact the seed 130a. Thus, the conductive layer 130 may be covered by the barrier 150 and the seed 130a. The top side of the conductive layer 130 may be covered by the barrier 150, and the bottom side and lateral sides of the conductive layer 130 may be covered by the seed 130a. The migration of copper ions of the conductive layer 130 into the dielectric 120 is reduced or prevented. Figure 2M The process shown in can be roughly similar to Figure 2F The craftsmanship shown in.

[0043] Figure 2N and Fig.2O A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2N and Fig.2O In the example shown in , something like Figures 2A-2MThe process of the manufacturing process shown in the figure can be repeated multiple times. Therefore, the dielectric 120 or the conductive layer 130 may include at least one or more layers. In some examples, the conductive layers may be interlaced between the dielectric layers. In some examples, the dielectric layers may be interlaced between the conductive layers. In some examples, the bottom side and the lateral side of the conductive layer 130 may be substantially covered by the seed 130a, and the top side of the conductive layer 130 may be substantially covered by the barrier 150. In some examples, the conductive paths 130b disposed on different layers may be electrically coupled to each other through the conductive vias 130c. In some examples, a portion of the top side of the conductive path 130b corresponding to the conductive via 130c may be covered by the seed 130a. In some examples, the seed 130a and the barrier 150 of the same layer may be coplanar.

[0044] Figure 2P A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2P In the example shown in FIG. 1 , a photoresist may be coated on the top side dielectric 120 , and then a photoresist pattern 160 may be provided by an exposure and development process. Thus, a portion of the seed 130 a may be exposed by the photoresist pattern 160 , for example, a portion corresponding to the conductive path 130 b.

[0045] Figure 2Q A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2Q In the example shown in , the external interconnect 140 may be disposed on the conductive layer 130, such as the topmost conductive path 130b. In some examples, the external interconnect 140 may include a contact pad 140a and a terminal tip 140b. The contact pad 140a may be disposed on the seed 130a. In some examples, the contact pad 140a may be disposed on a portion defined by the photoresist pattern 160. Therefore, a plurality of contact pads 140a may be provided independently when separated from each other. In addition to independently providing a plurality of contact pads 140a, Figure 2Q The manufacturing process of the contact pad 140a shown in FIG. Figure 2D and 2K In some examples, the thickness of the contact pad 140a can be in a range of about 3 μm to about 500 μm. In some examples, the terminal tip 140b can be electrolytically deposited on the contact pad 140a. The terminal tip 140b can also be disposed on a portion defined by the photoresist pattern 160. In some examples, the terminal tip 140b can include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn- 37 -Pb, Sn 95In some examples, the terminal tip 140b may have a thickness or width in the range of about 0.01 millimeters (mm) to about 10 mm. The terminal tip 140b may be used to mechanically or electrically couple the electronic component 100 to an external device.

[0046] Figure 2R A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2R In the example shown in , the photoresist pattern 160 can be removed by a liquid resist stripper. In some examples, the liquid resist stripper may include monoethanolamine and 2-butoxyethanol. In some examples, the photoresist pattern 160 can be removed by an oxygen-containing plasma. In some examples, the photoresist pattern 160 can also be removed by a 1-methyl-2-pyrrolidone (NMP) solvent. In some examples, once the photoresist pattern 160 is dissolved, the solvent can be removed by heating the solvent to about 80° C., so that no residue is left. As described above, the top side and lateral sides of the external interconnect 140 including the contact pad 140a and the terminal tip 140b can be exposed.

[0047] The external interconnect 140 may be used as a mask, and a portion of the seed 130a around the external interconnect 140 may be removed. The thickness of the seed 130a may be much smaller than the thickness of the external interconnect 140, and thus the external interconnect 140 may be used as a mask. In some examples, the portion of the seed 130a may be removed by a wet or dry etching process. In some examples, the Cu of the seed 130a may be etched first, and then the Ti or TiW of the seed 130a may be etched. In some examples, an etchant containing hydrogen peroxide (H2O2) in any of a carboxylic acid, a carboxylate, or an acetyl group (CH3CO-) may be used to etch and remove the portion of the seed 130a. Thus, the top side of the dielectric 120, which is the surrounding dielectric of the external interconnect 140, may be exposed, and the end of the seed 130a may also be exposed.

[0048] Figure 2S A cross-sectional view of electronic assembly 100 is shown at a later stage of manufacturing. Figure 2S In the example shown in FIG. 1 , the terminal tip 140 b of the external interconnect 140 can be substantially spherical by a reflow process or a laser-assisted process. In some examples, these processes can be performed at about 150° C. to about 250° C., so that the terminal tip 140 b can be reflowed.

[0049] In some examples, a redistribution layer ("RDL") substrate may be disposed on substrate 110. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, which may (a) be formed layer by layer over an electronic device to which the RDL substrate is to be coupled, or (b) may be formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer in a wafer-level process as a wafer-level substrate on a circular wafer, or layer by layer in a panel-level process as a panel-level substrate on a rectangular or square panel carrier. The RDL substrate may be formed in an additive buildup process, which may include alternating stacking of one or more dielectric layers with one or more conductive layers defining corresponding conductive redistribution patterns or traces, which are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern may be formed using a plating process such as, for example, an electroplating process or an electroless plating process. The conductive pattern may include a conductive material, such as copper or other plateable metals. The location of the conductive pattern may be made using a photopatterning process, such as a photolithography process and a photoresist material for forming a photolithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process that may include a photolithography mask, through which light is exposed to the desired features of the light pattern, such as through holes in the dielectric layer. Therefore, the dielectric layer may be made of a light-definable organic dielectric material such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), resin or ajinomoto stacked film (ABF). Such dielectric materials may be spin-coated or otherwise applied in liquid form, rather than attached in the form of a preformed film. In order to allow the desired light-definable features to be properly formed, such light-definable dielectric materials may omit structural reinforcing agents, or may be filler-free, without strands, woven fabrics or other particles that interfere with the light from the photopatterning process. In some examples, such filler-free properties of filler-free dielectric materials may reduce the thickness of the resulting dielectric layer. Although the photo-definable dielectric material described above may be an organic material, in other examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). One or more inorganic dielectric layers may be formed by growing inorganic dielectric layers using an oxidation or nitridation process rather than using a photo-definable organic dielectric material. Such inorganic dielectric layers may be filler-free, without strands, woven fabrics, or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.

[0050] In a subsequent process, the electronic component 100 may be provided by a singulation or sawing process. In some examples, the substrate 110, the dielectric structure 120', or the conductive structure 130' may be sawed by a diamond wheel or a laser beam, thereby providing the electronic component 100. Therefore, the lateral sides of the substrate 110, the dielectric structure 120', or the conductive structure 130' may be coplanar with each other.

[0051] In a subsequent process, if the substrate 110 is a removable carrier, the substrate 110 may be separated from the dielectric structure 120' or the conductive structure 130'. In some examples, the wafer support system may be attached to the redistribution structure including the dielectric structure 120' and the conductive structure 130', and then the substrate 110 may be removed. In some examples, when a temporary adhesive film is inserted between the redistribution structure and the substrate 110, heat or light such as a laser beam may be provided to the temporary adhesive film to reduce the adhesive strength of the temporary adhesive film, and thus the substrate 110 may be removed from the redistribution structure. In some examples, the substrate 110 may be forcibly peeled off from the redistribution structure by mechanical force. In some examples, the substrate 110 may be removed by mechanical grinding and chemical etching. In some examples, the wafer support system may fix the redistribution structure, and the grinder rubs against the substrate 110 and rotates, thereby removing the substrate 110. In some examples, the wafer support system and the grinder may rotate in opposite directions, and thus the substrate 110 may be removed.

[0052] The bottom side of the redistribution structure may be exposed by removing or separating the substrate 110. In some examples, the inward terminals 130d of the redistribution structure may be exposed from the dielectric structure 120'. In some examples, the bottom sides of the inward terminals 130d, such as the bottom sides of the seed 130a and the dielectric structure 120' may be coplanar.

[0053] Figure 3 A cross-sectional view of an exemplary electronic assembly 100 is shown. Figure 3 In both the illustrations (A) and (B) of FIG. 1 , the bottom and lateral sides of the conductive layer 130 made of Cu are buried in the bottom dielectric 120 while being surrounded by a seed 130 a or a trench barrier 130 a made of Ti. Figure 3 (A) shows a situation where the barrier 150 does not exist on the top side of the conductive structure 130 , such as at the boundary between the top and bottom of the dielectric 120 . Figure 3 1 shows a situation where a barrier 150 exists on the top side of the conductive layer 130, such as at the boundary between the top and bottom of the dielectric 120. The dielectric 120 on the top or upper side may be above the dielectric 120 on the bottom or lower side.

[0054] As in Figure 3As shown in the diagram (A) of FIG. 1 , copper ions may migrate from the conductive layer 130 to the top dielectric 120, or may be oxidized or generate voids in the top dielectric 120. The boundary between the top and bottom of the dielectric 120 may serve as a copper ion migration path. Figure 3 As shown in the diagram (B) of FIG. 1 , when the top side of the conductive layer 130 is covered by the barrier 150, the migration of copper ions may be limited, or the progress of oxidation or the generation of voids in the dielectric 120 may be limited. The barrier 150 or the barrier structure 150′ may mitigate the migration of copper ions, or may prevent the migration of copper ions from the conductive layer 130 to the upper dielectric 120 completely.

[0055] Figure 4 A cross-sectional view of an exemplary electronic device 100A is shown. Figure 4 In the example shown in FIG. 1 , the electronic device 100A may include a substrate 110, a dielectric 120, a conductive layer 130, an external interconnect 140, and a barrier 150. In some examples, the electronic device 100A may include a substrate 110, a dielectric 120, a conductive layer 130, an external interconnect 140, and a barrier 150 similar to the one described above. Figures 2A to 2S The electronic device 100A is manufactured in a process of the process shown in . In some examples, the electronic device 100A may include or be referred to as a WLP or a WLCSP. In some examples, the conductive via 130c of the conductive layer 130 may extend toward the substrate 110 and may be coupled with the substrate 110.

[0056] In some examples, substrate 110 may include or be referred to as a semiconductor die, a semiconductor chip, or a semiconductor package. In some examples, the die or chip may include an integrated circuit die separated from a semiconductor wafer. In some examples, substrate 110 may include a digital signal processor (DSP), a network processor, a power management unit, an audio processor, a radio frequency (RF) circuit, a wireless baseband system on chip (SoC) processor, a sensor, or an application specific integrated circuit (ASIC). Substrate 110 may perform computing and control processing, store data, or remove noise from an electrical signal.

[0057] Figure 5 A cross-sectional view of an exemplary electronic device 100B is shown. Figure 5 In the example shown in FIG. 1 , the electronic device 100B may include a substrate 110, a dielectric 120, a conductive layer 130, an external interconnect 140, a barrier 150, and an encapsulant 160B. In addition to the electronic device 100B including the encapsulant 160B, Figure 5 The electronic device 100B shown in FIG. Figure 4 In some examples, after encapsulating the substrate 110 with the encapsulant 160B, the encapsulant 160B may be encapsulated by a method similar to that described above. Figures 2A to 2SThe electronic device 100B is manufactured by the process shown in FIG. In some examples, the encapsulant 16B can be coupled with the lateral side of the substrate 110 and can be coupled with the dielectric 120 .

[0058] In some examples, encapsulant 160B may include epoxy or phenolic resins, carbon black or silica fillers. In some examples, encapsulant 160B may include or be referred to as a molding compound, a resin, a sealant, a reinforcing filler polymer or an organic body. In some examples, encapsulant 160B may contact or cover the bottom side or lateral side of substrate 110. In some examples, the bottom side of encapsulant 160B may be lower than the bottom side of substrate 110. In some examples, the bottom side of encapsulant 160B and the bottom side of substrate 110 may be coplanar, and the bottom side of substrate 110 may be exposed from the bottom side of encapsulant 160B.

[0059] In some examples, the encapsulant 160B can be provided by transfer molding, compression molding, liquid encapsulant molding, vacuum lamination, solder paste printing, or film assisted molding. Transfer molding can be a process of curing by supplying a fluid resin from a gate or supply port of a mold to the periphery of a corresponding substrate 110. Compression molding can be a process of supplying a fluid resin to a mold in advance, and then placing the substrate 110 in the mold to cure the fluid resin. The thickness of the encapsulant 160B can be in the range of about 100 μm to about 2000 μm. The encapsulant 160B can protect the substrate 110 from the external environment or environmental exposure, and can quickly dissipate heat from the substrate 110.

[0060] In some examples, the RDL substrate may be disposed on the top side of the encapsulant 160B and on the top side of the substrate 110. In some examples, the RDL substrate includes a dielectric structure 120' and a conductive structure 130'. Figures 2A-2S The processes shown in the figure may be implemented on the top side of the substrate 110 and the top side of the encapsulation 160B. In some examples, the top side of the substrate 110 and the top side of the encapsulation 160B may be coplanar. In some examples, the dielectric structure 120 and the conductive structure 130 may be disposed on the top side of the substrate 110 and the top side of the encapsulation 160B. In some examples, the external interconnect 140 may be located on the top side of the substrate 110 and the top side of the encapsulation 160B. In some examples, the electronic device 100B may include or be referred to as a WLFO. In some examples, later in the manufacturing process, the RDL substrate and the encapsulation 160B may be sawed in the vertical direction so that the lateral sides of the dielectric 120 or the conductive layer 130 may be coplanar with the lateral sides of the encapsulation 160B.

[0061] Figure 6 A cross-sectional view of an exemplary electronic device 100C is shown. Figure 6In the example shown in FIG. 1 , the electronic device 100C may include an electronic component 170C, a dielectric 120, a conductive layer 130, an external interconnect 140, a barrier 150, an encapsulant 160C, and a bottom filler 180C. In addition to providing an RDL substrate first and then providing the electronic component 170C, Figure 6 The electronic device 100C shown in FIG. 1 may be similar to Figure 5 In some examples, the RDL substrate may include a dielectric structure 120' and a conductive structure 130'.

[0062] In some examples, the Figure 2S 1. After the process shown in , the substrate 110 is removed from the RDL substrate. In some examples, the RDL substrate may be flipped, and the electronic component 170C may be connected to the top side of the RLD substrate. In some examples, the electronic component 170C may include or be referred to as a die, a chip, a package, or a passive element. In some examples, the thickness of the electronic component 170C may be in the range of about 20 μm to about 1000 μm. In some examples, the component interconnect 171C of the electronic component 170C may be electrically coupled to the inward terminal 130d of the RDL substrate. In some examples, the component interconnect 171C may include or be referred to as a bump, a pad, or a guide column. In some examples, the thickness of the component interconnect 171C may be in the range of about 1 μm to about 10 μm. In some examples, the component interconnect 171C may be electrically coupled to the seed 130a overlying the inward terminal 130d. In some examples, the component interconnect 171C may be electrically coupled to the inward terminal 130d via welding. In some examples, component interconnects 171C may be electrically coupled to inward terminals 130d by a thermocompression bonding process, an ultrasonic bonding process, or a laser-assisted bonding process.

[0063] The bottom filler 180C may be disposed between the RDL substrate and the electronic component 170C. In some examples, the bottom filler 180C may contact the RDL substrate, such as the dielectric 120 or the conductive layer 130, the component interconnect 171C, or the electronic component 170C. In some examples, the bottom filler 180C may include or be referred to as a capillary bottom filler (CUF), a non-conductive solder paste (NCP), a non-conductive film (NCF), or an anisotropic conductive film (ACF). In some examples, the bottom filler 180C may be inserted into the gap between the electronic component 170C and the RDL substrate after the electronic component 170C is electrically coupled to the RDL substrate. In some examples, the bottom filler 180C may be pre-applied to the RDL substrate before the electronic component 170C is coupled to the RDL substrate. Therefore, the electronic component 170C may pressurize the bottom filler 180C, and at the same time, the component interconnect 171C may penetrate the bottom filler 180C to electrically couple with the RDL substrate. In some examples, underfill 180C may be pre-applied on electronic component 170C before electronic component 170C is coupled to the RDL substrate. Thus, electronic component 170C may pressurize underfill 180C, and at the same time, component interconnect 171C may be electrically coupled to the RDL substrate. In some examples, a curing process of underfill 180C may be performed, such as a thermal curing process or a photocuring process.

[0064] An encapsulant 160C may be provided. In some examples, the encapsulant 160C may cover the RDL substrate, the electronic component 170C, and the bottom filler 180C. In some examples, the encapsulant 160C may contact or cover the RDL substrate, the electronic component 170C, and the bottom filler 180C. In some examples, the bottom filler 180C may be omitted, and the encapsulant 160C may be filled between the electronic component 170C and the RDL substrate. In some examples, when the size of the silica filler is smaller than the gap between the electronic component 170C and the RDL substrate, the encapsulant 160C may replace the role of the bottom filler 180C. In some examples, the electronic device 100C may include or be referred to as an HDFO or In some examples, substrate 110 may include electronic component 170C, which may include a semiconductor die. Electronic component 170C may include component interconnect 171C that may be coupled to conductive structure 130. Underfill 180C may be between electronic component 170C and dielectric 120 and may be coupled to component interconnect 171C.

[0065] Figure 7 A cross-sectional view of an exemplary electronic device 100D is shown. Figure 7In the example shown in , the electronic device 100D may include an electronic component 170D, a dielectric 120, a conductive layer 130, an external interconnect 140, a barrier 150, an encapsulant 160D, an underfill 180D, a base substrate 320D, an external interconnect 330D, an underfill 190D, and a heat sink 310D. The heat sink 310D may also be referred to as a cover 310D. In some examples, the first dielectric 120 and the first conductive layer 130 may be coupled with the second dielectric 120 and the second conductive layer 130. The first conductive layer 130 may be between the top side and the bottom side of the first dielectric 120, and the second conductive layer 130 may be between the top side and the bottom side of the second dielectric 120. The barrier 150 or barrier structure 150' may be between the first dielectric 120 and the second dielectric 120. The second dielectric 120 may be above the first dielectric 120, and the electronic component 170D may be coupled to the second conductive layer 130 of the second dielectric 120. The encapsulant 160D may be coupled to the second dielectric 120 and may cover the lateral sides of the electronic component 170D. The first conductive structure 130 may be coupled to the second conductive structure 130 through the barrier layer 150 or the opening in the barrier structure 150. One or more additional dielectrics 120 and one or more additional conductive layers 130 may be provided following the same pattern or structure as the first and second dielectrics 120 and the first and second conductive layers 130.

[0066] In some examples, the base substrate 320D may include a base dielectric structure 321D and a base conductive structure 322D. In some examples, the base dielectric structure 321D may include a dielectric layer. The dielectric layer may include one or more dielectric material layers interlaced with the conductive structure layer. In some examples, the dielectric material may include PI, BCB, PBO, resin, or ABF. In some examples, the base conductive structure 322D may include one or more conductive layers defining signal distribution elements, such as traces, vias, pads, conductive paths, or UBMs. The base conductive structure 322D may include a substrate inward terminal 324D1 and a substrate outward terminal 324D2. In some examples, the substrate inward terminal 324D1 may include a pad, a pad, a UBM, or a pillar. In some examples, the substrate outward terminal 324D2 may include a pad or a pad. The external interconnect 330D may include a solder ball, a bump, a pad, or a guide pillar. In some examples, a land grid array (LGA) may also be a possible design.

[0067] In some examples, base substrate 320D may be a preformed substrate. The preformed substrate may be manufactured before being attached to an electronic device and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer and may be attached in a preformed film form rather than in a liquid form, and may include a resin with fillers such as strands, woven fabrics or other inorganic particles for rigidity or structural support. Since the dielectric layer is not photoimageable, features such as through holes or openings may be formed by using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or an Ajinomoto stacked film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before being attached to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate.Such a preformed substrate may be formed by a semi-additive process or a modified semi-additive process.

[0068] The external interconnect 140 of the RDL substrate may be electrically coupled to the substrate inward terminal 324D1 of the base substrate 320D. In some examples, the external interconnect 140 may be electrically coupled to the inward terminal 324D1 by thermocompression bonding, ultrasonic bonding, or laser-assisted bonding. In some examples, solder may be inserted between the external interconnect 140 and the inward terminal 324D1. In some examples, the bottom filler 190D may be optionally inserted between the RDL substrate and the base substrate 320D. In some examples, the base substrate 320D may include a base dielectric structure 321D and a base conductive structure 322D. The base conductive structure 322D may be coupled to the first conductive layer 130, for example, via the substrate inward terminal 324D1 and the external interconnect 140.

[0069] In some examples, the heat sink 310D or the cover 310D may be attached to the base substrate 320D or the electronic component 170D by a thermal adhesive. In some examples, the thermal adhesive may also be inserted between the encapsulation 160D and the heat sink 310D. The heat sink 310D may include or be referred to as a cover, a cover, a housing, or a shell. In some examples, the thickness of the heat sink 310D may be in the range of about 100 μm to about 100 μm. The heat sink 310D may not only dissipate heat from the electronic component 170D, but also protect the RDL substrate and the electronic component 170D from the external environment. The electronic component 170D may include one or more component terminals 171D. In some examples, the heat sink 310D or the cover 310D may cover the electronic component 170D and may be coupled to the base substrate 320D.

[0070] The present disclosure includes references to certain examples. However, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is contemplated that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a first dielectric including a first side and a second side; a first conductive layer in the first dielectric and comprising a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; as well as a first barrier covering the first conductive layer and covering the first dielectric, wherein the first barrier is between the second side of the first dielectric and the first side of the second dielectric; in: The first conductive layer includes a trench barrier coupled to the first dielectric.

2. The semiconductor device according to claim 1, wherein: The first dielectric and the second dielectric include an organic dielectric material; and The first barrier includes an inorganic dielectric material.

3. The semiconductor device according to claim 1, wherein: The first barrier is configured to restrict migration of ions in the first conductive layer into the second dielectric.

4. The semiconductor device according to claim 1, wherein: The trench barrier includes titanium.

5. The semiconductor device according to claim 1, wherein: The first dielectric comprises a single layer of dielectric material; and The first conductive path and the first conductive via are in the single layer of dielectric material.

6. The semiconductor device according to claim 1, comprising: a second conductive layer in the second dielectric and comprising a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; The second conductive layer is coupled to the first conductive layer through an opening in the first barrier.

7. The semiconductor device according to claim 6, wherein the second conductive layer comprises: a first arcuate vertex between a lateral side of the second conductive path and a horizontal side of the second conductive path; as well as A second arcuate vertex is between the horizontal side of the second conductive path and a lateral side of the second conductive via.

8. The semiconductor device according to claim 1, wherein: The first barrier completely covers the first dielectric layer and partially covers the first conductive layer.

9. The semiconductor device according to claim 1, comprising: a first substrate including inwardly facing terminals; The inward terminal is coupled to the first conductive layer.

10. The semiconductor device according to claim 9, comprising: An encapsulant is coupled to the lateral side of the first substrate and to the first side of the first dielectric.

11. The semiconductor device according to claim 10, wherein: The encapsulant covers a side of the first substrate opposite to the inwardly facing terminals.

12. The semiconductor device according to claim 1, comprising: a first substrate comprising a semiconductor die having component interconnects; The component interconnect is coupled to the first conductive layer.

13. A semiconductor device comprising: a first dielectric including a first side and a second side; a first conductive layer comprising a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side and the second side of the first dielectric; a second dielectric including a first side and a second side; a second conductive layer comprising a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side and the second side of the second dielectric; a first barrier between the second side of the first conductive layer and the first side of the second dielectric layer; a first electronic component coupled to the second conductive layer; as well as a first encapsulant coupled to the second dielectric and covering a lateral side of the first electronic component; The second conductive layer is coupled to the first conductive layer through an opening in the first barrier.

14. The semiconductor device according to claim 13, comprising: a base substrate including a base dielectric structure and a base conductive structure; The base conductive structure is coupled to the first conductive layer via a substrate-inward terminal.

15. The semiconductor device according to claim 14, comprising: A cover covers the first electronic component and is coupled to the base substrate.

16. The semiconductor device according to claim 14, comprising: a third dielectric between the base substrate and the first dielectric; an external interconnect extending through the third dielectric; as well as A second barrier structure between the first conductive layer and the third dielectric; in: The external interconnect is coupled to the first conductive layer through the opening in the second barrier structure; and The external interconnect is coupled to the base conductive structure through the substrate inwardly facing terminal.

17. A method for manufacturing a semiconductor device, comprising: providing a substrate including a first side and a second side; providing a first dielectric including a first side and a second side, wherein the first side of the first dielectric is coupled to the second side of the substrate; providing a first conductive layer in the first dielectric and comprising a first conductive path integral with a first conductive via, wherein the first conductive path and the first conductive via extend between the first side of the first dielectric and the second side of the first dielectric; providing a first barrier covering the first conductive layer and covering the second side of the first dielectric; and providing a second dielectric including a first side and a second side, wherein the first side of the second dielectric is coupled to the second side of the first dielectric; The first barrier is between the second side of the first dielectric and the first side of the second dielectric.

18. The method according to claim 17, comprising Providing the first conductive layer comprises: providing a trench barrier into the first dielectric; as well as providing the first conductive via and the first conductive path above the trench barrier; Wherein the trench barrier is between the first dielectric and each of the first conductive path and the first conductive via.

19. The method according to claim 17, comprising: providing a second conductive layer in the second dielectric and comprising a second conductive path integral with a second conductive via, wherein the second conductive path and the second conductive via extend between the first side of the second dielectric and the second side of the second dielectric; The second conductive via is coupled to the first conductive layer through an opening in the first barrier.

20. The method of claim 17, wherein: The first dielectric comprises a single layer of dielectric material; and The first conductive path and the first conductive via are in the single layer of dielectric material.

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