A multi-chip packaging structure and packaging process

Abstract

The present application relates to a multi-chip packaging structure and packaging process, including: a circuit substrate, on which a patterned circuit layer is arranged; a plurality of chips, which are respectively arranged at preset positions of the circuit substrate and are electrically connected to the patterned circuit layer; and a plastic encapsulation layer, which covers the surface of the chip; the circuit substrate is folded so that the projection areas of the plurality of chips on the circuit substrate at least partially overlap, and a heat dissipation channel is formed between the chips located on opposite sides. The heat dissipation channel can utilize the convection effect of airflow to adaptively dissipate heat, so that the stacked chips can achieve good heat dissipation without a complex structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a multi-chip packaging structure and packaging process. Background Art

[0002] With the design requirements of high integration, miniaturization and multi-function of intelligent sensor products for high-voltage transmission lines, power monitoring devices are required to realize mechatronics design to reduce volume, enrich functions and improve reliability. The package size of microelectronic chips used in power monitoring devices is constantly shrinking and the package density is constantly increasing. Due to the limitation of package size, it is impossible to achieve a sufficiently small package size by placing chips with different functional modules in the package body using the traditional two-dimensional planar packaging method. Therefore, three-dimensional stacking of chips in the height direction is a trend in package design. The three-dimensional packaging structure not only makes the packaging density higher, but also has the characteristics of more functions, faster transmission speed, lower power consumption, better performance and reliability.

[0003] At present, there are various chip three-dimensional packaging structures, such as SiP (System-in-package), PoP (package-on-package), TSV (through-silicon-vias) and other chip-level packaging, which include different sizes of bare chips stacked up layer by layer in the form of a pyramid, chips of similar sizes stacked vertically or staggered layer by layer, etc.

[0004] However, in actual system-level packaging design, stacking chips will cause the problem of heat not being able to dissipate. Moreover, when chips of similar sizes are stacked, the bottom chip needs to be connected to the outer circuits, and a conductive joint is often required to be opened in the plastic layer to reach the solder pad position on the surface of the bottom chip. In this case, the length of the conductive joint is too long, which will pose a great challenge to the accuracy of the opening. Summary of the invention

[0005] The present application provides a multi-chip packaging structure to solve the technical problem of heat concentration generated by stacked chips in the current multi-chip packaging structure.

[0006] A multi-chip packaging structure, comprising:

[0007] A circuit substrate, wherein a patterned circuit layer is provided on the circuit substrate;

[0008] A plurality of chips are respectively disposed at predetermined positions of the circuit substrate and are electrically connected to the patterned circuit layer; and

[0009] The plastic packaging layer covers the surface of the chip; the circuit substrate is folded so that the projection areas of the multiple chips on the circuit substrate at least partially overlap, and the chips located on opposite sides are spaced to form a heat dissipation channel.

[0010] In one of the embodiments, the circuit substrate is folded into an "e" shape.

[0011] In one of the embodiments, the multi-chip packaging structure includes a side wall perpendicular to the chip arrangement plane, the side wall is provided with air flow holes, and the air flow holes are communicated with the heat dissipation channel to form convection.

[0012] In one of the embodiments, a support structure is formed on the plastic packaging layer, and the support structure is used to support two adjacent layers of folded circuit substrates.

[0013] In one of the embodiments, a heat-conducting structure is fixed to the side wall, and the heat-conducting structure is located in the heat dissipation channel and between two chips arranged opposite to each other.

[0014] In one embodiment, the heat-conducting structure can move in the heat dissipation channel to switch between two states: flattening to absorb heat and shrinking toward the side wall to form a wave shape to dissipate heat.

[0015] In one embodiment, a plurality of folds are formed on the heat-conducting structure, and the heat-conducting structure is an expandable material.

[0016] In one of the embodiments, the plastic encapsulation layer includes a first encapsulation layer and a second encapsulation layer which are arranged opposite to each other. The first encapsulation layer and the second encapsulation layer are formed after folding the circuit substrate. A first heat sink arranged in an array is protruded from the surface of the first encapsulation layer, and a second heat sink arranged in an array is protruded from the surface of the plastic encapsulation layer. The first heat sink and the second heat sink are staggered.

[0017] In one embodiment, the first heat sink and the second heat sink can absorb heat and expand to form a plurality of first baffle walls and second baffle walls that are spaced apart in sequence, and the first baffle walls and the second baffle walls define a heat dissipation channel, and the heat dissipation channel includes a plurality of the heat dissipation channels, and air flow holes are respectively provided at both ends of the heat dissipation channel.

[0018] The present application also relates to a multi-chip packaging process.

[0019] A multi-chip packaging process, comprising:

[0020] Providing a circuit substrate, wherein a patterned circuit layer is disposed on the circuit substrate;

[0021] Providing a plurality of chips, and placing the chips at predetermined positions of the circuit substrate and electrically conducting with the patterned circuit layer;

[0022] forming a plastic encapsulation layer to cover the surface of the chip; and

[0023] The circuit substrate is folded so that the projection areas of the plurality of chips on the circuit substrate at least partially overlap, and the chips located on opposite sides are spaced apart to form a heat dissipation channel.

[0024] The multi-chip packaging structure provided by the present application can achieve the following technical effects:

[0025] 1. The multi-chip packaging structure provided in the present application folds the circuit substrate so that multiple chips arranged on the surface of the circuit substrate are stacked in the vertical direction, and heat dissipation channels are formed between the stacked chips. The side walls of the circuit substrate are provided with air flow holes corresponding to the heat dissipation channels. The heat dissipation channels and the air flow holes can be used for air convection, thereby realizing automatic heat dissipation of the multi-chip packaging structure.

[0026] 2. By setting a heat-conducting structure in the heat dissipation channel and between two opposing chips, the heat in the heat dissipation channel is disturbed by the telescopic movement of the heat-conducting structure, and the heat can be transported to the outside to improve the heat dissipation effect.

[0027] 3. By arranging the first heat sink and the second heat sink on both sides of the heat dissipation channel and the surface of the plastic sealing layer, and utilizing the thermal expansion effect of the first heat sink and the second heat sink to isolate multiple heat dissipation channels, the heat dissipation effect can be improved. Moreover, since the first heat sink and the second heat sink are made of graphene, the first heat sink and the second heat sink can achieve the technical effect of elastic buffering. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a cross-sectional schematic diagram of a multi-chip packaging structure provided by the first embodiment of the present application;

[0029] Figure 2 A second embodiment of the present application provides a cross-sectional schematic diagram of a multi-chip packaging structure with a heat-conducting structure in a wavy shape;

[0030] Figure 3 yes Figure 2 A cross-sectional schematic diagram of a heat-conducting structure of a multi-chip packaging structure in a flattened state is provided;

[0031] Figure 4 is a schematic diagram of a first heat sink and a second heat sink included in a heat-conducting structure of a multi-chip package structure provided in a third embodiment of the present application when the heat is not absorbed;

[0032] Figure 5 yes Figure 4 Provided is a schematic diagram of a first heat sink and a second heat sink included in a heat-conducting structure of a multi-chip packaging structure when they expand by absorbing heat;

[0033] Figure 6 yes Figure 4 A schematic diagram of a heat dissipation channel formed by a multi-chip packaging structure is provided;

[0034] Figure 7 4 is a cross-sectional schematic diagram of a multi-chip packaging structure provided in accordance with the fourth embodiment of the present application.

[0035] Explanation of the reference numerals: 1. Circuit substrate; 2. Chip; 3. Plastic packaging layer; 101. Heat dissipation channel; 10. Side wall; 110. Air flow hole; 4. Support structure; 5. Heat conduction structure; 31. First packaging layer; 32. Second packaging layer; 50. Crease; 51. First heat sink; 52. Second heat sink; 510. First retaining wall; 512. Second retaining wall; 6. Fixing part; 111. Heat dissipation channel; 7. Passive device; 105. Neck portion. DETAILED DESCRIPTION

[0036] The following is combined with Figure 1-6 The multi-chip packaging structure and packaging process provided by the present application are further described in detail.

[0037] Example 1

[0038] See also Figure 1 The present application relates to a multi-chip packaging structure. The multi-chip packaging structure includes a circuit substrate 1, a plurality of chips 2 and a plastic packaging layer 3.

[0039] The circuit substrate 1 is a flexible circuit board, and the flexible circuit board includes a flexible substrate and a patterned circuit layer (not shown) disposed on the flexible substrate. In this embodiment, the material of the flexible substrate can be polyimide or other flexible plastic materials. The flexible circuit board can arbitrarily define the bending direction according to the size of the chip 2 and can also control the distance between the two layers after bending.

[0040] A plurality of chips 2 are respectively disposed at predetermined positions of the circuit substrate 1 and are electrically connected to the patterned circuit layer.

[0041] The plastic encapsulation layer 3 covers the surface of the chip 2 to protect the chip from water and oxygen; the circuit substrate 1 is folded so that the projection areas of the multiple chips 2 on the circuit substrate 1 at least partially overlap, and a heat dissipation channel 101 is formed between the chips 2 on opposite sides.

[0042] In this embodiment, the plastic packaging layers 3 disposed opposite to each other are defined as a first packaging layer 31 and a second packaging layer 32 , and the heat dissipation channel 101 is the gap area between the first packaging layer 31 and the plastic packaging layer 3 .

[0043] After multiple chips 2 are configured by folding the circuit substrate 1, intervals are formed between the chips 2 on opposite sides, and these intervals can be used as heat dissipation channels 101. Effective heat dissipation channels 101 can promote the conduction and dissipation of heat, reduce heat accumulation between chips 2, and improve heat dissipation efficiency. The design of the heat dissipation channel 101 ensures that the chip 2 will not be degraded or damaged due to overheating when it is under high load or running for a long time.

[0044] In this embodiment, the circuit substrate 1 is folded into an "e" shape. That is, the first end of the circuit substrate 1 is folded inward to reduce the thickness of the multi-chip packaging structure. In other embodiments, the circuit substrate 1 can also be a ceramic substrate with high thermal conductivity, and the ceramic substrate can be a plurality of sub-ceramic substrates spliced ​​together to form an "e" shape.

[0045] In this embodiment, the number of chips 2 is shown as 4, all of which are fixed to the inner side of the "e" shape formed by the circuit substrate 1. In other embodiments, the circuit substrate 1 can be folded in an S-shape as long as a heat dissipation channel 101 can be formed between two chips 2 disposed opposite to each other.

[0046] In a further embodiment, in the vertical direction, the heat generated by the chip 2 during operation can be set to form a heat gradient, so that the heat can be radiated and dissipated better.

[0047] The multi-chip package structure includes a side wall 10 perpendicular to the plane where the chip 2 is set, and an airflow hole 110 is opened on the side wall 10, and the airflow hole 110 is connected to the heat dissipation channel 101 to form convection. Due to the folding, the intervals between the chips 2 can be designed as heat dissipation channels 101. These channels can promote the flow of hot air and form natural convection, thereby taking away the generated heat. By rationally planning the heat dissipation channel 101, the heat can be distributed more evenly to prevent local overheating problems.

[0048] A support structure 4 is formed on the plastic encapsulation layer 3, and the support structure 4 is used to support the two adjacent layers of the folded circuit substrate 1, and also plays the role of radiation heat dissipation and convection heat dissipation. That is to say, after the circuit substrate 1 is folded, it can support the folded head end, and its position can be stabilized. The support structure 4 is preferably formed of one or more materials selected from copper, aluminum, aluminum oxide, and boron nitride and is porous honeycomb-shaped. The porous honeycomb structure has transverse convection holes distributed in the transverse direction and longitudinal radiation holes distributed in the longitudinal direction. More specifically, the support structure 4 includes a central area and an edge area surrounding the central area, the central area is provided with longitudinal radiation holes, and the edge area is provided with a circle of transverse convection holes. On the one hand, it reduces the stress applied to the plastic encapsulation layer 3, and on the other hand, the porous honeycomb shape allows the external airflow to smoothly enter the heat dissipation channel 101, which plays the effect of convection heat dissipation and radiation heat dissipation.

[0049] In a further embodiment, a heat dissipation fan may be arranged outside the multi-chip packaging structure, and the cooling air volume generated by the heat dissipation fan may be introduced into the heat dissipation channel 101 through the air flow holes 110, thereby further improving the heat dissipation effect.

[0050] In this embodiment, the projection areas of the two chips 2 arranged opposite to each other on the circuit substrate 1 partially overlap, that is, there is no other heat source in the direction opposite to the working surface of the chip 2, so that both convection heat dissipation and radiation heat dissipation can be utilized to further improve the heat dissipation effect.

[0051] In this embodiment, multiple chips are arranged on the same circuit substrate 1, and the circuit substrate 1 is folded so that the projected areas of the chips 2 at least partially overlap to form a heat dissipation channel 101. This structure allows multiple chips to be effectively and compactly arranged through the folding design, thereby improving the packaging density, and at the same time, the heat dissipation channel 101 formed improves the thermal management between chips and enhances the heat dissipation effect. This design is suitable for applications that require high integration and efficient heat dissipation.

[0052] Since the chip 2 of the present application is formed into a three-dimensional stack by folding the circuit substrate 1, the connection direction between each chip 2 and the circuit substrate 1 will not be changed, nor will it be affected by the chip size. Of course, there is no need to open a conductive bonding part in the plastic packaging layer 3 to achieve the interconnection between the bottom chip and the outer circuit. Therefore, the multi-chip packaging structure provided by the present application can simplify the packaging process.

[0053] Example 2

[0054] See also Figure 2-3 , is a multi-chip packaging structure provided in the second embodiment of the present application. The multi-chip packaging structure provided in the second embodiment is basically the same as the first embodiment, except that, in the present embodiment, a heat-conducting structure 5 is fixed to the side wall 10, and the heat-conducting structure 5 is located between the heat dissipation channel 101 and the two chips 2 arranged opposite to each other. The heat-conducting structure 5 can be a metal sheet, which can transfer the heat of the heat dissipation channel 101 to both sides of the heat dissipation channel 101.

[0055] In this embodiment, the heat conducting structure 5 is fixed in the heat dissipation channel 101 via a fixing member 6 .

[0056] In this embodiment, the heat-conducting structure 5 is expanded graphite, and a plurality of folds 50 are formed on the heat-conducting structure 5. Positioning grooves are respectively provided on the surfaces of the first encapsulation layer 31 and the second encapsulation layer 32, and the length of the positioning groove is consistent with the length of the fold 50. The heat-conducting structure 5 is an expandable material. More preferably, it is negatively expanded graphite. That is, the heat-conducting structure 5 can shrink along the fold 50 when absorbing heat. When the heat generated when the chip 2 is working is not high enough, the heat-conducting structure 5 is in a flattened state. When absorbing heat, the heat-conducting structure 5 shrinks. When shrinking, since the surfaces of the first encapsulation layer 31 and the second encapsulation layer 32 are respectively provided with positioning grooves, during the shrinking movement, the fold 50 encounters the positioning groove and is positioned until all the folds 50 are located in the corresponding grooves to form a wave state. Since the heat-conducting structure 5 in a wave state leaves the working surface of the chip 2, the temperature will gradually decrease, thereby expanding and leaving the positioning groove and gradually flattening. That is, the heat-conducting structure 5 can move in the heat dissipation channel 101 to switch between two states: flattening to absorb heat and shrinking to the side wall 10 to form a wave shape to dissipate heat. By continuously switching the flattened and contracted states of the heat-conducting structure 5, the airflow in the heat dissipation channel 101 can be disturbed to prevent heat from being concentrated between the two oppositely arranged chips 2. The airflow disturbance can help accelerate the conduction and dissipation of heat, thereby further enhancing the heat dissipation effect.

[0057] In addition, it should be noted that passive components 7 such as resistors, capacitors, filters, etc. can be arranged on the side wall 10. In this way, the circuit substrate 1 can be arranged in a partitioned manner, and the plastic layer 3 is only provided at the required position. In this way, the heat dissipation effect of the multi-chip packaging structure can be improved.

[0058] Example 3

[0059] See also Figure 4-6 , which is a multi-chip packaging structure provided in the third embodiment of the present application. The multi-chip packaging structure provided in Embodiment 3 is basically the same as that in the second embodiment, except that, in the present embodiment, the thermal conductive structure 5 includes a first heat sink 51 protruding from the surface of the first packaging layer 31 and arranged in an array, and a second heat sink 52 protruding from the surface of the plastic packaging layer 3 and arranged in an array; the first heat sink 51 and the second heat sink 52 are staggered.

[0060] In this embodiment, the first heat sink 51 and the second heat sink 52 are positively expanded graphite, which expands when heated. The first heat sink 51 absorbs heat and expands, so that the first heat sink 51 and the second heat sink 52 in the same row contact each other to form a first retaining wall 510, and the first heat sink 51 and the second heat sink 52 in another row contact each other to form a second retaining wall 512. The first retaining wall 510 and the second retaining wall 512 jointly define a heat dissipation channel, and the heat dissipation channel 101 includes a plurality of the heat dissipation channels 111, and the two ends of the heat dissipation channel 111 are respectively provided with air flow holes 110.

[0061] In this embodiment, the first heat sink 51 and the second heat sink 52 have different sizes. Through contact and bonding, a better heat conduction path is provided during thermal expansion. The larger heat sink generates stronger contact with the smaller heat sink through thermal expansion, thereby enhancing the heat conduction efficiency.

[0062] The distance between the first heat sink 51 and the second packaging layer 32 is much smaller than the thickness of the first heat sink 51 , and the distance between the second heat sink 52 and the first packaging layer 31 is much smaller than the thickness of the first heat sink 51 . Therefore, the first heat sink 51 and the second heat sink 52 can also play a buffering role between the chips 2 .

[0063] That is, in this embodiment, the first heat sink 51 and the second heat sink 52 can form a plurality of baffles by expansion, thereby defining a plurality of heat dissipation channels 111. Airflow holes 110 are respectively provided at both ends of the heat dissipation channel 111, which enhances air flow and heat dissipation effect. This design limits the airflow path so that the airflow can pass through the heat dissipation channel 111 in a targeted manner, thereby improving the heat exchange efficiency, ensuring that the heat in the packaging structure is quickly discharged, and improving the working stability of the chip 2.

[0064] In addition, during the expansion of the first heat sink 51 and the second heat sink 52 , the fixing method of the packaging layer and the chip 2 is further strengthened to a certain extent, thereby preventing the connection reliability between the chip 2 and the circuit substrate 1 from being reduced.

[0065] Example 4

[0066] See also Figure 7 , Figure 7 The fourth embodiment of the present application provides a cross-sectional schematic diagram of a multi-chip packaging structure. In this embodiment, the heat-conducting structure 5 is a metal heat-conducting sheet, which is sandwiched between two chips 2 arranged opposite to each other and has a mesoporous cavity structure, and the middle of the metal heat-conducting sheet includes a neck portion 105.

[0067] That is to say, the heat dissipation channel is formed by the middle hole shape of the metal heat conductive sheet, and the two ends of the metal heat conductive sheet are open. On the one hand, the practical metal heat conductive sheet plays the role of electromagnetic shielding between two relatively arranged chips, and the metal is also conducive to heat conduction. Secondly, the neck portion 105 is located in the middle of the metal heat conductive sheet, so that the entire metal heat conductive sheet is similar to an hourglass shape. The hourglass-shaped heat dissipation channel is thin in the middle and thick at both ends. When the air enters the channel from the thicker end, the cross-sectional area of ​​the channel suddenly decreases. According to the Bernoulli equation, the air flow rate will increase accordingly. This accelerated air flow can more effectively take away the heat in the channel; in the narrow part of the hourglass shape, the increase in air flow rate may cause the generation of local eddies. These eddies can disturb the air flow and enhance the heat exchange efficiency between the air and the channel wall.

[0068] The present application also relates to a multi-chip packaging process, comprising the following steps:

[0069] S1: providing a circuit substrate 1, on which a patterned circuit layer is arranged; the patterned circuit layer is used for signal communication between chips 2 or for signal communication with the outside world.

[0070] S2: Provide a plurality of chips 2, and respectively place the chips 2 at predetermined positions of the circuit substrate 1 and electrically connect the chips 2 to the patterned circuit layer; the chips 2 may be placed on the circuit substrate 1 by flip-chip or wire bonding. In this embodiment, the chips 2 are placed on the circuit substrate 1 by flip-chip.

[0071] S3: forming a plastic packaging layer 3 to cover the surface of the chip 2 .

[0072] S4: Fold the circuit substrate 1 so that the projection areas of the multiple chips 2 on the circuit substrate 1 at least partially overlap, and the chips 2 on opposite sides are spaced apart to form heat dissipation channels 101. It should be noted that the at least partial overlap mentioned here means full overlap or partial overlap.

[0073] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A multi-chip packaging structure, characterized in that: include: A circuit substrate (1), wherein a patterned circuit layer is provided on the circuit substrate (1); A plurality of chips (2) are respectively arranged at preset positions of the circuit substrate (1) and are electrically connected to the patterned circuit layer; A plastic encapsulation layer (3) covers the surface of the chip (2); the circuit substrate (1) is folded so that the projection areas of the plurality of chips (2) on the circuit substrate (1) at least partially overlap, a heat dissipation channel (101) is formed between two chips (2) arranged opposite to each other, and the heat-generating surfaces of the two chips (2) arranged opposite to each other are located in the same heat dissipation channel (101); The circuit substrate (1) is a flexible circuit substrate, and the circuit substrate (1) is folded into an "e" shape or an "s" shape; the circuit substrate (1) comprises a side wall (10) perpendicular to the plane on which the chip (2) is arranged, and the side wall (10) is provided with an air flow hole (110), and the air flow hole (110) is connected to the heat dissipation channel (101) to form air convection; as well as The heat-conducting structure (5) is located between the heat-dissipating channel (101) and two chips (2) arranged opposite to each other, and the heat-conducting structure (5) guides or transfers the heat of the heat-dissipating channel (101) to the outside of the heat-dissipating channel (101).

2. The multi-chip package structure according to claim 1, characterized in that: A support structure (4) is formed on the plastic sealing layer (3), and the support structure (4) is used to support two adjacent layers of folded circuit substrates (1). The support structure (4) is arranged as a porous honeycomb structure, and the porous honeycomb structure has transverse convection holes distributed in the transverse direction and longitudinal radiation holes distributed in the longitudinal direction, and the transverse convection holes are arranged around the longitudinal radiation holes.

3. The multi-chip package structure according to claim 1, characterized in that: The heat-conducting structure (5) is a heat-conducting sheet, which can move in the heat dissipation channel (101) to switch between two states: flattening to absorb heat and contracting toward the side wall (10) to form a wave shape to dissipate heat.

4. The multi-chip package structure according to claim 3, characterized in that: The plastic encapsulation layer (3) comprises a first encapsulation layer (31) and a second encapsulation layer (32) which are arranged opposite to each other, the first encapsulation layer (31) and the second encapsulation layer (32) are respectively provided with positioning grooves, a plurality of folds (50) are formed on the heat-conducting structure (5), the heat-conducting structure (5) is an expandable material, the heat-conducting structure (5) is in a contracted state when heated so that the folds (50) are limited in the positioning grooves, and is in a flat state when the temperature drops so as to contact the first encapsulation layer (31) or the second encapsulation layer (32).

5. The multi-chip package structure according to claim 1, characterized in that: The plastic encapsulation layer (3) comprises a first encapsulation layer (31) and a second encapsulation layer (32) arranged opposite to each other, the heat conducting structure (5) comprises first heat sinks (51) arranged in an array and protruding from the surface of the first encapsulation layer (31), and second heat sinks (52) arranged in an array and protruding from the surface of the plastic encapsulation layer (3), the first heat sinks (51) and the second heat sinks (52) being arranged in an array, the first heat sinks (51) and the second heat sinks (52) being arranged in an staggered manner.

6. The multi-chip package structure according to claim 5, characterized in that: The first heat sink (51) and the second heat sink (52) can absorb heat and expand to form a plurality of first retaining walls (510) and second retaining walls (512) that are sequentially spaced apart, the first retaining walls (510) and the second retaining walls (512) defining a heat dissipation channel, the heat dissipation channel (101) comprising a plurality of the heat dissipation channels, and the airflow holes (110) are respectively provided at both ends of the heat dissipation channels.

7. The multi-chip package structure according to claim 1, characterized in that: The heat-conducting structure (5) is a metal heat-conducting sheet, which is sandwiched between two chips (2) arranged opposite to each other and is a central cavity structure with two ends open. The metal heat-conducting sheet includes a neck portion (105) at the middle position along its length.

8. A multi-chip packaging process, characterized in that: include: Providing a circuit substrate (1), wherein a patterned circuit layer is arranged on the circuit substrate (1); Providing a plurality of chips (2), wherein the chips (2) are respectively arranged at preset positions of the circuit substrate (1) and are electrically connected to the patterned circuit layer; forming a plastic sealing layer (3) to cover the surface of the chip (2); The circuit substrate (1) is folded so that the projection areas of the plurality of chips (2) on the circuit substrate (1) at least partially overlap, a heat dissipation channel (101) is formed between the chips (2) located on opposite sides, and the heat-generating surfaces of the two chips (2) located opposite to each other are located in the same heat dissipation channel (101); and A heat-conducting structure (5) is arranged between two chips (2) arranged opposite to each other in the heat-dissipating channel (101), and the heat-conducting structure (5) guides or transfers the heat of the heat-dissipating channel (101) to the outside of the heat-dissipating channel (101); the circuit substrate (1) is a flexible circuit substrate, and the circuit substrate (1) is folded into an "e" shape or an "s" shape; the circuit substrate (1) comprises a side wall (10) perpendicular to the plane on which the chip (2) is arranged, and an airflow hole (110) is provided on the side wall (10), and the airflow hole (110) is communicated with the heat-dissipating channel (101) to form airflow convection.

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