Semiconductor device and forming method thereof

Abstract

In an embodiment, a device includes: an interposer including: a backside redistribution structure; an interconnect die over the backside redistribution structure, the interconnect die including a substrate, a substrate via protruding from the substrate, and an isolation layer around the substrate via; a first encapsulant around the interconnect die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via physically contacting the substrate via, the isolation layer separating the first conductive via from the substrate. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the demand for smaller and more creative packaging technologies for semiconductor dies has emerged. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, including: an interposer, including: a back-side redistribution structure; an interconnection die, located above the back-side redistribution structure, the interconnection die including a substrate, a substrate through-hole protruding from the substrate, and an isolation layer around the substrate through-hole; a first sealant, located around the interconnection die, the surface of the first sealant being substantially coplanar with the surface of the isolation layer and the surface of the substrate through-hole; and a front-side redistribution structure, located above the first sealant, the front-side redistribution structure including a first conductive through-hole physically contacting the substrate through-hole, the isolation layer separating the first conductive through-hole from the substrate.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: an interconnect die, comprising a substrate, a first substrate through hole protruding from the substrate in a cross-sectional view, and a first isolation layer surrounding the first substrate through hole in a top view; a molded through hole adjacent to the interconnect die; an encapsulant located around the molded through hole and the interconnect die; and a front-side redistribution structure located above the encapsulant, the front-side redistribution structure comprising a first conductive through hole and a second conductive through hole, the first conductive through hole physically contacting the first substrate through hole and the first isolation layer, and in a cross-sectional view, the width of the first conductive through hole is greater than the width of the substrate through hole, the second conductive through hole physically contacting the molded through hole, and in the cross-sectional view, the width of the second conductive through hole is less than the width of the molded through hole.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: sealing an interconnect die with a sealant, the interconnect die comprising a substrate and a substrate through-hole; patterning a groove in the substrate, the groove surrounding the substrate through-hole; forming an isolation layer in the groove; planarizing the isolation layer, the top surface of the isolation layer being substantially coplanar with the top surface of the substrate through-hole and the top surface of the sealant; and forming a front side redistribution structure on the isolation layer and the sealant, the front side redistribution structure comprising a first conductive through-hole physically contacting the substrate through-hole and the isolation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 It is a cross-sectional view of an integrated circuit die.

[0008] FIG. 2A to FIG. 2B is a cross-sectional view of a die stack.

[0009] Figures 3 to 15 is a diagram of an intermediate stage in the fabrication of an integrated circuit package in accordance with some embodiments.

[0010] Fig.16 is a diagram of an integrated circuit package according to some other embodiments.

[0011] Figures 17 to 23 is a diagram of an intermediate stage in the fabrication of an integrated circuit package according to some other embodiments.

[0012] Fig.24 is a diagram of an integrated circuit package according to some other embodiments. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0015] According to various embodiments, an interposer of an integrated circuit package includes a sealed interconnect die and a redistribution structure. The interconnect die includes a substrate through-hole, which is small and has a high density. The conductive through-holes of the redistribution structure are physically and electrically coupled to the substrate through-holes. The conductive through-holes are oversized (e.g., larger than the substrate through-holes), which can help reduce the risk of disengagement of the conductive through-holes (e.g., due to offset during processing). The interconnect die also includes an isolation layer around the substrate through-holes at the back side of the interconnect die. The isolation layer separates the oversized conductive through-holes of the redistribution structure from the substrate of the interconnect die. Therefore, the risk of leakage from the oversized conductive through-holes can be reduced, which can improve the performance of the integrated circuit package.

[0016] Figure 1 is a cross-sectional view of an integrated circuit die 50. A plurality of integrated circuit dies 50 will be packaged in a subsequent process to form an integrated circuit package. Each integrated circuit die 50 may be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC) die, a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof. The integrated circuit die 50 may be formed in a wafer, which may include different die regions that are segmented in a subsequent step to form a plurality of integrated circuit dies 50. The integrated circuit die 50 includes a semiconductor substrate 52, an interconnect structure 54, a die connector 56, and a dielectric layer 58.

[0017] Semiconductor substrate 52 may be a doped or undoped silicon substrate or an active layer of a semiconductor on insulator (SOI) substrate. Semiconductor substrate 52 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. Semiconductor substrate 52 has an active surface (e.g., Figure 1 upward-facing surface) and non-active surfaces (e.g. Figure 1 The device is located at the active surface of the semiconductor substrate 52. The device can be an active device (eg, a transistor, a diode, etc.), a capacitor, a resistor, etc. The inactive surface may be free of devices.

[0018] The interconnect structure 54 is located above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices of the semiconductor substrate 52 together to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and corresponding metallization layers in the dielectric layers. Acceptable dielectric materials for the dielectric layers include oxides such as silicon oxide or aluminum oxide, nitrides such as silicon nitride, combinations thereof such as silicon oxynitride, and the like. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, and the like. The metallization layer may include conductive vias and / or wires to interconnect the devices of the semiconductor substrate 52. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, and the like. The metallization layer of the interconnect structure 54 may be formed by a damascene process, such as a single damascene process, a dual damascene process, and the like.

[0019] Die connector 56 is located at front side 50F of integrated circuit die 50. Die connector 56 may be a conductive post, pad, etc. that makes an external connection. Die connector 56 is located in and / or on interconnect structure 54. For example, die connector 56 may be part of an upper metallization layer of interconnect structure 54. Die connector 56 may be formed of a metal, such as copper, aluminum, etc., and may be formed, for example, by plating, etc.

[0020] Optionally, during the formation of the integrated circuit die 50, a solder area (not shown separately) can be provided on the die connector 56. The solder area can be used to perform a chip probe (CP) test on the integrated circuit die 50. For example, the solder area can be a solder ball, a solder bump, etc., which is used to attach a chip probe to the die connector 56. The chip probe test can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 (which is a KGD) that has been subsequently processed is packaged, and the die that has not passed the chip probe test is not packaged. After the test, the solder area can be removed.

[0021] The dielectric layer 58 is located at the front side 50F of the integrated circuit die 50. The dielectric layer 58 is located in and / or on the interconnect structure 54. For example, the dielectric layer 58 can be an upper dielectric layer of the interconnect structure 54. The dielectric layer 58 laterally seals the die connector 56. The dielectric layer 58 can be an oxide, a nitride, a carbide, a polymer, etc., or a combination thereof, which can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The top surfaces of the die connector 56 and the dielectric layer 58 can be coplanar at the front side 50F of the integrated circuit die 50 (within process variations).

[0022] FIG. 2A to FIG. 2B 60A, 60B, respectively. The die stacks 60A, 60B may each have a single function (e.g., a logic device, a memory die, etc.), or may have multiple functions. In some embodiments, the die stack 60A is a logic device such as a system on an integrated chip (SoIC) device, and the die stack 60B is a memory device such as a high bandwidth memory (HBM) device.

[0023] like Figure 2AAs shown in , the die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, the first integrated circuit die 50A is a logic die, and the second integrated circuit die 50B is an interface die. The interface die bridges the logic die to the memory die and converts commands between the logic die and the memory die. In some embodiments, the first integrated circuit die 50A and the second integrated circuit die 50B are bonded so that the active surfaces face each other (e.g., are "face-to-face" bonded). A conductive via 62 can be formed through one of the integrated circuit dies 50 so that an external connection to the die stack 60A can be made. The conductive via 62 can be a through-substrate via (TSV), such as a through-silicon via, etc. In the illustrated embodiment, the conductive via 62 is formed in the second integrated circuit die 50B (e.g., an interface die). The conductive via 62 extends through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to be physically and electrically connected to the metallization layer of the interconnect structure 54.

[0024] like Figure 2B As shown in , the die stack 60B is a stacked device including a plurality of semiconductor substrates 52. For example, the die stack 60B may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) device, a high bandwidth memory (HBM) device, etc. Each semiconductor substrate 52 may (or may not) have a separate interconnect structure 54. The semiconductor substrates 52 are connected by conductive vias 62 such as TSVs.

[0025] Figures 3 to 15 is an integrated circuit package 200 according to some embodiments (see Fig.15 ) is a view of an intermediate stage in the manufacture of. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.12 , Fig.13 , Fig.14 and Fig.15 is a cross-sectional view, and Fig.11is a top view. A plurality of packaging regions 100P are shown, and an integrated circuit package 200 is formed in each packaging region 100P. An interposer wafer 100 is formed. The interposer wafer 100 includes an interposer 240 in each packaging region 100P. The integrated circuit device 202 is bonded to the interposer wafer 100. The interposer 240 in each packaging region 100P may include an interconnect die 120 for interconnecting the integrated circuit devices 202 in the corresponding packaging region 100P. Then, a packaging substrate 220 is mounted to the interposer wafer 100. Specifically, the packaging substrate 220 is attached to the interposer 240 in each packaging region 100P. Then, the packaging region 100P is segmented to form integrated circuit packages 200, each of which includes a segmented portion (e.g., an interposer 240) of the packaging substrate 220 and the interposer wafer 100. In an embodiment, the integrated circuit package 200 is a chip on wafer on a substrate. Packages such as CoWoS-L packages, but it should be understood that embodiments may be applicable to other 3DIC packages.

[0026] exist Figure 3 In the embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed on the carrier substrate 102 at the same time.

[0027] The release layer 104 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its viscosity when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its viscosity when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be flush and may have a high degree of planarity.

[0028] A backside redistribution structure 110 is formed on the release layer 104. The backside redistribution structure 110 includes dielectric layers 112 and metallization layers 114 (sometimes referred to as redistribution layers or redistribution lines) between the dielectric layers 112. Thus, the backside redistribution structure 110 includes metallization layers 114 separated from each other by respective dielectric layers 112.

[0029] In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, a BCB-based polymer, etc. In other embodiments, the dielectric layer 112 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. The dielectric layer 112 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After forming the dielectric layer 112, the dielectric layer 112 may be patterned to expose underlying conductive features (if present), such as portions of the underlying metallization layer 114. The patterning may be implemented by any acceptable process, such as by exposing the dielectric layer to light when the dielectric layer 112 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 112 is a photosensitive material, the dielectric layer 112 may be developed after exposure.

[0030] Each of the metallization layers 114 includes a conductive via and / or a conductor. The conductive via extends through the corresponding dielectric layer 112, and the conductor extends along the corresponding dielectric layer 112. As an example of forming the metallization layer 114, a seed layer (not shown separately) is formed above the corresponding lower component. For example, the seed layer can be formed on the corresponding dielectric layer 112 and in any opening through the corresponding dielectric layer 112. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above the titanium layer and the titanium layer. The seed layer can be formed using a deposition process, such as physical vapor deposition (PVD) and the like. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 114. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from a seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 114 of the backside redistribution structure 110.

[0031] The backside redistribution structure 110 is shown as an example. More or fewer dielectric layers 112 and metallization layers 114 than shown may be formed by performing the previously described steps any desired number of times.

[0032] An underbump metallization layer (UBML) 116 is formed for subsequent connection to the backside redistribution structure 110. The UBML 116 has a bump portion located on and extending along a major surface of an upper dielectric layer 112 of the backside redistribution structure 110, and has a via portion extending through the upper dielectric layer 112 of the backside redistribution structure 110 to physically and electrically couple the upper metallization layer 114 of the backside redistribution structure 110. The UBML 116 may be formed of the same material as the metallization layer 114, and may be formed by a similar process as the metallization layer 114. In some embodiments, the UBML 116 has a different size than the metallization layer 114.

[0033] exist Figure 4 1 , through-vias 118 are formed on a first subset of UBML 116. Additionally, an interconnect die 120 is attached to a second subset of UBML 116. The second subset of UBML 116 remains free of through-vias 118. Subsequently, the first subset of UBML 116 and through-vias 118 will be used to connect to higher layers of the integrated circuit package 200. Subsequently, the second subset of UBML 116 and interconnect die 120 will be used for direct communication between integrated circuit dies of the integrated circuit package 200.

[0034] As an example of forming a through hole 118, a photoresist is formed and patterned on the UBML 116 and the backside redistribution structure 110. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 118. Patterning forms an opening through the photoresist to expose the UBML 116. A conductive material is formed in the opening of the photoresist and on the exposed portion of the UBML 116. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material of the through hole 118 can be directly plated by the conductive material of the UBML 116. The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The photoresist is then removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. The remaining portion of the conductive material forms the through hole 118.

[0035] Each interconnect die 120 may be a local silicon interconnect (LSI), a large scale integrated package, an interposer die, etc. In the illustrated embodiment, one interconnect die 120 is attached in each package region 100P. It should be understood that any desired number of interconnect dies 120 may be attached in each package region 100P.

[0036] Each interconnect die 120 includes a substrate 122 in which conductive features are formed in and / or on the substrate 122. The substrate 122 may include a semiconductor substrate, one or more dielectric layers, etc. In addition, each interconnect die 120 may include a through substrate via (TSV) 124 that extends into or through the substrate 122 and may be coupled to the conductive features of the interconnect die 120. In the illustrated embodiment, the TSV 124 is exposed at the back side of the interconnect die 120. In another embodiment, the substrate 122 may initially cover the TSV 124 at the back side of the interconnect die 120. The interconnect die 120 is attached to the UBML 116 using die connectors 126 disposed at the front side of the interconnect die 120. Some of the die connectors 126 may be electrically coupled to the back side of the interconnect die 120 through the TSV 124. As described in more detail later, the TSV 124 is small, such as smaller than the through-hole 118. Because TSVs 124 are smaller, they can have a greater density, thereby increasing the amount of connections to interconnect die 120 .

[0037] In the embodiment where the interconnect die 120 is an LSI, the interconnect die 120 may be a bridge structure including a die bridge 128. The die bridge 128 may be a metallization layer formed in and / or on, for example, the substrate 122, and is used to interconnect integrated circuit devices (described later) to each other. The die bridge 128 is located at the front side of the interconnect die 120. Therefore, the LSI may be used to directly connect integrated circuit devices and allow communication between integrated circuit devices. In such an embodiment, the interconnect die 120 may be placed in an area disposed between the subsequently attached integrated circuit devices so that each interconnect die 120 overlaps the integrated circuit device above. In some embodiments, the interconnect die 120 may also include a logic device and / or a memory device. In some embodiments, the interconnect die 120 may not have a logic device and / or a memory device. The interconnect die 120 is attached to the UBML 116 so that the die bridge 128 faces the backside redistribution structure 110.

[0038] In the illustrated embodiment, the interconnect die 120 is attached to the backside redistribution structure 110 (via the UBML 116) with a solder joint, such as with a conductive connector 130. The conductive connector 130 may be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. The conductive connector 130 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 130 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, a reflow may be performed to shape the material into a desired bump shape. Attaching the interconnect die 120 to the UBML 116 may include placing the interconnect die 120 on the UBML 116 (e.g., using a pick and place process) and reflowing the conductive connectors 130 to physically and electrically couple the die connectors 126 to the UBML 116. In another embodiment, the interconnect die 120 is attached to the backside redistribution structure 110 using the die connectors 126 with direct bonding.

[0039] In some embodiments, an underfill 132 is formed around the conductive connector 130 and between the backside redistribution structure 110 and the interconnect die 120. The underfill 132 can reduce stress and protect joints caused by the reflow of the conductive connector 130. The underfill 132 can also be used to firmly bond the interconnect die 120 to the backside redistribution structure 110 and provide structural support and environmental protection. The underfill 132 can be formed of a molding compound, an epoxy resin, etc. The underfill 132 can be formed by a capillary flow process after attaching the interconnect die 120, or can be formed by a suitable deposition method before attaching the interconnect die 120. The underfill 132 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0040] exist Figure 5 In the embodiment of the present invention, an encapsulant 134 is formed on and around the various components. After being formed, the encapsulant 134 seals the UBML 116, the underfill 132, the through-hole 118 and / or the interconnection die 120. The encapsulant 134 may be a molding compound, an epoxy resin, etc. The encapsulant 134 may be applied by compression molding, transfer molding, etc., and may be formed over the carrier substrate 102, thereby burying or covering the through-hole 118 and / or the interconnection die 120. The encapsulant 134 is also formed in the gap area between the interconnection die 120 and the through-hole 118. The encapsulant 134 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0041] A planarization process may optionally be performed on the encapsulant 134 to expose the via 118, the substrate 122, and the TSV 124. The planarization process may remove material of the via 118, the substrate 122, and / or the TSV 124 until the TSV 124 and the via 118 are exposed. The top surfaces of the via 118, the substrate 122, the TSV 124, and the encapsulant 134 are substantially coplanar (within process variations) after the planarization process. The planarization process may be, for example, chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, planarization may be omitted, for example, if the via 118 and / or the TSV 124 are already exposed. After the planarization process, the via 118 extends through the encapsulant 134. Therefore, the via 118 may be referred to as a molded through via (TMV).

[0042] exist Figure 6 In the embodiment of the present invention, a groove 140 is patterned in the substrate 122 of the interconnect die 120. The bottom surface of the groove 140 is lower than the backside surface of the substrate 122, so that there is a corresponding step between them. In addition, the bottom surface of the groove 140 is lower than the surface of the TSV 124. Therefore, after the groove 140 is formed, the TSV 124 protrudes from the backside of the substrate 122. The sidewalls of the TSV 124 may be exposed by the groove 140. The groove 140 may be formed to a depth D1 in the range of 2 μm to 6 μm, such as about 2 μm. The sidewalls of the groove 140 may be inclined sidewalls (as shown in the figure), straight sidewalls (which are perpendicular to the backside surface of the substrate 122), etc.

[0043] In the illustrated embodiment, a single groove 140 is formed in each substrate 122 such that the groove 140 surrounds all TSVs 124 protruding from the substrate 122. The non-recessed portion of the substrate 122 extends around the TSVs 124. The non-recessed portion of the substrate 122 may have a non-zero width W1, such as in the range of 5 μm to 40 μm. The groove 140 in each substrate 122 may have any desired shape in top view (not shown separately). For example, the groove 140 may be a square groove, a rectangular groove, a circular groove, etc. In another embodiment, a plurality of grooves 140 are formed in each substrate 122 such that each groove 140 surrounds a corresponding TSV 124 protruding from the substrate 122.

[0044] As an example of patterning the groove 140, a mask 142 may be formed over the sealant 134 and at least the periphery of the substrate 122. Specifically, the non-recessed portion of the substrate 122 is covered by the mask 142. The mask 142 will be used as an etching mask during the etching process for patterning the groove 140. The sealant 134 may be completely covered by the components of the mask 142, which may help avoid contamination of the sealant 134, such as during the etching process for patterning the groove 140. In some embodiments, the mask 142 is formed of a photoresist, such as a single-layer photoresist, a three-layer photoresist, and the like. For example, the mask 142 may be a three-layer photoresist including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), an intermediate layer (e.g., a hard mask), and a top layer (e.g., a photoresist). The photoresist may be formed by spin coating, a deposition process such as CVD, a combination thereof, and the like, and may be patterned using any acceptable photolithography technique to have a desired pattern of the groove 140. Then, the groove 140 can be formed by etching the substrate 122 using the mask 142 as an etching mask. The etching can be any acceptable etching process, such as dry etching, such as reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. After the etching process, the mask 142 can be removed, such as by any acceptable ashing process, etching process, etc.

[0045] exist Figure 7 In the embodiment of the present invention, an isolation layer 144 is formed in the groove 140. The isolation layer 144 completely fills the groove 140 and surrounds the protruding portion of the TSV 124. The isolation layer 144 is formed of any material that can reduce leakage. In some embodiments, the isolation layer 144 is formed of a silicon-containing insulator, such as silicon nitride, silicon oxynitride, etc., which can be formed by a suitable deposition method, such as CVD, plasma enhanced CVD (PECVD), high-density plasma CVD (HDP-CVD), etc. In some embodiments, the isolation layer 144 is formed of a high-k dielectric material, such as a metal oxide, etc. In some embodiments, the isolation layer 144 is formed of a resin-based material, such as an epoxy resin, etc. Each isolation layer 144 may include a single material layer or multiple sublayers of different materials. Initially, the isolation layer 144 may bury the TSV 124. The isolation layer 144 is embedded in the interconnect die 120 and will be referred to as a part of the interconnect die 120. The portion of isolation layer 144 in recess 140 may have sloped sidewalls (as shown), straight sidewalls (which are perpendicular to the backside surface of substrate 122 ), etc. The thickness of isolation layer 144 may be greater than the depth of recess 140 .

[0046] In the illustrated embodiment, each interconnect die 120 includes a single isolation layer 144 surrounding all TSVs 124 protruding from the substrate 122. In another embodiment, each interconnect die 120 includes multiple isolation layers 144 such that each isolation layer 144 surrounds one TSV 124 protruding from the substrate 122.

[0047] In the illustrated embodiment, a respective isolation layer 144 is formed over the respective substrate 122. For example, a mask 146 may be optionally formed over the sealant 134. In some embodiments, the mask 146 is formed of a photoresist, such as a single-layer photoresist, a three-layer photoresist, and the like. For example, the mask 146 may be a three-layer photoresist including a bottom layer (e.g., a bottom anti-reflective coating (BARC) layer), an intermediate layer (e.g., a hard mask), and a top layer (e.g., a photoresist). The photoresist may be formed by spin coating, a deposition process such as CVD, a combination thereof, and the like, and may be patterned using any acceptable photolithography technique to have a desired pattern of the isolation layer 144. The isolation layer 144 may then be deposited in the opening in the mask 146. After the isolation layer 144 is deposited, the mask 146 may be removed, such as by any acceptable ashing process, etching process, and the like. In another embodiment, the mask 146 is omitted, and a single isolation layer 144 is formed over each substrate 122.

[0048] exist Figure 8 In the embodiment of the present invention, a removal process is applied to the isolation layer 144 to remove excess material above the TSV 124, thereby exposing the TSV 124. The removal process can be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc. The planarization process can remove material of the through hole 118, the substrate 122, the TSV 124, the sealant 134 and / or the isolation layer 144. The top surfaces of the through hole 118, the substrate 122, the TSV 124, the sealant 134 and the isolation layer 144 are substantially coplanar (within process variations) after the planarization process. The top surface of the isolation layer 144 may have a planarization mark after the planarization process. After the TSV 124 is exposed, they extend from the front side of the interconnect die 120 to the back side of the interconnect die 120.

[0049] exist Fig. 9In the embodiment of the present invention, a front side redistribution structure 150 is formed on the top surface of the through hole 118, the interconnection die 120 (e.g., the substrate 122, the TSV 124, and the isolation layer 144), and the encapsulant 134. The front side redistribution structure 150 includes a dielectric layer 152 and a metallization layer 154 (sometimes referred to as a redistribution layer or a redistribution line) between the dielectric layers 152. Therefore, the front side redistribution structure 150 includes metallization layers 154 separated from each other by corresponding dielectric layers 152. The metallization layers 154 of the front side redistribution structure 150 are connected to the through hole 118 and to the interconnection die 120 (e.g., the TSV 124).

[0050] In some embodiments, dielectric layer 152 is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithographic mask, such as PBO, polyimide, a BCB-based polymer, etc. In other embodiments, dielectric layer 152 is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, etc. Dielectric layer 152 may be formed by spin coating, lamination, CVD, etc., or a combination thereof. After dielectric layer 152 is formed, dielectric layer 152 may be patterned to expose underlying conductive features, such as portions of underlying vias 118, TSVs 124, and / or metallization layer 154. Patterning may be implemented by any acceptable process, such as by exposing the dielectric layer to light when dielectric layer 152 is a photosensitive material, or by etching using, for example, anisotropic etching. If dielectric layer 152 is a photosensitive material, dielectric layer 152 may be developed after exposure.

[0051] Each of the metallization layers 154 includes a conductive via and / or a conductor. The conductive via extends through the corresponding dielectric layer 152, and the conductor extends along the corresponding dielectric layer 152. As an example of forming the metallization layer 154, a seed layer (not shown separately) is formed above the corresponding lower component. For example, the seed layer can be formed on the corresponding dielectric layer 152 and in any opening through the corresponding dielectric layer 152. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above the titanium layer and the titanium layer. The seed layer can be formed using a deposition process, such as PVD, etc. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization layer 154. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material may be formed by plating, such as chemical plating or electroplating from a seed layer. The conductive material may include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed are then removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms the metallization layer 154 of the front side redistribution structure 150.

[0052] Front side redistribution structure 150 is shown as an example. Greater or fewer dielectric layers 152 and metallization layers 154 than shown may be formed by performing the previously depicted steps any desired number of times.

[0053] Other variations of the front side redistribution structure 150 are contemplated. For example, some of the dielectric layer 152 may be formed of an encapsulant, such as a molding compound, epoxy, etc. The metallization layer 154 may be formed by plating conductive vias from wires. The dielectric layer 152 may be formed by encapsulating the metallization layer 154. Any desired material stack may be used for the dielectric layer 152.

[0054] In some embodiments, dielectric layer 152 is formed of the same material as isolation layer 144. Therefore, there may not be a discernible interface between isolation layer 144 and bottom dielectric layer 152. In some embodiments, dielectric layer 152 is formed of a different material than isolation layer 144. Therefore, there may be a discernible interface between isolation layer 144 and bottom dielectric layer 152.

[0055] Fig.10 yes Fig. 9Detailed view of region 10 of FIG. 10 , with additional components shown. Conductive vias 154V of lower metallization layer 154 of front side redistribution structure 150 are shown. A first subset of conductive vias 154V are physically and electrically coupled to TSVs 124 , while a second subset of conductive vias 154V are physically and electrically coupled to vias 118 .

[0056] As previously noted, TSV 124 is smaller than via 118. For example, the critical dimension (e.g., width W2) of via 118 may be greater than the critical dimension (e.g., width W3) of TSV 124. TSV 124 is also smaller than conductive via 154V. For example, the critical dimension (e.g., width W4) of conductive via 154V may be greater than the critical dimension (e.g., width W3) of TSV 124. Furthermore, via 118 may be larger than conductive via 154V. For example, the critical dimension (e.g., width W4) of conductive via 154V may be less than the critical dimension (e.g., width W2) of via 118. In some embodiments, width W2 of via 118 is in a range of 40 μm to 120 μm, width W3 of TSV 124 is in a range of 4.5 μm to 23 μm, and width W4 of conductive via 154V is in a range of 12 μm to 45 μm. The critical dimension of the conductive via 154V can be measured at the bottom of the conductive via 154V. Forming the conductive via 154V larger than the TSV 124 can help reduce the risk of disengagement of the conductive via 154V (e.g., due to drift during processing), even when the TSV 124 is small. Thus, the process window and / or design flexibility can be improved. The manufacturing yield of the integrated circuit package 200 can be increased.

[0057] The isolation layer 144 is located at the back side of the interconnect die 120. The isolation layer 144 of the interconnect die 120 is disposed between the conductive via 154V and the substrate 122 of the interconnect die 120. Thus, the isolation layer 144 physically separates the substrate 122 from the conductive via 154V above.

[0058] Fig.111 is a top view of the interconnect die 120 of the interposer, wherein additional components are shown. A conductive via 154V of the lower metallization layer 154 of the front side redistribution structure 150 is shown. Specifically, the bottom 154VB and the top 154VT of the conductive via 154V are shown in dotted lines. As more clearly shown in the top view, the isolation layer 144 is formed around the TSV 124. The bottom 154VB and the top 154VT of the conductive via 154V are both larger than the TSV 124. The isolation layer 144 extends beyond the bottom 154VB and the top 154VT of the conductive via 154V. Because in the top view, the isolation layer 144 is formed around the TSV 124, the bottom 154VB of the conductive via 154V is bonded to the isolation layer 144 and contacts the isolation layer 144 instead of contacting the substrate 122. Therefore, the risk of leakage from the conductive via 154V can be reduced. The performance of the integrated circuit package 200 can be improved.

[0059] exist Fig.12 In the process, carrier substrate peeling is performed to detach (or "peel") carrier substrate 102 from the back side of interposer wafer 100. According to some embodiments, peeling includes projecting light such as laser or UV light onto release layer 104 so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. Then, interposer wafer 100 is flipped over to prepare for processing the back side of interposer wafer 100. The front side of interposer wafer 100 can be placed on carrier substrate 201 for subsequent processing. Carrier substrate 201 can be a glass carrier substrate, a ceramic carrier substrate, etc. Carrier substrate 201 can be a wafer.

[0060] exist Fig.13 In the embodiment of the present invention, the integrated circuit device 202 is attached to the back side of the interposer wafer 100 (e.g., attached to the back side redistribution structure 110). A plurality of integrated circuit devices 202 are placed adjacent to each other in each package region 100P. The integrated circuit devices 202 in each package region 100P may include a logic device 202A and a memory device 202B. The logic device 202A and the memory device 202B may be formed in a process of the same technology node, or may be formed in a process of different technology nodes. For example, the logic device 202A may be formed by a more advanced process node than the memory device 202B.

[0061] Each logic device 202A may be a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), a microcontroller, etc. The logic device 202A may be an integrated circuit die (similar to the Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the integrated circuit die 50 described above). Figure 2A1. In some embodiments, the logic device 202A is an integrated circuit die, such as a system-on-chip (SoC) die. In some embodiments, the logic device 202A is a die stack, such as a system-on-integrated chip (SoIC) device.

[0062] Each memory device 202B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The memory device 202B may be an integrated circuit die (similar to a device for a processor). Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the integrated circuit die 50 described above). Figure 2B In some embodiments, the memory device 202B is a die stack, such as a high bandwidth memory (HBM) device.

[0063] In the illustrated embodiment, the integrated circuit device 202 is attached to the backside redistribution structure 110 with a solder joint, such as with a conductive connector 204. The integrated circuit device 202 can be placed on the backside redistribution structure 110 using, for example, a pick-and-place tool. The conductive connector 204 can be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 204 is formed by initially forming a solder layer by a method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, a reflow can be performed to shape the conductive connector 204 into a desired bump shape. Attaching the integrated circuit device 202 to the backside redistribution structure 110 can include placing the integrated circuit device 202 on the backside redistribution structure 110 and reflowing the conductive connector 204. The die connector 206 is located at the front side of the integrated circuit device 202. The conductive connectors 204 form joints between the die connectors 206 of the integrated circuit device 202 and the die connectors (e.g., under bump metallization) of the backside redistribution structure 110, thereby electrically connecting the interposer wafer 100 to the integrated circuit device 202. In another embodiment, the integrated circuit device 202 is attached to the backside redistribution structure 110 using the die connectors 206 with direct bonding.

[0064] An underfill 210 may be formed around the conductive connectors 204 and between the backside redistribution structure 110 and the integrated circuit device 202. The underfill 210 may reduce stress and protect joints created by reflow of the conductive connectors 204. The underfill 210 may be formed of an underfill material, such as a molding compound, an epoxy resin, etc. The underfill 210 may be formed by a capillary flow process after the integrated circuit device 202 is attached to the backside redistribution structure 110, or may be formed by a suitable deposition method before the integrated circuit device 202 is attached to the backside redistribution structure 110. The underfill 210 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0065] An encapsulant 212 is formed over and around the various components. After being formed, the encapsulant 212 seals the underfill 210 (if present) and the integrated circuit device 202. The encapsulant 212 may be a molding compound, an epoxy resin, or the like. The encapsulant 212 may be applied by compression molding, transfer molding, or the like, and formed over the backside redistribution structure 110, thereby burying or covering the integrated circuit device 202. The encapsulant 212 is also formed in gap areas between the underfill 210 (if present) and / or the integrated circuit device 202. The encapsulant 212 may be applied in a liquid or semi-liquid form, and then subsequently cured.

[0066] Optionally, the encapsulant 212 may be thinned (not separately shown) to expose the integrated circuit device 202. The thinning process may be a grinding process, chemical mechanical polishing (CMP), etch back, a combination thereof, etc. After the thinning process, the top surfaces of the integrated circuit device 202 and the encapsulant 212 are substantially coplanar (within process variations). The thinning is performed until a desired amount of the integrated circuit device 202 and the encapsulant 212 have been removed.

[0067] exist Fig.14In the embodiment of the present invention, carrier substrate peeling is performed to detach (or "peel off") the carrier substrate 201 from the interposer wafer 100. Then, the package substrate 220 is bonded to the interposer wafer 100 (for example, bonded to the front-side redistribution structure 150). Each package substrate 220 is bonded to the corresponding interposer in the corresponding package area 100P. Each package substrate 220 includes a substrate core 222, which can be formed of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, etc. can also be used. In addition, the substrate core 222 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 222 is an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Alternative materials for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build-up films such as Ajinomoto Build-up Film (ABF) or other laminate materials may be used for substrate core 222 .

[0068] The substrate core 222 may include active and passive devices (not shown separately). Devices such as transistors, capacitors, resistors, combinations thereof, etc. may be used to generate the structural and functional requirements for the design of the system. The devices may be formed using any suitable method. In some embodiments, the substrate core 222 is substantially free of active and passive devices.

[0069] The substrate core 222 may also include metallization layers and vias (not shown separately). Each package substrate 220 also includes a metallization layer of the substrate core 222 and a bonding pad 224 over the via. The metallization layer may be formed over the active and passive devices and is designed to connect the various devices to form a functional circuit. The metallization layer may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the layers of conductive material and may be formed by any suitable process (such as deposition, damascene, etc.).

[0070] The package substrate 220 may be attached to the front side redistribution structure 150 with a solder joint, such as with a conductive connector 226. The conductive connector 226 may be formed of a reflowable conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc., or a combination thereof. In some embodiments, the conductive connector 226 is formed by initially forming a solder layer by a method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, a reflow may be performed to shape the conductive connector 226 into a desired bump shape.

[0071] Attaching the package substrate 220 to the front side redistribution structure 150 may include placing the package substrate 220 on the front side redistribution structure 150 and reflowing the conductive connectors 226. The conductive connectors 226 are reflowed to attach the bonding pads 224 to the die connectors (e.g., under bump metallization) of the front side redistribution structure 150. The conductive connectors 226 connect the interposer wafer 100 (including the metallization layer of the front side redistribution structure 150) to the package substrate 220 (including the metallization layer of the substrate core 222). Thus, the package substrate 220 is electrically connected to the integrated circuit devices 202 in the corresponding package region 100P.

[0072] In addition, passive devices 230 can be attached to the interposer wafer 100 and / or the package substrate 220. In the illustrated embodiment, the passive devices 230 are attached to the interposer wafer 100, such as to the same surface of the front-side redistribution structure 150 as the conductive connectors 226. In another embodiment, the passive devices 230 are attached to the package substrate 220, such as to the same surface of the package substrate 220 as the conductive connectors 226. The passive devices 230 can include capacitors, resistors, inductors, etc., or combinations thereof. The passive devices 230 can be surface mount devices (SMDs), 2-terminal integrated passive devices (IPDs), multi-terminal IPDs, etc.

[0073] In some embodiments, an encapsulant 232 is formed on and around the various components. After formation, the encapsulant 232 seals the passive devices 230, the conductive connectors 226, and / or the package substrate 220. The encapsulant 232 may be a molding compound, an epoxy resin, or the like. The encapsulant 232 may be applied by compression molding, transfer molding, or the like. The encapsulant 232 may also be formed in the gap region between the package substrate 220 and the front side redistribution structure 150. The encapsulant 232 may be applied in a liquid or semi-liquid form and then subsequently cured.

[0074] exist Fig.15 , a singulation process is performed by cutting along the scribe line regions between the package regions 100P. The singulation process may include sawing, dicing, etc. The singulation process separates the package regions 100P from each other. The resulting, singulated integrated circuit packages 200 are from the package regions 100P. The singulation process forms the interposer 240 from the singulated portions of the interposer wafer 100. Due to the singulation process, the outer sidewalls of the interposer 240, the sealant 212, and the sealant 232 laterally end in common (within process variations).

[0075] Fig.16 is a diagram of an integrated circuit package 200 according to some other embodiments. Fig.15The embodiment of FIG. 1 differs in that the interconnect die 120 is attached to the backside redistribution structure 110 with direct bonding using the die connector 126. In addition, instead of an underfill, an encapsulant 134 may be formed around the die connector 126 and between the backside redistribution structure 110 and the interconnect die 120.

[0076] Figures 17 to 23 is an integrated circuit package 200 according to some other embodiments (see Fig.23 ) is a view of an intermediate stage in the manufacture of. Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig.23 is a cross-sectional view, and Fig.22A and Fig. 22B is a top view. This embodiment is similar to Figures 3 to 15 The embodiment of the present invention is different in that each interconnect die 120 will include multiple isolation layers 144, so that each isolation layer 144 surrounds one TSV 124 protruding from the substrate 122. The isolation layer 144 can be annular in top view. Forming a separate isolation layer 144 around each TSV 124 can help reduce the stress between the substrate 122 and the dielectric layer of the front-side redistribution structure 150.

[0077] exist Fig.17 and from Figure 5 Beginning with the step of patterning a recess 140 in the substrate 122 of the interconnect die 120. The recess 140 may be patterned in the same manner as previously described for Figure 6 The substrate 122 is patterned in a similar manner as described above (eg, using the mask 142 as an etch mask). In the illustrated embodiment, a plurality of recesses 140 are formed in each substrate 122. Each recess 140 surrounds one TSV 124 protruding from the substrate 122.

[0078] exist Fig.18 In the embodiment, an isolation layer 144 is formed in the groove 140. The isolation layer 144 may be formed in the same manner as previously described. Figure 7 is formed in a similar manner as described (eg, using mask 146).

[0079] exist Fig.19 In the embodiment of the present invention, a removal process is applied to the isolation layer 144 to remove excess material above the TSV 124, thereby exposing the TSV 124. The removal process can be performed in the same manner as previously described for the isolation layer 144. Figure 8 The same method as described is used to implement the above method.

[0080] exist Fig. 20In the embodiment of the present invention, a front side redistribution structure 150 is formed on the top surface of the through hole 118, the interconnection tube core 120 (e.g., the substrate 122, the TSV 124 and the isolation layer 144) and the encapsulant 134. The front side redistribution structure 150 can be formed in the same manner as previously described for Fig. 9 Formed in a similar manner as described.

[0081] Fig.21 yes Fig. 20 Detailed view of region 21 of FIG. 1 , where additional components are shown. A conductive via 154V of the lower metallization layer 154 of the front side redistribution structure 150 is shown. The vias 118, TSVs 124, and conductive vias 154V may have the same configuration as previously described for the embodiment of FIG. Fig.10 The width described.

[0082] FIG. 22A to FIG. 22B 1 is a top view of the interconnect die 120 of the interposer, with additional components shown. The conductive vias 154V of the lower metallization layer 154 of the front side redistribution structure 150 are shown. Specifically, the bottom 154VB and the top 154VT of the conductive via 154V are shown in dashed lines. Each corresponding isolation layer 144 extends beyond the bottom 154VB and the top 154VT of the conductive via 154V above. The isolation layer 144 can have any desired shape in the top view. For example, the isolation layer 144 can be a circular isolation layer (such as Fig.22A As shown), rectangular isolation layer (as Fig. 22B shown) etc.

[0083] exist Fig.23 In the process, appropriate steps as previously described are performed to complete the manufacture of the integrated circuit package 200 .

[0084] Fig.24 is a diagram of an integrated circuit package 200 according to some other embodiments. Fig.23 The embodiment of FIG. 1 differs in that the interconnect die 120 is attached to the backside redistribution structure 110 with direct bonding using the die connector 126. In addition, instead of an underfill, an encapsulant 134 may be formed around the die connector 126 and between the backside redistribution structure 110 and the interconnect die 120.

[0085] Embodiments can achieve advantages. When TSVs 124 are smaller, they can be formed to a higher density, thereby increasing the amount of connections to the interconnect die 120. Forming the conductive vias 154V larger than the TSVs 124 can help reduce the risk of disengagement of the conductive vias 154V (e.g., due to drift during processing), which can increase the manufacturing yield of the integrated circuit package 200. Forming the isolation layer 144 around the TSVs 124 provides a dielectric component on which the oversized conductive vias 154V can be bonded, which can reduce the risk of leakage from the conductive vias 154V, which can improve the performance of the integrated circuit package 200.

[0086] In an embodiment, a device includes: an interposer including: a backside redistribution structure; an interconnect die located above the backside redistribution structure, the interconnect die including a substrate, a substrate through hole protruding from the substrate, and an isolation layer around the substrate through hole; a first encapsulant located around the interconnect die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the substrate through hole; and a front side redistribution structure located above the first encapsulant, the front side redistribution structure including a first conductive through hole physically contacting the substrate through hole, the isolation layer separating the first conductive through hole from the substrate. In some embodiments of the device, the device further includes: a molded through hole extending through the first encapsulant, a surface of the molded through hole being substantially coplanar with a surface of the first encapsulant, a surface of the isolation layer, and a surface of the substrate through hole. In some embodiments of the device, the front side redistribution structure further includes a second conductive through hole physically contacting the molded through hole. In some embodiments of the device, the width of the second conductive through hole is less than the width of the molded through hole. In some embodiments of the device, the width of the first conductive through hole is greater than the width of the substrate through hole. In some embodiments of the device, the substrate through via protrudes from the back side of the substrate, the isolation layer is located at the back side of the substrate, and the interconnect die further includes a die bridge at the front side of the substrate, the die bridge connected to the back side redistribution structure. In some embodiments, the device further includes: an integrated circuit device attached to the interposer, the interconnect die overlapping the integrated circuit device; and a second encapsulant located around the integrated circuit device. In some embodiments, the device further includes: a package substrate attached to the interposer; and a second encapsulant located around the package substrate.

[0087] In an embodiment, a device includes: an interconnect die including a substrate, a first substrate through hole protruding from the substrate in a cross-sectional view, and a first isolation layer surrounding the first substrate through hole in a top view; a molded through hole adjacent to the interconnect die; an encapsulant located around the molded through hole and the interconnect die; and a front-side redistribution structure located above the encapsulant, the front-side redistribution structure including a first conductive through hole and a second conductive through hole, the first conductive through hole physically contacting the first substrate through hole and the first isolation layer, the first conductive through hole having a width greater than the width of the substrate through hole in a cross-sectional view, the second conductive through hole physically contacting the molded through hole, the second conductive through hole having a width less than the width of the molded through hole in a cross-sectional view. In some embodiments of the device, the interconnect die further includes: a second substrate through hole protruding from the substrate in a cross-sectional view, and the first isolation layer surrounding the second substrate through hole in a top view. In some embodiments of the device, the interconnect die further includes: a second substrate through hole protruding from the substrate in a cross-sectional view; and a second isolation layer surrounding the second substrate through hole in a top view. In some embodiments of the device, the first isolation layer is circular in a top view. In some embodiments of the device, the first isolation layer is rectangular in top view. In some embodiments of the device, the first isolation layer has inclined sidewalls in cross-sectional view. In some embodiments of the device, the first isolation layer has straight sidewalls in cross-sectional view.

[0088] In an embodiment, a method includes: sealing an interconnect die with an encapsulant, the interconnect die including a substrate and a substrate through-hole; patterning a groove in the substrate, the groove surrounding the substrate through-hole; forming an isolation layer in the groove; planarizing the isolation layer, the top surface of the isolation layer being substantially coplanar with the top surface of the substrate through-hole and the top surface of the encapsulant; and forming a front side redistribution structure on the isolation layer and the encapsulant, the front side redistribution structure including a first conductive through-hole that physically contacts the substrate through-hole and the isolation layer. In some embodiments of the method, patterning the groove in the substrate includes etching the substrate with a dry etch. In some embodiments of the method, forming the isolation layer includes: forming a mask on the encapsulant; and depositing a material of the isolation layer in an opening through the mask. In some embodiments of the method, the substrate through-hole is one of a plurality of substrate through-holes of the interconnect die, and the groove surrounds each of the substrate through-holes. In some embodiments of the method, the substrate through-hole is one of a plurality of substrate through-holes of the interconnect die, the groove is one of a plurality of grooves patterned in the substrate, and the respective groove surrounds the respective substrate through-hole.

[0089] Some embodiments of the present application provide a semiconductor device, including: an interposer, including: a back-side redistribution structure; an interconnection die, located above the back-side redistribution structure, the interconnection die including a substrate, a substrate through-hole protruding from the substrate, and an isolation layer around the substrate through-hole; a first sealant, located around the interconnection die, the surface of the first sealant being substantially coplanar with the surface of the isolation layer and the surface of the substrate through-hole; and a front-side redistribution structure, located above the first sealant, the front-side redistribution structure including a first conductive through-hole physically contacting the substrate through-hole, the isolation layer separating the first conductive through-hole from the substrate.

[0090] In some embodiments, the semiconductor device further includes a molded via extending through the first encapsulant, a surface of the molded via being substantially coplanar with the surface of the first encapsulant, the surface of the isolation layer, and the surface of the through substrate via.

[0091] In some embodiments, the front side redistribution structure further includes a second conductive via physically contacting the molded via.

[0092] In some embodiments, a width of the second conductive via is smaller than a width of the molded via.

[0093] In some embodiments, a width of the first conductive via is greater than a width of the substrate via.

[0094] In some embodiments, the through substrate via protrudes from a back side of the substrate, the isolation layer is located at the back side of the substrate, and the interconnect die further includes a die bridge located at a front side of the substrate, the die bridge connected to the back side redistribution structure.

[0095] In some embodiments, the semiconductor device further includes: an integrated circuit device attached to the interposer, the interconnect die overlapping the integrated circuit device; and a second encapsulant located around the integrated circuit device.

[0096] In some embodiments, the semiconductor device further includes: a package substrate attached to the interposer; and a second encapsulant located around the package substrate.

[0097] Other embodiments of the present application provide a semiconductor device, comprising: an interconnect die, comprising a substrate, a first substrate through hole protruding from the substrate in a cross-sectional view, and a first isolation layer surrounding the first substrate through hole in a top view; a molded through hole adjacent to the interconnect die; an encapsulant located around the molded through hole and the interconnect die; and a front-side redistribution structure located above the encapsulant, the front-side redistribution structure comprising a first conductive through hole and a second conductive through hole, the first conductive through hole physically contacting the first substrate through hole and the first isolation layer, and in a cross-sectional view, the width of the first conductive through hole is greater than the width of the substrate through hole, the second conductive through hole physically contacting the molded through hole, and in the cross-sectional view, the width of the second conductive through hole is less than the width of the molded through hole.

[0098] In some embodiments, the interconnect die further includes: a second through substrate via protruding from the substrate in the cross-sectional view, and in the top view, the first isolation layer surrounds the second through substrate via.

[0099] In some embodiments, the interconnect die further includes: a second through substrate via protruding from the substrate in the cross-sectional view; and a second isolation layer surrounding the second through substrate via in the top view.

[0100] In some embodiments, the first isolation layer is circular in the top view.

[0101] In some embodiments, the first isolation layer is rectangular in the top view.

[0102] In some embodiments, the first isolation layer has an inclined sidewall in the cross-sectional view.

[0103] In some embodiments, the first isolation layer has straight sidewalls in the cross-sectional view.

[0104] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: sealing an interconnect die with a sealant, the interconnect die comprising a substrate and a substrate through-hole; patterning a groove in the substrate, the groove surrounding the substrate through-hole; forming an isolation layer in the groove; planarizing the isolation layer, the top surface of the isolation layer being substantially coplanar with the top surface of the substrate through-hole and the top surface of the sealant; and forming a front side redistribution structure on the isolation layer and the sealant, the front side redistribution structure comprising a first conductive through-hole physically contacting the substrate through-hole and the isolation layer.

[0105] In some embodiments, patterning the recesses in the substrate includes etching the substrate using a dry etch.

[0106] In some embodiments, forming the isolation layer includes: forming a mask on the sealant; and depositing a material of the isolation layer in an opening through the mask.

[0107] In some embodiments, the through substrate via is one of a plurality of through substrate vias of the interconnect die, and the groove surrounds each of the through substrate vias.

[0108] In some embodiments, the through substrate via is one of a plurality of through substrate vias of the interconnect die, the groove is one of a plurality of grooves patterned in the substrate, and a respective one of the grooves surrounds a respective one of the through substrate vias.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: The intermediary layer includes: Dorsal redistribution structures; an interconnection die located above the backside redistribution structure, the interconnection die comprising a substrate, a through substrate via protruding from the substrate, and an isolation layer around the through substrate via; a first encapsulant disposed around the interconnect die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through substrate via; and A front side redistribution structure is located above the first encapsulant, the front side redistribution structure includes a first conductive via physically contacting the substrate via, and the isolation layer separates the first conductive via from the substrate.

2. The semiconductor device according to claim 1, further comprising: A molded through hole extends through the first encapsulant, a surface of the molded through hole being substantially coplanar with the surface of the first encapsulant, the surface of the isolation layer, and the surface of the substrate through hole.

3. The semiconductor device according to claim 2, wherein: The front side redistribution structure also includes a second conductive via physically contacting the molded via.

4. The semiconductor device according to claim 3, wherein: The second conductive via has a width smaller than a width of the molded via.

5. The semiconductor device according to claim 1, wherein The width of the first conductive via is greater than the width of the substrate via.

6. The semiconductor device according to claim 1, wherein The through substrate via protrudes from a back side of the substrate, the isolation layer is located at the back side of the substrate, and the interconnect die further includes a die bridge located at a front side of the substrate, the die bridge connected to the back side redistribution structure.

7. The semiconductor device according to claim 1, further comprising: an integrated circuit device attached to the interposer, the interconnect die overlapping the integrated circuit device; as well as A second sealant is located around the integrated circuit device.

8. The semiconductor device according to claim 1, further comprising: a package substrate attached to the interposer; as well as The second sealant is located around the packaging substrate.

9. A semiconductor device comprising: An interconnect die comprising a substrate, a first through substrate via protruding from the substrate in a cross-sectional view, and a first isolation layer surrounding the first through substrate via in a top view; molding a through hole adjacent to the interconnect die; an encapsulant disposed around the molded through vias and the interconnect die; and A front-side redistribution structure is located above the sealant, and the front-side redistribution structure includes a first conductive via and a second conductive via, the first conductive via physically contacts the first substrate via and the first isolation layer, and in a cross-sectional view, the width of the first conductive via is greater than the width of the substrate via, and the second conductive via physically contacts the molded via, and in the cross-sectional view, the width of the second conductive via is less than the width of the molded via.

10. A method of forming a semiconductor device, comprising: sealing an interconnect die with an encapsulant, the interconnect die comprising a substrate and a through-substrate via; patterning a groove in the substrate, the groove surrounding the substrate through-hole; forming an isolation layer in the groove; planarizing the isolation layer, a top surface of the isolation layer being substantially coplanar with a top surface of the through substrate via and a top surface of the sealant; and A front side redistribution structure is formed on the isolation layer and the encapsulant, the front side redistribution structure including a first conductive via physically contacting the substrate via and the isolation layer.

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