Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device and a method for manufacturing the semiconductor device, which can prevent bubbles, peeling and condensation of an insulation sealing component and improve insulation reliability. This semiconductor device is provided with: an insulating substrate provided with a plurality of wiring patterns; a semiconductor chip disposed on at least one of the plurality of wiring patterns; a metal wire electrically connected to the semiconductor chip; and a housing in which the insulating substrate is disposed at the bottom. Furthermore, the insulating sealing member covers the semiconductor chip from the upper surface of the insulating substrate with respect to a region surrounded by the insulating substrate and the case, and fills the region to a depth at which at least a portion of the metal wire is exposed.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The semiconductor device has a structure in which an insulating circuit substrate with a power semiconductor element actually mounted is bonded to a heat dissipation base and is electrically connected to an external circuit via metal terminals. In addition, the semiconductor device and the resin case form a closed space, the interior of which is filled with an insulating sealing member.

[0003] As a related art, for example, a semiconductor power module is proposed in which a component having an opening only on the lower surface is formed in a housing of a support substrate, and the lower surface of the component is in contact with a primary sealing resin to have a sealed space inside (Patent Document 1).

[0004] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Publication No. 2001-210758 Summary of the invention Technical issues An object of the present invention is to prevent the occurrence of bubbles, peeling and condensation of an insulating sealing member and to improve insulation reliability.

[0005] Technical Solution In order to solve the above-mentioned problem, a semiconductor device is provided. The semiconductor device comprises: an insulating substrate having a plurality of wiring patterns; a semiconductor chip arranged on at least one of the plurality of wiring patterns; a metal wiring electrically connected to the semiconductor chip; a housing having the insulating substrate arranged at the bottom; and an insulating sealing member covering the semiconductor chip from the upper surface of the insulating substrate with respect to the area surrounded by the insulating substrate and the housing, and being filled to a thickness such that at least a portion of the metal wiring is exposed.

[0006] In order to solve the above-mentioned problem, a method for manufacturing a semiconductor device is provided. In the method for manufacturing a semiconductor device, for an area surrounded by an insulating substrate having a plurality of wiring patterns and a housing that arranges the insulating substrate at the bottom, a semiconductor chip arranged on at least one wiring pattern among the plurality of wiring patterns is covered from the upper surface of the insulating substrate and an insulating sealing component is filled to a thickness that exposes at least a portion of a metal wiring electrically connected to the semiconductor chip.

[0007] In addition, in order to solve the above-mentioned problem, a semiconductor device is provided. The semiconductor device comprises: an insulating substrate having a plurality of wiring patterns; a semiconductor chip arranged on at least one of the plurality of wiring patterns; a metal wiring electrically connected to the semiconductor chip; a housing having the insulating substrate arranged at the bottom; an insulating sealing component covering the semiconductor chip from the upper surface of the insulating substrate with respect to the area surrounded by the insulating substrate and the housing; and an insulating component covering a portion exposed from the insulating sealing component where insulation should be ensured, wherein the rated current is 100 A or more and the rated voltage is 1700 V or more, and the thickness of the insulating sealing component from the upper surface of the insulating substrate is 3 mm or less.

[0008] Technical Effects According to one aspect, it is possible to prevent the occurrence of bubbles, peeling, and condensation of the insulating sealing member, thereby improving insulation reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a diagram for explaining an example of the semiconductor device of the present invention.

[0010] Figure 2 : is a graph showing the relationship between the depth of the insulating sealing member and the generation of bubbles.

[0011] Figure 3 A diagram showing an example of the structure of a semiconductor device.

[0012] Figure 4 A diagram showing an example of a method for manufacturing a semiconductor device.

[0013] Figure 5 This is a diagram showing an example of the covering operation of the insulating member.

[0014] Figure 6 A diagram showing an example of a method for manufacturing a semiconductor device.

[0015] Figure 7 A diagram showing an example of a method for manufacturing a semiconductor device.

[0016] Figure 8 A diagram showing an example of a method for manufacturing a semiconductor device.

[0017] Fig. 9 This is a diagram showing an example of an equivalent circuit of a semiconductor device.

[0018] Fig.10 It is a top view of MOSFET.

[0019] Fig.11This is a diagram showing an example in which the space between the terminal led out to the outside and the lead wire is covered with an insulating member.

[0020] Fig.12 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.12 (a) is a diagram showing the filling of the insulating sealing member and the covering state of the terminal led out to the outside, Fig.12 (b) is a diagram showing the filling of the insulating sealing member and the covering state of the conductive wire.

[0021] Fig.13 This is a diagram showing an example in which the space between the terminal led out to the outside and the lead wire is covered with an insulating member.

[0022] Fig.14 yes Fig.13 A cross-sectional view of the portion X1-X2 shown.

[0023] Fig.15 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.15 (a) is a diagram showing the filling of the insulating sealing member and the covering state of the terminal led out to the outside, Fig.15 (b) is a diagram showing the filling of the insulating sealing member and the covering state of the conductive wire.

[0024] Fig.16 This is a diagram showing an example in which the space between the first terminal and the second terminal is covered by an insulating member.

[0025] Fig.17 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.17 (a) is a diagram showing a filling state of the insulating sealing member and a covering state of the second terminal, Fig.17 (b) is a diagram showing a filling state of the insulating sealing member and a covering state of the first terminal.

[0026] Fig.18 This is a diagram showing an example in which the control electrode wiring and the back electrode wiring are covered with an insulating member.

[0027] Fig.19 This is a diagram showing an example in which the front main electrode wiring and the back main electrode wiring are covered by an insulating member.

[0028] Fig. 20 This is a diagram showing an example of the structure of a semiconductor device including a vertical semiconductor chip.

[0029] Fig.21 This is a diagram showing an example of the structure of a semiconductor device including a vertical semiconductor chip.

[0030] Explanation of symbols Semiconductor Chip 10Semiconductor devices 11 cooling body 11a thermal grease 11b Metal base plate 12Insulation substrate 12a Ceramic 12b, 12c-1, 12c-2 pattern 13a, 13b solder 14-1, 14-2, 14-3 wires 15 Insulation sealing parts 16 Shell 16a, 16b external terminals h1 Filling height of insulating sealing component (invention) h2 Filling height of insulating sealing parts (conventional) DETAILED DESCRIPTION Hereinafter, the present embodiment will be described with reference to the drawings.

[0031] Figure 1 This is a diagram for explaining an example of the semiconductor device of the present invention. Figure 1 1 shows a cross-sectional view of a semiconductor device 10 . The semiconductor device 10 includes a semiconductor chip 1 mounted on a cooling body 11 and an insulating substrate (insulating circuit substrate) 12 .

[0032] The insulating substrate 12 includes a ceramic 12a, and patterns (foils) 12b, 12c-1, and 12c-2 (hereinafter, the patterns 12c-1 and 12c-2 are collectively referred to as pattern 12c). In addition, when the patterns 12b and 12c are, for example, copper patterns, a DCB (Direct Copper Bonding) substrate can be used in which the patterns 12b and 12c are directly bonded to the ceramic 12a.

[0033] One surface of a metal base plate (heat dissipation base) 11b is mounted on the upper surface of the cooling body 11 in a manner opposite to the upper surface of the cooling body 11 via a heat dissipation grease (thermal grease) 11a, and an insulating substrate 12 is mounted on the other surface of the metal base plate 11b. Then, the pattern 12b of the insulating substrate 12 is bonded to the metal base plate 11b via a solder 13a. On the pattern 12c-1 of the insulating substrate 12, for example, a semiconductor chip 1 formed of silicon is bonded via a solder 13b.

[0034] On the other hand, metal wires (hereinafter referred to as wires) 14-1, 14-2, and 14-3 as metal wiring are, for example, bonding wires made of aluminum with a wire diameter of 300 μm to 500 μm. The wire 14-1 connects the pattern 12c-1 to the external terminal 16a provided in the housing 16. The material of the wire may be copper, silver, gold, or the like.

[0035] The wire 14-2 connects the electrode of the semiconductor chip 1 to the pattern 12c-2 that becomes the lead electrode of the insulating substrate 12. It should be noted that the semiconductor chip 1 may be formed with an electrode covered with an Al-Si alloy film (Al-Si electrode), for example.

[0036] The wire 14-3 joins the pattern 12c-2 to the external terminal 16b provided in the housing 16. As a joining based on the wires 14-1, 14-2, and 14-3, wire bonding based on ultrasonic waves and loads is performed. It should be noted that, as a metal wiring connected to the semiconductor chip 1, in addition to the wire, a lead frame and a conductive pin composed of a metal plate can also be used. They can be composed of a metal material such as copper and can be connected to the semiconductor chip 1 via solder or a sintered material.

[0037] The insulating substrate 12 bonded with the semiconductor chip 1 is housed in a housing 16, and the region surrounded by the housing 16 and the metal base plate 11b is filled and sealed with an insulating sealing member 15. The housing 16 and the metal base plate 11b are fixed by an adhesive or the like.

[0038] Here, the patterns 12b and 12c of the insulating substrate 12 are made of a material having excellent conductivity. Such a material is made of, for example, copper, aluminum, or an alloy containing at least one of them. The thickness of the patterns 12b and 12c is preferably 0.10 mm or more and 2.00 mm or less, and more preferably 0.20 mm or more and 1.00 mm or less.

[0039] Furthermore, in the pattern 12 c , wiring members and electronic components such as bonding wires, lead frames, and connection terminals can be appropriately arranged as necessary in addition to the semiconductor chip 1 .

[0040] Such patterns 12c can also be plated with a material having excellent corrosion resistance. Such materials include, for example, aluminum, nickel, titanium, chromium, molybdenum, tantalum, niobium, tungsten, vanadium, bismuth, zirconium, hafnium, gold, silver, platinum, palladium, or an alloy containing at least one of them. It should be noted that the number, arrangement position, and shape of the patterns 12c can be selected by appropriate design.

[0041] On the other hand, the metal base plate 11b is made of a metal having excellent thermal conductivity. The metal is, for example, aluminum, iron, silver, copper, or an alloy containing at least one of them. Examples of such alloys include metal composite materials such as aluminum-silicon nitride (Al-SiC) or magnesium-silicon nitride (Mg-SiC).

[0042] In addition, in order to improve corrosion resistance, for example, nickel or other materials may be formed on the surface of the metal base plate 11b by plating. Specifically, in addition to nickel, there are nickel-phosphorus alloys, nickel-boron alloys, etc. The thickness of the plating film is preferably 1 μm or more, and more preferably 5 μm or more. In addition, the cooling body 11 is a radiator with one or more fins or a cooling device based on water cooling.

[0043] On the other hand, the semiconductor chip 1 is a power device made of silicon, silicon carbide or gallium nitride. The semiconductor chip 1 includes a switching element. The switching element is a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor) or the like.

[0044] Such a semiconductor chip 1 includes, for example, a drain electrode (a positive electrode, a collector electrode in an IGBT) and a source electrode (a negative electrode, an emitter electrode in an IGBT) as main electrodes, and a gate electrode as a control electrode.

[0045] The semiconductor chip 1 includes a diode element. The diode element is, for example, a SBD (Schottky Barrier Diode), a PiN (P-intrinsic-N) diode, or a FWD (Free Wheeling Diode).

[0046] The thickness of the semiconductor chip 1 is, for example, 80 μm or more and 500 μm or less, and the average thickness is about 200 μm. It should be noted that other electronic components can be arranged in the pattern 12 c as needed. The electronic components are, for example, capacitors, resistors, thermistors, current sensors, and control ICs (Integrated Circuits).

[0047] On the other hand, the insulating sealing member 15 covers the entire or a portion of the semiconductor chip 1 from the upper surface of the insulating substrate 12 in the area surrounded by the insulating substrate 12 and the housing 16 and fills the area to a depth that exposes at least a portion of the wires 14-1, 14-2, and 14-3.

[0048] Conventionally, for example, the filling height (filling thickness) h2 of the insulating sealing member 15 is set from the upper surface of the insulating substrate 12 (at Figure 1 In the example of the present invention, the filling height h1 of the insulating sealing member 15 is approximately 15 mm from the upper surface of the patterns 12c-1 and 12c-2. In contrast, in the semiconductor device 10 of the present invention, the filling height h1 of the insulating sealing member 15 is 3 mm or less from the upper surface of the insulating substrate 12. It should be noted that the insulating sealing member 15 uses a gel, for example, a silicone gel or a resin with good followability can be used as the gel.

[0049] Thus, the semiconductor device 10 includes an insulating sealing member 15, which covers the semiconductor chip 1 from the upper surface of the insulating substrate 12 in the area surrounded by the insulating substrate 12 and the housing 16, and fills the area to a depth that exposes at least a portion of the wires 14-1 and 14-2. The junction between the semiconductor chip 1 and the wire 14-2 is also covered by the insulating sealing member 15.

[0050] This structure can prevent the insulating sealing member from bubbling, peeling, and condensation, thereby improving insulation reliability in the semiconductor device 10. The semiconductor device 10 to which the above structure is applied is effective, for example, for semiconductor devices with small capacitance and general rated voltage.

[0051] On the other hand, for semiconductor devices with large capacity and high rated voltage, even if the filling height of the insulating sealing component is set to less than 3mm from the upper surface of the insulating substrate, it is required to ensure insulation between terminals, etc. Therefore, in semiconductor devices with large capacity and high rated voltage, not only the filling height of the insulating sealing component is reduced, but also the insulation is ensured by covering the part of the terminal and wire exposed from the insulating sealing component with the insulating component. Figure 3 Hereinafter, a semiconductor device having a large capacity and a high rated voltage and having a structure in which a part of a terminal, a wire, etc. is covered with such an insulating member will be described.

[0052] <Insulation sealing parts> Silicone gel or resin is used as the insulating sealing member filled in the semiconductor device, and silicone gel with good followability is most commonly used. In addition, in recent years, resin sealing structures are used in applications requiring heat resistance and heat cycle resistance (mainly automotive applications).

[0053] Insulation sealing components are components that provide mechanical protection (protection from foreign matter, etc.) of the internal circuit of a semiconductor device and insulation between electrodes (between circuits). Insulation reliability is ensured by covering and filling the circuit surface including the semiconductor element surface, lead surface, and terminal surface, as well as between electrodes (between circuits) with insulating materials.

[0054] For example, if conductive foreign matter is attached between exposed circuits, there is a possibility of short circuit and failure. In addition, even if the foreign matter has low conductivity, there is a possibility of short circuit failure due to tracking. Therefore, by covering and filling the circuit surface including the semiconductor element surface, wire surface, and terminal surface with an insulating sealing component, circuit protection can be performed and failure can be prevented. In addition, by covering and filling the electrodes with an insulating sealing component, the insulation distance can be significantly shortened compared to air insulation, and the miniaturization of semiconductor modules based on high-density mounting can be achieved.

[0055] <Problems caused by bubbles in insulating sealing parts> Silicone gel is soft and has high conformability, so it is difficult to cause peeling, but it has high moisture absorption (moisture permeability) and is prone to bubbles and / or condensation. Although it can be suppressed by hardening it, the conformability will decrease and it will become easy to peel.

[0056] In addition, although resin does not generate bubbles during use due to its high elasticity (due to its hardness), it is more likely to cause peeling than gel. Thus, if bubbles, peeling, and condensation occur in the insulating material, the insulation reliability will be reduced.

[0057] Here, since the dielectric constant of insulating sealing parts such as silicone gel and resin is higher than that of air, if gaps such as bubbles inside the insulating sealing part or peeling of the insulating sealing part are generated between the electrodes, the electric field strength increases in the gap and the insulation reliability decreases. For example, if gaps are generated, the discharge start voltage is reduced to about 1 / 3. In particular, electric field concentration is prone to occur on the surface of the bonding wire, so the discharge start voltage is reduced to about 1 / 6 relative to other areas. In addition, the thinner the bonding wire, the lower the insulation performance.

[0058] If the maximum rated voltage of a semiconductor chip is about 1.7 kV or less, even if gaps occur between electrodes, the insulation distance required for the bonding wire is relatively small, so the design restrictions (miniaturization) are low. However, if the maximum rated voltage of a semiconductor chip becomes a high withstand voltage of 3.3 kV or more, the insulation distance required for a bonding wire with a diameter of about 300 μm becomes larger than the insulation distance required for a bonding wire with a diameter of about 125 μm when the maximum rated voltage is about 1.7 kV or less, which becomes an obstacle to miniaturization.

[0059] The present invention has been made in view of the above problems, and aims to prevent the generation of bubbles, peeling and condensation of the insulating sealing member, thereby improving the insulation reliability.

[0060] <Depth of insulation seal> If the silicone gel is heated after absorbing moisture, bubbles will be generated inside the silicone gel (especially at the interface between the silicone gel and the parts). This is because the water that cannot be completely dissolved by heating increases the internal pressure of the bubble nucleus (microscopic space, defect) and causes foaming.

[0061] This phenomenon conflicts with the speed at which water is released from the upper surface of the gel when the temperature is raised. Therefore, even if the hygroscopic gel is heated, if the water concentration in the gel decreases before the internal pressure of the bubble cores rises sufficiently, no bubbles will be generated.

[0062] On the other hand, if the silicone gel that has absorbed moisture is cooled, the hygroscopic components will condense inside the gel. This is because the amount of water vapor (gas) that can exist in the gaps in the gel decreases, so this phenomenon also conflicts with the speed at which moisture escapes from the upper surface of the gel. If the moisture concentration in the gel decreases before the relative humidity in the gaps in the gel reaches 100%, condensation will not occur.

[0063] Since the water transport in the gel follows diffusion transport, the gel dehumidification speed is inversely proportional to the square of the thickness (when the thickness is reduced from 15mm to 3mm, the gel dehumidification speed increases 25 times). Therefore, by reducing the depth of the silicone gel as an insulating sealing member to a predetermined depth, the dehumidification speed can be increased, and the generation of bubbles and condensation can be suppressed.

[0064] Figure 2 Graph showing the relationship between the depth of the insulating sealing member and the generation of bubbles. The vertical axis is the density of bubble generation (number / cm 2 ), the horizontal axis is the depth of the insulating sealing part (mm). The graph shows the number of bubbles generated by placing the insulating sealing part on a 150°C hot plate after absorbing moisture at 85°C, 85%, and 24 hours. Figure 2 As shown, there is a positive correlation with the depth of the insulating sealing member, and the generation of bubbles is not observed when the insulating sealing member is at a depth of 3 mm.

[0065] Therefore, in the present invention, by setting the depth (thickness) of the insulating sealing member to 3 mm or less, the drying speed of the insulating sealing member is increased, and even when the hygroscopic gel is heated or cooled, the generation of bubbles and condensation is suppressed.

[0066] <Large-capacity, high-rated-voltage semiconductor devices> Next, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail. Figure 31 is a diagram showing an example of the structure of a semiconductor device. A schematic diagram showing a cross section for explaining the features of the present invention. The semiconductor device 20 is, for example, a large-capacity, high-rated-voltage semiconductor device having a rated current of 100 A or more and a rated voltage of 1700 V or more.

[0067] The semiconductor device 20 has an insulating substrate 22 mounted on one surface of a metal base plate 21, and patterns 22a-1, 22a-2, and 22a-3 are laid on the upper surface of the insulating substrate 22. In addition, the semiconductor device 20 has terminals 30a and 30b that are led out to the outside, the terminal 30a is connected to the pattern 22a-1, and the terminal 30b is connected to the pattern 22a-2. In addition, the pattern 22a-2 and the pattern 22a-3 are electrically connected via a wire 24.

[0068] Here, for the area surrounded by the insulating substrate 22 and the housing (not shown), the insulating sealing member 25 is filled to a height of 3 mm or less from the upper surface of the insulating substrate 22. In addition, the portions of the terminals 30a and 30b exposed from the insulating sealing member 25 and the portions of the lead wire 24 exposed from the insulating sealing member 25 are covered by the insulating member 26.

[0069] For example, an adhesive or a resin is suitable for the insulating member 26. Examples of the resin include PPS (polyphenylene sulfide), PBT (polybutylene terephthalate), polyamide, LCP (liquid crystal polymer), POM (polyoxymethylene), polyimide, polyamideimide, polyester, epoxy resin, fluororesin, acrylic resin, silicone resin, polyolefin, and polyetherimide.

[0070] Thus, for a semiconductor device 20 with large capacity and high rated voltage, the filling height of the insulating sealing member is set to be 3 mm or less from the upper surface of the insulating substrate, and the terminals and metal wirings exposed from the insulating sealing member are partially covered by the insulating member.

[0071] Thus, the generation of bubbles in the insulating sealing member can be suppressed, and the insulation between the terminals and the like can be ensured. Figure 3 Although the example shows a state in which all the portions exposed from the insulating sealing member are covered by the insulating member, the insulating member covers only the portions that need to be exposed in terms of insulation.

[0072] <Method for manufacturing semiconductor device> Next, use Figures 4 to 8A method for manufacturing a semiconductor device is described. In the following description, the insulating sealing component is sometimes referred to as gel. It should be noted that when the gel is filled, the gel is injected to fill the area where the insulating space distance is insufficient at the part where a high voltage of the rated voltage is applied. Furthermore, the part covered by the insulating component is set as a part exposed from the gel and required to ensure insulation.

[0073] Figure 4 A diagram showing an example of a method for manufacturing a semiconductor device.

[0074] [Step P1] The semiconductor chip and the terminals are connected to the wiring pattern on the insulating substrate.

[0075] [Step P2] The gel is injected into a region surrounded by the insulating substrate and the case having the insulating substrate disposed at the bottom so as to be filled with the gel from the upper surface of the insulating substrate to a thickness of 3 mm or less.

[0076] [Step P3] After the gel is filled in the region, the portions where insulation is to be ensured, such as terminals and / or wires, exposed from the gel are covered with an insulating member.

[0077] [Step P4] The gel is cured by heat treatment.

[0078] Figure 5 1 is a diagram showing an example of the covering operation of the insulating component. When the insulating component is covered on a predetermined portion, the distributor ds can be used. For example, for a portion where a high voltage of the rated voltage is applied, the distributor ds can be used to cover the insulating component 26 in an area where the insulating space distance is insufficient.

[0079] Figure 6 A diagram showing an example of a method for manufacturing a semiconductor device.

[0080] [Step P11] The semiconductor chip and the terminals are connected to the wiring pattern on the insulating substrate.

[0081] [Step P12] With respect to the region surrounded by the insulating substrate and the case having the insulating substrate disposed at the bottom, the exposed portion when the gel is injected from the upper surface of the insulating substrate to a thickness of 3 mm or less is covered in advance with an insulating member.

[0082] [Step P13] The gel is injected into the region so as to fill the region from the upper surface of the insulating substrate to a thickness of 3 mm or less.

[0083] [Step P14] The gel is cured by heat treatment.

[0084] Figure 7 A diagram showing an example of a method for manufacturing a semiconductor device.

[0085] [Step P21] The semiconductor chip and the terminals are connected to the wiring pattern on the insulating substrate.

[0086] [Step P22] The gel is injected from the upper surface of the insulating substrate to a position higher than a thickness of 3 mm or less into a region surrounded by the insulating substrate and the case having the insulating substrate disposed at the bottom.

[0087] [Step P23] The gel is sucked out until the thickness is 3 mm or less from the upper surface of the insulating substrate. After the gel is sucked out, the exposed terminals and / or wires, which are filled with the gel to a thickness of 3 mm or less from the upper surface of the insulating substrate, are covered with the gel.

[0088] [Step P24] The gel is cured by heat treatment.

[0089] So, in Figure 7 In the manufacturing method, after the insulating sealing component is injected to a position higher than 3 mm in thickness, the insulating sealing component is sucked until the thickness becomes less than 3 mm. Thus, the exposed terminals and / or wires, etc., where insulation is to be ensured, which are filled with gel to a thickness of less than 3 mm from the upper surface of the insulating substrate, can be covered with gel without using an insulating component.

[0090] Here, a suction machine (pump) is used for suction of the gel. As the suction machine, either a rotary pump or a positive displacement pump can be used, but since suction of the gel requires high viscosity, a small flow rate, and quantitative (measurement), a positive displacement type is preferred.

[0091] In addition, the amount of gel sucked is controlled by a flow meter. In the case of a rotary pump, the discharge amount is controlled by combining a flow meter to control the depth level of the gel in the semiconductor device. In addition, in a volumetric pump, since the discharge amount can be quantified, its characteristics are used to control the depth level of the gel in the semiconductor device.

[0092] Figure 8 A diagram showing an example of a method for manufacturing a semiconductor device.

[0093] [Step P31] The semiconductor chip and the terminals are connected to the wiring pattern on the insulating substrate.

[0094] [Step P32] With respect to the region surrounded by the insulating substrate and the case having the insulating substrate disposed at the bottom, the gel is discharged toward a portion that would be exposed if the gel was injected from the upper surface of the insulating substrate to a thickness of 3 mm or less.

[0095] [Step P33] When the thickness of the gel reaches 3 mm or less, the discharge of the gel is stopped and the exposed portion is covered with the gel.

[0096] [Step P34] The gel is cured by heat treatment.

[0097] So, in Figure 8 In the manufacturing method, the gel is discharged toward the exposed part when the gel is filled to a thickness of 3 mm or less until it reaches 3 mm or less, and the discharge is stopped when the gel reaches a thickness of 3 mm or less, thereby covering the exposed part with the gel.

[0098] Thus, the exposed portions of the gel filled to a thickness of 3 mm or less from the upper surface of the insulating substrate, such as terminals and / or wires, where insulation must be ensured, can be covered with the gel without using an insulating member.

[0099] Next, an example of a portion covered with an insulating member will be described. It should be noted that in the following description, the connection between the terminal and the pattern, or the connection between the wire and the pattern is performed by, for example, ultrasonic wave or laser.

[0100] <Equivalent Circuit of Semiconductor Device> Fig. 9 1 is a diagram showing an example of an equivalent circuit of a semiconductor device. The equivalent circuit of the semiconductor device 10 shows a full-bridge inverter circuit using MOSFETs as a semiconductor chip.

[0101] Terminals 41 a , 41 b , and 41 c that are led out to the outside as P terminals are electrically connected to drain electrodes of the upper arm semiconductor chips 31 a , 31 b , and 31 c via wirings 51 a , 51 b , and 51 c , respectively.

[0102] The U terminal 47a, V terminal 47b and W terminal 47c, which are terminals led out to the outside, are electrically connected to connection points of wirings 52a, 52b, 52c between source electrodes of the upper arm semiconductor chips 31a, 31b, 31c and drain electrodes of the lower arm semiconductor chips 32a, 32b, 32c, respectively.

[0103] Furthermore, terminals 44a, 44b, and 44c that are led out to the outside as N terminals are electrically connected to source electrodes of the lower arm semiconductor chips 32a, 32b, and 32c via wirings 53a, 53b, and 53c, respectively.

[0104] Furthermore, the auxiliary terminals 49a, 49b, 49c led out to the outside are electrically connected to the source electrodes of the lower arm semiconductor chips 32a, 32b, 32c and the terminals 44a, 44b, 44c via the wirings 53a, 53b, 53c, respectively.

[0105] The control electrodes G1, G3, G5 of the upper arm semiconductor chips 31a, 31b, 31c are electrically connected to the control terminals Ga, Gc, Ge output to the outside via the wirings 54a, 54b, 54c, and the control electrodes G2, G4, G6 of the lower arm semiconductor chips 32a, 32b, 32c are electrically connected to the control terminals Gb, Gd, Gf output to the outside via the wirings 55a, 55b, 55c.

[0106] Hereinafter, an example in which only one phase (U phase) is arranged in the semiconductor device 10 of this example will be described. Of course, only two phases or all three phases may be arranged in the semiconductor device 10 .

[0107] Fig.10 It is a top view of MOSFET. Fig.10 Yes Fig. 9 The MOSFET of the circuit shown is viewed from above in the figure below, and the front side is shown. Fig.10 The MOSFET shown has a semiconductor substrate 35 exposed at the periphery, a protection film 36 formed inside the semiconductor substrate 35, a source electrode 37, and a control electrode 38 disposed apart from the source electrode 37. A drain electrode is formed on the back surface (not shown).

[0108] <Insulation between the terminal electrically connected to the front electrode and the metal wiring> Fig.11 This is a diagram showing an example in which the space between the terminal led out to the outside and the lead wire is covered with an insulating member. Fig.12 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.12 (a) shows the filling of the insulating sealing member and the covering state of the terminal led out to the outside, Fig.12 (b) shows the filling of the insulating sealing member and the covering state of the wire.

[0109] exist Fig.11 In the embodiment, patterns 4a-1, 4a-2, and 4a-3 are laid on an insulating substrate 4a, and a vertical semiconductor chip 9a is bonded to the pattern 4a-2 by solder bonding or the like.

[0110] The front main electrode (source electrode) of the semiconductor chip 9a is electrically connected to the pattern 4a-1 through a plurality of wires w2, and the terminal 5a led out to the outside is connected to the pattern 4a-1. The wires w1 and w2 are metal wires electrically connected to the semiconductor chip.

[0111] The back main electrode (drain electrode) of the semiconductor chip 9a is connected to the pattern 4a-2. In addition, a plurality of wires w1 connect the pattern 4a-2 and the pattern 4a-3. It should be noted that the terminal 5a leading to the outside is close to the wire w1 and is considered to be a location where insulation should be ensured.

[0112] exist Fig.11 in Fig. 9 In the correspondence relationship between the U phases, for example, the terminal 5a corresponds to the terminal 44a, the semiconductor chip 9a corresponds to the lower arm semiconductor chip 32a, and the wire w1 corresponds to the wiring 52a between the source electrode of the upper arm semiconductor chip 31a and the drain electrode of the lower arm semiconductor chip 32a.

[0113] exist Fig.12 In (a), the insulating sealing member 7a is filled from the upper surface of the insulating substrate 4a (the upper surface of the pattern 4a-1) to a thickness of 3 mm or less. In addition, the terminal 5a is covered by the insulating member 6a-1 at the portion exposed from the insulating sealing member 7a as a portion where insulation with the wire w1 needs to be ensured.

[0114] exist Fig.12 In (b), the insulating sealing member 7a is filled from the upper surface of the insulating substrate 4a (the upper surface of the patterns 4a-2 and 4a-3) to a thickness of 3 mm or less. In addition, the portion where the wire w1 is exposed from the insulating sealing member 7a is considered to be a portion where insulation with the terminal 5a needs to be ensured, and is therefore covered by the insulating member 6a-2.

[0115] It should be noted that in the above description, both the terminal 5a and the wire w1 are covered by the insulating member, but it is also possible to have a structure where only one of them is covered by the insulating member. In addition, when there is a portion where the wire w2 is exposed from the insulating sealing member 7a, the portion may be covered with the insulating member. In addition, a lead frame may be used instead of the wires w1 and w2.

[0116] <Insulation between the terminal connected to the back electrode and the lead wire that leads to the outside> Fig.13 1 is a diagram showing an example in which the space between the terminal and the lead wire that is led out to the outside is covered by an insulating member. Fig.14 yes Fig.13 The cross-sectional view of the portion X1-X2 is shown. Patterns 4b-1, 4b-2, and 4b-3 are laid on the insulating substrate 4b, and the vertical semiconductor chip 9b1 is joined to the pattern 4b-3 by soldering or the like, and the vertical semiconductor chip 9b2 is joined to the pattern 4b-2 by soldering or the like.

[0117] The front main electrode of the semiconductor chip 9b1 is connected to the pattern 4b-2 through a plurality of wires w3. The front main electrode of the semiconductor chip 9b2 is connected to the pattern 4b-1 through a plurality of wires w3a. The wires w3 and w3a are metal wires electrically connected to the semiconductor chip.

[0118] Terminal 5b1 is connected to pattern 4b-1. Terminal 5b2, which is led out to the outside, is connected to pattern 4b-3 and connected to the main electrode on the back side of semiconductor chip 9b1. Terminals 5b1 and 5b2 are integrated while being insulated by molded resin md. It should be noted that terminal 5b2 is close to wire w3 and is considered to be a location where insulation should be ensured.

[0119] exist Fig.13 in Fig. 9 In the corresponding relationship of the U phase, for example, the terminal 5b2 corresponds to the terminal 41a, the semiconductor chip 9b1 corresponds to the upper arm semiconductor chip 31a, the wire w3 and the pattern 4b-2 correspond to the wiring 52a between the source electrode of the upper arm semiconductor chip 31a and the drain electrode of the lower arm semiconductor chip 32a. In addition, the semiconductor chip 9b2 corresponds to the lower arm semiconductor chip 32a, and the terminal 5b1 corresponds to the terminal 44a.

[0120] Fig.15 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.15 (a) is a diagram showing the filling of the insulating sealing member and the covering state of the terminal led out to the outside, Fig.15 (b) is a diagram showing the filling of the insulating sealing member and the covering state of the conductive wire.

[0121] exist Fig.15 In (a), the insulating sealing member 7b is filled from the upper surface of the insulating substrate 4b (the upper surface of the pattern 4b-3) to a thickness of 3 mm or less. In addition, the terminal 5b2 is covered by the insulating member 6b-1 at the portion exposed from the insulating sealing member 7b as a portion where insulation with the wire w3 needs to be ensured.

[0122] exist Fig.15 In (b), the insulating sealing member 7b is filled from the upper surface of the insulating substrate 4b (the upper surface of the patterns 4b-2 and 4b-3) to a thickness of approximately 3 mm or less. In addition, the portion where the wire w3 is exposed from the insulating sealing member 7b is considered to be a portion where insulation with the terminal 5b2 needs to be ensured, and is therefore covered by the insulating member 6b-2.

[0123] It should be noted that in the above description, both the terminal 5b2 and the wire w3 are covered by the insulating member, but it is also possible to have a structure where only one of them is covered by the insulating member. In addition, when there is a portion where the wire w3a is exposed from the insulating sealing member 7b, the portion may be covered with the insulating member. In addition, a lead frame may be used instead of the wires w3 and w3a.

[0124] <Insulation between the first terminal and the second terminal> Fig.16This is a diagram showing an example in which the space between the first terminal and the second terminal is covered by an insulating member. Fig.17 is a diagram showing an example of filling of an insulating sealing member and covering with an insulating member, Fig.17 (a) shows the filling of the insulating sealing member and the covering state of the second terminal, Fig.17 (b) shows the filling of the insulating sealing member and the covering state of the first terminal.

[0125] exist Fig.16 In the embodiment, patterns 4c-1, 4c-2, and 4c-3 are laid on an insulating substrate 4c, and a vertical semiconductor chip 9c is bonded to the pattern 4c-1 by solder bonding or the like.

[0126] The front main electrode of the semiconductor chip 9c is electrically connected to the pattern 4c-2 via a plurality of wires w4. The wires w4 and w5 are metal wires electrically connected to the semiconductor chip.

[0127] The first terminal 5c1 led out to the outside is connected to the pattern 4c-3 and electrically connected to the front main electrode of the semiconductor chip 9c. In addition, the second terminal 5c2 led out to the outside is connected to the pattern 4c-1 and electrically connected to the back main electrode of the semiconductor chip 9c. It should be noted that the first terminal 5c1 and the second terminal 5c2 are close to each other and are considered to be the parts where insulation should be ensured.

[0128] exist Fig.16 in Fig. 9 In the corresponding relationship of the U phase, for example, the second terminal 5c2 corresponds to the terminal 41a, the semiconductor chip 9c corresponds to the upper arm semiconductor chip 31a, the wire w4, the pattern 4c-2, the wire w5 and the pattern 4c-3 correspond to the wiring 52a connected to the source electrode of the upper arm semiconductor chip 31a. The first terminal 5c1 corresponds to the terminal 47a.

[0129] exist Fig.17 In (a), the insulating sealing member 7c is filled from the upper surface of the insulating substrate 4c (the upper surface of the pattern 4c-3) to a thickness of 3 mm or less. In addition, the first terminal 5c1 is covered by the insulating member 6c-1 at the portion exposed from the insulating sealing member 7c as a portion where insulation with the second terminal 5c2 needs to be ensured.

[0130] exist Fig.17 In (b), the insulating sealing member 7c is filled from the upper surface of the insulating substrate 4c (the upper surface of the pattern 4c-1) to a thickness of 3 mm or less. In addition, the second terminal 5c2 is covered by the insulating member 6c-2 at the portion exposed from the insulating sealing member 7c as a portion where insulation with the first terminal 5c1 needs to be ensured.

[0131] It should be noted that, in the above description, both the first terminal 5c1 and the second terminal 5c2 are covered by the insulating member, but it is also possible to have a structure in which only one of them is covered by the insulating member. In addition, in the case where there is a portion where the wires w4 and w5 are exposed from the insulating sealing member 7c, the portion may be covered with the insulating member. In addition, a lead frame may be used instead of the wires w4 and w5.

[0132] <Insulation between control electrode wiring and back electrode wiring> Fig.18 The figure shows an example where the control electrode wiring and the back electrode wiring are covered by an insulating member. Patterns 4d-1, 4d-2, 4d-3, and 4d-4 are laid on the insulating substrate 4d, and the vertical semiconductor chip 9d is joined to the pattern 4d-1 by soldering or the like.

[0133] The control electrode (gate electrode) G1 of the semiconductor chip 9d is electrically connected to the pattern 4d-2 through the wire w63, and the pattern 4d-2 is electrically connected to the pattern 4d-3 through multiple wires w61. The pattern 4d-4 is electrically connected to the pattern 4d-1 through multiple wires w62. The wires w61, w62, and w63 are metal wires electrically connected to the semiconductor chip.

[0134] exist Fig.18 in Fig. 9 In the correspondence relationship of the U phase, for example, the semiconductor chip 9d corresponds to the upper arm semiconductor chip 31a, the wire w61 corresponds to the wiring 54a between the control electrode G1 and the control terminal Ga of the upper arm semiconductor chip 31a, and the wire w62 corresponds to the wiring 51a between the upper arm semiconductor chip 31a and the terminal 41a.

[0135] The wire w61 and the wire w62 are close to each other and are considered to have a portion exposed from the insulating sealing member. In this case, the wire w61 is considered to be a portion where insulation with the wire w62 needs to be ensured, and is covered by the insulating member 6d-1 at the portion exposed from the insulating sealing member. In addition, the wire w62 is considered to be a portion where insulation with the wire w61 needs to be ensured at the portion exposed from the insulating sealing member, and is covered by the insulating member 6d-2.

[0136] It should be noted that in the above description, both the wire w61 corresponding to the control electrode wiring and the wire w62 corresponding to the back electrode wiring are covered by the insulating member, but it is also possible to have a structure in which only one of them is covered by the insulating member. In addition, a lead frame can be used instead of the wires w61 and w62.

[0137] <Insulation between front main electrode wiring and back electrode wiring> Fig.19The figure shows an example where the front main electrode wiring and the back electrode wiring are covered by an insulating member. Patterns 4e-1, 4e-2, and 4e-3 are laid on an insulating substrate 4e, and a vertical semiconductor chip 9e is bonded to the pattern 4e-1 by soldering or the like.

[0138] The front main electrode of the semiconductor chip 9e is connected to the pattern 4e-3 through a plurality of wires w71. The pattern 4e-1 is connected to the back main electrode of the semiconductor chip 9e, and the pattern 4e-1 is connected to the pattern 4e-2 through a plurality of wires w72. The wires w71 and w72 are metal wires electrically connected to the semiconductor chip.

[0139] exist Fig.19 in Fig. 9 In the correspondence relationship of the U phase, for example, the semiconductor chip 9e corresponds to the upper arm semiconductor chip 31a, the wire w71 corresponds to the wiring 52a between the upper arm semiconductor chip 31a and the lower arm semiconductor chip 32a, and the wire w72 corresponds to the wiring 51a between the upper arm semiconductor chip 31a and the terminal 41a.

[0140] The wire w71 and the wire w72 are close to each other and are considered to have a portion exposed from the insulating sealing member. In this case, the portion of the wire w71 exposed from the insulating sealing member is considered to be a portion where insulation with the wire w72 needs to be ensured, and is covered by the insulating member 6e-1. In addition, the portion of the wire w72 exposed from the insulating sealing member is considered to be a portion where insulation with the wire w71 needs to be ensured, and is covered by the insulating member 6e-2.

[0141] It should be noted that in the above description, both the wire w71 corresponding to the front main electrode wiring and the wire w72 corresponding to the back electrode wiring are covered by the insulating member, but it is also possible to have a structure in which only one of them is covered by the insulating member. In addition, a lead frame can be used instead of the wires w71 and w72.

[0142] <Semiconductor device including vertical semiconductor chip> Fig. 20 , Fig.21 This is a diagram showing an example of the structure of a semiconductor device including a vertical semiconductor chip. Fig. 20 It is a top view diagram. Fig.21 It is a side view schematic diagram.

[0143] In the semiconductor device 100, three main electrode terminals 121, 122, 123 and four auxiliary electrode terminals 124, 125, 126, 127 are connected as electrode terminals 120. The main electrode terminals 121, 122, 123 and the auxiliary electrode terminals 124, 125, 126, 127 are formed in advance using metal materials such as Al and Cu before being mounted on the semiconductor device 100.

[0144] The main electrode terminal 121 is connected to the first main conductor pattern 143a (C1 terminal) of the first DCB substrate 140A. The main electrode terminal 121 has a terminal body 121a and two leg portions 121b connected to the terminal body 121a. The two leg portions 121b of the main electrode terminal 121 are mounted on the first main conductor pattern 143a of the first DCB substrate 140A by soldering or the like.

[0145] It should be noted that the purpose of providing two legs 121b on the main electrode terminal 121 and connecting them to the first main conductor pattern 143a of the first DCB substrate 140A is to suppress the electrical deviation (imbalance of resistance and impedance) between one group of IGBT 151 and FWD 152 and another group of IGBT 151 and FWD 152 on the first DCB substrate 140A.

[0146] The main electrode terminal 122 is connected to the second main conductor pattern 143b (E2 terminal) of the second DCB substrate 140B. The main electrode terminal 122 has a terminal body 122a and two legs 122b connected to the terminal body 122a. The two legs 122b of the main electrode terminal 122 are mounted on the second main conductor pattern 143b of the second DCB substrate 140B by soldering or the like.

[0147] The main electrode terminal 122 is connected at two locations in this way to suppress electrical deviation between one set of IGBT 151 and FWD 152 and the other set of IGBT 151 and FWD 152 in the second DCB substrate 140B.

[0148] The main electrode terminal 123 is connected to the first main conductor pattern 143a (E1 terminal) of the second DCB substrate 140B connected to the second main conductor pattern 143b of the first DCB substrate 140A by the wire 160. The main electrode terminal 123 has a terminal body 123a and two legs 123b connected to the terminal body 123a. The two legs 123b of the main electrode terminal 123 are mounted on the first main conductor pattern 143a of the second DCB substrate 140B by soldering or the like.

[0149] The main electrode terminal 123 is connected at two locations in this way to suppress electrical deviation between one set of IGBT 151 and FWD 152 and the other set of IGBT 151 and FWD 152 in the second DCB substrate 140B.

[0150] The terminal body portions 121 a , 122 a , and 123 a of the main electrode terminals 121 , 122 , and 123 are respectively formed in a substantially U-shape with the leg portions 121 b , 122 b , and 123 b sides as the opening direction.

[0151] The auxiliary electrode terminal 124 has a terminal body 124a and a leg 124b. The leg 124b of the auxiliary electrode terminal 124 is mounted on an auxiliary conductor pattern electrically connected to the second main conductor pattern 143b of the first DCB substrate 140A via a wire 160 by soldering or the like.

[0152] The auxiliary electrode terminal 125 includes a terminal main body portion 125 a and a leg portion 125 b . The leg portion 125 b of the auxiliary electrode terminal 125 is mounted on the third main conductor pattern 143 c (G1 terminal) of the first DCB substrate 140A by soldering or the like.

[0153] Similarly, the auxiliary electrode terminal 126 has a terminal body and a leg portion. The leg portion of the auxiliary electrode terminal 126 is mounted on the auxiliary conductor pattern of the first DCB substrate 140A electrically connected to the second main conductor pattern 143 b (E2 terminal) of the second DCB substrate 140B via the wire 160 by soldering or the like.

[0154] The auxiliary electrode terminal 127 has a terminal body and a leg portion. The leg portion of the auxiliary electrode terminal 127 is mounted on the auxiliary conductor pattern of the first DCB substrate 140A electrically connected to the third main conductor pattern 143 c (G2 terminal) of the second DCB substrate 140B via the wire 160 by soldering or the like.

[0155] The main electrode terminals 121 , 122 , 123 and the auxiliary electrode terminals 124 , 125 , 126 , 127 are formed in advance in a shape in which each terminal body is arranged at a predetermined position in the semiconductor device 100 in a state where the leg portions are attached to predetermined positions.

[0156] For example, as shown in the figure, the terminal main bodies 121a, 122a, and 123a of the main electrode terminals 121, 122, and 123 are pre-formed and arranged in parallel at approximately equal intervals in the central part of the semiconductor device 100, and the terminal main bodies of the auxiliary electrode terminals 124, 125, 126, and 127 are arranged in parallel at the ends of the semiconductor device 100.

[0157] exist Fig. 20 , Fig.21Although the height t1 of the insulating sealing part 15 filled between the shell (not shown) and the insulating substrate 140 is higher than the height t2 of the insulating sealing part 15 from the upper surface of the insulating substrate 140, since the plane area of ​​the insulating sealing part 15 arranged above the insulating substrate 140 occupies most of the area, the effect of suppressing the generation of bubbles can be obtained by making the height from the insulating substrate 140 lower than before.

[0158] As described above, according to the present invention, by suppressing the peeling and bubbles generated when the hygroscopic gel is heated, the insulation reliability can be improved. In addition, the condensation generated when the hygroscopic gel is cooled can be suppressed, and the moisture resistance can be improved. In addition, the insulation distance can be shortened, for example, even a semiconductor chip with a high withstand voltage rated voltage of 3.3 kV can be miniaturized to the same level as a general-purpose semiconductor chip with a rated voltage of 1.7 kV.

[0159] In addition, even for semiconductor chips with a rated voltage of 3.3 kV, a thin wire diameter (Φ300 μm) can be used, which can minimize the gate pad used only for signal input in the device. In particular, in expensive SiC (silicon carbide) devices, the device size can be reduced, thereby achieving cost reduction.

[0160] Although the embodiments are illustrated above, the structures of the various parts shown in the embodiments can be replaced with other structures having the same functions. In addition, other arbitrary components and processes can also be added. Furthermore, any two or more structures (features) in the above embodiments can be combined.

Claims

1. A semiconductor device, characterized in that: have: an insulating substrate having a plurality of wiring patterns; a semiconductor chip disposed on at least one wiring pattern among the plurality of wiring patterns; Metal wiring electrically connected to the semiconductor chip; A housing, the insulating substrate being arranged at the bottom thereof; as well as An insulating sealing member covers the semiconductor chip from the upper surface of the insulating substrate in a region surrounded by the insulating substrate and the case and is filled to a thickness such that at least a portion of the metal wiring is exposed.

2. The semiconductor device according to claim 1, wherein: The insulating sealing component is gel.

3. The semiconductor device according to claim 2, wherein: The semiconductor chip is a vertical semiconductor chip having a front main electrode and a back main electrode connected to the wiring pattern. The semiconductor device includes a first terminal connected to the wiring pattern electrically connected to the front main electrode and led out to the outside. The first terminal has a portion that is not covered by the insulating sealing member and is exposed. The metal wiring is electrically connected to the back main electrode, The semiconductor device includes an insulating member that covers at least one of a portion of the metal wiring adjacent to the first terminal, that is, an exposed portion of the metal wiring not covered by the insulating sealing member and a portion where the first terminal is exposed.

4. The semiconductor device according to claim 2, wherein: The semiconductor chip is a vertical semiconductor chip having a front main electrode and a back main electrode connected to the wiring pattern. The semiconductor chip includes a first terminal connected to the wiring pattern electrically connected to the back main electrode and led out to the outside. The first terminal has a portion that is not covered by the insulating sealing member and is exposed. The metal wiring is electrically connected to the front main electrode, The semiconductor device includes an insulating member that covers at least one of a portion of the metal wiring adjacent to the first terminal, that is, an exposed portion of the metal wiring not covered by the insulating sealing member and a portion where the first terminal is exposed.

5. The semiconductor device according to claim 2, wherein: The semiconductor chip is a vertical semiconductor chip having a front main electrode and a back main electrode connected to the wiring pattern. The semiconductor device comprises: a first terminal connected to the wiring pattern electrically connected to the front main electrode and led out to the outside; as well as a second terminal connected to the wiring pattern electrically connected to the back main electrode and different from the wiring pattern connected to the first terminal, and led out to the outside; The first terminal and the second terminal have exposed portions that are not covered by the insulating sealing member. The semiconductor device includes an insulating member that covers at least one of a portion where the first terminal is exposed and a portion where the second terminal is exposed.

6. The semiconductor device according to claim 2, wherein: The semiconductor chip is a vertical semiconductor chip, and includes a back main electrode connected to the wiring pattern, a front main electrode, and a control electrode provided on the front surface of the semiconductor chip. The metal wiring includes a first metal wiring electrically connected to the control electrode and a second metal wiring electrically connected to the back main electrode. The semiconductor device includes an insulating member that covers at least one of the first metal wiring and the second metal wiring in a portion adjacent to the first metal wiring and the second metal wiring, that is, an exposed portion not covered by the insulating sealing member.

7. The semiconductor device according to claim 2, wherein: The semiconductor chip is a vertical semiconductor chip, and includes a back main electrode and a front main electrode connected to the wiring pattern. The metal wiring includes a first metal wiring electrically connected to the front main electrode and a second metal wiring electrically connected to the back main electrode. The semiconductor device includes an insulating member that covers at least one of the first metal wiring and the second metal wiring in a portion adjacent to the first metal wiring and the second metal wiring, that is, an exposed portion not covered by the insulating sealing member.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that The rated current is 100A or more and the rated voltage is 1700V or more.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that The thickness of the insulating sealing member from the upper surface of the insulating substrate is 3 mm or less.

10. The semiconductor device according to any one of claims 3 to 7, characterized in that The insulating component is an adhesive or a resin.

11. The semiconductor device according to any one of claims 3 to 7, characterized in that The semiconductor device includes a plurality of the semiconductor chips.

12. The semiconductor device according to claim 5, wherein: The semiconductor device includes a plurality of the semiconductor chips, and the semiconductor chip electrically connected to the first terminal is different from the semiconductor chip electrically connected to the second terminal.

13. A semiconductor device, characterized in that: have: an insulating substrate having a plurality of wiring patterns; a semiconductor chip disposed on at least one wiring pattern among the plurality of wiring patterns; Metal wiring electrically connected to the semiconductor chip; A housing, the insulating substrate being arranged at the bottom thereof; an insulating sealing member covering the semiconductor chip from the upper surface of the insulating substrate with respect to a region surrounded by the insulating substrate and the housing; as well as an insulating member covering a portion exposed from the insulating sealing member and to ensure insulation, In the semiconductor device, a rated current is 100 A or more and a rated voltage is 1700 V or more, and a thickness of the insulating sealing member from the upper surface of the insulating substrate is 3 mm or less.

14. A method for manufacturing a semiconductor device, characterized in that: In a method for manufacturing a semiconductor device, for an area surrounded by an insulating substrate having a plurality of wiring patterns and a shell with the insulating substrate arranged at the bottom, a semiconductor chip arranged on at least one wiring pattern among the plurality of wiring patterns is covered from the upper surface of the insulating substrate and an insulating sealing component is filled to a thickness that exposes at least a portion of a metal wiring electrically connected to the semiconductor chip.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The insulating sealing component is gel.

16. The method for manufacturing a semiconductor device according to claim 14, wherein: The insulating sealing member is filled to a thickness of 3 mm or less from the upper surface of the insulating substrate.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The portion exposed from the insulating sealing member and where insulation is to be ensured is covered with the insulating member.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: When the insulating sealing member is filled in the region to the thickness, the insulating sealing member is filled in the region to the thickness after the exposed portion is previously covered with the insulating member.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: The insulating sealing component is injected into the area to a position higher than the thickness, and after the portion is covered with the insulating sealing component, the insulating sealing component is sucked out to reach the thickness, so that the portion exposed from the insulating sealing component filled to the thickness after suction is covered by the insulating sealing component.

20. The method for manufacturing a semiconductor device according to claim 17, wherein: The insulating sealing component is discharged toward the portion exposed when the insulating sealing component is filled to the thickness in the area until the thickness is reached, and the discharge is stopped when the insulating sealing component reaches the thickness, thereby covering the exposed portion with the insulating sealing component.

21. The method for manufacturing a semiconductor device according to any one of claims 17 and 18, characterized in that: The insulating component is an adhesive or a resin.

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