Semiconductor device, manufacturing method thereof and related product

Abstract

The invention relates to a semiconductor device, a manufacturing method thereof and a related product. The semiconductor device includes a power device and a passive matching circuit. The power device comprises a substrate, an epitaxial layer and an element, the epitaxial layer is deposited on the substrate, the surface, away from the epitaxial layer, of the substrate is a first surface of the power device, the surface, away from the substrate, of the epitaxial layer is a second surface of the power device, and the element is located on the second surface; at least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected with the power device. According to the semiconductor device, at least part of the passive matching circuit is arranged on the first surface, the first surface can be fully utilized, and the integration level of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and related products. Background Art

[0002] Semiconductor devices are usually installed in electronic devices such as mobile phones, watches, headphones, computers, and smart screens. Semiconductor devices use a large number of passive devices and circuits. In order to reduce the size of semiconductor devices and achieve miniaturization of semiconductor devices, passive device integration technology is usually used. However, the integration of passive matching circuits in semiconductor devices is currently low, resulting in a large space occupied by semiconductor devices in electronic devices, which is not conducive to the miniaturization of equipment. Therefore, it is necessary to provide a semiconductor device with high integration. Summary of the invention

[0003] The present application embodiment provides a semiconductor device and a method for manufacturing the same, and related products. The related products include but are not limited to power amplifiers, radio frequency systems, and electronic devices. The semiconductor device of the present application embodiment has a high degree of integration, which is conducive to the miniaturization of the semiconductor device.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor device. The semiconductor device includes a power device and a passive matching circuit; the power device includes a substrate, an epitaxial layer and a component, the epitaxial layer is deposited on the substrate, the surface of the substrate away from the epitaxial layer is the first surface of the power device, the surface of the epitaxial layer away from the substrate is the second surface of the power device, and the component is located on the second surface; at least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

[0005] In some embodiments, the semiconductor device may further include a substrate, and the power device is fixed to the substrate. It can be understood that the first surface may be fixedly connected to the substrate to achieve fixing of the power device to the substrate.

[0006] The embodiment of the present application improves the integration of the semiconductor device by setting at least part of the passive matching circuit on the first surface of the power device. Compared with the passive matching circuit being set on the substrate, which occupies too much substrate area, or the passive matching circuit being set on the second surface, which occupies too much area of ​​the second surface, resulting in a design with a large volume and low integration of the semiconductor device, the embodiment of the present application sets at least part of the passive matching circuit on the first surface, which can effectively reduce the area occupied by the passive matching circuit on the substrate, or can reduce the area occupied by the passive matching circuit on the second surface, fully utilize the first surface of the power device, improve the integration of the semiconductor device, and help reduce the overall size of the semiconductor device and realize the miniaturization of the semiconductor device.

[0007] In a possible implementation, the passive matching circuit includes an input matching circuit and an output matching circuit, the input matching circuit is used to input a radio frequency signal into the power device, and the output matching circuit is used to output a radio frequency signal from the power device, and at least part of the input matching circuit is located on the first surface, or at least part of the output matching circuit is located on the first surface. It can be understood that part of the input matching circuit can be located on the first surface, or all of the input matching circuit can be located on the first surface, and part of the output matching circuit can be located on the first surface, or all of the output matching circuit can be located on the first surface. Compared to the design in which the input matching circuit and the output matching circuit are centrally arranged on the substrate and the second surface, in the implementation of the present application, at least part of the input matching circuit is arranged on the first surface, or at least part of the output matching circuit is arranged on the first surface, so that the first surface is fully utilized, which is conducive to improving the integration of the semiconductor device.

[0008] In some implementations, the input matching circuit is used to input the radio frequency signal to the power device to the maximum extent, and the output matching circuit is used to output the radio frequency signal to the power device to the maximum extent, thereby reducing the loss of the radio frequency signal.

[0009] In a possible implementation, the passive matching circuit includes an interstage matching circuit, the interstage matching circuit is used for the transmission of radio frequency signals in the power device, and at least part of the interstage matching circuit is located on the first surface. It can be understood that part of the interstage matching circuit can be located on the first surface, or all of the interstage matching circuit can be located on the first surface. Compared with the design in which the interstage matching circuit is located on the second surface, in the implementation of the present application, at least part of the interstage matching circuit is arranged on the first surface, making full use of the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0010] In some implementations, the inter-stage matching circuit is used to maximize the transmission of the radio frequency signal inside the power device, thereby reducing the loss of the radio frequency signal.

[0011] In a possible implementation, the power device includes a conductive member, the conductive member extends from the first surface to the second surface, the conductive member electrically connects the element on the second surface with the passive matching circuit on the first surface, or part of the passive matching circuit is located on the second surface, the conductive member electrically connects the passive matching circuit on the second surface with the passive matching circuit on the first surface. The conductive member can be made of metal, and the conductive member has the functions of heat conduction and electricity conduction. The conductive member in the embodiment of the present application can realize the electrical connection between the circuit on the first surface and the circuit or device on the second surface, without the need for additional bonding wires or other connection structures. The connection method and process are simple, and the connection path between the passive matching circuit and the device is shortened, which is conducive to improving the integration of the passive matching circuit.

[0012] In a possible implementation manner, the input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the element is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element. The element may include a source, a drain, and a gate. In the embodiment of the present application, the input matching circuit and the output matching circuit are both arranged on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0013] In a possible implementation, the input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence at intervals and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit. The element may include a source, a drain and a gate. The number of elements may be multiple, which is not limited in this application and can be set as needed. In the embodiment of the present application, the input matching circuit and the output matching circuit are both arranged on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0014] In one possible implementation, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the output matching circuit is located on the first surface, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element; or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element. In the embodiment of the present application, the input matching circuit or the output matching circuit is disposed on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0015] In a possible implementation, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, and the output matching circuit is located on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively a first element to an Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit; or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively a first element to an Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit. In the embodiment of the present application, the input matching circuit or the output matching circuit is disposed on the first surface, so as to fully utilize the space on the first surface of the power device, which is beneficial to improving the integration of the semiconductor device.

[0016] In one possible implementation, the number of the element is one, the input matching circuit includes a first input part and a second input part that are electrically connected, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the element; or, the number of the element is one, the output matching circuit includes a first output part and a second output part that are electrically connected, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the element. In the embodiment of the present application, part of the input matching circuit (first input part) or part of the output matching circuit (first output part) is disposed on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0017] In a possible implementation, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the input matching circuit includes an electrically connected first input part and a second input part, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the first element; or, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the output matching circuit includes a first output part and a second output part, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the Nth element. In the embodiment of the present application, part of the input matching circuit (first input part) or part of the output matching circuit (first output part) is arranged on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device.

[0018] In one possible implementation, the semiconductor device includes a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively a first element to an Nth element, the first elements to the Nth elements are arranged in sequence and spaced apart, and two adjacent elements are electrically connected; the input matching circuit includes a first input part, a second input part and the third input part, the first input part is located on the first surface, the second input part is located on the second surface, the second input part is electrically connected to the first element, the second input part is electrically connected to the first input part, and the third input part is located on the surface of the substrate facing the power device and connected to the The power device is arranged at intervals, and the third input part is electrically connected to the second input part; or, the number of the elements is N, N is an integer greater than or equal to 2, and the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and the adjacent two elements are electrically connected, the output matching circuit includes a first output part, a second output part and a third output part, the first output part is located on the first surface, the second output part is located on the second surface, the second output part is electrically connected to the Nth element, the second output part is electrically connected to the first input part, the third output part is located on the surface of the substrate facing the power device and is arranged at intervals from the power device, and the third output part is electrically connected to the second output part. The passive matching circuit is arranged on the substrate with simple process and low cost. In the embodiment of the present application, part of the input matching circuit (first input part) or part of the output matching circuit (first output part) is arranged on the first surface, making full use of the space on the first surface of the power device, which is conducive to improving the integration of the semiconductor device. In the embodiment of the present application, the third input part or the third output part is arranged on the substrate, which improves the flexibility of the semiconductor device arrangement, and the passive matching circuit can be arranged on the substrate as needed.

[0019] In one possible implementation, the passive matching circuit includes an interstage matching circuit, which is located on the first surface and between the input matching circuit and the output matching circuit, and the interstage matching circuit electrically connects two adjacent elements; or, the passive matching circuit includes an interstage matching circuit, which is located on the second surface and between two adjacent elements, and the interstage matching circuit electrically connects two adjacent elements.

[0020] In a possible implementation, the input matching circuit includes at least one of a resistor, a capacitor or an inductor, and the output matching circuit includes at least one of a resistor, a capacitor or an inductor. Resistors, capacitors or inductors are electrically connected to each other to form an output matching circuit or an output matching circuit.

[0021] In a second aspect, the present application provides a method for manufacturing a semiconductor device, which is used to prepare a semiconductor device in any possible implementation of the first aspect, including: manufacturing a power device, the power device including a substrate, an epitaxial layer and a component, the epitaxial layer is deposited on the substrate, the surface of the substrate facing away from the epitaxial layer is the first surface of the power device, the surface of the epitaxial layer facing away from the substrate is the second surface of the power device, and the component is located on the second surface; forming a passive matching circuit on the power device, at least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

[0022] In some embodiments, the semiconductor device may further include a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate. It can be understood that the first surface may be fixedly connected to the substrate to achieve fixing of the power device to the substrate.

[0023] The embodiment of the present application improves the integration of the semiconductor device by setting at least part of the passive matching circuit on the first surface of the power device. Compared with setting the passive matching circuit on the substrate, which occupies too much substrate area, or concentrating the passive matching circuit on the second surface, resulting in a larger volume and low integration of the semiconductor device, the embodiment of the present application sets at least part of the passive matching circuit on the first surface, fully utilizing the first surface of the power device, which can effectively reduce the area occupied by the passive matching circuit on the substrate, or can reduce the area occupied by the passive matching circuit on the second surface, thereby improving the integration of the semiconductor device and facilitating the miniaturization of the semiconductor device.

[0024] In a possible implementation, the steps of manufacturing the power device include: depositing the epitaxial layer on the substrate; forming the element on the second surface; bonding the second surface to a carrier; patterning the substrate and the epitaxial layer to form a back hole, wherein the back hole extends from the first surface to the second surface; coating photoresist, patterning the photoresist, exposing and developing the back hole and the remaining electroplated areas, and retaining the photoresist in the non-electroplated areas; electroplating metal in the areas not covered by the photoresist; removing the photoresist in the non-electroplated areas; after forming the passive matching circuit on the power device, the method for manufacturing the semiconductor device further includes: removing the carrier. Before removing the carrier, making the passive matching circuit in the non-electroplated area can avoid damaging the power device.

[0025] In a possible implementation, during the process of patterning the photoresist, at least two exposure and development processes are performed, and at least two exposure and development process areas partially overlap. Performing at least two exposure and development processes is conducive to avoiding photoresist residues, and at least two exposure and development process areas are different and partially overlapped, which can avoid overexposure, which will remove more photoresist and electroplate metal in areas where metal plating is not required.

[0026] In a possible implementation, the thickness of the photoresist on the first surface is greater than or equal to 1.2 times the thickness of the metal on the first surface. In the implementation of the present application, by setting the thickness of the photoresist on the first surface to be greater than or equal to 1.2 times the thickness of the metal on the first surface, it is possible to avoid that when electroplating metal, the metal overflows the photoresist and causes the pattern of the electroplated metal to change.

[0027] In a third aspect, the present application provides a power amplifier, comprising the semiconductor device described in any one of the aforementioned embodiments. The power amplifier can be used to amplify the power of a radio frequency signal.

[0028] In a fourth aspect, the present application provides a radio frequency system, comprising a radio frequency chip and the power amplifier described in the third aspect, wherein the radio frequency chip is used to send the radio frequency signal to the power amplifier, and the power amplifier is used to amplify the radio frequency signal.

[0029] In a fifth aspect, the present application provides an electronic device, comprising a signal output device and the radio frequency system described in the fourth aspect, wherein the signal output device is used to send a signal to the radio frequency system, and the radio frequency system is used to amplify the signal. The electronic device may be a tablet, a smart screen, a mobile phone, an electronic watch, electronic glasses, a headset, or a router, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0031] Figure 1 It is a schematic diagram of the structure of some electronic devices provided by the embodiments of the present application;

[0032] Figure 2 yes Figure 1 A schematic diagram of the structure of the radio frequency system shown;

[0033] Figure 3 yes Figure 2 A schematic diagram of the structure of a power amplifier shown;

[0034] Figure 4 yes Figure 3 A schematic structural diagram of a semiconductor device shown;

[0035] Figure 5 yes Figure 4 A schematic diagram of a stacked structure of a power device of a semiconductor device shown;

[0036] Figure 6 yes Figure 3 A schematic structural diagram of another semiconductor device shown;

[0037] Figure 7 yes Figure 3 A schematic structural diagram of another semiconductor device shown;

[0038] Figure 8 yes Figure 3 A schematic structural diagram of another semiconductor device shown;

[0039] Fig. 9 yes Figure 3 A schematic structural diagram of another semiconductor device shown;

[0040] Fig.10 is a manufacturing flow chart of a semiconductor device provided in an embodiment of the present application;

[0041] Fig.11 It is a manufacturing flow chart of a power device provided in an embodiment of the present application;

[0042] Fig.12 It is a schematic diagram of a structure after bonding an epitaxial layer to a carrier wafer provided in an embodiment of the present application;

[0043] Fig.13 This is a schematic diagram of a structure for forming a back hole provided in an embodiment of the present application;

[0044] Fig.14 It is a schematic diagram of the structure of a deposited metal seed layer provided in an embodiment of the present application;

[0045] Fig.15 It is a structural schematic diagram of performing a first photolithography on a photoresist provided by an embodiment of the present application;

[0046] Fig.16 It is a top view of a photoresist after the first photolithography provided by an embodiment of the present application;

[0047] Fig.17 It is a structural schematic diagram of performing a second photolithography on a photoresist provided by an embodiment of the present application;

[0048] Fig.18 This is a schematic diagram of a structure after metal electroplating provided by an embodiment of the present application;

[0049] Fig.19 This is a scanning electron microscope image of a back hole after focused ion beam cutting provided in an embodiment of the present application;

[0050] Fig. 20 It is a schematic diagram of a structure after removing the photoresist and part of the metal seed layer provided in an embodiment of the present application;

[0051] Fig.21 It is a schematic diagram of a structure after a passive matching circuit is deposited provided in an embodiment of the present application;

[0052] Fig. 22 is a top view of a passive matching circuit after deposition provided by an embodiment of the present application;

[0053] Fig.23 It is a schematic diagram of the structure of a power device after debonding the power device and the carrier provided in an embodiment of the present application;

[0054] Fig.24 It is a schematic diagram of a power device obtained by two different methods provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0056] like Figure 1 As shown, Figure 1 1 is a schematic diagram of the structure of some electronic devices 100. The electronic device 100 can be Figure 1 The tablet shown in (a), the smart screen shown in (b), the mobile phone shown in (c), the electronic watch shown in (d), the smart glasses shown in (e), the earphone shown in (f), or the router shown in (g). Figure 1 The electronic device 100 is introduced by taking the mobile phone shown in (c) as an example.

[0057] The electronic device 100 may include a signal output device 10 and a radio frequency system 20. The signal output device 10 sends a radio frequency signal to the radio frequency system 20. After the radio frequency signal enters the radio frequency system 20, the signal is amplified by the power amplifier 22 of the radio frequency system 20, and then output to an external receiving device (such as a wireless base station or a communication satellite) through a switch 24 and an antenna 23. Exemplarily, the signal output device 10 may send a voice signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the voice signal; the signal output device 10 may send an image signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the image signal; the signal output device 10 may send a video signal to the radio frequency system 20, and the power amplifier 22 of the radio frequency system 20 amplifies the video signal.

[0058] Understandably, Figure 1 The electronic device 100 is only schematically represented, and the position, shape, etc. of the signal output device 10 and the radio frequency system 20 can be set as needed. This application does not limit the specific structure of the electronic device 100.

[0059] like Figure 2 As shown, Figure 2 yes Figure 1 The structure diagram of the radio frequency system 20 is shown. The radio frequency system 20 may include a radio frequency chip 21 and a power amplifier 22. The radio frequency chip 21 sends a radio frequency signal to the power amplifier 22, and the power amplifier 22 is used to amplify the radio frequency signal.

[0060] In some embodiments, the RF system 20 may further include an antenna 23, a switch 24, a low noise amplifier 25, and a filter 26. The RF signal amplified by the power amplifier 22 is transmitted to the antenna 23, and the antenna 23 transmits the RF signal to a base station or a communication satellite ( Figure 2 In addition, the base station can also transmit the RF signal to the antenna 23, and the antenna 23 transmits the RF signal to the switch 24, and then transmits it to the low noise amplifier 25 and the filter 26 in turn, and then transmits it to the RF chip 21 to form a RF signal loop.

[0061] Understandably, Figure 2 The radio frequency system 20 is only schematically represented, and the present application does not limit the specific structure of the radio frequency system 20.

[0062] like Figure 3 As shown, Figure 3 for Figure 2 The power amplifier 22 is a schematic diagram of the structure of the power amplifier 22. The power amplifier 22 may include an output end load 222 and a semiconductor device 30. The radio frequency signal is input to the semiconductor device 30, and is output to the output end load 222 after being amplified by the semiconductor device 30.

[0063] Understandably, Figure 3 The power amplifier 22 is only schematically shown, and the embodiment of the present application does not limit the specific structure of the power amplifier 22.

[0064] like Figure 4 and Figure 5 As shown, Figure 4 for Figure 3 A schematic structural diagram of a semiconductor device 30 is shown, Figure 5 for Figure 4 The schematic diagram of the stacked structure of the power device 32 of the semiconductor device 30 shown in FIG. Figure 5 Only the multi-layer structure of the power device 32 is shown, and other structures on the power device 32 are not shown.

[0065] The semiconductor device 30 may include a power device 32 and a passive matching circuit 33. The passive matching circuit 33 can better exert the radio frequency output characteristics of the semiconductor device 30.

[0066] The power device 32 may include a substrate 321, an epitaxial layer 322 and a component. The substrate 321 may be a silicon-based substrate or a substrate of other materials. The epitaxial layer 322 is deposited on the substrate 321. The epitaxial layer 322 may include a nucleation layer 3221, a buffer layer 3222, a back barrier layer 3223, a channel layer 3224, an insertion layer 3225, a barrier layer 3226 and a cap layer 3227 stacked in sequence. The nucleation layer 3221 is used to provide a basis for the deposition of other layer structures, the buffer layer 3222 is used to buffer the stress between the epitaxial layer 322 and the substrate 321, the back barrier layer 3223 is used to improve the confinement of carriers and reduce leakage channels, the channel layer 3224 is used to provide a carrier channel, the insertion layer 3225 is used to reduce the carrier scattering effect and improve the carrier mobility, the barrier layer 3226 is used to form a heterostructure with the channel layer 3224, and the cap layer 3227 is used to prevent oxidation.

[0067] The number of the element may be one, or at least two. In the embodiment of the present application, the number of the element is two as an example, and the two elements are respectively a first element 34 and a second element 35. The element may include a source, a drain and a gate.

[0068] Understandably, Figure 5 The epitaxial layer 322 is only schematically shown, and the layer structure of the epitaxial layer 322 can also be of other designs, which can be specifically adjusted as needed. The embodiment of the present application does not limit the specific structure of the epitaxial layer 322.

[0069] The surface of the substrate 321 facing away from the epitaxial layer 322 is the first surface 323 of the power device 32, and the surface of the epitaxial layer 322 facing away from the substrate 321 is the second surface 324 of the power device 32. The first element 34 and the second element 35 are located on the second surface 324.

[0070] At least part of the passive matching circuit 33 is disposed on the first surface 323, and the passive matching circuit 33 located on the first surface 323 is electrically connected to the power device 32. It can be understood that in the semiconductor device 30, part of the passive matching circuit 33 can be disposed on the first surface 323, and all of the passive matching circuits 33 of the semiconductor device 30 can also be disposed on the first surface 323.

[0071] In some embodiments, the semiconductor device 30 further includes a substrate 31, which may be a circuit board or a flexible circuit board, etc. The power device 32 is fixed to the substrate 31, the first surface 323 is located between the second surface 324 and the substrate 31, the first surface 323 may contact and be fixedly connected to the substrate 31, and the power device 32 and the substrate 31 may be electrically connected.

[0072] The embodiment of the present application improves the integration of the semiconductor device 30 by setting at least part of the passive matching circuit 33 on the first surface 323 of the power device 32. In the prior art, the passive matching circuit 33 is concentrated on the surface of the substrate 31, which occupies too much area of ​​the substrate 31, or the passive matching circuit 33 is concentrated on the second surface 324, so that the size of the required power device 32 increases, resulting in a large volume and low integration of the semiconductor device 30. In the embodiment of the present application, at least part of the passive matching circuit 33 originally set on the substrate 31 or the second surface 324 can be set on the first surface 323, making full use of the space of the first surface 323 of the power device 32, which can effectively reduce the area occupied by the passive matching circuit 33 on the substrate 31, or can reduce the area occupied by the passive matching circuit 33 on the second surface 324, improve the integration of the semiconductor device 30, and help reduce the overall size of the semiconductor device 30, and realize the miniaturization of the semiconductor device 30.

[0073] In some embodiments, the passive matching circuit 33 may include an input matching circuit 331 and an output matching circuit 332, and at least part of the input matching circuit 331 is located on the first surface 323, or at least part of the output matching circuit 332 is located on the first surface 323. The input matching circuit 331 is used to input the RF signal into the power device 32, and the output matching circuit 332 is used to output the RF signal from the power device 32. It can be understood that part of the input matching circuit 331 may be located on the first surface 323, or all of the input matching circuit 331 may be located on the first surface 323, part of the output matching circuit 332 may be located on the first surface 323, or all of the output matching circuit may be located on the first surface 323. At least part of the input matching circuit 331 is located on the first surface 323, or at least part of the output matching circuit 332 is located on the first surface 323, or at least part of the input matching circuit 331 is located on the first surface 323 and at least part of the output matching circuit 332 is located on the first surface 323.

[0074] In some embodiments, the input matching circuit 331 is used to achieve impedance matching between the RF signal source and the first element 34, so that the RF signal is transmitted to the first element 34 to the maximum extent, and almost no signal is reflected back to the RF signal source, thereby reducing the loss of the RF signal.

[0075] Compared to the design in which the input matching circuit 331 and the output matching circuit 332 are centrally arranged on the substrate 31 and the second surface 324, in the embodiment of the present application, at least part of the input matching circuit 331 is arranged on the first surface 323, or at least part of the output matching circuit 332 is arranged on the first surface 323, so as to make full use of the first surface 323 of the power device 32, which is beneficial to improving the integration of the semiconductor device 30.

[0076] The input matching circuit 331 may include at least one of a resistor, a capacitor or an inductor, and the output matching circuit 332 may include at least one of a resistor, a capacitor or an inductor. The resistor, capacitor or inductor components are electrically connected to each other to form the input matching circuit 331 or the output matching circuit 332.

[0077] In some embodiments, the passive matching circuit 33 may include an inter-stage matching circuit 333, which is used for transmitting radio frequency signals in the power device, and at least part of the inter-stage matching circuit 333 is located on the first surface 323. It can be understood that part of the inter-stage matching circuit 333 may be located on the first surface 323, or all of the inter-stage matching circuit 333 may be located on the first surface 323. Compared with the design in which the inter-stage matching circuit 333 is located on the second surface 324, in the embodiment of the present application, at least part of the inter-stage matching circuit 333 is arranged on the first surface 323, making full use of the first surface 323, which is conducive to improving the integration of the semiconductor device 30.

[0078] In some embodiments, the inter-stage matching circuit 333 is used to perform impedance matching between the output end of the previous stage element and the input end of the subsequent stage element, so that the RF signal can be transmitted in the power device almost without reflection, thereby reducing the loss of the RF signal.

[0079] The inter-stage matching circuit 333 may include at least one of a resistor, a capacitor or an inductor. The resistor, capacitor or inductor and other components may be electrically connected to each other to form the inter-stage matching circuit 333 .

[0080] In some embodiments, the power device 32 may include a conductive member, which extends from the first surface 323 to the second surface 324. The conductive member may be used to electrically connect the components on the second surface 324 and the passive matching circuit on the first surface 323, or, when part of the passive matching circuit is located on the second surface 324, the conductive member may be used to electrically connect the passive matching circuit on the second surface 324 and the passive matching circuit on the first surface 323. The conductive member has the functions of heat conduction and electrical conduction. The conductive member in the embodiment of the present application can realize the electrical connection between the passive matching circuit on the first surface 323 and the passive matching circuit or device on the second surface 324, without the need to additionally set up bonding wires or other connection structures. The connection method and process are simple, and the connection path between the passive matching circuit and the device is shortened, thereby improving the integration of the semiconductor device 30.

[0081] like Figure 4 As shown, in some embodiments, the input matching circuit 331 and the output matching circuit 332 are arranged at intervals on the first surface 323, the number of elements is N, N is an integer greater than or equal to 2, the N elements are the first element 34 to the Nth element, the first element 34 to the Nth element are arranged at intervals in sequence and any two adjacent elements are electrically connected, the input matching circuit 331 is electrically connected to the first element 34, and the Nth element is electrically connected to the output matching circuit 332.

[0082] In some embodiments, the inter-stage matching circuit 333 is located on the first surface 323 and between the input matching circuit 331 and the output matching circuit 332 . The inter-stage matching circuit 333 electrically connects two adjacent elements.

[0083] Figure 4Taking the number of elements as two, that is, N is equal to 2 as an example, the two elements are the first element 34 and the second element 35, and the first element 34 and the second element 35 are arranged at intervals. The input matching circuit 331, the inter-stage matching circuit 333 and the output matching circuit 332 are arranged at intervals on the first surface 323 in sequence, making full use of the space on the first surface 323 of the power device 32, which is conducive to improving the integration of the semiconductor device 30. It can be understood that if the input matching circuit 331 and the output matching circuit 332 are located on the substrate 31, the space of the substrate 31 will be occupied, the substrate 31 needs to be designed with a larger size, and the integration of the semiconductor device 30 is low, or if the input matching circuit 331 and the output matching circuit 332 are located on the second surface 324, the power device 32 needs to be larger in size, and the integration of the semiconductor device 30 is low. By setting the input matching circuit 331, the inter-stage matching circuit 333 and the output matching circuit 332 on the first surface 323, the space on the first surface 323 of the power device 32 is fully utilized, and the integration of the semiconductor device 30 is effectively improved.

[0084] The power device 32 may include a first conductive member 325, a second conductive member 326, a third conductive member 327 and a fourth conductive member 328. The first conductive member 325 to the fourth conductive member 328 are arranged at intervals and extend from the first surface 323 to the second surface 324. The first conductive member 325 to the fourth conductive member 328 may be made of metal.

[0085] It can be understood that the number of conductive parts can be one, two, three or four, etc. The embodiment of the present application takes the number of conductive parts as four as an example. For the purpose of distinction, the four conductive parts are respectively the first conductive part 325, the second conductive part 326, the third conductive part 327 and the fourth conductive part 328.

[0086] The input matching circuit 331 and the first element 34 can be electrically connected through the first conductive member 325, the first element 34 and the inter-stage matching circuit 333 can be electrically connected through the second conductive member 326, the inter-stage matching circuit 333 and the second element 35 can be electrically connected through the third conductive member 327, and the second element 35 and the output matching circuit 332 can be electrically connected through the fourth conductive member 328. In the embodiment of the present application, the input matching circuit 331, the inter-stage matching circuit 333 and the output matching circuit 332 located on the first surface 323 and the first element 34 and the second element 35 located on the second surface 324 are electrically connected by using the existing first conductive member 325 to the fourth conductive member 328 of the power device 32, without the need to set up additional bonding wires or other connection structures, the connection method and process are simple, and the connection path is short.

[0087] In some embodiments, the number of the element may be one, the input matching circuit 331 and the output matching circuit 332 are arranged alternately on the first surface 323 , the input matching circuit 331 is electrically connected to the element, and the output matching circuit 332 is electrically connected to the element.

[0088] like Figure 6 As shown, Figure 6 for Figure 3 FIG. 1 is a schematic structural diagram of another semiconductor device 30 shown in FIG. Figure 6 The semiconductor device 30 shown is Figure 4 The structure of the semiconductor device 30 shown is different in that Figure 6 The inter-stage matching circuit 333 of the semiconductor device 30 is shown as being located on the second surface 324 and between two adjacent elements (the first element 34 and the second element 35 ). The inter-stage matching circuit 333 electrically connects the two adjacent elements (the first element 34 and the second element 35 ).

[0089] The power device 32 may have two conductive members, namely a first conductive member 325 and a second conductive member 326. The first conductive member 325 and the second conductive member 326 are arranged at intervals and both extend from the first surface 323 to the second surface 324. The input matching circuit 331 and the first element 34 are electrically connected through the first conductive member 325, and the second element 35 and the output matching circuit 332 are electrically connected through the second conductive member 326.

[0090] In the embodiment of the present application, the input matching circuit 331 and the output matching circuit 332 are both disposed on the first surface 323, so as to make full use of the space on the first surface 323 of the power device 32, which is beneficial to improving the integration of the semiconductor device 30. In the embodiment of the present application, the input matching circuit 331 and the output matching circuit 332 located on the first surface 323 are electrically connected to the first element 34 and the second element 35 located on the second surface 324 by using the existing first conductive member 325 and the second conductive member 326 of the power device 32, without the need to additionally set up bonding wires or other connection structures, and the connection method and process are simple, and the connection path is short.

[0091] like Figure 7 As shown, Figure 7 for Figure 3 A structural diagram of another semiconductor device 30 is shown. In some embodiments, the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, the output matching circuit 332 is located on the first surface 323, the number of elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element 34 to the Nth element, the first element 34 to the Nth element are arranged in sequence and spaced apart and two adjacent elements are electrically connected, the input matching circuit 331 is electrically connected to the first element 34, and the Nth element is electrically connected to the output matching circuit 332.

[0092] Figure 7 Taking the number of elements as two, that is, N is equal to 2, as an example, the two elements are respectively a first element 34 and a second element 35, and the first element 34 and the second element 35 are arranged at intervals. Exemplarily, the semiconductor device 30 further includes a bonding wire 36. The first element 34, the inter-stage matching circuit 333 and the second element 35 are sequentially arranged at intervals on the second surface 324, and the inter-stage matching circuit 333 electrically connects the first element 34 and the second element 35.

[0093] The output matching circuit 332 is located on the first surface 323, and the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32. The first conductive member 325 electrically connects the output matching circuit 332 and the second element 35, and the bonding wire 36 electrically connects the input matching circuit 331 and the first element 34. In the embodiment of the present application, the output matching circuit 332 is arranged on the first surface 323, which makes full use of the space on the first surface 323 of the power device 32, which is conducive to improving the integration of the semiconductor device 30. In the embodiment of the present application, the output matching circuit 332 located on the first surface 323 and the second element 35 located on the second surface 324 are electrically connected by using the existing first conductive member 325 of the power device 32, and the connection method and process are simple, and the connection path is short.

[0094] In other embodiments, the input matching circuit 331 may be arranged on the first surface 323, the output matching circuit 332 may be arranged on the surface of the substrate 31 facing the power device 32 and spaced from the power device 32, the number of elements may be N, N is an integer greater than or equal to 2, the N elements may be the first element 34 to the Nth element, the first element 34 to the Nth element may be arranged in sequence and spaced from each other, the input matching circuit 331 may be electrically connected to the first element 34, and the Nth element may be electrically connected to the output matching circuit 332. Exemplarily, the input matching circuit 331 may be arranged on the first surface 323, the output matching circuit 332 may be arranged on the surface of the substrate 31 facing the power device 32 and spaced from the power device 32. The first conductive member 325 connects the input matching circuit 331 and the first element 34, and the bonding wire 36 connects the output matching circuit 332 and the second element 35. In the embodiment of the present application, the input matching circuit 331 is arranged on the first surface 323, and the space on the first surface 323 of the power device 32 is fully utilized, which is conducive to improving the integration of the semiconductor device 30. In the embodiment of the present application, the input matching circuit 331 located on the first surface 323 and the first element 34 located on the second surface 324 are electrically connected by using the existing first conductive member 325 of the power device 32. The connection method and process are simple and the connection path is short.

[0095] In other embodiments, the inter-stage matching circuit 333 may be located on the first surface 323, and the inter-stage matching circuit 333 electrically connects the first element 34 and the second element 35. In other embodiments, the inter-stage matching circuit 333 may not be provided.

[0096] In some embodiments, the input matching circuit 331 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, the output matching circuit 332 is located on the first surface 323, the number of components is one, the input matching circuit 331 is electrically connected to the component, and the output matching circuit 332 is electrically connected to the component. Alternatively, the input matching circuit 331 is located on the first surface 323, the output matching circuit 332 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, the number of components is one, the input matching circuit 331 is electrically connected to the component, and the output matching circuit 332 is electrically connected to the component.

[0097] like Figure 8 As shown, Figure 8 for Figure 3 Another structural diagram of a semiconductor device 30 is shown. In some embodiments, the number of elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element 34 to the Nth element, the first element 34 to the Nth element are arranged in sequence and the adjacent two elements are electrically connected, the input matching circuit 331 includes an electrically connected first input portion 3311 and a second input portion 3312, the first input portion 3311 is located on the first surface 323, the second input portion 3312 is located on the second surface 324, and the second input portion 3312 is electrically connected to the first element 34; or, the number of elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element 34 to the Nth element, the first element 34 to the Nth element are arranged in sequence and the adjacent two elements are electrically connected, the output matching circuit 332 includes a first output portion 3321 and a second output portion 3322, the first output portion 3321 is located on the first surface 323, the second output portion 3322 is located on the second surface 324, and the second output portion 3322 is electrically connected to the Nth element.

[0098] For example, Figure 8Taking the number of elements as two, that is, N is equal to 2 as an example, the two elements are respectively a first element 34 and a second element 35, and the first element 34 and the second element 35 are arranged alternately. The power device 32 includes a first conductive member 325 and a second conductive member 326. The input matching circuit 331 includes a first input portion 3311 and a second input portion 3312, the first input portion 3311 is located on the first surface 323, and the second input portion 3312 is located on the second surface 324. The second input portion 3312 is electrically connected to the first element 34, and the first conductive member 325 is electrically connected to the first input portion 3311 and the second input portion 3312. The output matching circuit 332 includes a first output portion 3321 and a second output portion 3322, the first output portion 3321 is located on the first surface 323, the second output portion 3322 is located on the second surface 324, the second output portion 3322 is electrically connected to the second element 35, and the second conductive member 326 is electrically connected to the first output portion 3321 and the second output portion 3322. The second input portion 3312 , the first element 34 , the inter-stage matching circuit 333 , the second element 35 and the second output portion 3322 are sequentially arranged on the second surface 324 at intervals.

[0099] The embodiment of the present application arranges part of the input matching circuit (i.e., the first input part 3311) and part of the output matching circuit (i.e., the first output part 3321) on the first surface 323, making full use of the space on the first surface 323 of the power device 32, which is beneficial to improving the integration of the semiconductor device 30.

[0100] In other embodiments, the first input part 3311 and the second input part 3312 of the input matching circuit 331 can both be located on the first surface 323, that is, the entire input matching circuit 331 is located on the first surface 323, the first output part 3321 of the output matching circuit 332 is located on the first surface 323, and the second output part 3322 is located on the second surface 324.

[0101] In other embodiments, the first input part 3311 of the input matching circuit 331 is located on the first surface 323, the second input part 3312 is located on the second surface 324, and the first output part 3321 and the second output part 3322 of the output matching circuit 332 may both be located on the first surface 323, that is, all the output matching circuits 332 are located on the first surface 323.

[0102] In other embodiments, the inter-stage matching circuit 333 may also include two parts, one part of the inter-stage matching circuit 333 may be located on the first surface 323 of the power device 32, and the other part of the inter-stage matching circuit 333 may be located on the second surface 324 of the power device 32. Alternatively, the entire inter-stage matching circuit 333 may be located on the first surface 323 and between the input matching circuit 331 and the output matching circuit 332, and the inter-stage matching circuit 333 electrically connects two adjacent elements.

[0103] It can be understood that when the input matching circuit 331, the output matching circuit 332 or the inter-stage matching circuit 333 has many devices, concentrating them in one area will occupy too much space in this area. Therefore, the input matching circuit 331, the output matching circuit 332 or the inter-stage matching circuit 333 can be divided into multiple parts, and the multiple parts can be distributed in different areas to reasonably and fully utilize the space of the semiconductor device 30 and improve the integration of the semiconductor device 30.

[0104] In some embodiments, the number of elements is one, and the input matching circuit 331 includes an electrically connected first input portion 3311 and a second input portion 3312, the first input portion 3311 is located on the first surface 323, the second input portion 3312 is located on the second surface 324, and the second input portion 3312 is electrically connected to the element. Alternatively, the number of elements is one, and the output matching circuit 332 includes an electrically connected first output portion 3321 and a second output portion 3322, the first output portion 3321 is located on the first surface 323, the second output portion 3322 is located on the second surface 324, and the second output portion 3322 is electrically connected to the element.

[0105] like Fig. 9 As shown, Fig. 9 for Figure 3 FIG. 1 is a schematic structural diagram of another semiconductor device 30 shown in FIG. Fig. 9 The semiconductor device 30 shown is Figure 8The difference between the semiconductor device shown in the figure is that, in the embodiment of the present application, the input matching circuit 331 also includes a third input part 3313, the third input part 3313 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, and the third input part 3313 is electrically connected to the second input part 3312. Exemplarily, the third input part 3313 can be connected to the second input part 3312 through a bonding wire. The output matching circuit 332 also includes a third output part 3323, the third output part 3323 is located on the surface of the substrate 31 facing the power device 32 and is spaced apart from the power device 32, and the third output part 3323 is electrically connected to the second output part 3322. Exemplarily, the third output part 3323 can be connected to the second output part 3322 through a bonding wire. The second input part 3312, the first element 34, the inter-stage matching circuit 333, the second element 35 and the second output part 3322 are sequentially arranged on the second surface 324.

[0106] The passive matching circuit is arranged on the substrate 31 with simple process and low cost. In the embodiment of the present application, the third input part 3313 and the third output part 3323 are arranged on the substrate 31, which improves the flexibility of the semiconductor device 30 and allows the passive matching circuit to be arranged on the substrate 31 as needed.

[0107] In other embodiments, the input matching circuit 331 may include the third input part 3313 and the output matching circuit 332 may not include the third output part 3323 , or the input matching circuit 331 may not include the third input part 3313 and the output matching circuit 332 may include the third output part 3323 .

[0108] The present application embodiment provides a method for manufacturing a semiconductor device 30, which is used to prepare any of the above-mentioned semiconductor devices 30, such as Fig.10 As shown, Fig.10 is a flowchart of manufacturing the semiconductor device 30. The manufacturing method of the semiconductor device 30 in one embodiment specifically includes the following steps:

[0109] T10. Manufacturing a power device 32.

[0110] See also Figure 4 and Figure 5, the power device 32 may include a substrate 321, an epitaxial layer 322 and an element. The epitaxial layer 322 is deposited on the substrate 321. The substrate 321 may be a silicon-based substrate or a substrate of other materials. The surface of the substrate 321 away from the epitaxial layer 322 is the first surface 323 of the power device 32, and the surface of the epitaxial layer 322 away from the substrate 321 is the second surface 324 of the power device 32. The element is located on the second surface 324. The number of elements may be one, or the number of elements may be at least two. The embodiment of the present application takes the number of elements as two as an example, and the two elements are respectively a first element 34 and a second element 35. The element may include a source, a drain and a gate.

[0111] T20 . Form a passive matching circuit 33 on the power device 32 . At least a portion of the passive matching circuit 33 is located on the first surface 323 of the power device 32 .

[0112] It is understandable that in the semiconductor device 30 , part of the passive matching circuit 33 may be disposed on the first surface 323 , or all of the passive matching circuit 33 of the semiconductor device 30 may be disposed on the first surface 323 . The passive matching circuit located on the first surface 323 is electrically connected to the power device 32 .

[0113] The embodiment of the present application can set at least part of the passive matching circuit 33 originally set on the substrate 31 or the second surface 324 on the first surface 323, so as to make full use of the space on the first surface 323 of the power device 32, and can effectively reduce the area occupied by the passive matching circuit 33 on the substrate 31, or can reduce the area occupied by the passive matching circuit 33 on the second surface 324, thereby improving the integration of the semiconductor device 30, which is beneficial to reducing the overall size of the semiconductor device 30 and realizing the miniaturization of the semiconductor device 30.

[0114] In some embodiments, the passive matching circuit 33 may include an input matching circuit 331 and an output matching circuit 332, and at least part of the input matching circuit 331 is located on the first surface 323, or at least part of the output matching circuit 332 is located on the first surface 323. It can be understood that part of the input matching circuit 331 may be located on the first surface 323, or all of the input matching circuit 331 may be located on the first surface 323, part of the output matching circuit 332 may be located on the first surface 323, or all of the output matching circuit may be located on the first surface 323. At least part of the input matching circuit 331 is located on the first surface 323, or at least part of the output matching circuit 332 is located on the first surface 323, or at least part of the input matching circuit 331 is located on the first surface 323 and at least part of the output matching circuit 332 is located on the first surface 323.

[0115] Compared to the design in which the input matching circuit 331 and the output matching circuit 332 are centrally arranged on the substrate 31 and the second surface 324, in the embodiment of the present application, at least part of the input matching circuit 331 is arranged on the first surface 323, or at least part of the output matching circuit 332 is arranged on the first surface 323, so as to make full use of the first surface 323 and help improve the integration of the semiconductor device 30.

[0116] The input matching circuit 331 may include at least one of a resistor, a capacitor or an inductor, and the output matching circuit 332 may include at least one of a resistor, a capacitor or an inductor. The resistor, capacitor or inductor components are electrically connected to each other to form the input matching circuit 331 or the output matching circuit 332.

[0117] In some embodiments, the passive matching circuit 33 may include an inter-stage matching circuit 333, and at least part of the inter-stage matching circuit 333 is located on the first surface 323. It can be understood that part of the inter-stage matching circuit 333 may be located on the first surface 323, or all of the inter-stage matching circuit 333 may be located on the first surface 323. Compared with the design in which the inter-stage matching circuit 333 is located on the second surface 324, in the embodiment of the present application, at least part of the inter-stage matching circuit 333 is arranged on the first surface 323, making full use of the first surface 323, which is conducive to improving the integration of the semiconductor device 30.

[0118] The inter-stage matching circuit 333 may include at least one of a resistor, a capacitor or an inductor. The resistor, capacitor or inductor and other components may be electrically connected to each other to form the inter-stage matching circuit 333 .

[0119] In some embodiments, a power device 32 provided with a passive matching circuit 33 is fixed to a substrate 31. The substrate 31 may be a circuit board or a flexible circuit board, etc. The power device 32 is fixed to the substrate 31, and the first surface 323 is located between the second surface 324 and the substrate 31, and the first surface 323 may contact and be fixedly connected to the substrate 31. The power device 32 and the substrate 31 may be electrically connected.

[0120] like Fig.11 As shown, Fig.11 FIG. 1 is a flowchart of manufacturing a power device 32. In one embodiment, manufacturing a power device 32 specifically includes the following steps:

[0121] T101 . Deposit an epitaxial layer 322 on a substrate 321 .

[0122] See also Figure 5The substrate 321 may be a silicon-based substrate or a substrate of other materials. The epitaxial layer 322 may include a nucleation layer 3221, a buffer layer 3222, a back barrier layer 3223, a channel layer 3224, an insertion layer 3225, a barrier layer 3226 and a cap layer 3227 stacked in sequence. It can be understood that Figure 5 The epitaxial layer 322 in the figure is only schematically shown, and the layer structure of the epitaxial layer 322 can also be of other designs, which can be specifically set as needed.

[0123] T102 . Forming components on the second surface 324 .

[0124] After the epitaxial layer 322 is deposited, the components ( Figure 5 Devices not shown, see Figure 4 and Fig.12 ), the number of elements may be one, or the number of elements may be at least two. In the embodiment of the present application, the number of elements is two as an example, and the two elements are respectively a first element 34 and a second element 35. The element may include a source 3202, a drain and a gate.

[0125] The second surface 324 is subjected to dielectric protection. For example, a photoresist, an insulating layer, an oxide layer, etc. may be provided on the second surface 324. The dielectric protection may be used to protect the devices on the second surface 324 and prevent the devices on the second surface 324 from being damaged during subsequent processing.

[0126] T103. Bond the second surface 324 to the carrier wafer 3201.

[0127] See also Fig.12 , Fig.12 Schematic diagram of the structure after the epitaxial layer 322 is bonded to the carrier 3201. The material of the carrier 3201 can be glass, silicon carbide or silicon. The epitaxial layer 322 can be bonded to the carrier 3201 by bonding glue 3203, so that the substrate 321 and the epitaxial layer 322 are firmly fixed to the carrier 3201. The bonding glue 3203 can be resin or paraffin.

[0128] After the substrate 321 and the epitaxial layer 322 are bonded to the carrier 3201, the substrate 321 may be thinned. For example, the substrate 321 may be thinned by mechanical grinding, and the thickness of the thinned substrate 321 and the epitaxial layer 322 may be less than or equal to 200um. Thinning the substrate 321 may reduce the overall thickness of the substrate 321 and the epitaxial layer 322, shorten the transmission path, and facilitate better heat dissipation and reduce ground parasitic inductance.

[0129] Due to thermal stress, the substrate 321 may crack due to stress release after thinning, causing the power device 32 to be easily damaged during subsequent processing. Therefore, the substrate 321 and the epitaxial layer 322 need to be bonded to the carrier 3201 before thinning. The carrier 3201 can prevent the substrate 321 and the epitaxial layer 322 from warping or cracking during subsequent processing.

[0130] T104 , patterning the substrate 321 and the epitaxial layer 322 to form a back hole 3204 .

[0131] See also Fig.13 , Fig.13 A schematic diagram of the structure for making a back hole 3204. Before etching the substrate 321 and the epitaxial layer 322, the etching area needs to be patterned. The back hole 3204 can be patterned by a photolithography process, and the substrate 321 and the epitaxial layer 322 are etched using a photoresist as a mask. The etching process can be dry deep reactive ion etching, inductively coupled plasma, or a potassium hydroxide wet etching process. A combination of dry and wet etching can also be used to etch through the substrate 321 to the source 3202 on the second surface 324. It can be understood that the back hole 3204 extends from the first surface 323 to the second surface 324. After etching to form the back hole 3204, the photoresist mask of the second surface 324 is removed.

[0132] See also Fig.14 , Fig.14 Schematic diagram of the structure of depositing a metal seed layer 3205. The metal seed layer 3205 is deposited on the first surface 323 and the inner wall of the back hole 3204. The provision of the metal seed layer 3205 is conducive to the subsequent electroplating of metals, and is conducive to the electroplating of thicker metals. The thickness of the metal seed layer 3205 can be 10nm~1um, and the thickness of the metal seed layer 3205 is not limited in the embodiment of the present application. The material of the metal seed layer 3205 can be metals such as copper, gold, tungsten, nickel, tin, etc., and can also be alloy materials such as titanium tungsten and titanium gold. It can be understood that in other embodiments, the metal seed layer 3205 may not be provided.

[0133] In some embodiments, before depositing the metal seed layer 3205, an adhesion layer ( Fig.14 The adhesion layer is not shown in the figure), and the adhesion layer can be used to adhere the metal seed layer 3205. The material of the adhesion layer can be titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0134] T105 , coating the photoresist 3206 , and patterning the photoresist 3206 .

[0135] See also Fig.15 , Fig.16 and Fig.17 , Fig.15This is a schematic diagram of the structure of the first photolithography of the photoresist 3206. Fig.16 This is a top view of the photoresist 3206 after the first photolithography. Fig.17 It is a schematic diagram of the structure of performing a second photolithography on the photoresist 3206.

[0136] The photoresist 3206 is patterned, and the back hole 3204 and the remaining electroplated areas are exposed and developed, and the photoresist in the non-electroplated area is retained. It can be understood that the remaining electroplated area refers to the area on the first surface 323 that needs to be electroplated with metal, and the embodiment of the present application needs to electroplate metal in the back hole 3204 and the area on the first surface 323 that needs to be electroplated with metal later. In the process of patterning the photoresist, at least two exposure and development processes are performed, and at least the areas of the two exposure and development processes partially overlap.

[0137] The photoresist 3206 can be selected as a single layer or a multilayer, and the photoresist 3206 can be applied by spin coating. For example, the spin coating operation can be performed at a spin coating speed of 2500 rpm to 5000 rpm, a pre-baking temperature of 100° C., and a pre-baking time of 2 min to 4 min. The rotation speed and baking temperature have a great influence on the thickness of the photoresist 3206, and the specific thickness is determined according to the thickness of the metal to be electroplated, which is not limited in the embodiments of the present application.

[0138] In some embodiments, the thickness of the photoresist 3206 on the first surface 323 is greater than or equal to the thickness of the metal on the first surface 323 (for the arrangement of the metal on the first surface 323, see Fig.18 ) is 1.2 times the thickness of the electroplated metal, which can prevent the metal from overflowing the photoresist and causing the pattern of the electroplated metal to change during metal electroplating.

[0139] See also Fig.15 , the first photolithography is performed, and the photomask 3027 is set so that the first exposure area includes the back hole 3204 and the remaining electroplating area, and the photoresist in the non-electroplating area is retained. The exposure is performed in a non-continuous exposure mode, and the exposure mode is contact exposure. Exemplarily, the light source is turned on for exposure for 5.5 seconds to 11 seconds, and then the light source is turned off for a rest of 5 seconds to 10 seconds, and this cycle is repeated for multiple times, and the first development is performed after exposure.

[0140] Using multiple exposures can completely expose the thicker photoresist at the edge of the back hole 3204. When spin coating the photoresist 3206 on the first surface 323 of the power device provided with the back hole 3204, first drip the glue at the center of the first surface 323. The photoresist 3206 quickly flows to the edge of the first surface 323 under the action of centrifugal force, but the back hole 3204 blocks the flow of the liquid photoresist 3206, making the photoresist 3206 at the edge of the back hole 3204 thicker than other areas of the first surface 323. If a continuous exposure method is used, the photoresist 3206 at the edge of the back hole 3204 is too thick and cannot be photosensitized and denatured in time, making it difficult to be thoroughly exposed. However, using a non-continuous exposure method, the photoresist 3206 is gradually photosensitized and denatured in the thickness direction, and is finally thoroughly exposed and developed. In this step, the back hole 3204 area and the remaining electroplating areas are exposed and developed. Fig.16 It can be seen that the back hole 3204 is exposed.

[0141] After the first photolithography, the photoresist at the bottom and side walls of the back hole 3204 is difficult to be completely exposed because it is farther away from the light source than the photoresist on the first surface 323. Therefore, it is necessary to expose again to remove the photoresist at the bottom and side walls of the back hole 3204.

[0142] See also Fig.17 , the second photolithography is performed. In order to prevent overexposure of the larger area pattern of the first photolithography during the second exposure (overexposure will remove more photoresist and electroplate metal in areas where metal plating is not required), the exposure area of ​​the second photolithography is only the back hole 3204 area. The aperture of the exposure area is generally slightly larger than the aperture of the back hole 3204 because there is a system deviation in the photolithography alignment. The second exposure still adopts the non-continuous exposure method. The light source is turned on for exposure for 5.5 seconds to 11 seconds, and then the light source is turned off and paused for 5 seconds to 10 seconds. This cycle is repeated many times, and the second development is performed after exposure.

[0143] It is understandable that after the first photolithography, the photoresist in the non-electroplating area is retained after exposure and development without being removed, and then the photolithography of the back hole 3204 is performed. If there is still photoresist residue on the bottom and sidewall of the back hole 3204 after the second exposure and development, the third or more photolithography is performed to make sure that there is no photoresist residue on the bottom and sidewall of the back hole 3204. Except for the first photolithography, the exposure areas of other photolithography are all the back hole 3204 areas.

[0144] Understandably, it is also possible to first Fig.17 The second photolithography is shown, and then Fig.15 The first photolithography is shown.

[0145] T106. Electroplate metal in the areas not covered by photoresist 3206.

[0146] See also Fig.18 , Fig.18 Schematic diagram of the structure after electroplating metal. After the photoresist 3206 is patterned, electroplating can be performed. The area covered by the photoresist 3206 (i.e., the non-electroplating area) cannot be electroplated with metal, while the area not covered by the photoresist 3206 (i.e., the electroplating area) can be electroplated with metal to form a conductive member (such as the first conductive member 325). The material of the electroplated metal can be a metal or alloy such as copper, gold, tin, nickel, etc.

[0147] Fig.19 This is a scanning electron microscope image after the back hole 3204 is cut by a focused ion beam. Fig.19 It can be seen that after multiple exposures, there is no photoresist residue in the back hole 3204, the electroplated metal is well combined with the substrate and the epitaxial layer, and the electroplated metal has a good effect.

[0148] Fig.18 The back hole 3204 is completely occupied by the electroplated metal. In other embodiments, the metal may be electroplated only on the bottom and sidewalls of the back hole 3204, and the back hole 3204 still has a hollow space.

[0149] T107, remove photoresist 3206.

[0150] See also Fig. 20 , Fig. 20 Schematic diagram of the structure after removing the photoresist 3206 and removing part of the metal seed layer 3205. The photoresist 3206 in the non-electroplating area is removed, and the metal seed layer 3205 not covered by the electroplated metal on the first surface 323 is etched, that is, the patterning of the electroplated metal is achieved. The photoresist 3206 can be washed away with an organic solution. The metal seed layer 3205 can be etched by ion beam etching, inductively coupled plasma etching, etc.

[0151] Since the thickness of the metal seed layer 3205 is thinner than that of the electroplated metal (the thickness of the metal seed layer 3205 is generally 10nm~1um, while the electroplated metal is generally more than 3um, and the thickness of the electroplated metal is generally thicker to improve the heat transfer and conductivity of the electroplated metal), when the metal seed layer 3205 is etched by the whole-surface etching method in this step, although part of the metal plated at the bottom of the back hole 3204 will also be etched, since the thickness of the metal seed layer 3205 is relatively thin, the damage to the metal plated at the bottom of the back hole 3204 is relatively small, and the metal at the bottom of the back hole 3204 still has a relatively thick thickness.

[0152] See also Fig.21 and Fig. 22 , Fig.21 This is a schematic diagram of the structure after the passive matching circuit is deposited. Fig. 22The top view after the passive matching circuit is deposited. The area without metal coverage on the first surface 323 (which can be understood as a non-electroplating area or a passive matching circuit manufacturing area) can be used to manufacture passive devices and passive matching circuits. The passive devices can include at least one of a resistor, a capacitor or an inductor. The passive devices are connected through interconnects to form a passive matching circuit 33.

[0153] Before removing the carrier 3201, the passive matching circuit 33 is made in the non-electroplating area to avoid damaging the power device. The power device is relatively thin, and making the passive matching circuit 33 on the thinner power device is easy to damage the power device. The carrier 3201 can reduce the damage to the power device during the process of making the passive matching circuit 33.

[0154] The conductive member can realize the electrical connection between the passive matching circuit on the first surface 323 and the passive matching circuit or device on the second surface 324 , shortening the connection path between the passive matching circuit and the device and improving the integration of the semiconductor device 30 .

[0155] See also Fig.23 , Fig.23 Schematic diagram of the structure of the power device 32 after the power device 32 and the carrier 3201 are debonded. After the passive matching circuit is formed on the power device, the method for manufacturing the semiconductor device further includes debonding the power device 32 and the carrier 3201 to remove the carrier 3201, and performing subsequent testing, dicing, packaging, taping and other processes. The power device 32 and the carrier 3201 can be debonded by heating the bonding glue or dissolving the bonding glue in a solution.

[0156] The semiconductor device 30 formed by mounting the power device 32 provided with the passive matching circuit 33 on the substrate 31 in the embodiment of the present application has high integration and small size.

[0157] See also Fig.23 and Fig.24 , Fig.24 Schematic diagrams of power device 32 obtained by two different methods. It can be understood that Fig.24 The existing power device 32 in (h1) and the power device 32 in the embodiment of the present application in (h2) are placed on the same plane ( Fig.24 The plane is not shown), and the warping degree of the two power devices 32 is observed.

[0158] Fig.24 The middle (h1) is the existing method of electroplating the entire area of ​​the first surface 323 and the back hole 3204 with metal and debonding from the carrier 3201. Fig.24 In (h2), the embodiment of the present application is to electroplate the partial area of ​​the first surface 323 and the back hole 3204 with metal and debond with the carrier 3201. It can be understood that, Fig.24 The area of ​​metal deposited in (h1) is larger than Fig.24 The area of ​​metal deposited in (h2), Fig.24 The power device 32 in (h1) is more likely to bend or break. Fig.24 The warpage degree of the power device 32 in (h2) is Fig.24 The warping degree of the power device 32 in the middle (h1) is small.

[0159] The embodiment of the present application sets at least part of the passive matching circuit 33 on the first surface 323 of the power device 32, fully utilizes the space of the first surface 323 of the power device 32, can effectively reduce the area occupied by the passive matching circuit 33 on the substrate 31, or can reduce the area occupied by the passive matching circuit 33 on the second surface 324, improves the integration of the semiconductor device 30, is conducive to reducing the overall size of the semiconductor device 30, and realizes the miniaturization of the semiconductor device 30. The embodiment of the present application electroplates metal on a part of the first surface 323 and the back hole 3204 and debonds from the carrier 3201, thereby reducing the warping degree of the power device 32. The embodiment of the present application electroplates metal in the area where metal plating is required, retains photoresist in the area where metal plating is not required, and does not need to etch the plated metal. In this way, when the metal seed layer 3205 is etched by the whole-surface etching method, although the metal plated at the bottom of the back hole 3204 will also be etched, the metal plated at the bottom of the back hole 3204 is less damaged because the thickness of the metal seed layer 3205 is relatively thin.

[0160] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: Including power devices and passive matching circuits; The power device comprises a substrate, an epitaxial layer and a component, wherein the epitaxial layer is deposited on the substrate, a surface of the substrate away from the epitaxial layer is a first surface of the power device, a surface of the epitaxial layer away from the substrate is a second surface of the power device, and the component is located on the second surface; At least part of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

2. The semiconductor device as described in claim 1, wherein the passive matching circuit includes an input matching circuit and an output matching circuit, the input matching circuit is used to input the radio frequency signal into the power device, and the output matching circuit is used to output the radio frequency signal from the power device, at least part of the input matching circuit is located on the first surface, or at least part of the output matching circuit is located on the first surface.

3. The semiconductor device according to claim 1 or 2, wherein: The passive matching circuit includes an inter-stage matching circuit, which is used for transmitting radio frequency signals in the power device, and at least a part of the inter-stage matching circuit is located on the first surface.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The power device includes a conductive member, which extends from the first surface to the second surface, and the conductive member electrically connects the element on the second surface with the passive matching circuit on the first surface, or, part of the passive matching circuit is located on the second surface, and the conductive member electrically connects the passive matching circuit on the second surface with the passive matching circuit on the first surface.

5. The semiconductor device according to claim 2, wherein: The input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the element is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element.

6. The semiconductor device according to claim 2, wherein: The input matching circuit and the output matching circuit are arranged at intervals on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged at intervals in sequence and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit.

7. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the output matching circuit is located on the first surface, the number of the element is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element; Alternatively, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is one, the input matching circuit is electrically connected to the element, and the output matching circuit is electrically connected to the element.

8. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The input matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the output matching circuit is located on the first surface, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are sequentially spaced apart and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit; Or, the input matching circuit is located on the first surface, the output matching circuit is located on the surface of the substrate facing the power device and is spaced apart from the power device, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart and two adjacent elements are electrically connected, the input matching circuit is electrically connected to the first element, and the Nth element is electrically connected to the output matching circuit.

9. The semiconductor device according to claim 2, wherein: The number of the element is one, the input matching circuit comprises a first input part and a second input part which are electrically connected, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the element; Or, the number of the element is one, the output matching circuit includes a first output part and a second output part that are electrically connected, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the element.

10. The semiconductor device according to claim 2, wherein: The number of the elements is N, where N is an integer greater than or equal to 2, and the N elements are respectively a first element to an Nth element, the first element to the Nth element are sequentially arranged at intervals and two adjacent elements are electrically connected, the input matching circuit comprises a first input part and a second input part that are electrically connected, the first input part is located on the first surface, the second input part is located on the second surface, and the second input part is electrically connected to the first element; Or, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart, and two adjacent elements are electrically connected, the output matching circuit includes a first output part and a second output part, the first output part is located on the first surface, the second output part is located on the second surface, and the second output part is electrically connected to the Nth element.

11. The semiconductor device according to claim 2, wherein: The semiconductor device comprises a substrate, the power device is fixed to the substrate, and the first surface is located between the second surface and the substrate; The number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are sequentially arranged at intervals and two adjacent elements are electrically connected, the input matching circuit comprises a first input part, a second input part and the third input part, the first input part is located on the first surface, the second input part is located on the second surface, the second input part is electrically connected to the first element, the second input part is electrically connected to the first input part, the third input part is located on the surface of the substrate facing the power device and is spaced from the power device, and the third input part is electrically connected to the second input part; Or, the number of the elements is N, N is an integer greater than or equal to 2, the N elements are respectively the first element to the Nth element, the first element to the Nth element are arranged in sequence and spaced apart and two adjacent elements are electrically connected, the output matching circuit includes a first output part, a second output part and a third output part, the first output part is located on the first surface, the second output part is located on the second surface, the second output part is electrically connected to the Nth element, the second output part is electrically connected to the first input part, the third output part is located on the surface of the substrate facing the power device and is spaced apart from the power device, and the third output part is electrically connected to the second output part.

12. The semiconductor device according to claim 6, 8, 10 or 11, wherein: The passive matching circuit includes an inter-stage matching circuit, the inter-stage matching circuit is located on the first surface and between the input matching circuit and the output matching circuit, and the inter-stage matching circuit electrically connects two adjacent elements; Alternatively, the passive matching circuit includes an inter-stage matching circuit, the inter-stage matching circuit is located on the second surface and between two adjacent elements, and the inter-stage matching circuit electrically connects the two adjacent elements.

13. The semiconductor device according to any one of claims 2 to 12, characterized in that: The input matching circuit includes at least one of a resistor, a capacitor or an inductor, and the output matching circuit includes at least one of a resistor, a capacitor or an inductor.

14. A method for manufacturing a semiconductor device, used for preparing the semiconductor device according to any one of claims 1 to 13, characterized in that: include: Manufacturing a power device, the power device comprising a substrate, an epitaxial layer and a component, the epitaxial layer being deposited on the substrate, the surface of the substrate facing away from the epitaxial layer being the first surface of the power device, the surface of the epitaxial layer facing away from the substrate being the second surface of the power device, and the component being located on the second surface; A passive matching circuit is formed on the power device, at least a portion of the passive matching circuit is located on the first surface, and the passive matching circuit located on the first surface is electrically connected to the power device.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The steps of manufacturing the power device include: depositing the epitaxial layer on the substrate; forming the element on the second surface; bonding the second surface to a slide; Performing patterning on the substrate and the epitaxial layer to form a back hole, wherein the back hole extends from the first surface to the second surface; Coating a photoresist, patterning the photoresist, exposing and developing the back hole and the remaining electroplating areas, and retaining the photoresist in the non-electroplating area; Electroplating metal in areas not covered by the photoresist; removing the photoresist in the non-plating area; After forming the passive matching circuit on the power device, the method for manufacturing the semiconductor device further includes: removing the carrier.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: During the process of patterning the photoresist, at least two exposure and development processes are performed, and at least two exposure and development process regions partially overlap.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The thickness of the photoresist on the first surface is greater than or equal to 1.2 times the thickness of the metal on the first surface.

18. A power amplifier, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 13.

19. A radio frequency system, characterized in that: It comprises a radio frequency chip and a power amplifier as claimed in claim 18, wherein the radio frequency chip is used to send the radio frequency signal to the power amplifier, and the power amplifier is used to amplify the radio frequency signal.

20. An electronic device, characterized in that: It comprises a signal output device and the radio frequency system as claimed in claim 19, wherein the signal output device is used to send a signal to the radio frequency system, and the radio frequency system is used to amplify the signal.

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