Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. In one example, an electronic device includes: first and second substrates including first and second dielectric structures and first and second conductive structures; a first electronic component over the first substrate, a second substrate over the first substrate and the first electronic component; the first interconnection structure is positioned between the first substrate and the second substrate and is coupled with the first conductive structure and the second conductive structure; a first encapsulation between the first substrate and the second substrate and covering a lateral side of the first interconnect structure and a lateral side of the first electronic component; a second interconnect structure over the second substrate and coupled with the second conductive structure; a second encapsulation over the second substrate and covering lateral sides of the second interconnect structure; and a photonic integrated circuit over the second encapsulation and coupled with the second interconnect structure.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for fabricating semiconductor devices. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will become apparent to those of ordinary skill in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device, comprising: a first substrate, which includes a first dielectric structure and a first conductive structure; a first electronic component, which is located above the first substrate; a second substrate, which includes a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component; a first interconnect structure, which is located between the first substrate and the second substrate, wherein the first interconnect structure is coupled to the first conductive structure and the second conductive structure; a first encapsulation, which is located between the first substrate and the second substrate and covers the lateral side of the first interconnect structure and the lateral side of the first electronic component; a second interconnect structure, which is located above the second substrate and coupled to the second conductive structure; a second encapsulation, which is located above the second substrate and covers the lateral side of the second interconnect structure; and a second electronic component, which is located above the second encapsulation, wherein the second electronic component is coupled to the second interconnect structure, and wherein the second electronic component includes a photonic integrated circuit.

[0004] In the electronic device according to an aspect of the present invention, the second packaging body does not contain any electronic components.

[0005] In the electronic device according to an aspect of the present invention, the second electronic component is located above the first portion of the second enclosure, and the second portion of the second enclosure is not covered by the second electronic component.

[0006] The electronic device according to an aspect of the present invention includes: a dielectric located above the second encapsulation body and between the second encapsulation body and the second electronic component.

[0007] The electronic device according to an aspect of the present invention comprises: a metallization coupled between a component interconnect of the second electronic component and the second interconnect structure; wherein the dielectric covers a lateral side of the metallization; and a portion of the metallization is exposed from the dielectric.

[0008] In the electronic device according to an aspect of the present invention, the first dielectric structure includes a single dielectric stack; and the first conductive structure includes a single conductive stack in the single dielectric stack, wherein the single conductive stack includes an outward terminal.

[0009] In the electronic device according to an aspect of the present invention, the first dielectric structure includes a plurality of dielectric stacks; and the first conductive structure includes a plurality of conductive stacks among the plurality of dielectric stacks.

[0010] In the electronic device according to an aspect of the present invention, a portion of the second electronic component extends beyond a lateral side of the second enclosure.

[0011] In the electronic device according to an aspect of the present invention, the first electronic component includes a component interconnect coupled to the second conductive structure; and the first encapsulation body is located between the first electronic component and the second substrate and covers a lateral side of the component interconnect.

[0012] In the electronic device according to an aspect of the present invention, at least one of the first substrate or the second substrate includes a redistribution layer substrate.

[0013] According to an aspect of the present invention, the electronic device comprises: a base substrate, which comprises a base substrate dielectric structure and a base substrate conductive structure; wherein: the first substrate and the second substrate are located above the base substrate; and the base substrate conductive structure is coupled to the first conductive structure.

[0014] The electronic device according to aspects of the present invention includes: a cover located above the second electronic component; wherein the cover is coupled to a top side of the second electronic component and a top side of the base substrate.

[0015] In the electronic device according to an aspect of the present invention, a portion of the second electronic component extends beyond a lateral side of the cover.

[0016] The electronic device according to an aspect of the present invention comprises: a third electronic component located above the top side of the base substrate; wherein the third electronic component is coupled to the base substrate conductive structure.

[0017] In the electronic device according to an aspect of the present invention, the base substrate includes a preformed substrate.

[0018] Another aspect of the present invention is a method for manufacturing an electronic component, comprising: providing a first substrate, the first substrate comprising a first dielectric structure and a first conductive structure, wherein the first conductive structure comprises an outward terminal; providing a first interconnect structure located above the first substrate, wherein the first interconnect structure is coupled to the first conductive structure; providing a first electronic component located above the first substrate; providing a first encapsulation located above the first substrate and covering the lateral sides of the first interconnect structure and the lateral sides of the first electronic component; providing a second substrate, the second substrate comprising a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component, and the second conductive structure is coupled to the first interconnect structure; providing a second interconnect structure located above the second substrate and coupled to the second conductive structure; providing a second encapsulation located above the second substrate and covering the lateral sides of the second interconnect structure; and providing a second electronic component located above the second encapsulation; wherein the second electronic component is coupled to the second interconnect structure; and wherein the first encapsulation is located between the first electronic component and the second substrate.

[0019] In the method according to another aspect of the present invention, the second electronic component is located above the first portion of the second encapsulation body, and the second portion of the second encapsulation body is not covered by the second electronic component.

[0020] In the method according to another aspect of the present invention, a portion of the second electronic component extends beyond a lateral side of the second enclosure.

[0021] According to another aspect of the present invention, the method described includes: setting a base substrate, the base substrate including a base substrate dielectric structure and a base substrate conductive structure, wherein the base substrate conductive structure includes an inward terminal; wherein: the first substrate and the second substrate are located above the base substrate; and the inward terminal of the base substrate conductive structure is coupled with the outward terminal of the first conductive structure.

[0022] According to another aspect of the invention, the method includes providing a cover over the second electronic component; wherein the cover is coupled to a top side of the second electronic component and a top side of the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A cross-sectional view of an example electronic device is shown.

[0024] Figure 2 A cross-sectional view of an example electronic device is shown.

[0025] FIG. 3A to FIG. 3JA cross-sectional view of an example method for manufacturing an example electronic device is shown.

[0026] Figure 4 A cross-sectional view of an example electronic device is shown.

[0027] Figure 5 A cross-sectional view of an example electronic device is shown.

[0028] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0029] The figures illustrate a general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings are not drawn to scale. For example, the size of some elements in the figures may be exaggerated relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same element symbols in different figures represent the same elements.

[0030] The term "or" means any one or more of the items in the list joined by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0031] The terms "comprises / comprising" and "includes / including" are "open" terms and specify the presence of stated features, but do not exclude the presence or addition of one or more other features. The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0032] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. For example, if element A is coupled to element B, then element A may be in direct contact with element B or indirectly connected to element B through an intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected through one or more other elements. DETAILED DESCRIPTION

[0033] In one example, an electronic device includes: a first substrate including a first dielectric structure and a first conductive structure; a first electronic component located above the first substrate; a second substrate including a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component; a first interconnect structure located between the first substrate and the second substrate, wherein the first interconnect structure is coupled to the first conductive structure and the second conductive structure, a first encapsulation located between the first substrate and the second substrate and covering lateral sides of the first interconnect structure and lateral sides of the first electronic component; a second interconnect structure located above the second substrate and coupled to the second conductive structure; a second encapsulation located above the second substrate and covering lateral sides of the second interconnect structure; and a second electronic component located above the second encapsulation, wherein the second electronic component is coupled to the second interconnect structure, and wherein the second electronic component includes a photonic integrated circuit (PIC).

[0034] In another example, a method of manufacturing an electronic component includes: providing a first substrate, the first substrate including a first dielectric structure and a first conductive structure, wherein the first conductive structure includes an outward terminal; providing a first interconnect structure located above the first substrate, wherein the first interconnect structure is coupled to the first conductive structure; providing a first electronic component located above the first substrate; providing a first encapsulation located above the first substrate and covering a lateral side of the first interconnect structure and a lateral side of the first electronic component; providing a second substrate, the second substrate including a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component, and the second conductive structure is coupled to the first interconnect structure; providing a second interconnect structure located above the second substrate and coupled to the second conductive structure; providing a second encapsulation located above the second substrate and covering a lateral side of the second interconnect structure; and providing a second electronic component located above the second encapsulation. The second electronic component is coupled to the second interconnect structure, and the first encapsulation is located between the first electronic component and the second substrate.

[0035] Other examples are included in the present disclosure. Such examples can be found in the drawings, claims or description of the present disclosure.

[0036] Figure 1 A cross-sectional view of an example electronic device 100 is shown. Figure 1In the example shown in , electronic device 100 may include electronic component 110, substrate 120, substrate 130, encapsulation 140, encapsulation 150, interconnect structure 160, interconnect structure 170, external interconnect 180, dielectric or dielectric structure 190 (optional) and metallization 191 (optional). In some examples, substrate 120, substrate 130, or both may include a redistribution layer (RDL) substrate or a preformed substrate.

[0037] Electronic component 110 may include component interconnect 111 and component attach material 115. Substrate 120 may include dielectric structure 121 and conductive structure 122. Conductive structure 122 of substrate 120 may include trace 1221, via 1222, inward terminal 1223, and outward terminal 1224. Substrate 130 may include dielectric structure 131 and conductive structure 132. Conductive structure 132 of substrate 130 may include trace 1321, via 1322, inward terminal 1323, and outward terminal 1324. In some examples, electronic component 110 may be located above substrate 120, and substrate 130 may be located above substrate 120. In some examples, interconnect structure 160 may be located between substrate 120 and substrate 130, and may be coupled with conductive structure 122 and conductive structure 132. In some examples, encapsulation 140 may be located between substrate 120 and substrate 130, and may cover lateral sides of interconnect structure 160 or lateral sides of electronic component 110. In some examples, interconnect structure 170 may be located above substrate 130 and may be coupled with conductive structure 132. In some examples, encapsulation 150 may be located above substrate 130 and may cover lateral sides of interconnect structure 170. In some examples, encapsulation 140 may contain electronic component 110, and encapsulation 150 may not contain electronic component. In some examples, dielectric structure 121 or dielectric structure 131 may include one or more stacks of dielectric materials, and conductive structure 122 or conductive structure 132 may include one or more stacks of conductive materials. In some examples, electronic component 110 includes component interconnect 111 coupled with conductive structure 132. The encapsulation body 140 may be located between the electronic component 110 and the substrate 130 , and may cover lateral sides of the component interconnects 111 .

[0038] Substrate 120, substrate 130, encapsulation 140, encapsulation 150, interconnect structure 160, interconnect structure 170, external interconnect 180, dielectric structure 190 (optional), and metallization 191 (optional) may be referred to as an electronic package and may provide protection from external elements or environmental exposure to electronic component 110. The electronic package may provide coupling to external electrical components through external interconnect 180.

[0039] Figure 2A cross-sectional view of an example electronic device 100A is shown. Figure 2 In the example shown in FIG. , the electronic device 100A may be similar to Figure 1 , except that substrate 120A includes dielectric structure 121A including a single layer of dielectric material, and substrate 120A includes conductive structure 122A including a single layer of conductive material. In some examples, conductive structure 122A may include outward terminal 1224A as a single layer of conductive material. It should be noted that although the following description of Figures 3A to 3J Demonstrated and described manufacturing Figure 2 The method of the electronic device 100A, but Figure 1 The electronic device 100 shown in FIG. 1 can also be manufactured by a similar manufacturing method.

[0040] FIG. 3A to FIG. 3J A cross-sectional view of an example method for manufacturing electronic device 100A is shown. Figure 3A A cross-sectional view of an electronic device 100A is shown in an early stage of manufacture. Figure 3A In the example shown in , a support carrier 10 may be provided. In some examples, the support carrier 10 may be provided in the form of a circular wafer or a rectangular panel. In some examples, the support carrier 10 may include silicon, glass, ceramic or metal.

[0041] Figure 3B A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3BIn the example shown in , the substrate 120A may be disposed on the support carrier 10. As described above, the substrate 120A may include a dielectric structure 121A and a conductive structure 122A. In some examples, the dielectric structure 121A may be disposed on the support carrier 10 in a first operation, and the conductive structure 122A may be disposed on the support carrier 10 in a subsequent operation. In some examples, the conductive structure 122A may be disposed on the support carrier 10 in a first operation, and the dielectric structure 121A may be disposed on the support carrier 10 in a subsequent operation. In some examples, the dielectric structure 121A may include or be referred to as one or more dielectric layers or dielectric stacks. In some examples, the dielectric structure 121A may be disposed on the support carrier 10 by coating, laminating, or depositing polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), resin, or Ajinomoto build-up film (ABF). In some examples, the conductive structure 122A may include or be referred to as one or more conductive layers, conductive stacks, traces, vias, pads, conductive paths, or under bump metal (UBM). In some examples, the conductive structure 122A may be provided by plating or depositing copper, copper alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy, or tin-silver. As described above, the conductive structure 122A may include an outward terminal 1224A. The outward terminal 1224A may include or be referred to as a pad, a pad, or a UBM. In some examples, the top side of the outward terminal 1224A may be coplanar with the top side of the dielectric structure 121A. In some examples, the bottom side of the outward terminal 1224A may be coplanar with the bottom side of the dielectric structure 121A. The thickness of the substrate 120A including the dielectric structure 121A and the conductive structure 122A may be in the range of about 2 micrometers (μm) to about 30 μm. The substrate 120A may support the electronic component 110 , the encapsulation 140 , or the interconnection structure 160 , and may couple the interconnection structure 160 to an external device.

[0042] Figure 3C A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3CIn the example shown in , the interconnect structure 160 may be disposed on the substrate 120A. In some examples, the interconnect structure 160 may include a bottom side, a lateral side, and a top side. A portion of the bottom side of the interconnect structure 160 may be coupled to the outward terminal 1224A of the conductive structure 122A, and another portion of the bottom side of the interconnect structure 160 may contact the top side of the dielectric structure 121A. In some examples, the interconnect structure 160 may be disposed around the electronic component 110, where the electronic component 110 is disposed at a later stage or operation. In some examples, the one or more interconnect structures 160 of the first group may be disposed on one lateral side of the electronic component 110, and the one or more interconnect structures 160 of the second group may be disposed on another lateral side of the electronic component 110, where the electronic component 110 is disposed at a later stage or operation. The interconnect structure 160 may include or be referred to as a column, a pillar, a through mold via (TMV), a ball-type structure such as a copper core solder ball (CCB), a solder ball or a copper cube column (CCC), or a wire. In some examples, the interconnect structure 160 may include copper, copper alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy, or tin silver. The interconnect structure 160 may be arranged in any of a variety of ways. In some examples, the interconnect structure 160 may be plated on the outward terminal 1224A of the conductive structure 122A. In some examples, the interconnect structure 160 may be printed and reflowed or wire bonded. In some examples, the thickness of the interconnect structure 160 may be greater than the thickness of the electronic component 110 to be arranged at a later stage. The thickness of the interconnect structure 160 may be in the range of about 38 μm to about 840 μm. The thickness of the interconnect structure 160 may depend on the resolution of the photoresist used in the photolithography process, and the higher the resolution of the photoresist, the higher the thickness or height of the interconnect structure 160. The interconnect structure 160 may couple the substrate 130 disposed at a later stage to the substrate 120A.

[0043] Figure 3D A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3D In the example shown in , the electronic component 110 may be disposed on the substrate 120A. The electronic component 110 may be disposed on a portion of the substrate 120A that does not contain the interconnect structure 160. The electronic component 110 may include a top side, a bottom side opposite the top side, and a lateral side connecting the top side and the bottom side. In some examples, the top side may include an active side, and the bottom side may include an inactive side. In some examples, the component interconnect 111 may be disposed on the top side of the electronic component 110, and the component attach material 115 may be disposed on the bottom side of the electronic component 110. In some examples, the electronic component 110 may be attached to the substrate 120A by the component attach material 115.

[0044] In some instances, the electronic component 110 may include or be referred to as an electronic integrated circuit (EIC), a semiconductor die, a semiconductor chip, a semiconductor package, or a stacked structure. In some instances, the die or chip may include an integrated circuit die separated from a semiconductor wafer. In some instances, the electronic component 110 may include a transimpedance amplifier (TIA), a laser diode driver (LD-DRV), a digital signal processor (DSP), a network processor, a power management unit, an audio processor, a radio-frequency (RF) circuit, a wireless baseband system-on-chip (SoC) processor, a sensor, or an application specific integrated circuit (ASIC). The thickness of the electronic component 110 may be less than the thickness of the interconnect structure 160. The thickness of the electronic component 110 may be in the range of about 30 μm to about 780 μm.

[0045] In some examples, component interconnects 111 may include or be referred to as bumps, pads, columns, pillars, through-mold vias (TMVs), ball structures (CCBs or CCCs), or wires. In some examples, component interconnects 111 may include copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, nickel, nickel alloys, palladium, palladium alloys, or tin-silver. Component interconnects 111 may be provided in any of a variety of ways. In some examples, component interconnects 111 may be plated on the top side of electronic component 110. In some examples, component interconnects 111 may be printed and reflowed or wire bonded. In some examples, the thickness of component interconnects 111 may be less than the thickness of interconnect structure 160. The thickness of component interconnects 111 may be in the range of about 3 μm to about 35 μm. Component interconnects 111 may couple electronic component 110 to substrate 130 to be provided at a later stage.

[0046] In some examples, the component attach material 115 may include or be referred to as an adhesive film or adhesive paste. In some examples, the component attach material 115 may be first disposed on the top side of the substrate 120A, and then the electronic component 110 may be attached to the component attach material 115. In some examples, the component attach material 115 may be first disposed on the bottom side of the electronic component 110, and then the electronic component 110 may be attached to the substrate 120A. The thickness of the component attach material 115 may be in the range of about 5 μm to about 25 μm. The component attach material 115 may stably fix the electronic component 110 on the substrate 120A.

[0047] Figure 3E A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3E In the example shown in , an encapsulant 140 may be provided. In some examples, the encapsulant 140 may surround, cover, or contact the substrate 120A, the interconnect structure 160, the electronic component 110, the component interconnect 111, or the component attachment material 115. In some examples, the encapsulant 140 may cover the top side of the substrate 120A. In some examples, the encapsulant 140 may cover the top side or the lateral side of the interconnect structure 160. In some examples, the encapsulant 140 may cover the top side or the lateral side of the electronic component 110. In some examples, the encapsulant 140 may cover the top side or the lateral side of the component interconnect 111. In some examples, the encapsulant 140 may cover the lateral side of the component attachment material 115. The encapsulant 140 may include or be referred to as an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film, or a gel. In some examples, the encapsulant 140 may include an epoxy resin or a phenolic resin, carbon black, or a silica filler. In some examples, the encapsulant 140 may be provided by compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, or film-assisted molding. Compression molding may be a process in which a fluid resin is supplied to a mold in advance, and then the electronic component is placed in the mold to cure the fluid resin, and transfer molding may be a process in which the fluid resin is cured by supplying it from a gate or supply port of the mold to the periphery of the corresponding electronic component. The thickness of the encapsulant 140 may be in the range of about 38 μm to about 840 μm. The encapsulant 140 may protect the electronic component 110 and the interconnect structure 160 from external factors or environmental exposure, and may quickly dissipate heat from the electronic component 110.

[0048] In some examples, the thickness of the encapsulant 140 may be set to be greater than the final desired thickness. In such examples, the encapsulant 140 may be ground or otherwise thinned or planarized. Figure 3EIn the example shown in , the encapsulant 140 has been ground to produce the encapsulant 140. The top surface of the ground or thinned or planarized encapsulant 140 may be coplanar with the top surface of the interconnect structure 160 or the component interconnect 111, wherein the top surface of the interconnect structure 160 or the top surface of the component interconnect 111 is exposed from the encapsulant 140.

[0049] Figure 3F A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3F In the example shown in , the substrate 130 may be disposed on the electronic component 110, the encapsulation 140, and the interconnect structure 160. As described above, the substrate 130 may include a dielectric structure 131 and a conductive structure 132. In some examples, the dielectric structure 131 may be disposed on or in contact with the top side or top surface of the encapsulation 140 or the top side or top surface of the interconnect structure 160. In some examples, the dielectric structure 131 may be disposed on or in contact with the top side or top surface of the encapsulation 140 or the top side or top surface of the component interconnect 111. In some examples, the dielectric structure 131 may be disposed, and then the conductive structure 132 may be disposed. In some examples, the conductive structure 132 may be disposed, and then the dielectric structure 131 may be disposed. In some examples, the dielectric structure 131 and the conductive structure 132 may include a multilayer structure. In some examples, the conductive structures 132 may be interlaced between the dielectric structures 131. In some examples, the dielectric structures 131 may be interlaced between the conductive structures 132. In some examples, the dielectric structures 131 may include or be referred to as one or more dielectric layers or dielectric stacks. In some examples, the dielectric structures 131 may be provided by coating, laminating, or depositing PI, BCB, PBO, resin, or ABF. In some examples, the conductive structures 132 may include or be referred to as one or more conductive layers, traces, vias, pads, conductive paths, or UBMs. In some examples, the conductive structures 132 may be provided by plating or depositing copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, nickel, nickel alloys, palladium, palladium alloys, or tin-silver.

[0050] As described above, the conductive structure 132 may include a trace 1321, a via 1322, an inward terminal 1323, or an outward terminal 1324. In some examples, the trace 1321 may include or be referred to as an RDL pattern or a horizontal pattern, and may carry an electrical signal in the horizontal direction. The thickness of the trace 1321 may be in the range of about 2 μm to about 30 μm. In some examples, the via 1322 may include or be referred to as an RDL pattern or a vertical pattern, and may carry an electrical signal in the vertical direction. The thickness of the via 1322 may be in the range of about 2 μm to about 30 μm. The diameter of the via 1322 may be in the range of about 2 μm to about 300 μm. The via 1322 may couple the upper trace and the lower trace. The thickness of the inward terminal 1323 may be in the range of about 2 μm to about 30 μm. The diameter of the inward terminal 1323 may be in the range of about 2 μm to about 300 μm. One or more of the inward terminals 1323 may be coupled to the interconnect structure 160. One or more of the inward terminals 1323 may be coupled to the component interconnect 111. In some examples, the top side of the outward terminals 1324 may be coplanar with the top side of the dielectric structure 131. The thickness of the outward terminals 1324 may be in the range of about 2 μm to about 30 μm. The diameter of the outward terminals 1324 may be in the range of about 2 μm to about 300 μm. The outward terminals 1324 may be coupled to the interconnect structure 170 to be provided at a later stage.

[0051] The total thickness of substrate 130 including dielectric structure 131 and conductive structure 132 may be in a range of about 24 μm to about 360 μm. In some examples, substrate 130 may couple interconnect structure 160 to interconnect structure 170 , where interconnect structure 170 is provided at a later stage or operation.

[0052] In some examples, substrate 130 may include a single layer or a single stacked structure similar to substrate 120A. In some examples, substrate 130 may include a multi-layer or multi-stacked structure similar to substrate 120.

[0053] In some examples, substrate 120 or substrate 130 may include one or more conductive redistribution layers and one or more dielectric layers or dielectric stacks that may be formed layer by layer over the electronic device to which the RDL substrate is to be coupled, or may be formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer on a circular wafer as a wafer-level substrate in a wafer-level process, or layer by layer on a rectangular or square panel carrier as a panel-level substrate in a panel-level process. The RDL substrate may be formed by an additive stacking process, and the RDL substrate may include one or more dielectric layers or dielectric stacks alternately stacked with one or more conductive layers defining corresponding conductive redistribution patterns or traces, and the conductive redistribution patterns or traces are configured to collectively fan out the electrical traces from the occupied space of the electronic device, or fan the electrical traces into the occupied space of the electronic device. The conductive pattern may be formed using a plating process, such as, for example, an electroplating process or an electroless plating process. The conductive pattern may include a conductive material, such as, for example, copper or other plateable metals. The location of the conductive pattern can be made using a photopatterning process such as, for example, a photolithography process and a photoresist material to form a photolithography mask. The dielectric layer or dielectric stack of the RDL substrate can be patterned using a photopatterning process and can include a photolithography mask through which light is exposed to the desired features of the photopattern, such as through holes in the dielectric layer or dielectric stack. Therefore, the dielectric layer or dielectric stack can be made of a photodefinable organic dielectric material such as, for example, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), resin, or Ajinomoto stacked film (ABF). Such dielectric materials can be spin-coated or otherwise applied in liquid form rather than attached in preformed film form. In order to allow the desired photodefinable features to be properly formed, such photodefinable dielectric materials can omit structural enhancers or can be filler-free, without strands, fabrics, or other particles that can interfere with the light from the photopatterning process. In some examples, such unfilled characteristics of unfilled dielectric materials may allow the thickness of the resulting dielectric layer to be reduced. Although the photo-definable dielectric material described above may be an organic material, in other examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers or dielectric stacks. Some examples of one or more inorganic dielectric layers or dielectric stacks may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). One or more inorganic dielectric layers or dielectric stacks may be formed by growing inorganic dielectric layers or dielectric stacks using an oxidation or nitridation process rather than using a photo-defined organic dielectric material. Such inorganic dielectric layers or dielectric stacks may be unfilled, without strands, fabrics, or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as, for example, a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.

[0054] Figure 3G A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3G In the example shown in , the interconnect structure 170 may be disposed on the substrate 130. In some examples, the interconnect structure 170 may include a bottom side, a top side opposite to the bottom side, and a lateral side connecting the bottom side and the top side. A portion of the bottom side of the interconnect structure 170 may be coupled to the outward terminal 1324 of the conductive structure 132, and another portion of the bottom side of the interconnect structure 170 may contact the top side of the dielectric structure 131. In some examples, the interconnect structure 170 may be arranged on the top side of the substrate 130. The interconnect structure 170 may include or be referred to as a column, a pillar, a TMV, a ball structure (CCB or CCC), or a wire. In some examples, the interconnect structure 170 may include copper, copper alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy, or tin-silver. The interconnect structure 170 may be disposed in any of a variety of ways. In some examples, the interconnect structure 170 may be plated on the outward terminal 1324 of the conductive structure 132. In some examples, the interconnect structure 170 may be printed and reflowed or wire bonded. The thickness of the interconnect structure 170 may be in the range of about 38 μm to about 840 μm. The thickness of the interconnect structure 170 may depend on the resolution of the photoresist used in the photolithography process, and the higher the resolution of the photoresist, the higher the thickness or height of the interconnect structure 170 may be. The interconnect structure 170 may couple an external device (e.g., a photonic integrated circuit (PIC)) to be set at a later stage or operation to the RDL substrate.

[0055] Figure 3H A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3HIn the example shown in , an encapsulant 150 may be provided. In some examples, the encapsulant 150 may surround, cover or contact the substrate 130 or the interconnect structure 170. In some examples, the encapsulant 150 may cover the top side of the substrate 120A. In some examples, the encapsulant 150 may cover the top side or lateral side of the interconnect structure 170. The encapsulant 150 may include or be referred to as an epoxy molding compound, a resin, a filler-reinforced polymer, a B-stage pressed film or a gel. In some examples, the encapsulant 150 may include an epoxy resin or a phenolic resin, carbon black or a silica filler. In some examples, the encapsulant 150 may be provided by compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing or film-assisted molding. The thickness of the encapsulant 150 may be in the range of about 38 μm to about 840 μm. The encapsulant 150 may protect the substrate 130 and the interconnect structure 170 from external factors or environmental exposure. In some examples, the encapsulation 140 may contain the electronic component 110, and the encapsulation 150 may not contain the electronic component. In some examples where the electronic component such as the PIC is coupled to the top side of the interconnection structure 170 in the form of an overhanging fan-out structure, peeling or cracking of the substrate 130 may be mitigated or prevented by the encapsulation 150. Since the double-molded structure is respectively provided on the top side of the substrate 130 and the bottom side of the substrate 130, the rigidity of the substrate 130 may be enhanced, and thus peeling or cracking of the substrate 130 may be mitigated or prevented. In some examples where the electronic component is coupled to the interconnection structure 170 in the form of an overhanging fan-out structure, the encapsulation 150 may be coupled to the top side of the substrate 130 and the bottom side of the substrate 130. Figure 4 and will be described in detail below.

[0056] In some examples, the initial thickness of the encapsulant 150 may be greater than the final desired thickness. In such examples, the encapsulant 150 may be ground or otherwise thinned or planarized to set the desired thickness. Figure 3H In the example shown in , the encapsulant 150 has been ground to produce the encapsulant 150. The top side of the ground or thinned or planarized encapsulant 150 may be coplanar with the top surface of the interconnect structure 170, and the top side of the interconnect structure 170 is exposed from the encapsulant 150.

[0057] In some examples, dielectric 190 and metallization 191 may be disposed on the top side of interconnect structure 170 exposed by encapsulation 150. In some examples, materials such as copper-nickel-gold (Cu / Ni / Au) alloy, copper-nickel-solder (Cu / Ni / Cu / solder) alloy, copper-solder (Cu / solder) alloy, organic solderability preservative (Cu / OSP), electroless nickel / immersion gold (Cu / ENIG), electroless nickel / electroless palladium / immersion gold Cu / immersion silver (Cu / ENEPIG), or Cu / immersion tin may optionally be disposed on the top side of interconnect structure 170.

[0058] Fig. 3IA cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Fig. 3I In the example shown in , a support carrier 20 may be provided, and the support carrier 10 may be removed. In some examples, the support carrier 20 may be referred to as a wafer support system. In some examples, the wafer support system 20 may be attached to the encapsulation 150 or the interconnect structure 170 by a temporary adhesive 21. The temporary adhesive 21 may lose viscosity due to heat or light later. The support carrier 10 may be removed in any of various ways. In some examples, the support carrier 10 may be removed from the substrate 120A by grinding or etching. In some examples, if a temporary adhesive that loses viscosity due to heat or light is inserted between the support carrier 10 and the substrate 120A, the support carrier 10 may be removed from the substrate 120A by providing heat or light. In some examples, the support carrier 10 may be forcibly separated from the substrate 120A. After removing the support carrier 10, the dielectric structure 121A and the outward terminal 1224A of the (optional) substrate 120A may be exposed.

[0059] Figure 3J A cross-sectional view of electronic device 100A is shown in a later stage of manufacturing. Figure 3J In the example shown in , the external interconnect 180 may be disposed on the substrate 120A. In some examples, the external interconnect 180 may be coupled to the bottom side of the outward terminal 1224A. In some examples, the external interconnect 180 may include a top side, a bottom side opposite the top side, and a lateral side connected to the top side and the bottom side. In some examples, a portion of the top side of the external interconnect 180 may be coupled to the bottom side of the outward terminal 1224A, and another portion of the top side of the external interconnect 180 may contact the bottom side of the dielectric structure 121A. In some examples, the external interconnect 180 may include or be referred to as a column, a pillar, a pad, a bump, a solder bump, a solder ball, or a column with a solder cap. In some examples, external interconnect 180 may include tin, silver, lead, copper, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the thickness of external interconnect 180 may be in a range of about 20 μm to about 600 μm. External interconnect 180 may be used to couple electronic device 100A to an external device.

[0060] In some examples, a singulation process may be optionally performed. In some examples, the singulation process may be performed by a cutting wheel or a laser beam. In some examples, when the electronic device 100A is manufactured in a form having rows or columns, the electronic device 100A may be separated into individual electronic devices 100A by a singulation or sawing process. In some examples, individual electronic devices 100A may be arranged by sawing the substrate 120A, the encapsulation 140, the substrate 130, and the encapsulation 150 using a cutting wheel. Therefore, the lateral sides of the substrate 120A, the encapsulation 140, the substrate 130, and the encapsulation 150 may be coplanar.

[0061] Figure 4 A cross-sectional view of an example electronic device 200 is shown. Figure 4 In the example shown in , the electronic device 200 may include an electronic component 110, a substrate 120A, a substrate 130, an encapsulation 140, an encapsulation 150, an interconnect structure 160, an interconnect structure 170, an external interconnect 180, and an electronic component 210A. In some examples, the electronic component 210A may include or be referred to as a photonic integrated circuit (PIC), an integrated optical circuit, a semiconductor die, a semiconductor chip, a semiconductor package, or a stacked structure. The thickness of the electronic component 210A may be in the range of about 20 μm to about 1000 μm. In some examples, the photonic integrated circuit or integrated optical circuit 210A may be a microchip containing two or more photonic components forming a functional circuit. The photonic integrated circuit 210A may detect, generate, receive, transmit, or process light. The photonic integrated circuit 210A may utilize photons or particles or light beams instead of electrons that may be utilized by electronic integrated circuits. The photonic integrated circuit 210A may use wavelengths of light that are typically in the visible spectrum or near infrared to provide functionality for information signals. In some examples, the photonic integrated circuit 210A can be located above the encapsulation 150 and can be coupled with the interconnect structure 170. The encapsulation 150 can be free of any electronic components.

[0062] In some examples, the electronic component 210A may include a component interconnect 211A. In some examples, the component interconnect 211A may include or be referred to as a bump, a pad, a column, a pillar, a ball-type structure (CCB, CCC) or a wire. In some examples, the component interconnect 211A may include a Cu / solder alloy, a Cu / Ni / Cu / solder alloy or a Cu / Ni / solder alloy. The component interconnect 211A may be provided in any of a variety of ways. In some examples, the component interconnect 211A may be plated on the bottom side of the electronic component 210A. In some examples, the component interconnect 211A may be printed and reflowed or wire bonded. The thickness of the component interconnect 211A may be in the range of about 20 μm to about 300 μm. The component interconnect 211A may couple the electronic component 210A to the metallization 191 by solder. In some examples, the primer 230A may be provided or inserted between the component interconnect 211A and the dielectric 190. In some examples, the underfill 230A may include or be referred to as a capillary underfill (CUF), a non-conductive pasted (NCP), a non-conductive film (NCF), or an anisotropic conductive film (ACF). In some examples, after the electronic component 210A is coupled to the metallization 191, the underfill 230A may be injected into the gap between the electronic component 210A and the dielectric 190. In some examples, before the electronic component 210A is coupled to the metallization 191, the underfill 230A may be pre-applied to the dielectric 190. Thus, the component interconnect 211A may penetrate the underfill 230A to be coupled to the metallization 191. In some examples, before the electronic component 210A is coupled to the metallization 191, the underfill 230A may be pre-applied to the electronic component 210A. Thus, electronic component 210A may pressurize underfill 230A, and simultaneously component interconnect 211A may be coupled to metallization 191. In some examples, a curing process of underfill 230A may be performed, for example, using a thermal curing process or a photocuring process.

[0063] In some instances, such as Figure 4, the electronic component 210A can be coupled to the metallization 191 in an overhanging configuration. In some instances, the electronic component 210A is located above a first portion of the enclosure 150, and a second portion of the enclosure 150 is not covered by the second electronic component 210A. In some instances, a portion of the electronic component 210A extends beyond a lateral side of the enclosure 150. In some instances, an optical fiber can be coupled to the electronic component 210A, such as to an extended portion of the electronic component 210A. In some instances, another portion of the electronic component 210A can be located above the dielectric 190. In some instances, the dielectric 190 can be located above the enclosure 150 and can be located between the enclosure 150 and the electronic component 210A. In some instances, the external interconnect 180 can be provided after the electronic component 210A is coupled to the metallization 191, such as where the external interconnect 180 is provided by solder ball attachment. In some examples where there is an overhang arrangement of the electronic component 210A, the encapsulation 150 is located on the top side of the substrate 130 and the encapsulation 140 is located on the bottom side of the substrate 130 to prevent or reduce peeling or cracking of the substrate 130. In some examples, the metallization 191 may be coupled between the component interconnect 211A and the interconnect structure 170. In some examples, the dielectric 190 covers the lateral sides of the metallization 191, and a portion of the metallization 191 is exposed from the dielectric 190. In some examples, the electronic device 200 may be referred to as an optical engine structure for co-packaged optics (CPO). In some examples, the connection component 211A may have one or more grooves or sockets on one or more sides to couple with one or more optical fibers, optical cables, optical waveguides, or optical transmission lines.

[0064] Figure 5 A cross-sectional view of an example electronic device 200A is shown. Figure 5 In the example shown in Figure 4 In addition to the electronic device 200 shown, the electronic device 200A may include a connection component 210B, a base substrate 220, an underfill material 230A, an underfill material 230B, a cover 250, and a base interconnect 260. In some examples, the electronic device 100 or 100A may first be coupled to the base substrate 220, and then the electronic component 210A may subsequently be coupled to the electronic device 100 or 100A as an optional process flow.

[0065] The connection component 210B may include or be referred to as clock and data recovery (CDR). The thickness of the connection component 210B may be in the range of about 20 μm to about 1000 μm. In some instances, the connection component 210B may include a component interconnect 211B. In some instances, the component interconnect 211B may include or be referred to as a bump, a pad, a column, a column, a ball-type structure (CCB, CCC) or a wire. In some instances, the component interconnect 211B may include copper, copper alloy, copper / solder alloy, solder alloy, aluminum, aluminum alloy, gold, gold alloy, silver, silver alloy, nickel, nickel alloy, palladium, palladium alloy or tin-silver. The component interconnect 211B may be set in any of various ways. In some instances, the component interconnect 211B may be plated on the bottom side of the connection component 210B. In some instances, the component interconnect 211B may be printed and reflowed or wire bonded. The thickness of component interconnect 211B may be in a range of about 1 μm to about 600 μm. Component interconnect 211B may allow connection component 210B to be coupled to base substrate 220. In some examples, connection component 210 may be located on or above the top side of base substrate 220, and connection component 210 may be coupled with conductive structure 222.

[0066] Base substrate 220 may include dielectric structure 221 and conductive structure 222. In some examples, substrate 120 and substrate 130 are located above base substrate 220, and conductive structure 222 is coupled to conductive structure 122. In some examples, dielectric structure 221 may include one or more dielectric layers or dielectric stacks. Dielectric layers or dielectric stacks may include one or more dielectric material layers or stacks interlaced with layers or stacks of conductive structures. In some examples, the dielectric material may include PI, BCB, PBO, resin, or ABF. In some examples, conductive structure 222 may include one or more conductive layers defining signal distribution elements, such as traces, vias, pads, conductive paths, or UBMs. Conductive structure 222 may include traces 2221, vias 2222, inward terminals 2223, and outward terminals 2224. In some examples, trace 2221 may include or be referred to as a pattern or horizontal pattern, and may carry electrical signals in a horizontal direction. The thickness of the trace 2221 may be in the range of about 3 μm to about 30 μm. In some examples, the through hole 2222 may include or be referred to as a pattern or a vertical pattern, and may carry an electrical signal in the vertical direction. The thickness of the through hole 2222 may be in the range of about 3 μm to about 1200 μm. The diameter of the through hole 2222 may be in the range of about 20 μm to about 500 μm. The through hole 2222 may couple the upper trace and the lower trace. In some examples, the inward terminal 2223 may include or be referred to as a pad, a pad, a UBM, or a stud. The thickness of the inward terminal 2223 may be in the range of about 5 μm to about 30 μm. The diameter of the inward terminal 2223 may be in the range of about 20 μm to about 200 μm. The outward terminal 2224 may include or be referred to as a pad, a pad, a UBM, or a stud. The thickness of the outward terminal 2224 may be in the range of about 5 μm to about 30 μm. The diameter of the outward terminal 2224 may be in the range of approximately 100 μm to 1000 μm.

[0067] In some examples, base substrate 220 may be a preformed substrate. The preformed substrate may be manufactured before being attached to an electronic device, and may include a dielectric layer or dielectric stack located between corresponding conductive layers or conductive stacks. The conductive layer or conductive stack may include copper and may be formed using an electroplating process. The dielectric layer or dielectric stack may be a relatively thick non-photodefinable layer and may be attached in a preformed film form rather than in a liquid form, and may include a resin with fillers such as strands, fabrics or other inorganic particles for rigidity or structural support. Since the dielectric layer or dielectric stack is non-photodefinable, features such as through holes or openings may be formed by using drilling or lasers. In some examples, the dielectric layer or dielectric stack may include a prepreg material or an Ajinomoto stacked film (ABF). The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, for example, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before being attached to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. This preformed substrate may be formed by a semi-build-up or modified semi-build-up process.

[0068] In some examples, the external interconnect 180 of the electronic device 200 may be coupled to one or more inward terminals 2223 of the base substrate 220. In some examples, the component interconnect 211B of the connection component 210B may be coupled to one or more inward terminals 2223 of the base substrate 220.

[0069] In some examples, the primer material 230 may be disposed between the electronic device 200 and the base substrate 220. In some examples, the primer material 230B may be disposed between the connection component 210B and the base substrate 220.

[0070] The base interconnect 260 may include a solder ball, a bump, a pad, or a pillar. The base interconnect 260 may be coupled to the outward terminals 2224 of the base substrate 220. In some examples, a land grid array (LGA) may also be an example design.

[0071] In some examples, the cover 250 can be disposed on or above the electronic component 210A and the base substrate 220 by thermal adhesive 240A and thermal adhesive 240B. In some examples, the cover 250 can be coupled to the top side of the base substrate 220 with thermal adhesive 240b, and the cover can be coupled to the top side of the electronic component 210A with thermal adhesive 240A. A portion of the electronic component 210A can extend beyond the lateral side of the cover 250. The cover 250 can include or be referred to as a heat spreader, a cover, a housing, or a shell. The cover 250 can include aluminum, an aluminum alloy, copper, or a copper alloy. The thickness of the cover 250 can be in the range of about 0.1 millimeters (mm) to about 10 mm. The cover 250 can not only dissipate heat from the electronic device 200A but also protect the electronic device 200A from the external environment.

[0072] The present disclosure includes reference to certain examples. However, it will be appreciated by those of ordinary skill in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, the disclosed examples may be modified without departing from the scope of the present disclosure. Therefore, it is intended that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples falling within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: include: a first substrate comprising a first dielectric structure and a first conductive structure; a first electronic component located above the first substrate; a second substrate including a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component; a first interconnect structure disposed between the first substrate and the second substrate, wherein the first interconnect structure is coupled to the first conductive structure and the second conductive structure; a first encapsulant located between the first substrate and the second substrate and covering a lateral side of the first interconnect structure and a lateral side of the first electronic component; a second interconnect structure located above the second substrate and coupled to the second conductive structure; a second encapsulant located above the second substrate and covering lateral sides of the second interconnect structure; and A second electronic component is located over the second encapsulation, wherein the second electronic component is coupled to the second interconnect structure, and wherein the second electronic component comprises a photonic integrated circuit.

2. The electronic device according to claim 1, wherein: The second enclosure does not contain any electronic components.

3. The electronic device according to claim 1, wherein: The second electronic component is located above the first portion of the second enclosure, and the second portion of the second enclosure is not covered by the second electronic component.

4. The electronic device according to claim 1, characterized in that: include: A dielectric is located above the second packaging body and between the second packaging body and the second electronic component.

5. The electronic device according to claim 4, characterized in that: include: a metallization coupled between a component interconnect of the second electronic component and the second interconnect structure; wherein the dielectric covers lateral sides of the metallization; and A portion of the metallization is exposed from the dielectric.

6. The electronic device according to claim 1, characterized in that: The first dielectric structure comprises a single dielectric stack; and The first conductive structure includes a single conductive stack in the single dielectric stack, wherein the single conductive stack includes an outward terminal.

7. The electronic device according to claim 1, characterized in that: The first dielectric structure includes a plurality of dielectric stacks; and The first conductive structure includes a plurality of conductive stacks among the plurality of dielectric stacks.

8. The electronic device according to claim 1, characterized in that: A portion of the second electronic component extends beyond a lateral side of the second enclosure.

9. The electronic device according to claim 1, characterized in that: The first electronic component includes a component interconnect coupled to the second conductive structure; and The first encapsulant is located between the first electronic component and the second substrate and covers lateral sides of the component interconnects.

10. The electronic device according to claim 1, characterized in that: At least one of the first substrate or the second substrate includes a redistribution layer substrate.

11. The electronic device according to claim 1, characterized in that: include: a base substrate, comprising a base substrate dielectric structure and a base substrate conductive structure; in: The first substrate and the second substrate are located above the base substrate; and The base substrate conductive structure is coupled to the first conductive structure.

12. The electronic device according to claim 11, characterized in that: include: a cover located above the second electronic component; Wherein the cover is coupled with a top side of the second electronic component and a top side of the base substrate.

13. The electronic device according to claim 12, characterized in that: A portion of the second electronic component extends beyond a lateral side of the cover.

14. The electronic device according to claim 11, characterized in that: include: a third electronic component located over the top side of the base substrate; The third electronic component is coupled to the base substrate conductive structure.

15. The electronic device according to claim 11, characterized in that: The base substrate includes a preformed substrate.

16. A method for manufacturing an electronic component, characterized in that: include: providing a first substrate, the first substrate comprising a first dielectric structure and a first conductive structure, wherein the first conductive structure comprises an outward terminal; providing a first interconnect structure over the first substrate, wherein the first interconnect structure is coupled to the first conductive structure; Disposing a first electronic component located above the first substrate; Disposing a first encapsulant over the first substrate and covering lateral sides of the first interconnect structure and lateral sides of the first electronic component; providing a second substrate, wherein the second substrate comprises a second dielectric structure and a second conductive structure, wherein the second substrate is located above the first substrate and the first electronic component, and the second conductive structure is coupled to the first interconnect structure; providing a second interconnect structure located above the second substrate and coupled to the second conductive structure; Disposing a second encapsulant over the second substrate and covering lateral sides of the second interconnect structure; and Disposing a second electronic component above the second enclosure; wherein the second electronic component is coupled to the second interconnect structure; and The first encapsulation body is located between the first electronic component and the second substrate.

17. The method according to claim 16, characterized in that: The second electronic component is located above the first portion of the second enclosure, and the second portion of the second enclosure is not covered by the second electronic component.

18. The method according to claim 16, characterized in that: A portion of the second electronic component extends beyond a lateral side of the second enclosure.

19. The method according to claim 16, characterized in that include: providing a base substrate, the base substrate comprising a base substrate dielectric structure and a base substrate conductive structure, wherein the base substrate conductive structure comprises an inward terminal; in: The first substrate and the second substrate are located above the base substrate; and The inward terminals of the base substrate conductive structure are coupled with the outward terminals of the first conductive structure.

20. The method according to claim 19, characterized in that include: providing a cover positioned above the second electronic component; Wherein the cover is coupled with a top side of the second electronic component and a top side of the base substrate.

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