Chip stacking structure and preparation method thereof, packaging structure and electronic equipment

Abstract

The invention provides a chip stacking structure, a preparation method thereof, a packaging structure and electronic equipment, relates to the technical field of semiconductor packaging, and aims to solve the problem that a traditional semiconductor packaging mode is large in occupied area. The chip stack structure includes a device component and a flexible interposer. The device assembly comprises a first device and a second device which are arranged in a stacked mode, the first surface of the first device and the first surface of the second device are oppositely arranged and connected, and the second surface of the first device and the second surface of the second device are oppositely arranged. A first portion of the flexible interposer is located on one side of the second surface of the first device, and a second portion of the flexible interposer is located on one side of the second surface of the second device. The bending portion of the flexible interposer is connected between the first portion and the second portion and located on one side of the device assembly. Orthographic projections of the device components on the flexible interposer are located within the flexible interposer. By stacking the first device and the second device, 3D packaging is realized, and the packaging area is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging technology, and in particular to a chip stacking structure and a preparation method thereof, a packaging structure, and an electronic device. Background Art

[0002] With the rapid growth of the electronics industry and the increase in user demand, electronic devices are developing in a smaller and smaller direction. Therefore, it is necessary to have a small and light semiconductor package in the electronic device. The recent major trend in the development of technology related to semiconductor chips is to reduce the size of semiconductor chips. Therefore, in the field of packaging technology, with the rapid growth of demand for small-sized semiconductor chips, it is necessary to realize a chip stacking structure with a compact size. Summary of the invention

[0003] The embodiments of the present disclosure provide a chip stacking structure and a preparation method thereof, a packaging structure, and an electronic device, aiming to improve the problem that a traditional chip stacking structure occupies a large area on a packaging substrate.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a chip stacking structure is provided. The chip stacking structure includes a device assembly and a flexible interposer. The device assembly includes a first device and a second device arranged in a stacked manner, wherein the first surface of the first device and the first surface of the second device are arranged opposite to each other and connected, and the second surface of the first device and the second surface of the second device are arranged opposite to each other. The first part of the flexible interposer is located on the side where the second surface of the first device is located, and the second part of the flexible interposer is located on the side where the second surface of the second device is located; the bending part of the flexible interposer is connected between the first part and the second part and is located on the side of the device assembly; the orthographic projection of the device assembly on the flexible interposer is located within the flexible interposer.

[0006] In the chip stacking structure provided by the above-mentioned embodiment of the present disclosure, the first part of the flexible interposer is located on one side of the second surface of the first device. It should be noted that the first part of the flexible interposer is located on one side of the second surface of the first device and is connected to the second surface; the second part of the flexible interposer is located on one side of the second surface of the second device. It should be noted that the second part of the flexible interposer is located on one side of the second surface of the second device and is connected to the second surface. The bending portion of the flexible interposer is connected between the first part and the second part. Through the above-mentioned arrangement, the first device and the second device are stacked to form a 3D (three-dimensional) package, which is conducive to reducing the area occupied by the packaged semiconductor structure.

[0007] Furthermore, the orthographic projection of the device component on the flexible interposer is located within the flexible interposer, and it should be noted that the first device and the second device can be connected through the flexible interposer. Traditional 3D packaging requires the provision of through silicon vias. The chip stacking structure provided in this embodiment can omit through silicon vias, reduce the difficulty of the manufacturing process, and save manufacturing costs compared to traditional 3D packaging.

[0008] In addition, in the related art, the device components and the package substrate are connected by metal leads. Since the area of ​​the package substrate is limited, the lines arranged are limited. The chip stacking structure provided by the embodiment of the present disclosure can realize the communication and interconnection of the device components through the flexible interposer. The flexible interposer has a larger area, which is conducive to the arrangement of more lines.

[0009] In some embodiments, the flexible interposer includes a flexible substrate and a first electrical connection layer that are stacked, and the first electrical connection layer is located on one side of the flexible substrate.

[0010] In some embodiments, the thickness of the flexible intermediary layer ranges from 20 μm to 200 μm.

[0011] In some embodiments, the material of the flexible substrate includes at least one of polyimide and polyester resin.

[0012] In some embodiments, there are a plurality of the device components, and the plurality of the device components are stacked along a first direction, where the first direction is perpendicular to the first surface of the first device.

[0013] In some embodiments, in two adjacent device components, the two flexible interposing layers located between the two device components are bonded.

[0014] In some embodiments, the flexible intermediary layer further includes a connection portion. Among the plurality of stacked device components, a portion of the flexible intermediary layer connected to the device component on the outermost layer is bonded to the connection portion.

[0015] In some embodiments, the chip stacking structure further includes a silicon interposer, and the silicon interposer is located on a side of the connecting portion away from the device component.

[0016] In some embodiments, a plurality of the device components are spaced apart along a second direction, and the second direction is parallel to the first surface of the first device.

[0017] In some embodiments, the flexible interposer further includes a second electrical connection layer and a conductive via, wherein the conductive via penetrates the flexible substrate, and the second electrical connection layer is located on a side of the flexible substrate facing away from the first electrical connection layer.

[0018] In some embodiments, the chip stacking structure further includes a first interposer and a second interposer, wherein the first interposer is located between the device component and the first portion, and / or the second interposer is located between the device component and the second portion.

[0019] On the other hand, a method for preparing a chip stacking structure is provided, comprising: providing a flexible interposer, a first device, and a second device. Connecting a second surface of the first device to the flexible interposer, and connecting a second surface of the second device to the flexible interposer. Bending the flexible interposer to form a bending portion, and stacking the first device and the second device.

[0020] In some embodiments, the first portion of the flexible intermediary layer is located on the side where the second surface of the first device is located, and the second portion of the flexible intermediary layer is located on the side where the second surface of the second device is located; bending the flexible intermediary layer includes: bending the flexible intermediary layer between the first portion and the second portion to form the bending portion, and making the first surface of the first device and the first surface of the second device relatively arranged and connected, the second surface of the first device and the second surface of the second device are arranged back to back, the bending portion is located on the side of the device assembly, and the device assembly includes the first device and the second device arranged in a stacked manner.

[0021] In some embodiments, orthographic projections of the first device and the second device on the flexible interposer are located within the flexible interposer.

[0022] In some embodiments, the preparation method includes: connecting the second surfaces of multiple first devices to the flexible intermediary layer, connecting the second surfaces of multiple second devices to the flexible intermediary layer, and alternatingly arranging multiple first devices and multiple second devices, the flexible intermediary layer located between the first part and the second part includes a first transition part and a second transition part, and the first transition part and the second transition part are alternately arranged.

[0023] The bending of the flexible intermediary layer includes: bending the first transition portion and the second transition portion in sequence, wherein the bending direction of the first transition portion is opposite to the bending direction of the second transition portion, so that the plurality of device components are stacked along a first direction, and the first direction is perpendicular to the first surface of the first device.

[0024] In some embodiments, among the plurality of the first devices and the second devices, the flexible intermediary layer further includes a connecting portion extending beyond the outermost device, and the flexible intermediary layer further includes a third transition portion, wherein the third transition portion is located between a portion of the flexible intermediary layer connected to the outermost device and the connecting portion.

[0025] The bending the flexible intermediate layer further includes: bending the third transition portion to form the connecting portion.

[0026] After bending the flexible interposer, the preparation method further comprises: connecting the connecting portion to a silicon interposer, and positioning the silicon interposer at a side of the connecting portion away from the device component.

[0027] In some embodiments, the manufacturing method includes: connecting the second surfaces of a plurality of the first devices to a first intermediary layer, and connecting the second surfaces of a plurality of the second devices to a second intermediary layer.

[0028] A surface of the first intermediary layer facing away from the first device is connected to the flexible intermediary layer, and a surface of the second intermediary layer facing away from the second device is connected to the flexible intermediary layer.

[0029] The bending the flexible intermediary layer includes: bending the flexible intermediary layer between the first portion and the second portion so that the plurality of device components are arranged at intervals along a second direction, wherein the second direction is parallel to the first surface of the first device.

[0030] In another aspect, a packaging structure is provided, comprising: a chip stacking structure and a packaging substrate. The chip stacking structure is the chip stacking structure as described in the above embodiment, or the chip stacking structure is prepared by the chip stacking structure preparation method as described in the above embodiment. The packaging substrate is electrically connected to the chip stacking structure.

[0031] On the other hand, an electronic device is provided, comprising a circuit board and the packaging structure as described in the above embodiment, wherein the circuit board is electrically connected to the packaging structure.

[0032] It can be understood that the beneficial effects that can be achieved by the chip stacking structure preparation method, packaging structure, and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip stacking structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0034] Figure 1 is a block diagram of an electronic device according to some embodiments;

[0035] Figure 2 is a schematic structural diagram of an electronic device according to some embodiments;

[0036] Figure 3 is a schematic diagram of a chip structure according to some current embodiments;

[0037] Figure 4 is a schematic diagram of a chip stacking structure according to some current embodiments;

[0038] Figure 5 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0039] Figure 6 is a schematic diagram of the structure of a flexible interposer according to some embodiments;

[0040] Figure 7 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0041] Figure 8 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0042] Fig. 9 is a schematic diagram of the structure of a flexible interposer according to some embodiments;

[0043] Fig.10 is a schematic structural diagram of a chip stacking structure according to some embodiments;

[0044] Fig.11 is a flow chart of a method for preparing a chip stacking structure according to some embodiments;

[0045] Fig.12 A schematic diagram of the structure of a chip stacking structure before bending provided in some embodiments of the present disclosure;

[0046] Fig.13 for Fig.12 A schematic diagram of the structure of the chip stacking structure after bending;

[0047] Fig.14 is a schematic structural diagram of a chip stacking structure before bending according to some embodiments;

[0048] Fig.15 for Fig.14 A schematic diagram of the structure of the chip stacking structure after bending;

[0049] Fig.16 is a schematic structural diagram of a chip stacking structure before bending according to some embodiments;

[0050] Fig.17 for Fig.16 Schematic diagram of the chip stacking structure after bending. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0052] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0053] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0055] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0056] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0057] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0058] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0059] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0060] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0061] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0062] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0063] Figure 1 A block diagram of an electronic device provided for some embodiments of the present disclosure. Figure 2 This is a schematic diagram of the structure of an electronic device provided by some embodiments of the present disclosure. Figure 1 and Figure 2 As shown, the electronic device 1000 may include an image sensor, a NAND flash memory, a high bandwidth memory, a mobile phone, a tablet computer (pad), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, and other electronic products. The disclosed embodiment does not impose any special restrictions on the specific form of the electronic device 1000.

[0064] The electronic device 1000 may include a circuit board 200, a package structure 100, and a connector 7 disposed between the circuit board 200 and the package structure 100, and the package structure 100 is electrically connected to the circuit board 200 via the connector 7. The connector 7 may be, for example, a ball grid array (BGA).

[0065] The electronic device 1000 may include a circuit board 200 and a packaging structure 100. Typically, a plurality of microelectronic circuits are integrated in a semiconductor chip. The semiconductor chip itself cannot be used as a finished product and may be damaged by external physical or chemical impact. The semiconductor chip may be packaged to form a packaging structure 100. The packaging structure 100 includes a chip structure and a packaging substrate. The circuit board 200 is electrically connected to the packaging structure 100. In addition, the electronic device may further include at least one of a central processing unit (CPU) and a cache.

[0066] Figure 3 The schematic diagram of a chip structure provided by some current embodiments is shown in FIG. Figure 3As shown, the chip structure 10' includes a device component 1' and a silicon interposer 3'. The device component 1' includes: a first device 11', a second device 12', a third device 13', and a fourth device 14'. The first device 11', the second device 12', the third device 13' and the fourth device 14' are arranged on the silicon interposer 3' at intervals, and the first device 11', the second device 12', the third device 13' and the fourth device 14' are all electrically connected to the silicon interposer 3'. The communication and interconnection between the first device 11', the second device 12', the third device 13' and the fourth device 14' can be achieved through the silicon interposer 3'. The chip structure 10' is mounted on a packaging substrate (not shown in the figure). Among them, the packaging substrate can be a circuit board with a wiring circuit, or it can be a substrate formed by silicon (such as single crystal silicon), ceramics, glass or any other suitable material. In some embodiments, a plurality of structures for forming electrical connections may be provided on the package substrate, such as a pad structure located on the upper surface of the package substrate, a contact structure located on the lower surface of the package substrate, and a circuit structure located inside the package substrate. Exemplarily, metal leads may be connected to the package substrate to achieve electrical connection, and the metal leads act as bridges. Since the area of ​​the package substrate is limited, and in order to avoid short circuits, the metal leads need to be spaced apart, and therefore, the arranged circuits are limited.

[0067] In addition, Figure 1 , Figure 2 and Figure 3 As shown, the first device 11', the second device 12', the third device 13' and the fourth device 14' are arranged at intervals on the silicon interposer 3'. It can be understood that the more devices the device assembly 1' includes, the larger the area occupied by the device assembly 1' on the silicon interposer 3', and the larger the area of ​​the chip structure on the packaging substrate, which is not conducive to the development of the electronic device 1000 towards miniaturization.

[0068] Based on this, some current embodiments provide a chip stacking structure. Figure 4 Schematic diagram of a chip stacking structure provided by some current embodiments. The following explanation is given by taking the direction perpendicular to the package substrate 20 as the first direction X and the direction parallel to the package substrate 20 as the second direction Y as an example. Figure 4As shown, the first device 11', the second device 12', the third device 13', the fourth device 14' and the fifth device 15' are stacked along the first direction X. The device assembly 1 also includes a through silicon via 6 and a connector 7. The first device 11', the second device 12', the third device 13', the fourth device 14' and the fifth device 15' all include a through silicon via 6 and a connector 7 that are relatively arranged (that is, the connector 7 is connected to one end of the through silicon via 6). The connector 7 of the first device 11' is connected to the through silicon via 6 of the second device 12', the connector 7 of the second device 12' is connected to the through silicon via 6 of the third device 13', the connector 7 of the third device 13' is connected to the through silicon via 6 of the fourth device 14', the connector 7 of the fourth device 14' is connected to the through silicon via 6 of the fifth device 15', and the connector 7 of the fifth device 15' is connected to the package substrate 20. Exemplarily, the connector 7 may include a bump, such as a solder ball. The material of the connector 7 may include, for example, metals such as tin. Through the above arrangement, the components of the device assembly 1' are stacked to form a 3D package, which can reduce the area occupied by the device assembly 1' on the package substrate 20, reduce the size of the package, and facilitate the development of electronic equipment towards miniaturization. However, the manufacturing process of the through silicon via 6 is difficult and the manufacturing cost is high.

[0069] Based on this, some embodiments of the present disclosure provide a chip stacking structure. Figure 5 The schematic diagram of the chip stacking structure provided by some embodiments of the present disclosure is shown in FIG. Figure 5 As shown, the chip stacking structure 10 further includes a flexible interposer 2. In this embodiment, the first device 11 and the second device 12 are stacked, the first surface 111 of the first device 11 and the first surface 121 of the second device 12 are arranged opposite to each other and connected, and the second surface 112 of the first device 11 and the second surface 122 of the second device 12 are arranged opposite to each other. Exemplarily, the first device 11 may include a chip. Exemplarily, the second device 12 may include a chip.

[0070] The first portion 201 of the flexible intermediary layer 2 is located on the side where the second surface 112 of the first device 11 is located. The second portion 202 of the flexible intermediary layer 2 is located on the side where the second surface 122 of the second device 12 is located. The bending portion 203 of the flexible intermediary layer 2 is connected between the first portion 201 and the second portion 202, and is located on the side of the device component 1. In addition, the orthographic projection of the device component 1 on the flexible intermediary layer 2 is located inside the flexible intermediary layer 2.

[0071] It should be noted that “the side surface of the device component” refers to: assuming that the first surface 111 of the first device 11 is a horizontal plane, when the device component 1 is placed horizontally on the horizontal plane, the side surface of the device component 1 .

[0072] It should be noted that “the orthographic projection of the device assembly 1 on the flexible intermediary layer 2 is located inside the flexible intermediary layer 2” means that the sizes of the first surface 111 and the second surface of the first device 11 of the device assembly 1, as well as the sizes of the first surface 121 and the second surface of the second device 12, are smaller than the sizes of the first part 201 and the second part 202 of the flexible intermediary layer 2. That is, the flexible intermediary layer 2 completely covers the second surface 112 of the first device 11 and the second surface 122 of the second device 12.

[0073] In this embodiment, the first portion 201 of the flexible intermediary layer 2 is located on the side where the second surface 112 of the first device 11 is located. Further, the first portion 201 of the flexible intermediary layer 2 is located on the side where the second surface 112 of the first device 11 is located, so that the first portion 201 of the flexible intermediary layer 2 is connected to the second surface 112 of the first device 11. Exemplarily, a connector 7 is provided on the side of the first portion 201 of the flexible intermediary layer 2 opposite to the second surface 112 of the first device 11, and the flexible intermediary layer 2 can be electrically connected to the first device 11 through the connector 7. The second portion 202 of the flexible intermediary layer 2 is located on the side of the second surface 122 of the second device 12. Further, the second portion 202 of the flexible intermediary layer 2 is located on the side of the second surface 122 of the second device 12, so that the second portion 202 of the flexible intermediary layer 2 is connected to the second surface 122 of the second device 12. Exemplarily, a connector 7 is provided on the side of the second portion 202 of the flexible intermediary layer 2 opposite to the second surface 122 of the second device 12, and the flexible intermediary layer 2 can be electrically connected to the second device 12 through the connector 7.

[0074] The bending portion 203 of the flexible intermediary layer 2 is connected between the first part 201 and the second part 202. Exemplarily, the first part 201, the second part 202 and the bending portion 203 can be integrally arranged. The material of the flexible intermediary layer 2 can include ultra-thin flexible materials such as polyimide and polyester resin, which is conducive to saving manufacturing costs. Through the above arrangement, the first device 11 and the second device 12 of the device assembly 1 can be stacked along the first direction X to form a 3D package, which is conducive to reducing the area occupied by the packaging structure 100 and making the electronic device miniaturized.

[0075] In addition, the first device 11 and the second device 12 of the embodiment of the present disclosure achieve communication and interconnection through the flexible intermediate layer 2. Compared with the traditional 3D packaging that requires the provision of silicon through vias 6 to interconnect the devices, the chip stacking structure 10 provided in the present embodiment can omit the silicon through vias 6, thereby reducing the difficulty of the manufacturing process and saving manufacturing costs.

[0076] In addition, since the partial contact of the metal lead (not shown in the figure) in the air is prone to short circuit, the metal leads need to be spaced a certain distance apart. Compared with connecting the first device 11 and the second device 12 by means of metal leads, the first device 11 and the second device 12 can achieve communication and interconnection through the flexible intermediary layer 2. In this embodiment, the flexible intermediary layer 2 may include a connector 7, which is disposed on the flexible intermediary layer 2. Compared with the metal leads, the connector 7 can be arranged more densely on the flexible intermediary layer 2. Therefore, connecting the first device 11 and the second device 12 through the flexible intermediary layer 2 is conducive to arranging more circuits. For example, more connectors 7 can be arranged.

[0077] Figure 6 A schematic diagram of a flexible interposer provided in some embodiments of the present disclosure. Figure 6 As shown, the flexible intermediary layer 2 includes a flexible substrate 21 and a first electrical connection layer 22 which are stacked, and the first electrical connection layer 22 is located on one side of the flexible substrate 21. Figure 4 and Figure 5 The first electrical connection layer 22 is located on a side of the flexible substrate 21 close to the device assembly 1 , so that the first electrical connection layer 22 can be electrically connected to the first device 11 and the second device 12 .

[0078] By way of example, the first electrical connection layer 22 may include a metal line, and the metal line is used to electrically connect the first device 11 , the second device 12 , and the package substrate 20 together.

[0079] Exemplarily, a surface of the first electrical connection layer 22 electrically connected to the first device 11 and the second device 12 may be provided with a connector 7 , and the first device 11 and the second device 12 are electrically connected together through the connector 7 .

[0080] In some embodiments, reference Figure 5 and Figure 6 , the thickness of the flexible intermediary layer 2 ranges from 20μm to 200μm. When the thickness of the flexible intermediary layer 2 is within the range of 20μm to 200μm, the overall thickness of the chip stacking structure 10 of this embodiment will not be too large, which is conducive to the miniaturization of electronic devices. Exemplarily, the thickness of the flexible intermediary layer 2 can be 20μm, 90μm or 200μm, and when the thickness of the flexible intermediary layer 2 is closer to 20μm, it is more conducive to reducing the overall thickness of the chip stacking structure 10, which is more conducive to the miniaturization of electronic devices. The thickness of the flexible intermediary layer 2 can be within the range of 20μm to 200μm, and the present disclosure does not impose any restrictions on this.

[0081] In some embodiments, reference Figure 5 and Figure 6, the material of the flexible substrate 21 includes at least one of polyimide and polyester resin. For example, the flexible substrate 21 can be a film made of polyimide, or the flexible substrate 21 can be a film made of polyester resin. It can be understood that the selection of polyimide or polyester resin to form the flexible substrate 21 can make the thickness of the flexible substrate 21 within the value range of 20μm-200μm, ensuring that the thickness of the chip stacking structure 10 after packaging will not be too large, which is beneficial for the overall thickness of the electronic device not to be too large, and is beneficial for the development of electronic devices towards miniaturization. In addition, the flexible substrate 21 made of at least one of polyimide and polyester resin can have a certain flexibility, which is beneficial for forming the bending portion 203 of the flexible interposer 2.

[0082] In some embodiments, a device assembly 1 may include a first device 11 and a second device 12, and the first device 11 and the second device 12 are stacked. In this embodiment, there may be multiple device assemblies 1, and the flexible interposer 2 is used to connect with the multiple device assemblies 1.

[0083] Figure 7 The schematic diagram of the chip stacking structure provided by some embodiments of the present disclosure is shown in FIG. Figure 7 As shown, a plurality of device components 1 may be stacked along a first direction X.

[0084] Accordingly, if Figure 6 As shown, the flexible interposer 2 further includes a flexible substrate 21 and a first electrical connection layer 22 , so that a plurality of device components 1 are electrically connected to the same flexible interposer 2 .

[0085] Compared with arranging multiple devices at intervals on the packaging substrate 20, the embodiment of the present application stacks multiple device components 1 along the first direction X, which is beneficial to further reduce the area occupied by the multiple device components 1 on the packaging substrate 20, thereby facilitating further miniaturization of electronic equipment.

[0086] In some embodiments, Figure 7 As shown, in two adjacent device components 1, the two flexible intermediary layers 2 located between the two device components 1 are bonded. Figure 7 The position A in the diagram has adhesive, which can bond two flexible interposers 2 between two adjacent device components 1 , thereby facilitating improving the stability of the chip stacking structure 10 .

[0087] In some embodiments, Figure 7As shown, the flexible interposer 2 also includes a connection portion 204. Among the multiple device components 1 stacked, the portion of the flexible interposer 2 connected to the device component 1 on the outermost layer is bonded to the connection portion 204, and the connection portion 204 is used to electrically connect to the package substrate, so that the device component 1 is electrically connected to the package substrate. Therefore, the first electrical connection layer 22 of the connection portion 204 is arranged opposite to the package substrate, and the connection portion 204 is electrically connected to the package substrate 20 through the first electrical connection layer 22. Here, the "outermost device component 1" refers to: when multiple device components 1 are stacked, the device component 1 located at the edge layer (for example Figure 7 The bottommost device component 1).

[0088] Furthermore, the portion of the flexible interposer 2 connected to the outermost device component 1 is bonded to the connecting portion 204, that is, Figure 7 There is adhesive at the position B, so that the part of the flexible interposer 2 connected to the outermost device component 1 is bonded to the connecting portion 204 , which is beneficial to ensure the overall stability of the chip stacking structure 10 .

[0089] Continue to refer Figure 7 For example, the connecting portion 204 and the end of the portion of the flexible intermediary layer 2 connected to the outermost device component 1 can be connected through the bending portion 203, that is, the connecting portion 204 and the portion of the flexible intermediary layer 2 connected to the outermost device component 1 can be integrally arranged.

[0090] Figure 8 Schematic diagram of a chip stacking structure provided in some other embodiments of the present disclosure. Figure 8 As shown, the chip stacking structure 10 further includes a silicon interposer 3, which is located on the side of the connection portion 204 away from the device assembly 1. One side of the silicon interposer 3 is connected to the first electrical connection layer 22 of the connection portion 204, and the other side of the silicon interposer 3 is connected to the package substrate 20.

[0091] Exemplarily, the first electrical connection layer 22 of the connection portion 204 may include a connector 7. The connection portion 204 may be electrically connected to one side of the silicon interposer 3 through the connector 7. In addition, a through silicon via 6 (not shown in the figure) may be provided at a position where the silicon interposer 3 contacts the connector 7 of the connection portion 204, and a conductive material is filled in the through silicon via 6 to ensure the conductive function of the through silicon via 6. A connector 7 is provided on the other side of the silicon interposer 3 opposite to the through silicon via 6, and the silicon interposer 3 is electrically connected to the packaging substrate 20 through the connector 7. Further, the connection portion 204 can be electrically connected to the packaging substrate 20 through the silicon interposer 3.

[0092] Fig. 9 Schematic diagram of the structure of the flexible interposer provided in some other embodiments of the present disclosure. Fig. 9As shown, the flexible interposer 2 located between the device component 1 and the package substrate 20 further includes a second electrical connection layer 23 and a conductive through hole 24. The conductive through hole 24 can penetrate the flexible substrate 21 along the first direction X, and the second electrical connection layer 23 is located on the side of the flexible substrate 21 away from the first electrical connection layer 22. One end of the conductive through hole 24 is electrically connected to the first electrical connection layer 22, and the other end of the conductive through hole 24 is electrically connected to the second electrical connection layer 23. Among them, the conductive through hole 24 can be a through silicon via 6 (Through Silicon Via, TSV), or a through hole of other materials, and a conductive material can be filled in the through hole to ensure its conductive function.

[0093] As described in the above embodiment, the flexible interposer 2 located between the device component 1 and the package substrate 20 may include a first electrical connection layer 22, a conductive via 24, and a second electrical connection layer 23. The first electrical connection layer 22 is electrically connected to the device component 1, the second electrical connection layer 23 is electrically connected to the package substrate 20, and the conductive via 24 enables the first electrical connection layer 22 and the second electrical connection layer 23 to be conductive, and further, the device component 1 is electrically connected to the package substrate 20.

[0094] Fig.10 Schematic diagram of a chip stacking structure provided in some other embodiments of the present disclosure. Fig.10 As shown, the plurality of device assemblies 1 are spaced apart along the second direction Y. The first portion 201 of the flexible interposer 2 is connected to the second surface 112 of the first device 11 of the plurality of device assemblies 1. The second portion 202 of the flexible interposer 2 is connected to the second surface 122 of the second device 12 of the plurality of device assemblies 1.

[0095] In this embodiment, the flexible intermediary layer 2 may be formed as follows: Fig. 9 The flexible interposer 2 is shown. Fig. 9 and Fig.10 , the first part 201 of the flexible intermediary layer 2 is electrically connected to the second surface 112 of the first device 11 of the plurality of device components 1 through the first electrical connection layer 22. The first electrical connection layer 22 may include, for example, a connector 7. The second part 202 of the flexible intermediary layer 2 may be electrically connected to the second surface 122 of the second device 12 of the plurality of device components 1 through the first electrical connection layer 23. In addition, the second part 202 of the flexible intermediary layer 2 may include a conductive via 24 and a second electrical connection layer 23, and be electrically connected to the package substrate through the second electrical connection layer 23. The first part 201 and the second part 202 of the flexible intermediary layer 2 connected to the device component 1 located at one end of the second direction Y are connected through a bending portion 203. Exemplarily, the first part 201, the second part 202 and the bending portion 203 may be integrally arranged.

[0096] The flexible interposer 2 may be electrically connected to the package substrate. Fig.10 Combined with Figure 7 , the flexible interposer 2 may include a connection portion 204. The connection portion 204 may be connected to the second portion 202 via the bending portion 203, and the flexible substrate 21 of the connection portion 204 may be bonded to the flexible substrate 21 of the second portion 202 via an adhesive, which is beneficial to the stability of the chip stacking structure 10. The first electrical connection layer 22 of the connection portion 204 is electrically connected to the package substrate 20, thereby electrically connecting the plurality of device components 1 to the package substrate 20. Alternatively, continue to refer to Fig.10 Combined with Fig. 9 The flexible interposer 2 may be electrically connected to the package substrate 20 through the first electrical connection layer 22 , the second electrical connection layer 23 and the conductive via 24 .

[0097] Through the above arrangement, the first devices 11 and the second devices 12 of the multiple groups of device components 1 are stacked, which is beneficial to reducing the area of ​​the device components 1 on the packaging substrate 20, thereby forming a 3D package and miniaturizing the electronic equipment.

[0098] In some embodiments, continue to refer to Fig.10 , the chip stacking structure 10 further includes a first interposer 4, which is located between the device assembly 1 and the first part 201. The chip stacking structure 10 may further include a second interposer 5, which is located between the device assembly 1 and the second part 202. The first interposer 4 is electrically connected to the first devices 11 of the plurality of device assemblies 1, and at the same time, the first interposer 4 is electrically connected to the first part 201 of the flexible interposer 2. Exemplarily, the first interposer 4 may include a plurality of conductive vias 24 (not shown in the figure), which penetrate the first interposer 4 along the first direction X. One end of the conductive via 24 is electrically connected to the first devices 11 of the plurality of device assemblies 1, and the other end of the conductive via 24 is electrically connected to the first part 201 of the flexible interposer 2. Through the above arrangement, the first devices 11 of the plurality of device assemblies 1 can be electrically connected to the first part 201 through the first interposer 4.

[0099] Similarly, the second interposer 5 may not include a plurality of conductive vias 24 (not shown in the figure), and the conductive vias 24 penetrate the second interposer 5 along the first direction X. One end of the conductive via 24 is electrically connected to the second devices 12 of the plurality of device assemblies 1, and the other end of the conductive via 24 is electrically connected to the second portion 202 of the flexible interposer 2. Through the above arrangement, the second devices 12 of the plurality of device assemblies 1 can be electrically connected to the second portion 202 through the second interposer 5.

[0100] In the above embodiment, the conductive through hole 24 may be a through silicon via 6 or a through hole made of other materials, and a conductive material may be filled in the through hole to ensure its conductive function.

[0101] Fig.11 It is a flow chart of a method for preparing a chip stacking structure provided in some embodiments of the present disclosure. Fig.12 It is a schematic structural diagram of the chip stacking structure before bending provided in some embodiments of the present disclosure. Fig.13 yes Fig.12 Schematic diagram of the structure of the chip stacking structure after bending. In some embodiments, Fig.11 , Fig.12 and Fig.13 As shown, the present disclosure also provides a method for preparing a chip stacking structure, comprising:

[0102] S1. Provide a flexible intermediate layer, a first device, and a second device.

[0103] like Figure 6 As shown, the flexible intermediary layer 2 may include a flexible substrate 21 and a first electrical connection layer 22 which are stacked, and the first electrical connection layer 22 is located on one side of the flexible substrate 21. The material of the flexible intermediary layer 2 may include ultra-thin flexible materials such as polyimide and polyester resin. Preferably, the thickness of the flexible intermediary layer 2 is in the range of 20 μm-200 μm. The first device 11 may include a chip. The second device 12 may include a chip.

[0104] S2. Connect the second surface of the first device to the flexible intermediate layer, and connect the second surface of the second device to the flexible intermediate layer.

[0105] like Fig.12 As shown, exemplarily, the second surface 112 of the first device 11 is electrically connected to the first electrical connection layer 22 of the flexible interposer 2 , and the second surface 122 of the second device 12 is electrically connected to the first electrical connection layer 22 of the flexible interposer 2 .

[0106] S3, bending the flexible intermediate layer to form a bending portion, and stacking a first device and a second device.

[0107] like Fig.12 and Fig.13 As shown, bending Fig.12 The flexible interposer 2 at the C position is formed Fig.13 The bending portion 203 in the package substrate 20 is shown in FIG. A first device 11 and a second device 12 are stacked along the first direction X to form a device assembly 1. It can be seen that a device assembly 1 includes a first device 11 and a second device 12. However, the area of ​​a device assembly 1 on the package substrate 20 is only the area of ​​a first device 11 or a second device 12 on the package substrate 20. Compared with the first device 11 and the second device 12 being arranged at intervals, the stacking arrangement of the first device 11 and the second device 12 is conducive to reducing the area of ​​the device assembly 1 on the package substrate 20, which is conducive to the miniaturization of electronic devices.

[0108] Exemplarily, the flexible interposer 2 may completely cover the second surface 112 of the first device 11 and the second surface 122 of the second device 12, and the first electrical connection layer 22 of the flexible interposer 2 may be electrically connected to the package substrate 20, and further, the first device 11 and the second device 12 may be electrically connected to the package substrate 20. Exemplarily, the first electrical connection layer 22 of the flexible interposer 2 may include a connector 7. Through the above arrangement, compared with the conventional method of connecting the first device 11, the second device 12 and the package substrate 20 through metal wires, the flexible interposer 2 is conducive to arranging more circuits.

[0109] In some embodiments, the first portion 201 of the flexible intermediary layer 2 is located on the side where the second surface 112 of the first device 11 is located, so that the first portion 201 of the flexible intermediary layer 2 is connected to the second surface 112 of the first device 11. The second portion 202 of the flexible intermediary layer 2 is located on the side where the second surface 122 of the second device 12 is located, so that the second portion 202 of the flexible intermediary layer 2 is connected to the second surface 122 of the second device 12.

[0110] In the embodiment of the present application, bending the flexible intermediary layer 2 includes: bending the flexible intermediary layer 2 (such as Fig.12 The flexible interposer 2 at the C position in the package is formed to form a bending portion 203, and the first surface 111 of the first device 11 and the first surface 121 of the second device 12 are arranged opposite to each other and connected, the second surface 112 of the first device 11 and the second surface 122 of the second device 12 are arranged opposite to each other, and the bending portion 203 is located on the side of the device assembly 1, and the device assembly 1 includes the first device 11 and the second device 12 arranged in a stacked manner. Through the above arrangement, the first device 11 and the second device 12 can be stacked, which is conducive to reducing the area of ​​the chip stacking structure on the packaging substrate and is conducive to the miniaturization of electronic devices.

[0111] In some embodiments, Fig.13 As shown, the orthographic projections of the first device 11 and the second device 12 on the flexible intermediary layer 2 are located within the flexible intermediary layer 2 , that is, the first device 11 and the second device 12 are located within the flexible intermediary layer 2 , that is, the flexible intermediary layer 2 completely covers the second surface 112 of the first device 11 and the second surface 122 of the second device 12 .

[0112] Fig.14 It is a schematic structural diagram of the chip stacking structure before bending provided in some embodiments of the present disclosure. Fig.15 yes Fig.14 Schematic diagram of the structure of the chip stacking structure after bending. In some embodiments, Fig.14 and Fig.15As shown, when the chip stacking structure 10 includes a plurality of first devices 11 and a plurality of second devices 12, the preparation method of the chip stacking structure 10 also includes: connecting the second surfaces 112 of the plurality of first devices 11 to the flexible intermediary layer 2, connecting the second surfaces 122 of the plurality of second devices 12 to the flexible intermediary layer 2, and arranging the plurality of first devices 11 and the plurality of second devices 12 alternately, and the flexible intermediary layer 2 located between the first part 201 and the second part 202 includes a first transition part 205 and a second transition part 206, and the first transition part 205 and the second transition part 206 are alternately arranged.

[0113] Based on the above steps, the step of bending the flexible interposer 2 also includes: bending the first transition portion 205 and the second transition portion 206 in sequence, wherein the bending direction of the first transition portion 205 is opposite to the bending direction of the second transition portion 206, so that the plurality of device components 1 are stacked along a first direction X, and the first direction X is perpendicular to the first surface 111 of the first device 11.

[0114] It can be understood that the flexible interposer 2 between the first device 11 and the second device 12 is bent to form the bent portion 203, that is, the first transition portion 205 in the above embodiment is bent to form the bent portion 203. Fig.13 As shown, the first portion 201, the bent portion 203, and the second portion 202 of the flexible interposer 2 cover a device component 1 to form a chip stacking structure 10. Fig.15 , multiple Fig.13 The chip stacking structure 10 continues to be stacked along the first direction, and the adjacent flexible interposers 2 are connected together, and the flexible interposers can be arranged in one piece. Through the above arrangement, multiple device components 1 are stacked along the first direction X, which is conducive to reducing the area occupied by multiple device groups on the packaging substrate 20, and is conducive to the miniaturization of electronic devices.

[0115] In some embodiments, Fig.14 and Fig.15 As shown, among the plurality of first devices 11 and second devices 12, the flexible interposer 2 further includes a connection portion 204 extending beyond the outermost device. It should be noted that the “connection portion 204 extending beyond the outermost device” refers to the device (e.g. Fig.14 The portion of the device at the rightmost end of the figure is the connecting portion 204.

[0116] Continue to refer Fig.14 and Fig.15The flexible intermediary layer 2 further includes a third transition portion 207, and the third transition portion 207 is located between the portion of the flexible intermediary layer 2 connected to the outermost device and the connecting portion 204. The bending flexible intermediary layer 2 in the above embodiment further includes: bending the third transition portion 207 to form the connecting portion 204.

[0117] refer to Figure 7 After bending the flexible interposer 2, the method for preparing the chip stacking structure 10 further includes: connecting the connection portion 204 to the silicon interposer 3, and making the silicon interposer 3 located on the side of the connection portion 204 away from the device component 1. In this embodiment, the silicon interposer 3 includes a conductive through hole 24, wherein the conductive through hole 24 can be a silicon through hole 6, or a through hole of other materials, and a conductive material can be filled in the through hole to ensure its conductive function. The first electrical connection layer 22 of the connection portion 204 is electrically connected to one end of the conductive through hole 24 of the silicon interposer 3, and the packaging substrate 20 is electrically connected to the other end of the conductive through hole 24 of the silicon interposer 3. Further, the connection portion 204 can be electrically connected to the packaging substrate 20, so that the device component 1 is electrically connected to the packaging substrate 20.

[0118] refer to Fig. 9 Some of the above embodiments provide a flexible intermediary layer 2, which includes a first electrical connection layer 22, a conductive through hole 24 and a second electrical connection layer 23. The structural features thereof are as described in the above embodiments and will not be described again.

[0119] Fig.16 It is a schematic structural diagram of the chip stacking structure before bending provided in some embodiments of the present disclosure. Fig.17 yes Fig.16 Schematic diagram of the chip stacking structure after bending. Fig. 9 The flexible interposer 2 provided, in some embodiments, is Fig.16 and Fig.17 As shown, the method for preparing the chip stacking structure 10 further includes: connecting the second surfaces 112 of the plurality of first devices 11 to the first interposer 4, and connecting the second surfaces 122 of the plurality of second devices 12 to the second interposer 5. That is, one first device 11 and one second device 12 constitute a device assembly 1, and the plurality of device assemblies 1 are arranged at intervals along the second direction, the second surfaces 112 of the plurality of first devices 11 are all electrically connected to the first interposer 4, and the second surfaces 122 of the plurality of second devices 12 are all electrically connected to the second interposer 5. The surface of the first interposer 4 facing away from the first device 11 is connected to the flexible interposer 2, and the surface of the second interposer 5 facing away from the second device 12 is connected to the flexible interposer 2.

[0120] Based on the above steps, the step of bending the flexible intermediary layer 2 further includes: bending the flexible intermediary layer 2 between the first portion 201 and the second portion 202 ( Fig.16A flexible intermediate layer 2 is provided at a position D in the middle so that the plurality of device components 1 are arranged at intervals along the second direction Y.

[0121] Through the above arrangement, the first devices 11 and the second devices 12 of the multiple groups of device components 1 can be stacked, which is beneficial to reducing the area of ​​the device components 1 on the packaging substrate 20, thereby forming a 3D package and miniaturizing the electronic equipment.

[0122] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip stacking structure, characterized in that: include: A device assembly, the device assembly comprising a first device and a second device arranged in a stacked manner, wherein a first surface of the first device and a first surface of the second device are arranged opposite to each other and connected, and a second surface of the first device and a second surface of the second device are arranged opposite to each other; A flexible intermediary layer, wherein the first portion of the flexible intermediary layer is located on the side where the second surface of the first device is located, and the second portion of the flexible intermediary layer is located on the side where the second surface of the second device is located; the bent portion of the flexible intermediary layer is connected between the first portion and the second portion and is located on the side of the device component; and the orthographic projection of the device component on the flexible intermediary layer is located within the flexible intermediary layer.

2. The chip stacking structure according to claim 1, characterized in that: The flexible intermediate layer includes a flexible substrate and a first electrical connection layer which are stacked, and the first electrical connection layer is located on one side of the flexible substrate.

3. The chip stacking structure according to claim 2, characterized in that: The thickness of the flexible intermediate layer ranges from 20 μm to 200 μm.

4. The chip stacking structure according to claim 2, characterized in that: The material of the flexible substrate includes at least one of polyimide and polyester resin.

5. The chip stacking structure according to any one of claims 2 to 4, characterized in that: There are a plurality of device components, and the plurality of device components are stacked along a first direction, and the first direction is perpendicular to a first surface of the first device.

6. The chip stacking structure according to claim 5, characterized in that: In two adjacent device components, the two flexible intermediate layers located between the two device components are bonded.

7. The chip stacking structure according to claim 6, characterized in that: The flexible intermediary layer further includes a connecting portion; Among the plurality of device components stacked in layers, the portion of the flexible intermediate layer connected to the device component on the outermost layer is bonded to the connecting portion.

8. The chip stacking structure according to claim 7, characterized in that: The chip stacking structure further includes a silicon interposer, and the silicon interposer is located at a side of the connecting portion away from the device component.

9. The chip stacking structure according to any one of claims 2 to 4, characterized in that: A plurality of the device components are arranged at intervals along a second direction, and the second direction is parallel to the first surface of the first device.

10. The chip stacking structure according to claim 9, characterized in that: The flexible intermediate layer further includes a second electrical connection layer and a conductive through hole, wherein the conductive through hole penetrates the flexible substrate, and the second electrical connection layer is located on a side of the flexible substrate away from the first electrical connection layer.

11. The chip stacking structure according to claim 10, characterized in that: The chip stacking structure further includes a first interposer and a second interposer, wherein the first interposer is located between the device component and the first portion, and / or the second interposer is located between the device component and the second portion.

12. A method for preparing a chip stacking structure, characterized in that: include: Providing a flexible interposer, a first device, and a second device; Connecting the second surface of the first device to the flexible intermediary layer, and connecting the second surface of the second device to the flexible intermediary layer; The flexible intermediate layer is bent to form a bent portion, and the first device and the second device are stacked.

13. The method for preparing a chip stacking structure according to claim 12, characterized in that: The first portion of the flexible intermediary layer is located on a side where the second surface of the first device is located, and the second portion of the flexible intermediary layer is located on a side where the second surface of the second device is located; and the bending of the flexible intermediary layer comprises: The flexible intermediary layer located between the first part and the second part is bent to form the bent portion, and the first surface of the first device and the first surface of the second device are arranged opposite to each other and connected, and the second surface of the first device and the second surface of the second device are arranged back to back, and the bent portion is located on the side of the device assembly, and the device assembly includes the first device and the second device arranged in a stacked manner.

14. The method for preparing a chip stacking structure according to claim 12, characterized in that: Orthographic projections of the first component and the second component on the flexible interposer are located within the flexible interposer.

15. The method for preparing a chip stacking structure according to claim 13, characterized in that: The preparation method comprises: Connecting the second surfaces of the plurality of first devices to the flexible intermediary layer, connecting the second surfaces of the plurality of second devices to the flexible intermediary layer, and arranging the plurality of first devices and the plurality of second devices alternately, wherein the flexible intermediary layer located between the first portion and the second portion comprises a first transition portion and a second transition portion, and the first transition portion and the second transition portion are alternately arranged; The bending of the flexible intermediary layer includes: bending the first transition portion and the second transition portion in sequence, wherein the bending direction of the first transition portion is opposite to the bending direction of the second transition portion, so that the plurality of device components are stacked along a first direction, and the first direction is perpendicular to the first surface of the first device.

16. The method for preparing a chip stacking structure according to claim 15, characterized in that: Among the plurality of the first devices and the second devices, the flexible intermediary layer further comprises a connection portion extending beyond the outermost device, and the flexible intermediary layer further comprises a third transition portion, wherein the third transition portion is located between a portion of the flexible intermediary layer connected to the outermost device and the connection portion; The bending the flexible intermediary layer further comprises: bending the third transition portion to form the connecting portion; After bending the flexible interposer, the preparation method further comprises: connecting the connection portion to a silicon interposer, and positioning the silicon interposer at a side of the connection portion away from the device component.

17. The method for preparing a chip stacking structure according to claim 13, characterized in that: The preparation method comprises: Connecting the second surfaces of the plurality of the first devices to the first interposer, and connecting the second surfaces of the plurality of the second devices to the second interposer; Connecting a surface of the first intermediary layer facing away from the first device to the flexible intermediary layer, and connecting a surface of the second intermediary layer facing away from the second device to the flexible intermediary layer; The bending the flexible intermediary layer includes: bending the flexible intermediary layer between the first portion and the second portion so that the plurality of device components are arranged at intervals along a second direction, wherein the second direction is parallel to the first surface of the first device.

18. A packaging structure, characterized in that: include: A chip stacking structure, wherein the chip stacking structure is the chip stacking structure according to any one of claims 1 to 11, or the chip stacking structure is prepared by the chip stacking structure preparation method according to any one of claims 12 to 17; A packaging substrate is electrically connected to the chip stacking structure.

19. An electronic device, characterized in that: It comprises a circuit board and the packaging structure as claimed in claim 18, wherein the circuit board is electrically connected to the packaging structure.

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