Semiconductor package

Abstract

The semiconductor package includes: a package substrate having a plurality of substrate pads; a first semiconductor chip stacked on the package substrate and having a plurality of first chip pads and a plurality of first selection pads along a first horizontal direction, a plurality of first sub-chip pads along a second horizontal direction, and a plurality of first wirings electrically connecting the plurality of first chip pads and the plurality of first sub-chip pads; a second semiconductor chip stacked on the first semiconductor chip to cover the plurality of first sub-chip pads, and having a plurality of second chip pads and a plurality of second selection pads along a first horizontal direction, and a plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads; and a plurality of connecting lines electrically connecting the package substrate, the first semiconductor chip, and the second semiconductor chip.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2023-0104215 filed on August 9, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] Example embodiments relate to a semiconductor package. More particularly, example embodiments relate to a semiconductor package including a plurality of semiconductor chips stacked on a package substrate. Background Art

[0003] In the process of stacking a plurality of semiconductor chips on a package substrate, the package substrate and the plurality of semiconductor chips may be electrically connected by a wire bonding process. In order to expose the chip pad for wire bonding, the plurality of semiconductor chips may be stacked in a step shape and tilted diagonally. When the plurality of semiconductor chips are stacked in a diagonal tilt, the overhanging portion of the semiconductor chip may be easily bent. When the chip pad of the semiconductor chip and the base pad of the package substrate are electrically connected by a wire, there is a problem of increasing the height of the semiconductor package. Summary of the invention

[0004] Some example embodiments provide a semiconductor package having a structure that reduces an overhanging portion to increase stability and reduces the number of wires to reduce the height of the package.

[0005] According to an example embodiment, a semiconductor package includes: a packaging substrate having a plurality of substrate pads; a first semiconductor chip stacked on the packaging substrate, the first semiconductor chip including a plurality of first chip pads, a plurality of first selection pads, a plurality of first sub-chip pads, and a plurality of first wirings, the plurality of first chip pads and the plurality of first selection pads are along a first horizontal direction, the plurality of first sub-chip pads are along a second horizontal direction perpendicular to the first horizontal direction, the plurality of first wirings electrically connecting the plurality of first chip pads and the plurality of first sub-chip pads to each other; a second semiconductor chip stacked on the first semiconductor chip to cover the plurality of first sub-chip pads, the second semiconductor chip including a plurality of second chip pads, a plurality of second selection pads, a plurality of second sub-chip pads, and a plurality of second wirings, the plurality of second chip pads and the plurality of second selection pads are along the first horizontal direction, the plurality of second sub-chip pads are along the second horizontal direction, the plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads to each other; and a plurality of connecting wires electrically connecting the packaging substrate, the first semiconductor chip, and the second semiconductor chip.

[0006] According to an example embodiment, a semiconductor package includes: a packaging substrate having a plurality of substrate pads; a first semiconductor chip stacked on the packaging substrate, the first semiconductor chip including a plurality of first chip pads, a plurality of first sub-chip pads, and a plurality of first wirings, the plurality of first chip pads being along a first horizontal direction, the plurality of first sub-chip pads being along a second horizontal direction perpendicular to the first horizontal direction, the plurality of first wirings electrically connecting the plurality of first chip pads and the plurality of first sub-chip pads to each other; a second semiconductor chip stacked on the first semiconductor chip to cover the plurality of first sub-chip pads, the second semiconductor chip including a plurality of second chip pads, a plurality of second sub-chip pads, and a plurality of second wirings, the plurality of second chip pads being along the first horizontal direction, the plurality of second sub-chip pads being along the second horizontal direction, the plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads to each other; and a plurality of connecting lines electrically connecting the plurality of first chip pads, the plurality of second chip pads, and the plurality of second sub-chip pads to the plurality of substrate pads and being configured to transmit power signals or ground signals.

[0007] According to an example embodiment, a semiconductor package includes: a package substrate having a plurality of substrate pads; a first half package having a first semiconductor chip and a second semiconductor chip sequentially stacked on the package substrate; a second half package having a third semiconductor chip and a fourth semiconductor chip sequentially stacked on the first half package; and a plurality of connection lines electrically connecting the first half package and the second half package to the package substrate and configured to transmit a power signal or a ground signal. The first semiconductor chip includes a plurality of first chip pads along a first horizontal direction, a plurality of first sub-chip pads along a second horizontal direction perpendicular to the first horizontal direction, and a plurality of first wirings electrically connecting the plurality of first chip pads and the plurality of first sub-chip pads to each other. The second semiconductor chip includes a plurality of second chip pads along a first horizontal direction, a plurality of second sub-chip pads along a second horizontal direction, and a plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads to each other. The second semiconductor chip is stacked on the first semiconductor chip to cover the plurality of first sub-chip pads and expose the plurality of first chip pads. The third semiconductor chip includes a plurality of third chip pads along a first horizontal direction, a plurality of third sub-chip pads along a second horizontal direction, and a plurality of third wirings electrically connecting the plurality of third chip pads and the plurality of third sub-chip pads to each other. The third semiconductor chip is stacked on the second semiconductor chip to expose the plurality of second chip pads and the plurality of second sub-chip pads. The fourth semiconductor chip includes a plurality of fourth chip pads along the first horizontal direction, a plurality of fourth sub-chip pads along the second horizontal direction, and a plurality of fourth wirings electrically connecting the plurality of fourth chip pads and the plurality of sub-chip pads to each other. The fourth semiconductor chip is stacked on the third semiconductor chip to cover the plurality of third sub-chip pads and expose the plurality of third chip pads.

[0008] The first semiconductor chip and the second semiconductor chip may be sequentially stacked on the package substrate. Since the second semiconductor chip is stacked to cover the first sub-chip pad of the first semiconductor chip, the overlapping area between the first semiconductor chip and the second semiconductor chip may be increased when viewed in a plan view. Since the overlapping area between the first semiconductor chip and the second semiconductor chip is increased, the overhang portion may be reduced, thereby reducing the bending phenomenon occurring in the second semiconductor chip.

[0009] Because the first sub-chip pad of the first semiconductor chip is covered by the second semiconductor chip, the first sub-chip pad can be electrically connected to the first chip pad through the first wiring. Because the first sub-chip pad is electrically connected to the first chip pad through the first wiring, the first sub-chip pad can enhance the power signal or ground signal transmitted through the first chip pad.

[0010] In addition, since the plurality of connection lines may not electrically connect the first sub-chip pad to the plurality of upper substrate pads, the first height of the molding member for covering the plurality of connection lines on the package substrate may be reduced. Since the first height of the molding member is reduced, the overall height of the semiconductor package may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 6 represents non-limiting example embodiments described herein.

[0012] Figure 1 is a perspective view illustrating a semiconductor package according to example embodiments.

[0013] Figure 2 is a plan view illustrating a package substrate on which a first semiconductor chip is stacked according to example embodiments.

[0014] Figure 3 is a plan view illustrating a package substrate on which a first semiconductor chip and a second semiconductor chip are stacked according to example embodiments.

[0015] Figure 4 It is along Figure 3 Cross-sectional views taken along lines AA', BB' and CC'.

[0016] Figure 5 is a perspective view illustrating a semiconductor package according to example embodiments.

[0017] Figure 6 is a plan view illustrating a package substrate on which first to fourth semiconductor chips are stacked according to example embodiments. DETAILED DESCRIPTION

[0018] Hereinafter, some example embodiments will be explained in detail with reference to the accompanying drawings.

[0019] Figure 1 is a perspective view illustrating a semiconductor package according to example embodiments. Figure 2 is a plan view illustrating a package substrate on which a first semiconductor chip is stacked according to example embodiments. Figure 3 is a plan view illustrating a package substrate on which a first semiconductor chip and a second semiconductor chip are stacked according to example embodiments. Figure 4 It is along Figure 3 Cross-sectional views taken along lines AA', BB' and CC'.

[0020] Reference Figures 1 to 4The semiconductor package 10 may include a package substrate 100, a first semiconductor chip 200 and a second semiconductor chip 300 sequentially stacked on the package substrate 100, and a plurality of connection wires 400 configured to electrically connect the package substrate 100 with the first semiconductor chip 200 and the second semiconductor chip 300. The first semiconductor chip 200 and the second semiconductor chip 300 may be semiconductor devices of the same type.

[0021] The first semiconductor chip 200 and the second semiconductor chip 300 may be stacked on the semiconductor package 10 in an inclined step shape. In this specification, the direction (Y direction) in which the inclined step shape (or step shape) extends may be referred to as the second horizontal direction, and the horizontal direction (X direction) perpendicular to the second horizontal direction may be referred to as the first horizontal direction. The direction (Z direction) perpendicular to the first horizontal direction and the second horizontal direction will be referred to as the vertical direction.

[0022] In some example embodiments, the package substrate 100 may have a first surface 102 and a second surface 104 opposite to the first surface 102. The first semiconductor chip 200 and the second semiconductor chip 300 may be sequentially stacked on the first surface 102 of the package substrate 100, and the package substrate 100 may be electrically connected to the first semiconductor chip 200 and the second semiconductor chip 300. For example, the package substrate 100 may include a printed circuit board (PCB), a flexible substrate, a tape substrate, etc. The printed circuit board may be a multilayer circuit board having vias and various circuits therein.

[0023] The package substrate 100 may include a core layer 110 , conductive through vias 120 , an upper conductive pattern 130 , an upper insulating layer 140 , a plurality of upper substrate pads 150 , a lower conductive pattern 160 , a lower insulating layer 170 , a plurality of lower substrate pads 180 , and a plurality of external connection bumps 190 .

[0024] The core layer 110 may include a non-conductive material layer. The core layer 110 may include a reinforced polymer, etc. The core layer 110 may serve as a boundary layer dividing the package substrate 100 into an upper portion and a lower portion.

[0025] The conductive through vias 120 may penetrate the core layer 110 (e.g., extend into the core layer 110), and may electrically connect the upper conductive pattern 130 and the lower conductive pattern 160. When the first semiconductor chip 200 and the second semiconductor chip 300 are disposed on the first surface 102 of the package substrate 100, the conductive through vias 120 may electrically connect the first semiconductor chip 200 and the second semiconductor chip 300 and other semiconductor devices disposed on the second surface 104 of the package substrate 100. That is, the conductive through vias 120 may electrically connect the first semiconductor chip 200 and the second semiconductor chip 300 on the first surface 102 of the package substrate 100 to other semiconductor devices disposed on the second surface 104 of the package substrate 100.

[0026] The upper insulating layer 140 and the lower insulating layer 170 may include a polymer or a dielectric layer. The upper insulating layer 140 and the lower insulating layer 170 may be formed by a vapor deposition process, a spin coating process, or the like.

[0027] The upper conductive pattern 130 may be disposed in the upper insulating layer 140. The upper conductive pattern 130 may be electrically connected to the first semiconductor chip 200 and the second semiconductor chip 300. The upper conductive pattern 130 may include a power line or a ground line as a power grid for supplying power to the electronic components mounted on the package substrate 100. A power signal or a ground signal may be transmitted through the upper conductive pattern 130. The upper conductive pattern 130 may extend in the longitudinal direction of the core layer 110 within the upper insulating layer 140. The lower surface of the upper conductive pattern 130 may contact the core layer 110.

[0028] The upper substrate pad 150 may be exposed from the first surface 102 of the package substrate 100. The upper substrate pad 150 may be disposed in the upper insulating layer 140. The upper substrate pad 150 may be electrically connected to the upper conductive pattern 130.

[0029] The upper substrate pad 150 may include at least one power pad 152 electrically connected to a power line and at least one ground pad 154 connected to a ground line. The upper substrate pad 150 may also include a plurality of signal pads 156 configured to transmit data signals to electronic components.

[0030] Although only some of the upper substrate pads are shown in the drawings, it will be understood that the number and arrangement of the upper substrate pads in the drawings are merely examples and are not limiting.

[0031] The lower conductive pattern 160 may be disposed in the lower insulating layer 170. The lower conductive pattern 160 may be electrically connected to the first semiconductor chip 200 and the second semiconductor chip 300. A power signal or a ground signal may be transmitted through the lower conductive pattern 160. A data signal may be transmitted through the lower conductive pattern 160. The lower conductive pattern 160 may extend in the longitudinal direction of the core layer 110 within the lower insulating layer 170. An upper surface of the lower conductive pattern 160 may contact the core layer 110.

[0032] The lower substrate pad 180 may be exposed from the second surface 104 of the package substrate 100. The lower substrate pad 180 may be disposed in the lower insulating layer 170. The lower substrate pad 180 may be electrically connected to the lower conductive pattern 160. The external connection bump 190 may be disposed on the lower substrate pad 180 to be electrically connected to an external device. For example, the external connection bump 190 may include a solder ball.

[0033] The upper and lower substrate pads 150 and 180 and the upper and lower conductive patterns 130 and 160 may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof. The upper and lower substrate pads 150 and 180 and the upper and lower conductive patterns 130 and 160 may be formed by an electroplating process, an electroless plating process, a vapor deposition process, or the like.

[0034] In some example embodiments, the first semiconductor chip 200 may include a first substrate 210, a first activation layer 212 disposed on a first surface of the first substrate 210, and a first wiring layer 230 having first wirings 220 disposed on the first activation layer 212 and electrically connected to the plurality of first circuit patterns 214. The first semiconductor chip 200 may have a first upper surface 202 and a first lower surface 204 opposite to the first upper surface 202.

[0035] In some example embodiments, the first activation layer 212 may include a first circuit layer therein. The first circuit layer may include a plurality of first circuit patterns 214 therein. The first circuit patterns 214 may include transistors, diodes, etc. The first circuit patterns 214 may be formed on the first surface of the first substrate 210 by a wafer process called a front end of line (FEOL).

[0036] The type of the first semiconductor chip 200 may be determined based on the first circuit pattern of the first activation layer 212. For example, the first activation layer 212 may include an application processor (AP). The first activation layer 212 may include an SRAM (static random access memory), a DRAM (dynamic random access memory), a NAND flash memory, a silicon carbide circuit (SiC circuit), etc.

[0037] The first wiring layer 230 may be disposed on the first upper surface 202 of the first semiconductor chip 200. The first wiring layer 230 may be formed on the first surface of the first substrate 210 by a wiring process called a back-end-of-line (BEOL). The first wiring layer 230 may include a first insulating layer 222 and a first wiring 220 disposed in the first insulating layer 222. For example, the first insulating layer 222 may include a polymer, a dielectric layer, etc. The first insulating layer 222 may include polyimide (PI), lead oxide (PbO), polyhydroxystyrene (PHS), or novolac. The first insulating layer 222 may be formed by a vapor deposition process, a spin coating process, etc.

[0038] The first wiring 220 may be formed by forming a seed layer on a portion of the first insulating layer 222 and in an opening in the first insulating layer 222; patterning the seed layer; and then performing an electrolytic plating process. Thus, at least a portion of the first wiring 220 may directly contact a wiring of another layer through the opening. The first wiring 220 may be electrically connected to the first circuit pattern 214. For example, the first wiring 220 may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0039] In some example embodiments, the first semiconductor chip 200 may include a plurality of first chip pads 240 and first selection pads 250 arranged to be spaced apart from each other in a first horizontal direction (X direction) and a plurality of first sub-chip pads 260 arranged to be spaced apart from each other in a second horizontal direction (Y direction). The first chip pads 240, the first selection pads 250, and the first sub-chip pads 260 may be exposed from the first upper surface 202 of the first semiconductor chip 200.

[0040] The first chip pad 240 may be arranged to be spaced apart from the power pad 152 or the ground pad 154 in the second horizontal direction (Y direction). The first chip pad 240 may be electrically connected to the power pad 152 or the ground pad 154 through the connection line 400. The first chip pad 240 may receive a power signal from the power pad 152 or a ground signal from the ground pad 154.

[0041] The first selection pad 250 may be arranged to be spaced apart from the first chip pad 240 in the first horizontal direction (X direction). The first selection pad 250 may be arranged to be spaced apart from the upper substrate pad 150 in the second horizontal direction (Y direction). The first selection pad 250 may be electrically connected to the upper substrate pad 150 through the connection line 400. The first selection pad 250 may receive a data signal from the upper substrate pad 150.

[0042] The plurality of first sub-chip pads 260 may be arranged to be spaced apart from the first chip pad 240 in the second horizontal direction (Y direction). For example, the plurality of first sub-chip pads 260 may be arranged to be sequentially spaced apart from any one of the first chip pads 240 in the second horizontal direction (Y direction). In some example embodiments, the plurality of first sub-chip pads 260 may be arranged to be spaced apart from the first selection pad 250 in the second horizontal direction (Y direction).

[0043] A plurality of first sub chip pads 260 may be arranged along the first side 206 of the first semiconductor chip 200. The plurality of first sub chip pads 260 may be arranged adjacent to the first side 206. For example, the first side 206 may have a side surface extending in a longitudinal direction (Y direction) of the first semiconductor chip 200.

[0044] The plurality of first sub chip pads 260 may be electrically connected to the plurality of first chip pads 240 through the first wirings 220, respectively. The plurality of first sub chip pads 260 may receive a power signal or a ground signal from the first chip pad 240.

[0045] Since the plurality of first sub-chip pads 260 are electrically connected to the plurality of first chip pads 240 through the first wiring 220, the plurality of first sub-chip pads 260 can reduce an electrical load applied from a power signal or a ground signal to the plurality of first chip pads 240. The first sub-chip pads 260 can enhance the power signal or the ground signal through the first wiring 220.

[0046] A plurality of first sub-chip pads 260 may be disposed on a first corner region CR1 of the first semiconductor chip 200 together with the first chip pad 240. The first corner region CR1 may be disposed on any one of the four corners of the first semiconductor chip 200. For example, the package substrate 100 may further include an upper substrate pad 150' exposed from the first surface 102 of the package substrate 100. The upper substrate pad 150' may be arranged along a second horizontal direction (Y direction) and include at least one power pad 152' and at least one ground pad 154', but is not limited thereto. The first corner region CR1 may be disposed on an area adjacent to the upper substrate pad 150' among the four corner regions. For example, the first corner region CR1 may have an "L" shape.

[0047] A plurality of first chip pads 240 and first selection pads 250 may be arranged to be spaced apart from each other in the first horizontal direction (X direction). For example, the number of first chip pads 240 may be in the range of 4 to 8. The number of first sub-chip pads 260 may be in the range of 4 to 8.

[0048] In some example embodiments, the second semiconductor chip 300 may include a second substrate 310, a second activation layer 312, and a second wiring layer 330, the second activation layer 312 being disposed on a first surface of the second substrate 310, and the second wiring layer 330 having second wirings 320 disposed on the second activation layer 312 and electrically connected to the plurality of second circuit patterns 314. The second semiconductor chip 300 may be a semiconductor device of the same type as the first semiconductor chip 200. The second semiconductor chip 300 may have a second upper surface 302 and a second lower surface 304 opposite to the second upper surface 302.

[0049] The second semiconductor chip 300 may be stacked in a stepped shape on the first semiconductor chip 200 (eg, in the second horizontal direction (Y direction)). The second semiconductor chip 300 may be stacked in a stepped shape such that the second semiconductor chip 300 exposes the first chip pad 240 and the first selection pad 250 of the first semiconductor chip 200.

[0050] The second semiconductor chip 300 may be disposed to cover the first sub-chip pad 260 of the first semiconductor chip 200. Since the second semiconductor chip 300 covers the first sub-chip pad 260, the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 may be increased. As the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 increases, the overhang portion of the second semiconductor chip 300 protruding from the first semiconductor chip 200 may be reduced. Due to the reduction of the overhang portion, deflection at the overhang portion may be reduced or prevented.

[0051] Since the first sub chip pad 260 is electrically connected to the first chip pad 240 through the first wiring 220 , the first sub chip pad 260 may enhance a power signal or a ground signal even if the second semiconductor chip 300 covers the first sub chip pad 260 .

[0052] In some example embodiments, the second activation layer 312 may include a second circuit layer therein. The second circuit layer may include a plurality of second circuit patterns 314 therein. The second wiring layer 330 may be disposed on the second upper surface 302 of the second semiconductor chip 300. The second wiring layer 330 may include a second insulating layer 322 and a second wiring 320 disposed in the second insulating layer 322.

[0053] In some example embodiments, the second semiconductor chip 300 may include a plurality of second chip pads 340 and second selection pads 350 arranged to be spaced apart from each other in a first horizontal direction (X direction) and a plurality of second sub-chip pads 360 arranged to be spaced apart from each other in a second horizontal direction (Y direction). The second chip pads 340, the second selection pads 350, and the second sub-chip pads 360 may be exposed from the second upper surface 302 of the second semiconductor chip 300.

[0054] The second chip pad 340 may be arranged to be spaced apart from the first chip pad 240 of the first semiconductor chip 200 in the second horizontal direction (Y direction). The second chip pad 340 may be electrically connected to the first chip pad 240 through the connection line 400. The second chip pad 340 may receive a power signal or a ground signal from the first chip pad 240.

[0055] The second selection pad 350 may be arranged to be spaced apart from the second chip pad 340 in the first horizontal direction (X direction). The second selection pad 350 may be arranged to be spaced apart from the first selection pad 250 of the first semiconductor chip 200 in the second horizontal direction (Y direction). The second selection pad 350 may be electrically connected to the first selection pad 250 through a connection line 400. The second selection pad 350 may receive a data signal from the first selection pad 250.

[0056] The plurality of second sub-chip pads 360 may be arranged to be spaced apart from the second chip pad 340 in the second horizontal direction (Y direction). For example, the plurality of second sub-chip pads 360 may be arranged to be sequentially spaced apart from any one of the second chip pads 340 in the second horizontal direction (Y direction). In some example embodiments, the plurality of second sub-chip pads 360 may be arranged to be spaced apart from the second selection pad 350 in the second horizontal direction (Y direction).

[0057] A plurality of second sub chip pads 360 may be arranged along the second side 306 of the second semiconductor chip 300. The plurality of second sub chip pads 360 may be arranged adjacent to the second side 306. For example, the second side 306 may have a side surface extending in a longitudinal direction (Y direction) of the second semiconductor chip 300.

[0058] For example, the second side 306 of the second semiconductor chip 300 may be disposed in the same plane as the first side 206 of the first semiconductor chip 200. Because the first side 206 and the second side 306 are disposed in the same plane, the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 may be increased. As the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 increases, the structural stability between the first semiconductor chip 200 and the second semiconductor chip 300 may be increased.

[0059] The plurality of second sub chip pads 360 may be electrically connected to the plurality of second chip pads 340 through the second wirings 320 , respectively. The plurality of second sub chip pads 360 may receive a power signal or a ground signal from the second chip pad 340 .

[0060] Since the plurality of second sub chip pads 360 are electrically connected to the plurality of second chip pads 340 through the second wiring 320, the plurality of second sub chip pads 360 can reduce an electrical load applied from a power signal or a ground signal to the plurality of second chip pads 340. The second sub chip pads 360 can enhance the power signal or the ground signal through the second wiring 320.

[0061] The plurality of second sub chip pads 360 may be electrically connected to the upper substrate pad 150' of the package substrate 100 through connection lines 400, respectively. The plurality of second sub chip pads 360 may transmit a power signal or a ground signal to the upper substrate pad 150'.

[0062] Since the plurality of second sub chip pads 360 are electrically connected to the plurality of upper substrate pads 150' through the connection wires 400, the plurality of second sub chip pads 360 can reduce the electrical load applied from the power signal or the ground signal to the plurality of second chip pads 340. The second sub chip pads 360 can enhance the power signal or the ground signal through the second wiring 320 and the connection wires 400.

[0063] A plurality of second sub-chip pads 360 may be disposed on the second corner region CR2 of the second semiconductor chip 300 together with the second chip pad 340. The second corner region CR2 may be disposed on any one of the four corners of the second semiconductor chip 300. The second corner region CR2 may be a region corresponding to the first corner region CR1 of the first semiconductor chip 200. The second corner region CR2 may be disposed on a region adjacent to the first chip pad 240 among the four corner regions. For example, the second corner region CR2 may have an "L" shape.

[0064] In some example embodiments, the plurality of connection lines 400 may electrically connect the package substrate 100 with the first semiconductor chip 200 and the second semiconductor chip 300. The plurality of connection lines 400 may include a first wire 410, a second wire 420, and a third wire 430. The first wire 410 and the second wire 420 may extend in the second horizontal direction (Y direction), respectively. The third wire 430 may extend in the first horizontal direction (X direction), respectively.

[0065] The first conductive line 410 may transmit a power signal, a ground signal, or a data signal between the package substrate 100 and the first semiconductor chip 200. The first conductive line 410 may electrically connect the upper substrate pad 150 to the first chip pad 240 and the first selection pad 250, respectively.

[0066] The first wire 410 may transmit a power signal from the power pad 152 to the first chip pad 240. The first wire 410 may transmit a ground signal from the ground pad 154 to the first chip pad 240. The first wire 410 may transmit a data signal from the signal pad 156 to the first selection pad 250.

[0067] The second conductive line 420 may transmit a power signal, a ground signal, or a data signal between the first semiconductor chip 200 and the second semiconductor chip 300. The second conductive line 420 may electrically connect the first chip pad 240 and the second chip pad 340 to each other. The second conductive line 420 may electrically connect the first selection pad 250 and the second selection pad 350 to each other.

[0068] The second conductive line 420 may transmit a power signal or a ground signal from the first chip pad 240 to the second chip pad 340. The second conductive line 420 may transmit a data signal from the first selection pad 250 to the second selection pad 350.

[0069] The third wire 430 may transmit a power signal or a ground signal between the package substrate 100 and the second semiconductor chip 300. The third wire 430 may electrically connect the upper substrate pad 150' and the second sub-chip pad 360 to each other. The third wire 430 may transmit a power signal or a ground signal from the second sub-chip pad 360 to the upper substrate pad 150'.

[0070] For example, the first to third conductive lines 410 , 420 , and 430 may include copper (Cu), aluminum (Al), tungsten, nickel (Ni), molybdenum (Mo), gold (Au), silver (Ag), chromium (Cr), tin (Sn), titanium (Ti), or alloys thereof.

[0071] In some example embodiments, the semiconductor package 10 may further include a molding member 500 covering the first and second semiconductor chips 200 and 300 on the package substrate 100 .

[0072] The molding member 500 may be formed on the package substrate 100 to protect the first and second semiconductor chips 200 and 300 and the connection wires 400 from external influences. For example, the molding member 500 may include an epoxy molding compound (EMC).

[0073] The molding member 500 may have a first height H1 from the first surface 102 of the package substrate 100. Since the first sub chip pad 260 of the first semiconductor chip 200 is electrically connected to the first chip pad 240 through the first wiring 220, the first sub chip pad 260 may not be in direct contact with the connection wire 400. Since the number of connection wires 400 for electrically connecting the first sub chip pad 260 to the package substrate 100 is reduced, the first height H1 of the molding member 500 may be reduced. Since the first height H1 of the molding member 500 is reduced, the thickness of the semiconductor package 10 may be reduced.

[0074] As described above, the first semiconductor chip 200 and the second semiconductor chip 300 may be sequentially stacked on the package substrate 100. Since the second semiconductor chip 300 is stacked to cover the first sub-chip pad 260 of the first semiconductor chip 200, the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 may be increased when viewed in a plan view. Since the overlapping area between the first semiconductor chip 200 and the second semiconductor chip 300 is increased, the overhang portion may be reduced, thereby reducing the bending phenomenon occurring in the second semiconductor chip 300.

[0075] Because the first sub chip pad 260 of the first semiconductor chip 200 is covered by the second semiconductor chip 300, the first sub chip pad 260 may be electrically connected to the first chip pad 240 through the first wiring 220. Because the first sub chip pad 260 is electrically connected to the first chip pad 240 through the first wiring 220, the first sub chip pad 260 may enhance a power signal or a ground signal transmitted through the first chip pad 240.

[0076] Since the plurality of connection lines 400 do not need to electrically connect the first sub-chip pad 260 to the plurality of upper substrate pads 150, the first height H1 of the molding member 500 for covering the plurality of connection lines on the package substrate 100 can be reduced. Since the first height H1 of the molding member 500 is reduced, the overall height of the semiconductor package 10 can be reduced.

[0077] Figure 5 is a perspective view illustrating a semiconductor package according to example embodiments. Figure 6 1 is a plan view showing a package substrate on which first to fourth semiconductor chips are stacked according to an example embodiment. In addition to the additional third and fourth semiconductor chips, the semiconductor package may be similar to the reference Figures 1 to 4 The described semiconductor packages are substantially the same or similar. Therefore, the same reference numerals may be used for the same or similar elements, and any further repeated explanation regarding the above elements will be omitted.

[0078] Reference Figure 5 and Figure 6 , the semiconductor package 12 may include a first semi-package 20 having a first semiconductor chip 200 and a second semiconductor chip 300 and a second semi-package 30 having a third semiconductor chip 600 and a fourth semiconductor chip 700. The first to fourth semiconductor chips 200, 300, 600, and 700 may be the same type of semiconductor devices.

[0079] The first half package 20 may be disposed on the package substrate 100. The first semiconductor chip 200 and the second semiconductor chip 300 may be sequentially stacked on the package substrate 100 to form the first half package 20. The second half package 30 may be disposed on the first half package 20. The third semiconductor chip 600 and the fourth semiconductor chip 700 may be sequentially stacked on the first half package 20 as the second half package 30.

[0080] In some example embodiments, the plurality of connection lines 400 may electrically connect the package substrate 100 and the first and second half packages 20 and 30. The plurality of connection lines 400 may include first to sixth conductive lines 410, 420, 430, 440, 450, and 460.

[0081] In some example embodiments, the third semiconductor chip 600 may include a plurality of third chip pads 620 and third selection pads 630 arranged to be spaced apart from each other in a first horizontal direction (X direction) and a plurality of third sub chip pads (not shown) arranged to be spaced apart from each other in a second horizontal direction (Y direction).

[0082] The third chip pad 620 may be electrically connected to the power pad 152 or the ground pad 154 through the fourth wire 440. The third selection pad 630 may be electrically connected to the upper substrate pad 150 through the fourth wire 440. The plurality of third sub-chip pads may be electrically connected to the plurality of third chip pads 620 through the third wiring 610, respectively. The plurality of third sub-chip pads may receive a power signal or a ground signal from the third chip pad 620 through the third wiring 610.

[0083] The third semiconductor chip 600 may be stacked such that the second chip pad 340 , the second selection pad 350 , and the second sub chip pad 360 of the second semiconductor chip 300 are exposed. The third semiconductor chip 600 may be stacked on the second semiconductor chip 300 to expose the second corner region CR2 of the second semiconductor chip 300 .

[0084] Because the third semiconductor chip 600 exposes the second chip pad 340 , the second selection pad 350 , and the second sub chip pad 360 , the second wires 420 and the third wires 430 may electrically connect the second chip pad 340 , the second selection pad 350 , and the second sub chip pad 360 to the package substrate 100 or the first semiconductor chip 200 .

[0085] In some example embodiments, the fourth semiconductor chip 700 may be stacked in a step shape on the third semiconductor chip 600. Because the fourth semiconductor chip 700 is stacked in a step shape, the fourth semiconductor chip 700 may expose the third chip pad 620 and the third selection pad 630 of the third semiconductor chip 600.

[0086] The fourth semiconductor chip 700 may be disposed to cover the third sub chip pad of the third semiconductor chip 600. Since the fourth semiconductor chip 700 covers the third sub chip pad, the overlapping area between the third semiconductor chip 600 and the fourth semiconductor chip 700 may be increased. Since the overlapping area between the third semiconductor chip 600 and the fourth semiconductor chip 700 is increased, the overhanging portion of the fourth semiconductor chip 700 protruding from the third semiconductor chip 600 may be reduced.

[0087] The fourth semiconductor chip 700 may include a plurality of fourth chip pads 720 and fourth selection pads 730 arranged to be spaced apart from each other in the first horizontal direction (X direction) and a plurality of fourth sub chip pads 740 arranged to be spaced apart from each other in the second horizontal direction (Y direction).

[0088] The fourth chip pad 720 may be electrically connected to the third chip pad 620 through the fifth wire 450. The fourth selection pad 730 may be electrically connected to the third selection pad 630 through the fifth wire 450. The plurality of fourth sub-chip pads 740 may be electrically connected to the upper substrate pad 150' of the package substrate 100 through the sixth wire 460, respectively. The plurality of fourth sub-chip pads 740 may receive a power signal or a ground signal from the fourth chip pad 720 through the fourth wiring 710.

[0089] The foregoing is an illustration of some example embodiments and should not be construed as limiting thereof. Although several example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the disclosed example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims.

Claims

1. A semiconductor package, comprising: A packaging substrate having a plurality of substrate pads; A first semiconductor chip is stacked on the package substrate, the first semiconductor chip comprises a plurality of first chip pads, a plurality of first selection pads, a plurality of first sub-chip pads and a plurality of first wirings, the plurality of first chip pads and the plurality of first selection pads are along a first horizontal direction, the plurality of first sub-chip pads are along a second horizontal direction perpendicular to the first horizontal direction, and the plurality of first wirings electrically connect the plurality of first chip pads and the plurality of first sub-chip pads to each other; a second semiconductor chip, stacked on the first semiconductor chip to cover the plurality of first sub-chip pads, the second semiconductor chip comprising a plurality of second chip pads, a plurality of second selection pads, a plurality of second sub-chip pads, and a plurality of second wirings, the plurality of second chip pads and the plurality of second selection pads are along a first horizontal direction, the plurality of second sub-chip pads are along a second horizontal direction, and the plurality of second wirings electrically connect the plurality of second chip pads and the plurality of second sub-chip pads to each other; as well as A plurality of connection lines electrically connect the package substrate, the first semiconductor chip and the second semiconductor chip.

2. The semiconductor package according to claim 1, wherein: The plurality of connecting lines include: a first conductive wire electrically connecting the plurality of substrate pads and the plurality of first chip pads; and The second conductive wire electrically connects the plurality of first chip pads and the plurality of second chip pads.

3. The semiconductor package according to claim 2, wherein: The plurality of first chip pads and the plurality of second chip pads are configured to receive a power signal or a ground signal from a package substrate through first and second conductive lines.

4. The semiconductor package according to claim 3, wherein: The plurality of first sub-chip pads are configured to receive a power signal or a ground signal from the plurality of first chip pads through the plurality of first wirings.

5. The semiconductor package according to claim 2, wherein: The first conductive wires electrically connect the plurality of base pads and the plurality of first selection pads respectively, and The second conductive lines electrically connect the plurality of first selection pads and the plurality of second selection pads, respectively.

6. The semiconductor package according to claim 5, wherein: The plurality of first selection pads and the plurality of second selection pads receive data signals from a package substrate through first and second conductive lines.

7. The semiconductor package according to claim 1, wherein: The plurality of connection lines include third conductive lines electrically connecting the plurality of base pads and the plurality of second sub-chip pads, respectively.

8. The semiconductor package according to claim 7, wherein: The plurality of second sub-chip pads are configured to transmit a power signal or a ground signal to the package substrate through a third conductive line.

9. The semiconductor package according to claim 1, wherein: The second semiconductor chip is stacked on the first semiconductor chip in a step shape in a second horizontal direction.

10. The semiconductor package according to claim 1, wherein The plurality of first chip pads are spaced apart from the plurality of second chip pads in a second horizontal direction, and the plurality of first selection pads are spaced apart from the plurality of second selection pads in the second horizontal direction.

11. The semiconductor package according to claim 1, wherein: The plurality of first sub-chip pads are along a first side of the first semiconductor chip, The plurality of second sub-chip pads are along a second side of the second semiconductor chip, and The first side portion and the second side portion are in the same plane.

12. The semiconductor package according to claim 1, wherein The plurality of first chip pads and the plurality of first sub-chip pads are on a first corner region of the first semiconductor chip, and The plurality of second chip pads and the plurality of second sub-chip pads are on a second corner region of the second semiconductor chip corresponding to the first corner region.

13. The semiconductor package according to claim 1, wherein: The first semiconductor chip and the second semiconductor chip are the same type of semiconductor devices.

14. The semiconductor package according to any one of claims 1 to 13, further comprising: a third semiconductor chip, stacked on the second semiconductor chip to expose the plurality of second chip pads, the plurality of second selection pads, and the plurality of second sub-chip pads, the third semiconductor chip comprising a plurality of third chip pads, a plurality of third sub-chip pads, and a plurality of third wirings, the plurality of third chip pads being along a first horizontal direction, the plurality of third sub-chip pads being along a second horizontal direction, and the plurality of third wirings electrically connecting the plurality of third chip pads and the plurality of third sub-chip pads to each other; as well as a fourth semiconductor chip, stacked on the third semiconductor chip to cover the plurality of third sub-chip pads, the fourth semiconductor chip comprising a plurality of fourth chip pads, a plurality of fourth sub-chip pads and a plurality of fourth wirings, the plurality of fourth chip pads being along a first horizontal direction, the plurality of fourth sub-chip pads being along a second horizontal direction, the plurality of fourth wirings electrically connecting the plurality of fourth chip pads and the plurality of fourth sub-chip pads to each other, The plurality of connection lines electrically connect the package substrate, the third semiconductor chip and the fourth semiconductor chip.

15. The semiconductor package according to claim 14, wherein: The plurality of connecting lines also include: fourth wires, electrically connecting the plurality of base pads and the plurality of third chip pads respectively; fifth conductive wires, electrically connecting the plurality of third chip pads and the plurality of fourth chip pads respectively; and A sixth conductive wire electrically connects the plurality of base pads and the plurality of fourth sub-chip pads.

16. The semiconductor package according to claim 15, wherein: The plurality of third chip pads, the plurality of fourth chip pads, and the plurality of fourth sub-chip pads are configured to receive a power signal or a ground signal from a package substrate through fourth to sixth wires.

17. A semiconductor package, comprising: A packaging substrate having a plurality of substrate pads; A first semiconductor chip is stacked on the package substrate, the first semiconductor chip comprises a plurality of first chip pads, a plurality of first sub-chip pads and a plurality of first wirings, the plurality of first chip pads are along a first horizontal direction, the plurality of first sub-chip pads are along a second horizontal direction perpendicular to the first horizontal direction, and the plurality of first wirings electrically connect the plurality of first chip pads and the plurality of first sub-chip pads to each other; a second semiconductor chip, stacked on the first semiconductor chip to cover the plurality of first sub-chip pads, the second semiconductor chip comprising a plurality of second chip pads, a plurality of second sub-chip pads, and a plurality of second wirings, the plurality of second chip pads being along a first horizontal direction, the plurality of second sub-chip pads being along a second horizontal direction, the plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads to each other; as well as A plurality of connection lines electrically connect the plurality of first chip pads, the plurality of second chip pads, and the plurality of second sub-chip pads to the plurality of substrate pads, and are configured to transmit a power signal or a ground signal.

18. The semiconductor package according to claim 17, wherein: The plurality of connecting lines include: a first conductive wire electrically connecting the plurality of base pads and the plurality of first chip pads; a second conductive wire electrically connecting the plurality of first chip pads and the plurality of second chip pads; and The third conductive wire electrically connects the plurality of base pads and the plurality of second sub-chip pads.

19. The semiconductor package according to claim 17, wherein: The plurality of first sub-chip pads receive power signals or ground signals from the plurality of first chip pads through the plurality of first wirings.

20. A semiconductor package, comprising: A packaging substrate having a plurality of substrate pads; A first half package having a first semiconductor chip and a second semiconductor chip sequentially stacked on a package substrate; a second half package having a third semiconductor chip and a fourth semiconductor chip sequentially stacked on the first half package; as well as a plurality of connection lines electrically connecting the first half package and the second half package to the package substrate and configured to transmit a power signal or a ground signal, The first semiconductor chip includes a plurality of first chip pads along a first horizontal direction, a plurality of first sub-chip pads along a second horizontal direction perpendicular to the first horizontal direction, and a plurality of first wirings electrically connecting the plurality of first chip pads and the plurality of first sub-chip pads to each other. The second semiconductor chip includes a plurality of second chip pads along a first horizontal direction, a plurality of second sub-chip pads along a second horizontal direction, and a plurality of second wirings electrically connecting the plurality of second chip pads and the plurality of second sub-chip pads to each other. wherein the second semiconductor chip is stacked on the first semiconductor chip to cover the plurality of first sub-chip pads and expose the plurality of first chip pads, The third semiconductor chip includes a plurality of third chip pads along a first horizontal direction, a plurality of third sub-chip pads along a second horizontal direction, and a plurality of third wirings electrically connecting the plurality of third chip pads and the plurality of third sub-chip pads to each other. wherein the third semiconductor chip is stacked on the second semiconductor chip to expose the plurality of second chip pads and the plurality of second sub-chip pads, The fourth semiconductor chip includes a plurality of fourth chip pads along the first horizontal direction, a plurality of fourth sub-chip pads along the second horizontal direction, and a plurality of fourth wirings electrically connecting the plurality of fourth chip pads and the plurality of fourth sub-chip pads to each other, and The fourth semiconductor chip is stacked on the third semiconductor chip to cover the plurality of third sub-chip pads and expose the plurality of third chip pads.

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