Test structure, system and method

Abstract

The invention relates to a test structure, system and method. The test structure comprises a wafer and a plurality of test pads. Wherein the wafer comprises to-be-tested chips which are arranged in an array mode in the first direction and the second direction, cutting channels are arranged between every two adjacent to-be-tested chips in the first direction and between every two adjacent to-be-tested chips in the second direction, and every two adjacent to-be-tested chips in the second direction are in central symmetry; wherein the to-be-tested chip comprises a plurality of chip bonding pads arranged in the first direction, and the chip bonding pads are arranged on the side, close to the cutting channel in the second direction, of the to-be-tested chip; the plurality of test bonding pads are arranged corresponding to the chip bonding pads and are located in the cutting channels between the adjacent chip bonding pads in the second direction; wherein the same test bonding pad is electrically connected with the chip bonding pad adjacent to the same test bonding pad along the second direction, the channel lengths are equal, and the first direction intersects with the second direction. The above structure can improve the test efficiency, improve the chip capacity, guarantee the test stability and reduce the test cost.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a test structure, system and method. Background Art

[0002] In the semiconductor manufacturing process, wafers need to be probed after production to check whether their quality is qualified, that is, probe cards are used to connect to the test pads of each chip on the wafer to form a test path for testing. Among them, the number and position design of test pads is an important part of chip design, which affects the maximum number of simultaneous tests in the test process, and thus affects the cost and efficiency of the entire test process.

[0003] With the development of semiconductor technology and the shrinkage of process nodes, the test pads in the common wafer probe test occupy a large space and will result in a small number of chips being tested, reducing the yield and efficiency of wafer testing. Summary of the invention

[0004] Based on this, the present disclosure provides a test structure, system and method, which can save the space occupied by the test pads, increase the maximum number of simultaneous measurements during the wafer testing process, and ensure the stability and accuracy of the testing process, thereby improving the yield of the product.

[0005] According to various embodiments of the present disclosure, on the one hand, a test structure is provided, including a wafer and a plurality of test pads; wherein the wafer includes chips to be tested arranged in an array along a first direction and a second direction, a cutting path is provided between two adjacent chips to be tested along the first direction and between two adjacent chips to be tested along the second direction, and two adjacent chips to be tested along the second direction are centrally symmetrical with each other; wherein the chip to be tested includes a plurality of chip pads arranged along the first direction, and the chip pads are provided on a side of the chip to be tested close to the cutting path along the second direction; a plurality of test pads are provided corresponding to the chip pads, and are located in the cutting path between the adjacent chip pads along the second direction; wherein the same test pad is electrically connected to the chip pad adjacent to it along the second direction and the channel lengths are equal, and the first direction intersects with the second direction.

[0006] In the test structure in the above embodiment, by arranging a plurality of test pads in the cutting path between the chip pads adjacent along the second direction, and correspondingly arranged with the chip pads, at least two chips to be tested can be tested at the same time based on one test pad, the number of simultaneous tests of the test is increased, thereby improving the test efficiency, and the space reserved for the test inside the chip to be tested can be saved, thereby improving the capacity of the chip to be tested. In addition, since the number of test pads is reduced, the test cost can be reduced, that is, the cost of the test equipment and the cost of the test process can be reduced. Also, since the two chips to be tested adjacent to each other along the second direction are centrally symmetrical, it can be ensured that the channel length of a test pad is equal when testing multiple chips to be tested, that is, the signal transmission paths are of equal length, thereby ensuring the consistency and stability of the test results and improving the accuracy of the test. The above test structure can improve the problems of small simultaneous tests, high test costs, and low test efficiency in the related art when directly testing the chip pads. In addition, the large number of pads used in the related art will also reduce the success rate of the probe card design and reduce the accuracy of the test. The present invention arranges the test pad in the cutting path so that one test pad can electrically connect at least two chips to be tested at the same time, and arranges the two adjacent chips to be tested along the second direction to be centrally symmetrical with each other, thereby reducing the wiring difference from the test pad to different chips and ensuring the consistency of signals and power supply, thereby improving the yield and efficiency of wafer probe testing and providing further guarantee for improving wafer quality.

[0007] In some embodiments, a same test pad is connected to a chip pad adjacent to the same test pad along the second direction via a wire, and the lengths of the wires along the second direction are equal.

[0008] In some embodiments, there are two chips to be tested adjacent to the same test pad along the second direction, namely a first chip and a second chip, and the first chip and the second chip share a group of test pads; the chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad and a first ground pad arranged in sequence along the first direction; the chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad and a second ground pad arranged in sequence along the first direction.

[0009] In some embodiments, each group of test pads includes a first test pad, a second test pad, a third test pad, a fourth test pad, a fifth test pad, a sixth test pad and a seventh test pad; wherein the first test pad is electrically connected to the first ground pad of the second chip and the second ground pad of the first chip; the second test pad is electrically connected to the first voltage pad of the second chip and the second voltage pad of the first chip; the third test pad is electrically connected to the power pad of the second chip; the fourth test pad is electrically connected to the address pad of the second chip and the address pad of the first chip; the fifth test pad is electrically connected to the power pad of the first chip; the sixth test pad is electrically connected to the second voltage pad of the second chip and the first voltage pad of the first chip; and the seventh test pad is electrically connected to the second ground pad of the second chip and the first ground pad of the first chip.

[0010] In some embodiments, the address pad includes a plurality of address sub-pads arranged along a first direction, and the address sub-pads have address serial numbers.

[0011] In some embodiments, the address serial number of each address sub-pad of the first chip and the address serial number of each address sub-pad of the second chip are centrally symmetric to each other.

[0012] In some of the embodiments, each group of test pads also includes a signal exchange pad, which is located between a second test pad and a third test pad adjacent to each other along the first direction, and between a fifth test pad and a sixth test pad adjacent to each other along the first direction, and is used to change the address numbers of each address sub-pad of the first chip and the address numbers of each address sub-pad of the second chip from central symmetry to mirror symmetry when receiving a first electrical signal.

[0013] In some embodiments, there are four chips to be tested adjacent to the test pads along the second direction and the first direction, namely the first chip, the second chip, the third chip and the fourth chip, and the first chip, the second chip, the third chip and the fourth chip share a set of test pads.

[0014] Another aspect of the present disclosure further provides a test system, comprising the test structure described in any one of the embodiments of the present disclosure and a plurality of probe cards, each probe card being electrically connected to each group of test pads.

[0015] In the test system of the above embodiment, the probe card is connected to the test pad, and one test pad can be connected to at least two chip pads, so that one probe card can test at least two chips to be tested, which improves the number of wafer tests, saves the cost of the probe card and the space occupied by the probe card, and the reduction in the number of test pads can also keep a certain distance between adjacent probe cards, avoid mutual squeezing of the probe cards, and further improve the stability of the test. The above test system can improve the problems of small number of tests, high test cost, low test efficiency, and probe card design failure in the related art of directly testing chip pads. The present disclosure arranges the test pad in the cutting path so that one test pad can be electrically connected to at least two chips to be tested at the same time, that is, one probe card can test at least two chips to be tested at the same time, and sets the two adjacent chips to be tested along the second direction to be centrally symmetrical with each other, reduces the wiring difference from the test pad to different chips to be tested, and ensures the consistency of signals and power supply, thereby improving the yield and efficiency of wafer probe testing, and reducing the test cost.

[0016] In some embodiments, two probe cards connected to two groups of test pads adjacent to each other along the first direction are respectively located at two opposite sides of the test pads along the second direction.

[0017] In some of the embodiments, each probe card includes a circuit board and a plurality of probes disposed on the same side of the circuit board, and the probes in each probe card correspond one-to-one to each group of test pads.

[0018] Another aspect of the present disclosure also provides a testing method for testing the test structure described in any one of the embodiments of the present disclosure, the method comprising: providing a test structure and a probe card; electrically connecting each probe card to each group of test pads; providing a first electrical signal to the test pads electrically connected thereto based on the probe card to test the chip to be tested electrically connected to the test pads; and providing a second electrical signal to the test pads electrically connected thereto based on the probe card to end the test.

[0019] In the test method in the above embodiment, the probe card provides a first electrical signal to the test pad electrically connected thereto, so as to test at least two chips to be tested that are electrically connected to the test pad, and the same test pad is electrically connected to the chip pad adjacent thereto along the second direction and the channel length is equal, so that it can be ensured that there is no test difference between the same test pad and different chips to be tested, that is, the accuracy and yield of the test are improved. The above test method improves the problems of small capacity of the chip to be tested, slow test progress, and low test yield caused by a large number of test pads in the related art, and can improve the stability and consistency of the test while increasing the number of chips to be tested, thereby improving the yield and efficiency of the test and reducing the test cost.

[0020] In some embodiments, each probe card is electrically connected to each group of test pads, including: each probe card is electrically connected to each group of test pads, and two probe cards connected to two adjacent groups of test pads along a first direction are respectively located on opposite sides of the test pads along a second direction.

[0021] In some of these embodiments, the first electrical signal is greater than the second electrical signal.

[0022] In some embodiments, there are two chips to be tested adjacent to the same test pad along the second direction, namely a first chip and a second chip, and the first chip and the second chip share a group of test pads; the chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad and a first ground pad arranged in sequence along the first direction; the chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad and a second ground pad arranged in sequence along the first direction; based on the probe card, a first electrical signal is provided to the test pad electrically connected to it, including: based on the probe card, a first electrical signal is provided to the test pad electrically connected to it, so that the address serial number of each address sub-pad of the first chip where the chip pad corresponding to the test pad is located and the address serial number of each address sub-pad of the second chip are changed from central symmetry to mirror symmetry. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A cross-sectional schematic diagram of a test structure in a related art provided by an embodiment of the present disclosure is shown;

[0025] Figure 2 Shown is a cross-sectional schematic diagram of a test system in a related art provided by an embodiment of the present disclosure;

[0026] Figure 3 A cross-sectional schematic diagram showing a test system in a related art provided by another embodiment of the present disclosure;

[0027] Figure 4 A cross-sectional schematic diagram of a test structure provided by an embodiment of the present disclosure is shown;

[0028] Figure 5 A cross-sectional schematic diagram showing a test structure provided by another embodiment of the present disclosure;

[0029] Figure 6 A cross-sectional schematic diagram showing a test structure provided by another embodiment of the present disclosure;

[0030] Figure 7 A cross-sectional schematic diagram showing a test structure provided by yet another embodiment of the present disclosure;

[0031] Figure 8 A cross-sectional schematic diagram showing a test structure provided by another embodiment of the present disclosure;

[0032] Fig. 9 A cross-sectional schematic diagram of a testing system provided by an embodiment of the present disclosure is shown;

[0033] Fig.10 A cross-sectional schematic diagram showing a testing system provided by another embodiment of the present disclosure;

[0034] Fig.11 Shown is a flow chart of a testing method provided by an embodiment of the present disclosure.

[0035] Description of reference numerals:

[0036] 10 / 20, wafer; 101, chip; 1011, pad; 11 / 21, probe card; 111 / 211, circuit board; 112 / 212, probe; 201, chip to be tested; 201a, first chip; 201b, second chip; 201c, third chip; 201d, fourth chip; 2011, chip pad; 20111, first ground pad; 20112, first voltage pad; 20113, power pad; 201 14. address pad; 20115. second voltage pad; 20116. second ground pad; 202. cutting path; 2021. test pad; 20211. first test pad; 20212. second test pad; 20213. third test pad; 20214. fourth test pad; 20215. fifth test pad; 20216. sixth test pad; 20217. seventh test pad; 20218. signal exchange pad. DETAILED DESCRIPTION

[0037] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0039] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0040] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0041] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0042] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.

[0043] In the semiconductor manufacturing process, wafers need to be probed after production to check whether their quality is qualified. The test signal is transmitted by the test machine and connected to the test pads in each chip through the probe card to form a test path. Among them, the number and position design of the test pads are an important part of chip design, which directly affects the placement of each chip in the whole wafer and the maximum number of simultaneous tests, affecting the cost of the entire testing process. However, the number of test pads is limited by test resources, test methods, and the design and manufacture of probe cards. After the wafer is packaged into chip particles, the test pads also need to test each particle to form a subsequent finished product test path.

[0044] However, with the development of semiconductor technology and the shrinkage of process nodes, in the current high-bandwidth memory (HBM) chip test, the design of the test pad still follows the common design method, that is, the test pad is set inside each chip. However, since the high-bandwidth memory storage chip has a through silicon via (TSV) structure, the chip stacking is completed through the TSV. Therefore, the test pad of the wafer in the high-bandwidth memory storage chip does not need to be reused in the package. If the test pad is set to test multiple chips at the same time, wiring differences will occur, which will in turn affect the signal and power supply, and cause different chips on the same wafer to have different test conditions. For example, the wiring difference will cause delays, resulting in a decrease in the accuracy of the test results and a decrease in the test yield.

[0045] It should be noted that the first direction described in the embodiments of the present disclosure may be the ox direction in the drawings, and the second direction may be the oy direction in the drawings.

[0046] See also Figure 1 , Figure 2 and Figure 3 , in the test structure adopted by the related technology, Figure 1 The wafer 10 shown includes a plurality of chips 101 arranged in an array along a first direction (eg, ox direction) and a second direction (eg, oy direction), and pads 1011 are disposed on the chips 101. Figure 2 When performing a probe test on the wafer 10, the probe card 11 is connected to the pad 1011 to test the chip 101, and one probe card 11 corresponds to one chip 101. Figure 3The probe card 11 includes a circuit board 111 and a probe 112. Since each chip 101 needs to be connected to the probe card 11, the circuit board 111 in the probe card 11 occupies a large space. The miniaturization technology of the probe card 11 has not yet reached the point where its size is smaller than the size of the chip 101. The width of the circuit board 111 along the first direction (e.g., the ox direction) is even greater than the width of the chip 101 along the first direction (e.g., the ox direction). Therefore, it is impossible to test all the chips 101 on a wafer 10 at the same time, and only the chips at intervals can be tested in batches, resulting in more test time. In addition, in the common wafer probe test, the pad 1011 occupies a large space, and the number of chips tested at the same time is small, which reduces the yield and efficiency of the wafer test.

[0047] Based on the above technical problems, the present disclosure provides a test structure, system and method, which can save the space occupied by the test pads, increase the maximum number of simultaneous measurements during the wafer testing process, and ensure the stability and accuracy of the testing process, thereby improving the yield of the product.

[0048] As an example, see Figure 4 and Figure 5 In one aspect, the present disclosure provides a test structure, including a wafer 20 and a plurality of test pads 2021; wherein the wafer 20 includes chips to be tested 201 arranged in an array along a first direction (e.g., ox direction) and a second direction (e.g., oy direction), a cutting path 202 is provided between two adjacent chips to be tested 201 along the first direction (e.g., ox direction) and between two adjacent chips to be tested 201 along the second direction (e.g., oy direction), and two adjacent chips to be tested 201 along the second direction (e.g., oy direction) are centrally symmetrical with each other; wherein the chips to be tested 201 include a plurality of chips to be tested arranged in an array along the first direction (e.g., ox direction) and a plurality of test pads 2021; wherein the chips to be tested 201 include a plurality of chips to be tested arranged in an array along the first direction (e.g., ox direction) and a plurality of test pads 2021; wherein the chips to be tested 201 include a plurality of chips to be tested arranged in an array along the first direction (e.g., ox direction) and a plurality of test pads 2021; wherein the chips to be tested 201 include a plurality of chips to be tested arranged in an array along the first direction (e.g., oy direction) and a plurality of test pads 2021; wherein the chips to be tested 201 include a plurality of chips to be tested arranged in an array along the first direction (e.g., ox ... The chip pads 2011 are arranged in a second direction (for example, in the ox direction), and the chip pads 2011 are arranged on a side of the chip to be tested 201 along the second direction (for example, in the oy direction) close to the cutting path 202; a plurality of test pads 2021 are arranged corresponding to the chip pads 2011, and are located in the cutting path 202 between the chip pads 2011 adjacent to each other along the second direction (for example, in the oy direction); wherein the same test pad 2021 is electrically connected to the chip pads 2011 adjacent to it along the second direction (for example, in the oy direction), and the channel lengths are equal, and the first direction (for example, in the ox direction) intersects with the second direction (for example, in the oy direction).

[0049] In the test structure in the above embodiment, by arranging a plurality of test pads 2021 in the cutting path 202 between the chip pads 2011 adjacent along the second direction (e.g., oy direction), and correspondingly arranged with the chip pads 2011, it is possible to test at least two chips to be tested 201 at the same time based on one test pad 2021, thereby increasing the number of simultaneous tests, thereby improving the test efficiency, and also saving the space reserved for the test inside the chip to be tested 201, thereby increasing the capacity of the chip to be tested 201. In addition, due to the reduction in the number of test pads 2021, the test cost can be reduced, that is, the cost of the test equipment and the cost of the test process can be reduced. Also, due to the central symmetry of the two chips to be tested 201 adjacent along the second direction (e.g., oy direction), it is possible to ensure that the channel length of one test pad 2021 when testing a plurality of chips to be tested 201 is equal, that is, the signal transmission path is equal in length, thereby ensuring the consistency and stability of the test result, thereby improving the accuracy of the test. The above-mentioned test structure can improve the problems of small number of tests, high test cost, low test efficiency, etc. in the related art when directly testing the chip pad 2011. In addition, the large number of pads used in the related art will also reduce the success rate of the probe card design and reduce the accuracy of the test. The present invention sets the test pad 2021 in the cutting path 202 so that one test pad 2021 can be electrically connected to at least two chips to be tested 201 at the same time, and sets the two adjacent chips to be tested 201 along the second direction (such as the oy direction) to be centrally symmetrical with each other, thereby reducing the wiring difference from the test pad 2021 to different chips, and ensuring the consistency of signals and power supply, thereby improving the yield and efficiency of the probe test of the wafer 20, and providing further guarantee for the improvement of the quality of the wafer 20.

[0050] As an example, see Figure 4 and Figure 5 Since the two adjacent chips to be tested 201 along the second direction (for example, the oy direction) are centrally symmetrical with each other, the structures in the two chips to be tested 201 are centrally symmetrical, that is, the chip pads 2011 and circuit structures in the two chips to be tested 201 are symmetrical with each other, so as to ensure the power supply stability and consistency during the test, eliminate the test differences between different chips to be tested 201 in the same wafer 20, and improve the test yield.

[0051] As an example, see Figure 4 and Figure 5 The same test pad 2021 corresponds to two adjacent chip pads 2011, that is, a group of test pads 2021 can test two chips 201 to be tested at the same time, which improves the test efficiency compared with the related art that a group of test pads 2021 can only test one group of chips.

[0052] As an example, see Figure 6The same test pad 2021 and the chip pad 2011 adjacent to it along the second direction (for example, the oy direction) are connected by a wire, and the length of the wire along the second direction (for example, the oy direction) is equal, that is, the signal transmission path is ensured to be of equal length, the test differences between different chips are eliminated, and the accuracy of the test is ensured.

[0053] As an example, see Figure 5 and Figure 6 There are two chips 201 to be tested adjacent to the same test pad 2021 along the second direction (for example, the oy direction), namely, a first chip 201a and a second chip 201b, and the first chip 201a and the second chip 201b share a group of test pads 2021; the chip pads 2011 in the second chip 201b include a first ground pad 20111, a first voltage pad 20112, a power pad 20113, an address pad 20114, a second voltage pad 20115 and a second ground pad 20116 arranged in sequence along the first direction (for example, the ox direction); the chip pads 2011 in the first chip 201a include a second ground pad 20116, a second voltage pad 20115, an address pad 20114, a power pad 20113, a first voltage pad 20112 and a first ground pad 20111 arranged in sequence along the first direction (for example, the ox direction).

[0054] As an example, see Figure 6 The abbreviation of the first ground pad 20111 can be expressed as a VSS (VoltageSource Source, source power supply voltage) pad; the abbreviation of the first voltage pad 20112 can be expressed as a VDD (VoltageDrain Drain, drain power supply voltage) pad; the abbreviation of the power pad 20113 can be expressed as a TDQ ((Test dataqueues, test data queues) pad, TDQA is expressed as the power pad 20113 in the first chip 201a, and TDQB is expressed as the power pad 20113 in the second chip 201b; the abbreviation of the address pad 20114 can be expressed as an ADD (Address, address) pad; the abbreviation of the second voltage pad 20115 can be expressed as a VDD pad; the abbreviation of the second ground pad 20116 can be expressed as a VSS pad.

[0055] As an example, see Figure 6Each group of test pads 2021 includes a first test pad 20211, a second test pad 20212, a third test pad 20213, a fourth test pad 20214, a fifth test pad 20215, a sixth test pad 20216 and a seventh test pad 20217; wherein the first test pad 20211 is electrically connected to the first ground pad 20111 of the second chip 201b and the second ground pad 20116 of the first chip 201a; the second test pad 20212 is electrically connected to the first voltage pad 20112 of the second chip 201b and the second voltage pad 20115 of the first chip 201a; the third test pad 2021 3 is electrically connected to the power pad 20113 of the second chip 201b; the fourth test pad 20214 is electrically connected to the address pad 20114 of the second chip 201b and the address pad 20114 of the first chip 201a; the fifth test pad 20215 is electrically connected to the power pad 20113 of the first chip 201a; the sixth test pad 20216 is electrically connected to the second voltage pad 20115 of the second chip 201b and the first voltage pad 20112 of the first chip 201a; the seventh test pad 20217 is electrically connected to the second ground pad 20116 of the second chip 201b and the first ground pad 20111 of the first chip 201a.

[0056] As an example, see Figure 6 The abbreviation of the first test pad 20211 can be expressed as a VSS pad, which is used to ground the first ground pad 20111 of the second chip 201b and the second ground pad 20116 of the first chip 201a.

[0057] As an example, see Figure 6 The second test pad 20212 may be referred to as a VDD pad, which is used to provide an electrical signal to the first voltage pad 20112 of the second chip 201b and the second voltage pad 20115 of the first chip 201a, so as to test the voltage pads of different chips 201 under test.

[0058] As an example, see Figure 6 The abbreviation of the third test pad 20213 can be expressed as a TDQB pad, which is used to provide an enable electrical signal for the electrical connection of the power pad 20113 of the second chip 201b.

[0059] As an example, see Figure 6 The fourth test pad 20214 may be referred to as an ADD pad, and is used to provide an electrical signal to the address pad 20114 of the second chip 201b and the address pad 20114 of the first chip 201a, so as to test the address pad 20114. The electrical signal includes a high level signal and a low level signal.

[0060] As an example, see Figure 6 The fifth test pad 20215 may be abbreviated as a TDQA pad, which is used to provide an enable electrical signal for the electrical connection of the power pad 20113 of the first chip 201a.

[0061] As an example, see Figure 6 The abbreviation of the sixth test pad 20216 can be expressed as a VDD pad, which is used to provide an electrical signal to the second voltage pad 20115 of the second chip 201b and the first voltage pad 20112 of the first chip 201a to test the voltage pads of different chips 201 under test.

[0062] As an example, see Figure 6 The seventh test pad 20217 may be abbreviated as a VSS pad, which is used to ground the second ground pad 20116 of the second chip 201b and the first ground pad 20111 of the first chip 201a.

[0063] As an example, see Figure 6 The address pad 20114 includes a plurality of address sub-pads arranged along a first direction (e.g., ox direction), and the address sub-pads have address serial numbers. The number of the address sub-pads is N+1, N is an integer greater than or equal to 1, and the address serial numbers of the address sub-pads are arranged in a descending order or a descending order along the first direction (e.g., ox direction).

[0064] As an example, see Figure 6 The fourth test pad 20214 includes a plurality of fourth sub-test pads, whose number and positions correspond to the number and positions of the address sub-pads in the first chip 201a and the second chip 201b, respectively, so as to perform signal testing on the address sub-pads.

[0065] As an example, see Figure 6 , the address serial numbers of each address sub-pad of the first chip 201a and the address serial numbers of each address sub-pad of the second chip 201b are centrally symmetric to each other. Wherein, the address serial numbers of each address sub-pad of the first chip 201a are arranged in order from small to large along the first direction (for example, the ox direction), and the address serial numbers of each address sub-pad of the second chip 201b are arranged in order from large to small along the first direction (for example, the ox direction); for example, the address serial numbers of the address sub-pad of the first chip 201a are 0, 1, ..., N in sequence along the first direction (for example, the ox direction), and the address serial numbers of the address sub-pad of the second chip 201b are N, ..., 1, 0 in sequence along the first direction (for example, the ox direction).

[0066] As an example, see Figure 6Each group of test pads 2021 also includes a signal exchange pad 20218, which is located between the second test pad 20212 and the third test pad 20213 adjacent to each other along the first direction (for example, the ox direction), and between the fifth test pad 20215 and the sixth test pad 20216 adjacent to each other along the first direction (for example, the ox direction), and is used to change the address serial numbers of each address sub-pad of the first chip 201a and the address serial numbers of each address sub-pad of the second chip 201b from central symmetry to mirror symmetry when receiving the first electrical signal.

[0067] The abbreviation of the above-mentioned signal exchange pad 20218 can be expressed as a WP (Wafer Probing) pad, the signal exchange pad 20218 for controlling the first chip 201a can be expressed as a WPA pad, and the signal exchange pad 20218 for controlling the second chip 201b can be expressed as a WPB pad. Since the first chip 201a and the second chip 201b are centrally symmetrical, the positions of their address pads 20114 are also centrally symmetrical. Therefore, the address numbers of the address sub-pads on the opposite sides of the same fourth sub-test pad along the second direction (for example, the oy direction) are usually different. The signal exchange pad 20218 can change the address numbers of the address sub-pads on the opposite sides of the same fourth sub-test pad along the second direction (for example, the oy direction) to the same number, so that the length of the signal transmission path from the same fourth sub-test pad to different address sub-pads is equal to eliminate the difference in signal transmission.

[0068] As an example, see Figure 6 , when Figure 6 When testing the first chip 201a and the second chip 201b in the circuit, first, a high level can be provided to the WPB pad or the WPA pad in the signal exchange pad 20218 to power the VSS pad and the VDD pad of the second chip 201b or the first chip 201a, thereby enabling the TDQB pad or the TDQA pad in the power pad 20113 to internally exchange the signals of the address sub-pads of the second chip 201b or the first chip 201a, so that the length of the signal transmission path between the same fourth sub-test pad and different address sub-pads is equal to eliminate the difference in signal transmission. When the signal exchange is completed, a low level is provided to the WPB pad or the WPA pad in the signal exchange pad 20218 to disconnect the power supply of the VSS pad and the VDD pad in the second chip 201b or the first chip 201a. The above signal exchange process can ensure that when the wafer is tested, the channel lengths from the test pad to different chips are equal, thereby eliminating signal differences in the test, ensuring the consistency of the test results, and improving the test yield.

[0069] As an example, see Figure 7 and Figure 8There can also be four chips 201 to be tested that are adjacent to the test pad 2021 along the second direction (for example, the oy direction) and the first direction (for example, the ox direction), namely the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d. The first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d share a group of test pads 2021, so that a group of test pads 2021 can test four chips to be tested at the same time, further improving the test efficiency.

[0070] As an example, see Figure 7 The test pad 2021 is located in the cutting path 202 shared by the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d. The chip pads 2011 of the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d are all located on one side close to the shared cutting path 202, and the first chip 201a and the second chip 201b are centrally symmetrical to each other, and the third chip 201c and the fourth chip 201d are centrally symmetrical to each other, so that the test pad 2021 has stable power supply to the chip 201 under test when it is located in the cutting path 202.

[0071] As an example, see Figure 8 The chip pads 2011 in the second chip 201b and the fourth chip 201d respectively include a first ground pad 20111, a first voltage pad 20112, a power pad 20113, an address pad 20114, a second voltage pad 20115 and a second ground pad 20116 arranged in sequence along a first direction (for example, an ox direction); the chip pads 2011 in the first chip 201a and the third chip 201c respectively include a second ground pad 20116, a second voltage pad 20115, an address pad 20114, a power pad 20113, a first voltage pad 20112 and a first ground pad 20111 arranged in sequence along a first direction (for example, an ox direction).

[0072] As an example, see Figure 8The abbreviation of the first ground pad 20111 can be expressed as a VSS pad; the abbreviation of the first voltage pad 20112 can be expressed as a VDD pad; the abbreviation of the power pad 20113 can be expressed as a TDQ pad, TDQA is expressed as the power pad 20113 in the first chip 201a, TDQB is expressed as the power pad 20113 in the second chip 201b, TDQC is expressed as the power pad 20113 in the third chip 201c, and TDQD is expressed as the power pad 20113 in the fourth chip 201d; the abbreviation of the address pad 20114 can be expressed as an ADD pad; the abbreviation of the second voltage pad 20115 can be expressed as a VDD pad; the abbreviation of the second ground pad 20116 can be expressed as a VSS pad.

[0073] As an example, see Figure 8Each group of test pads 2021 includes a first group of test pads arranged in sequence along a first direction (e.g., ox direction) in the cutting path 202 between the first chip 201a and the second chip 201b, including a first test pad 20211, a second test pad 20212, a third test pad 20213, two signal exchange pads 20218, and a fifth test pad 20215, and also includes a second group of test pads arranged in sequence along a first direction (e.g., ox direction) in the cutting path 202 between the third chip 201c and the fourth chip 201d, including a fifth test pad 2021 5. Two signal exchange pads 20218, a third test pad 20213, a second test pad 20212 and a first test pad 20211, each group of test pads 2021 also includes a fourth test pad 20214 located between the first group of test pads and the second group of test pads, a sixth test pad 20216 and a seventh test pad 20217 located within the cutting path 202 between the second chip 201b and the fourth chip 201d, and a sixth test pad 20216 and a seventh test pad 20217 located within the cutting path 202 between the first chip 201a and the third chip 201c. Among them, the first test pad 20211 is electrically connected to the second ground pad 20116 of the first chip 201a and the fourth chip 201d and the first ground pad 20111 of the second chip 201b and the third chip 201c; the second test pad 20212 is electrically connected to the second voltage pad 20115 of the first chip 201a and the fourth chip 201d and the first voltage pad 20112 of the second chip 201b and the third chip 201c; the third test pad 20213 is electrically connected to the power pad 20113 of the second chip 201b and the third chip 201c; the fourth test pad 20214 is electrically connected to the first chip 201a and the second chip 201b The address pads 20114 of the first chip 201a, the third chip 201c and the fourth chip 201d are all electrically connected; the fifth test pad 20215 is electrically connected to the power pad 20113 of the first chip 201a and the fourth chip 201d; the sixth test pad 20216 is electrically connected to the second voltage pad 20115 of the first chip 201a, the fourth chip 201d and the first voltage pad 20112 of the second chip 201b and the third chip 201c; the seventh test pad 20217 is electrically connected to the second grounding pad 20116 of the first chip 201a, the fourth chip 201d and the first grounding pad 20111 of the second chip 201b and the third chip 201c. The above test structure enables a group of test pads to test four adjacent chips to be tested at the same time, further improving the number of simultaneous tests and test efficiency.

[0074] As an example, see Figure 8The abbreviation of the first test pad 20211 can be expressed as a VSS pad; the abbreviation of the second test pad 20212 can be expressed as a VDD pad; the abbreviation of the third test pad 20213 can be expressed as a TDQB or TDQC pad, which is used to provide an enable signal for the power pad 20113 of the second chip 201b and the third chip 201c; the abbreviation of the fourth test pad 20214 can be expressed as an ADD pad, which is used to provide an electrical signal for the address pad 20114 of the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d; the abbreviation of the fifth test pad 20215 can be expressed as a TDQA or TDQD pad, which is used to provide an enable electrical signal for the power pad 20113 of the first chip 201a and the fourth chip 201d; the abbreviation of the sixth test pad 20216 can be expressed as a VDD pad; the abbreviation of the seventh test pad 20217 can be expressed as a VSS pad.

[0075] As an example, see Figure 8 The address pad 20114 includes a plurality of address sub-pads arranged along a first direction (e.g., ox direction), and the address sub-pads have address serial numbers. The number of the address sub-pads is N+1, N is an integer greater than or equal to 1, and the address serial numbers of the address sub-pads are arranged in a descending order or a descending order along the first direction (e.g., ox direction).

[0076] As an example, see Figure 8 , the address numbers of the address sub-pads of the first chip 201a and the address numbers of the address sub-pads of the second chip 201b are mutually symmetrical, and the address numbers of the address sub-pads of the third chip 201c and the address numbers of the address sub-pads of the fourth chip 201d are mutually symmetrical. Wherein, the address numbers of the address sub-pads of the first chip 201a and the third chip 201c are arranged in order from small to large along the first direction (for example, the ox direction), and the address numbers of the address sub-pads of the second chip 201b and the fourth chip 201d are arranged in order from large to small along the first direction (for example, the ox direction); for example, the address numbers of the address sub-pads of the first chip 201a and the third chip 201c are 0, 1, ..., N in sequence along the first direction (for example, the ox direction), and the address numbers of the address sub-pads of the second chip 201b and the fourth chip 201d are N, ..., 1, 0 in sequence along the first direction (for example, the ox direction).

[0077] As an example, see Figure 8Each group of test pads 2021 also includes a signal exchange pad 20218, which is located between the third test pad 20213 and the fifth test pad 20215 adjacent to each other along the first direction (for example, the ox direction), and is used to change the address numbers of the address sub-pads of the first chip 201a and the address numbers of the address sub-pads of the second chip 201b from central symmetry to mirror symmetry when receiving the first electrical signal.

[0078] The abbreviation of the above-mentioned signal exchange pad 20218 can be expressed as a WP pad. The signal exchange pad 20218 for controlling the first chip 201a can be expressed as a WPA pad, the signal exchange pad 20218 for controlling the second chip 201b can be expressed as a WPB pad, the signal exchange pad 20218 for controlling the third chip 201c can be expressed as a WPC pad, and the signal exchange pad 20218 for controlling the fourth chip 201d can be expressed as a WPD pad.

[0079] As an example, see Figure 8 The fourth test pad 20214 includes a plurality of fourth sub-test pads, the number of which is the same as the number of address sub-pads of the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d, and one fourth sub-test pad is respectively connected to one address sub-pad of the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d. The signal exchange pad 20218 can change the address serial numbers of different address sub-pads connected to the same fourth sub-test pad to the same serial number, so that the signal transmission path lengths from the same fourth sub-test pad to different address sub-pads are equal to eliminate the difference in signal transmission.

[0080] As an example, see Figure 8 , when Figure 6 When testing the first chip 201a, the second chip 201b, the third chip 201c and the fourth chip 201d, firstly, a high level can be provided to one or more of the WPA pad, WPB pad, WPC pad and WPD pad in the signal exchange pad 20218 to power the corresponding chip 201 to be tested, thereby enabling one or more of the TDQA pad, TDQB pad, TDQC pad and TDQD pad in the corresponding power pad 20113 to exchange the signals of the address sub-pads of the corresponding chip 201 to be tested internally, so that the length of the signal transmission path between the same fourth sub-test pad and different address sub-pads is equal to eliminate the difference in signal transmission. Then, a low level is provided to one or more of the WPA pad, WPB pad, WPC pad and WPD pad in the signal exchange pad 20218 to end the signal exchange process.

[0081] As an example, see Fig. 9 Another aspect of the present disclosure further provides a test system, comprising the test structure described in any one of the embodiments of the present disclosure and a plurality of probe cards 21 , each probe card 21 being electrically connected to each group of test pads 2021 .

[0082] In the test system of the above embodiment, the probe card 21 is connected to the test pad 2021 in the cutting path 202, and one test pad 2021 can be connected to at least two chip pads 2011, so that one probe card 21 can test at least two chips 201 to be tested, which improves the number of simultaneous tests of the wafer 20, saves the cost of the probe card 21 and the space occupied by the probe card 21, and the reduction in the number of test pads 2021 can also keep a certain distance between adjacent probe cards 21, avoid mutual squeezing of the probe cards 21, and further improve the stability of the test. The above test system can improve the problems of the related art in that the number of simultaneous tests of directly testing the chip pad 2011 is small, the test cost is high, the test efficiency is low, and the design failure of the probe card 21 is failed. The present disclosure arranges the test pad 2021 in the cutting path 202 so that one test pad 2021 can be electrically connected to at least two chips to be tested 201 at the same time, that is, one probe card 21 can test at least two chips to be tested 201 at the same time, and arranges two adjacent chips to be tested 201 along the second direction (for example, the oy direction) to be centrally symmetrical with each other, thereby reducing the wiring difference from the test pad 2021 to different chips to be tested 201 and ensuring the consistency of signals and power supply, thereby improving the yield and efficiency of the probe test of the wafer 20 and reducing the testing cost.

[0083] As an example, see Fig. 9 The two probe cards 21 connected to the two groups of test pads 2021 adjacent to each other along the first direction (for example, the ox direction) are respectively located on the opposite sides of the test pads 2021 along the second direction (for example, the oy direction), so that the probe cards 21 connected to the adjacent chips to be tested 201 have a spacing between each other, and can perform probe testing on all the chips to be tested 201 in the same wafer 20 at the same time without the need to test in batches. The reduction in the number of probe cards 21 and the arrangement of their positions in the present disclosure can save testing time and improve testing efficiency.

[0084] As an example, see Fig.10Each probe card 21 includes a circuit board 211 and a plurality of probes 212 arranged on the same side of the circuit board 211. The probes 212 in each probe card 21 correspond one-to-one to each group of test pads 2021. Since the two probe cards 21 connected to two groups of test pads 2021 adjacent to each other along a first direction (for example, the ox direction) are respectively located on opposite sides of the test pads 2021 along a second direction (for example, the oy direction), the problem that adjacent chips cannot be tested at the same time due to the large size of the probe card 21 is improved, thereby saving test time.

[0085] As an example, see Fig.11 Another aspect of the present disclosure further provides a testing method for testing the test structure described in any one of the embodiments of the present disclosure, the method comprising:

[0086] Step S2: providing a test structure and a probe card;

[0087] Step S4: electrically connecting each probe card to each group of test pads;

[0088] Step S6: providing a first electrical signal to the test pad electrically connected to the probe card based on the probe card, so as to test the chip to be tested electrically connected to the test pad;

[0089] Step S8: providing a second electrical signal to the test pad electrically connected to the probe card to end the test.

[0090] In the test method in the above embodiment, the probe card provides a first electrical signal to the test pad electrically connected thereto, so as to test at least two chips to be tested that are electrically connected to the test pad, and the same test pad is electrically connected to the chip pad adjacent thereto along the second direction and the channel length is equal, so that it can be ensured that there is no test difference between the same test pad and different chips to be tested, that is, the accuracy and yield of the test are improved. The above test method improves the problems of small capacity of the chip to be tested, slow test progress, and low test yield caused by a large number of test pads in the related art, and can improve the stability and consistency of the test while increasing the number of chips to be tested, thereby improving the yield and efficiency of the test and reducing the test cost.

[0091] As an example, see Fig.11 Step S4 in which each probe card is electrically connected to each group of test pads includes:

[0092] Step S41: electrically connecting each probe card to each group of test pads, and making two probe cards connected to two adjacent groups of test pads along the first direction be located at two opposite sides of the test pads along the second direction.

[0093] The above-mentioned probe card position arrangement method can ensure that there is a spacing between adjacent probe cards, thereby avoiding the problem that the probe cards squeeze each other and cause adjacent chips to be unable to be tested simultaneously, thereby saving test costs and improving test efficiency.

[0094] As an example, the first electrical signal is greater than the second electrical signal, wherein the first electrical signal may be a high-level signal and the second electrical signal may be a low-level signal.

[0095] As an example, see Fig.11 In step S6, there are two chips to be tested adjacent to the same test pad along the second direction, namely, a first chip and a second chip, and the first chip and the second chip share a group of test pads; the chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad, and a second ground pad arranged in sequence along the first direction; the chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad, and a first ground pad arranged in sequence along the first direction; step S6 includes:

[0096] Step S61: Based on the probe card, a first electrical signal is provided to the test pad electrically connected to it, including: based on the probe card, a first electrical signal is provided to the test pad electrically connected to it, so that the address serial numbers of each address sub-pad of the first chip where the chip pad corresponding to the test pad is located and the address serial numbers of each address sub-pad of the second chip are changed from central symmetry to mirror symmetry.

[0097] The above method can make the signal transmission paths of the same test pad and the address pad connected thereto equal in length, thereby eliminating signal differences during the test and improving the stability and accuracy of the test.

[0098] In the above-mentioned test structure, system and method, by setting the test pad in the cutting path, and at the same time setting the chip to be tested to be centrally symmetrical, and setting a signal exchange structure, the number of tests can be increased, the test efficiency can be improved, the chip capacity can be improved, the number of chips that can be produced per wafer (Dies Per Wafer, abbreviated as DPW) can be increased, the test cost can be reduced, and at the same time the consistency and accuracy of the test can be guaranteed.

[0099] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0100] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0101] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the disclosed patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the disclosed patent shall be subject to the attached claims.

Claims

1. A test structure, characterized in that: include: A wafer, comprising chips to be tested arranged in an array along a first direction and a second direction, a cutting path is provided between two adjacent chips to be tested along the first direction and between two adjacent chips to be tested along the second direction, and two adjacent chips to be tested along the second direction are centrally symmetrical to each other; wherein the chip to be tested comprises a plurality of chip pads arranged along the first direction, and the chip pads are provided on one side of the chip to be tested close to the cutting path along the second direction; A plurality of test pads are arranged corresponding to the chip pads and are located in the cutting path between the chip pads adjacent to each other along the second direction; wherein the same test pad is electrically connected to the chip pads adjacent to it along the second direction and the channel lengths are equal, and the first direction intersects with the second direction.

2. The test structure according to claim 1, characterized in that: The same test pad is connected to the chip pad adjacent to it along the second direction through a wire, and the lengths of the wires along the second direction are equal.

3. The test structure according to claim 2, characterized in that: There are two chips to be tested adjacent to the same test pad along the second direction, namely a first chip and a second chip, and the first chip and the second chip share a group of the test pads; The chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad and a first ground pad arranged in sequence along the first direction; The chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad and a second ground pad which are sequentially arranged along the first direction.

4. The test structure according to claim 3, characterized in that: Each group of test pads includes: A first test pad is electrically connected to a first ground pad of the second chip and a second ground pad of the first chip; a second test pad electrically connected to the first voltage pad of the second chip and the second voltage pad of the first chip; A third test pad is electrically connected to the power pad of the second chip; a fourth test pad electrically connected to the address pad of the second chip and the address pad of the first chip; a fifth test pad, electrically connected to the power pad of the first chip; a sixth test pad, electrically connected to the second voltage pad of the second chip and the first voltage pad of the first chip; The seventh test pad is electrically connected to the second ground pad of the second chip and the first ground pad of the first chip.

5. The test structure according to claim 4, characterized in that: The address pad includes a plurality of address sub-pads arranged along the first direction, and the address sub-pads have address serial numbers.

6. The test structure according to claim 5, characterized in that: The address serial numbers of the address sub-pads of the first chip and the address serial numbers of the address sub-pads of the second chip are centrally symmetrical to each other.

7. The test structure according to any one of claims 3 to 6, characterized in that: Each group of test pads further includes: The signal exchange pad is located between the second test pad and the third test pad adjacent to each other along the first direction, and between the fifth test pad and the sixth test pad adjacent to each other along the first direction, and is used to change the address serial numbers of the address sub-pads of the first chip and the address serial numbers of the address sub-pads of the second chip from central symmetry to mirror symmetry when receiving the first electrical signal.

8. The test structure according to claim 1, characterized in that: There are four chips to be tested adjacent to the test pad along the second direction and the first direction, namely a first chip, a second chip, a third chip and a fourth chip. The first chip, the second chip, the third chip and the fourth chip share a group of the test pads.

9. A testing system, characterized in that: include: The test structure according to any one of claims 1 to 8; and A plurality of probe cards are provided, each of the probe cards being electrically connected to each group of the test pads.

10. The test system according to claim 9, characterized in that: The two probe cards connected to the two groups of test pads adjacent to each other along the first direction are respectively located at two opposite sides of the test pads along the second direction.

11. The test system according to claim 10, characterized in that: Each of the probe cards comprises a circuit board and a plurality of probes arranged on the same side of the circuit board, and the probes in each of the probe cards correspond one-to-one to each group of the test pads.

12. A testing method, characterized in that: For testing the test structure according to any one of claims 1 to 8, the method comprises: Providing the test structure and the probe card; Electrically connecting each of the probe cards to each group of the test pads; Providing a first electrical signal to the test pad electrically connected to the probe card based on the probe card, so as to test the chip to be tested electrically connected to the test pad; The probe card provides a second electrical signal to the test pad electrically connected thereto to end the test.

13. The testing method according to claim 12, characterized in that: The step of electrically connecting each of the probe cards to each group of the test pads comprises: Each of the probe cards is electrically connected to each group of the test pads, and two of the probe cards connected to two adjacent groups of the test pads along the first direction are located at opposite sides of the test pads along the second direction.

14. The testing method according to claim 12, characterized in that: The first electrical signal is greater than the second electrical signal.

15. The testing method according to claim 14, characterized in that: There are two chips to be tested adjacent to the same test pad along the second direction, namely a first chip and a second chip, and the first chip and the second chip share a group of the test pads; The chip pads in the first chip include a second ground pad, a second voltage pad, an address pad, a power pad, a first voltage pad and a first ground pad arranged in sequence along the first direction; The chip pads in the second chip include a first ground pad, a first voltage pad, a power pad, an address pad, a second voltage pad and a second ground pad arranged in sequence along the first direction; The step of providing a first electrical signal to the test pad electrically connected to the probe card based on the probe card comprises: Based on the probe card providing a first electrical signal to the test pad electrically connected thereto, the address serial numbers of the address sub-pads of the first chip where the chip pad corresponding to the test pad is located and the address serial numbers of the address sub-pads of the second chip change from central symmetry to mirror symmetry.

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