A method and structure for testing on-resistance of thick chip power device

Abstract

The present invention discloses an on-resistance test method and test structure for thick-chip power devices. The on-resistance test structure of the present invention includes a wafer after edge washing treatment, and a metallized epitaxial layer; the metallized epitaxial layer is located on the substrate area exposed after the edge washing treatment of the wafer; during testing, the metallized epitaxial layer serves as a drain access point, and the source and gate of each chip on the wafer serve as a source access point and a gate access point respectively; the present invention deposits a layer of metal through physical vapor deposition technology to form a reliable electrical connection point, which serves as a drain access point during testing, thereby solving the Rdson test problem of thick-chip power devices. The present invention also improves the utilization rate of the inactive area at the edge of the wafer, making the area that was originally difficult to use in traditional testing a key part for realizing the test function, reducing dependence on other areas of the wafer.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to an on-resistance testing method and a testing structure for a thick-chip power device. Background Art

[0002] In the field of precision manufacturing and performance evaluation of semiconductor power devices, on-resistance (Rdson) is a core indicator used to measure the performance and energy efficiency of devices. Accurate measurement of Rdson is of great significance for optimizing device design, improving production efficiency and ensuring product quality.

[0003] However, with the increasing complexity and diversity of semiconductor manufacturing processes, especially for the processing of thicker wafers, traditional testing methods face huge challenges, such as (1) Increased wafer thickness: Due to their larger volume and mass, thicker wafers have a longer path for current to pass through and a more complex resistance distribution. This makes it extremely difficult to directly and accurately measure the Rdson value of these wafers. (2) Limitations of contact testing methods: Traditional contact testing methods have difficulty directly touching the key areas inside the wafer and cannot obtain accurate Rdson data. In addition, additional contact resistance and error sources may be introduced during the test process, reducing the reliability of the measurement results.

[0004] Therefore, those skilled in the art urgently need an innovative method to solve the Rdson measurement problem in the production of semiconductor power devices in order to improve device performance and production efficiency. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a method and a test structure for testing the on-resistance of a thick-chip power device, so as to solve the problem that direct Rdson testing is difficult due to thickness limitations.

[0006] The present invention is implemented as follows. In a first aspect, the present invention provides an on-resistance test structure for a thick-chip power device, characterized in that it includes a wafer after edge cleaning, and a metallized epitaxial layer; the metallized epitaxial layer is located on the substrate area exposed after the edge cleaning of the wafer;

[0007] During testing, the metallized epitaxial layer serves as a drain access point, and the source pad and gate pad of each chip on the wafer serve as a source access point and a gate access point, respectively.

[0008] Preferably, the substrate is made of silicon.

[0009] Preferably, the material used for the metallized epitaxial layer is titanium-nickel-silver alloy.

[0010] Preferably, the thickness of the metallized epitaxial layer is 1-2 μm, more preferably 1 μm.

[0011] Preferably, the metallized epitaxial layer is ring-shaped.

[0012] Preferably, the metallized epitaxial layer is 2-3 mm, more preferably 3 mm.

[0013] Preferably, the metallized epitaxial layer is in contact with the wafer.

[0014] Preferably, the metallization epitaxial layer is deposited on the substrate region exposed after edge cleaning of the wafer by physical vapor deposition (PVD) technology.

[0015] Preferably, the wafer of the thick power device is 8 or 12 inches.

[0016] In a second aspect, the present invention provides a method for testing the on-resistance of a thick chip power device, specifically:

[0017] In the chip level (CP) test phase, the drain terminal of the test equipment is connected to the metallized epitaxial layer at the edge of the wafer through the test electrode, and the source and gate of the chip are connected to the source and gate of the test equipment using a probe card;

[0018] During the test, the relays are closed to connect the source terminal and ground terminal of the test chip to the high and low ends of the voltage source and provide a negative voltage to turn on the thick power device. Then, the source of the test chip is connected to the low end of the current source and a forward current is provided to the metallized epitaxial layer (drain). At the same time, the voltage across the source and drain is measured to obtain the on-resistance value.

[0019] The beneficial effects of the present invention are:

[0020] The present invention deposits a layer of metal through physical vapor deposition (PVD) technology to form a reliable electrical connection area, which serves as a drain terminal access point during testing, solving the Rdson test problem of thick-wafer power devices. The present invention also improves the utilization rate of the inactive area at the edge of the wafer, making the area that was originally difficult to use in traditional testing a key part for realizing the test function, reducing dependence on other areas of the wafer. At the same time, it reduces the cost and complexity of testing, reduces the equipment investment, labor cost and time cost caused by complex test structures and methods, improves production efficiency, and enhances the competitiveness of products in the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a front view of the on-resistance test structure provided by an embodiment of the present invention.

[0023] Figure 2 It is a side view of an on-resistance test structure provided by an embodiment of the present invention.

[0024] Markings in the figure: 1. Wafer after edge cleaning; 2. Metallized epitaxial layer; 1-1. Source of the chip; 1-2. Gate of the chip. DETAILED DESCRIPTION

[0025] As can be seen from the background technology, thicker wafers have larger volume and mass, longer current paths, and complex resistance distribution, making it extremely difficult to accurately measure their Rdson values. Traditional contact testing methods have difficulty reaching key areas inside the wafer and cannot obtain accurate Rdson data. In addition, the test process is prone to introduce additional contact resistance and error sources, reducing the reliability of the measurement results.

[0026] Therefore, this embodiment aims to elaborate on a method for testing the on-resistance (Rdson) of a thick power device and a specific implementation process of the test structure, see Figure 1-Figure 2 As shown, through meticulous process steps and technical means, the excellent performance of the present invention in overcoming the Rdson test problem of thick-wafer power devices is deeply verified, laying a solid foundation for the efficient production and accurate performance evaluation of power devices in the industry, and promoting semiconductor manufacturing technology to a new level.

[0027] Step 1: Wafer preprocessing

[0028] Step 1.1: Select an 8-inch or 12-inch wafer that has completed basic processing and ensure that there are no impurities, cracks or other defects on its surface.

[0029] Because the initial state of the wafer surface will affect all subsequent process steps, the wafer must ensure that there are no impurities, cracks or other defects on its surface. Any tiny flaws may be magnified in subsequent processing, affecting the integrity of the test structure and the accuracy of the test results. For example, surface impurities may cause uneven deposition of the metallization epitaxial layer, thereby affecting the reliability of the electrical connection; cracks may cause abnormal current paths and interfere with the measurement of the Rdson value.

[0030] Step 1.2: Clean the wafer edge and use chemical or physical methods to remove burrs, impurities and oxide layers on the edge to ensure that the silicon surface in an area about 3 mm wide is clean and free of impurities.

[0031] When using chemical or physical methods for edge cleaning, it is necessary to scientifically select edge cleaning reagents and accurately optimize process parameters based on the wafer material characteristics (such as different semiconductor materials such as silicon and gallium arsenide) and process requirements. For silicon wafers, commonly used chemical edge cleaning reagents are hydrofluoric acid (HF) and hydrogen peroxide ( ) mixed solution, the ratio of which needs to be finely adjusted according to the thickness of the oxide layer on the wafer surface, the type and distribution of impurities. For example, when the oxide layer thickness is between 50nm - 100nm and contains more metal impurities (such as iron, copper, etc.), HF and The volume ratio is set to 1:5 - 1:10, and an appropriate amount of buffer (such as ammonium fluoride, ) to ensure that while the oxide layer and impurities are effectively removed, excessive corrosion of the silicon surface is prevented and the atomic-level flatness of the silicon surface is maintained.

[0032] Physical edge cleaning methods such as plasma etching require the design of an appropriate plasma source and precise etching parameters based on the shape (such as round, square, etc.) and size of the wafer edge. For example, when using inductively coupled plasma (ICP) etching, the RF power must be precisely controlled between 300W and 800W, the argon (Ar) flow rate must be 20sccm to 50sccm, and the oxygen ( ) flow rate is 5sccm - 15sccm, the chamber pressure is maintained at 0.5Pa - 1.5Pa, and the etching time is determined according to the edge impurities and the thickness of the oxide layer, generally 30s - 120s. By optimizing these parameters, the edge burrs, impurities and oxide layers can be accurately removed, ensuring that the silicon surface in the area of ​​about 3mm wide at the edge reaches atomic-level flatness (surface flatness deviation is less than 0.1nm) and ultra-high cleanliness (surface impurity concentration is less than ), providing a nearly ideal substrate surface for subsequent metal deposition. During the edge cleaning process, X-ray photoelectron spectroscopy (XPS) is used to monitor the chemical composition changes on the silicon surface in real time to ensure that the content of impurity elements is reduced to the minimum standard; at the same time, the surface morphology is observed with the help of scanning electron microscopy (SEM) to ensure that the edge flatness meets the requirements, laying a solid foundation for the subsequent deposition of the metallized epitaxial layer.

[0033] This operation can effectively prevent impurities and irregular structures in the edge area from having adverse effects on subsequent metal deposition and testing processes, provide a clean and flat base surface for the deposition of the metallization epitaxial layer, and ensure good adhesion and electrical connection between metal and silicon.

[0034] After the wafer is edge washed, further pretreatment can be performed, such as increasing adhesion treatment, to improve the quality of metal deposition. This can be achieved through chemical treatment, plasma treatment, or physical grinding. For example, chemical treatment can enhance its adsorption capacity for metal atoms by forming specific chemical bonds on the edge surface of the wafer; plasma treatment can clean the surface and activate surface atoms, promoting the deposition and diffusion of metal atoms on the surface; physical grinding can improve the surface roughness, making the metal layer easier to adhere and more evenly distributed. These pretreatment measures help to improve the bonding strength and quality of the metallized epitaxial layer and the silicon area at the edge of the wafer, thereby improving the stability and reliability of the entire test structure.

[0035] Step 2: Edge Metallization

[0036] Step 2.1: Figure 1 As shown, select appropriate metal deposition technology, such as physical vapor deposition (PVD) technology. PVD technology includes sputtering, evaporation and ion implantation, which can be selected according to specific needs.

[0037] PVD technology is widely used in semiconductor manufacturing. Its advantage lies in the ability to accurately control the deposition rate, film thickness uniformity and film quality. For example, sputtering can be performed at a lower temperature to reduce thermal damage to the wafer, while achieving a higher film density and good adhesion; evaporation is suitable for the deposition of some metals with higher purity requirements; ion implantation can be used to introduce specific impurity atoms during the deposition process to change the electrical properties of metal films to meet different testing requirements.

[0038] The sputtering method in physical vapor deposition (PVD) technology is based on ion bombardment of the target material, so that the target atoms are sputtered and deposited on the wafer surface. It involves complex physical processes and many key parameters. During the sputtering process, precise control of the pressure, flow rate and ion energy of the sputtering gas (such as argon) is crucial. For example, the argon pressure needs to be precisely controlled between 0.2Pa and 0.8Pa. A higher argon pressure (such as 0.6Pa-0.8Pa) can increase the scattering of sputtered atoms, which is conducive to obtaining a more uniform film thickness, but too high a pressure may cause the energy of the sputtered atoms to decrease, affecting the density of the film. By optimizing the sputtering power (100W-500W) and time (determined according to the film thickness requirements, such as depositing a 1μm thick metal film, the sputtering time is about 30min-120min), precise control of thickness from sub-nanometer to micron level can be achieved to meet the performance requirements of different test structures and devices. At the same time, the uniformity and efficiency of atomic deposition can be further optimized according to the relative position and movement mode of the target and wafer (such as DC sputtering, RF sputtering, magnetron sputtering and other different modes). For example, the magnetron sputtering mode can use the magnetic field to confine the plasma, improve the utilization rate of sputtered atoms and the deposition rate, and obtain high-quality films at a lower gas pressure.

[0039] The evaporation method uses the vapor pressure difference of metals at high temperatures to achieve the evaporation and deposition of atoms. When selecting an evaporation source (such as a resistance heating evaporation source, an electron beam evaporation source, a laser evaporation source, etc.), it is necessary to comprehensively consider the melting point of the metal material, the vapor pressure characteristics, and the requirements for the purity of the thin film. For example, for high-melting-point metals (such as tungsten, with a melting point of 3410°C), an electron beam evaporation source can provide an electron beam with a high energy density to achieve efficient evaporation and effectively reduce impurity contamination. The evaporation rate can be precisely controlled by adjusting the electron beam current (10mA - 100mA) and the acceleration voltage (5kV - 15kV). During the evaporation process, the evaporation temperature (depending on the metal material, such as the evaporation temperature of aluminum is approximately 1200°C - 1400°C), rate (0.1nm / s- 10nm / s) and vacuum degree ( ), ensuring that metal atoms are deposited at the edge of the wafer with a uniform flux to form a high-quality metal film. In addition, to prevent impurity contamination during the evaporation process, high-purity metal materials (purity > 99.99%) can be used, and a baffle can be set between the evaporation source and the wafer to control the flight direction and deposition area of ​​the evaporated atoms.

[0040] The application of ion implantation technology in metal deposition can be achieved by precisely controlling the energy (10keV -100keV) and dose ( ) and types to achieve fine control of the electrical properties of metal films. For example, when depositing titanium-nickel-silver (Ti / Ni / Ag) alloy films, injecting an appropriate amount of boron ions ( ) or phosphorus ions ( ), which can change the resistivity and work function of the film, optimize its electrical contact performance with the silicon substrate and subsequent test electrodes, and improve the overall performance of the test structure. The energy of the injected ions determines its penetration depth in the film, and the dose affects the doping concentration. By accurately adjusting these parameters, the electrical properties of the film can be accurately customized. At the same time, appropriate annealing treatment (such as rapid thermal annealing, temperature of 300℃ - 600℃, time of 10s - 60s) is required after ion implantation to repair the lattice damage caused by the implantation process, activate the implanted ions, and ensure the stability of the electrical properties of the film. According to the specific power device characteristics and test requirements, the most suitable PVD technology and its parameter combination are comprehensively evaluated and selected to ensure that the metallized epitaxial layer has excellent conductivity, stability and good adhesion to silicon.

[0041] Step 2.2: Deposit one or more metal films, i.e., metallized epitaxial layer 2, on the exposed silicon region at the edge of the wafer 1 after edge cleaning by the metal deposition technology selected in step 2.1. The material of the metal film should have good conductivity and good adhesion to silicon, such as titanium nickel silver (Ti / Ni / Ag) alloy. During the deposition process, parameters such as temperature, pressure, and deposition rate need to be controlled to ensure the uniformity and density of the metal film. Accurate control of these parameters is crucial to the formation of high-quality metallized epitaxial layer 2. For example, too high a temperature may cause metal atoms to diffuse too quickly, affecting the crystallization quality and uniformity of the film; improper pressure may cause uneven scattering of metal atoms, resulting in uneven film thickness; too fast a deposition rate may cause defects inside the film, reducing its conductivity and stability. By optimizing these parameters, a metal film with good electrical properties and structural stability can be obtained as a reliable drain access point.

[0042] Taking titanium nickel silver (Ti / Ni / Ag) alloy as an example, the titanium layer is used as the bottom layer, and a good ohmic contact is achieved with the silicon substrate by forming titanium silicide (TiSix). Its thickness is usually controlled between 30nm and 100nm. The specific thickness depends on the doping concentration of the silicon substrate (e.g., the doping concentration of n-type silicon substrate is When the titanium layer is used, the thickness of the titanium layer can be selected from 50nm to 80nm) and the surface state can be optimized. As an intermediate layer, the nickel layer mainly acts as a barrier layer to prevent silver atoms from diffusing into the silicon substrate. Its thickness is generally around 20nm to 50nm, and its uniformity needs to be precisely controlled (thickness uniformity deviation is less than ±5%) to ensure a stable and reliable barrier effect. As the top layer, the silver layer provides good conductivity, and its thickness can be flexibly adjusted according to the required current carrying capacity, generally between 500nm and 1.2μm.

[0043] During the deposition process, temperature control has a decisive influence on the crystallization quality and stress state of the metal film. For example, for the deposition of titanium, the substrate temperature is appropriately controlled between 200℃ and 400℃. Within this temperature range, titanium atoms have an appropriate diffusion rate, which can promote the reaction between titanium and silicon atoms and form a high-quality titanium silicide interface. However, too high a temperature (such as >450℃) may lead to increased diffusion of impurities in the silicon substrate, affecting device performance; too low a temperature (such as <150℃) may cause insufficient diffusion of titanium atoms, affecting the crystallization quality and adhesion of the film. The pressure parameter not only affects the scattering and deposition rate of metal atoms, but is also closely related to the density of the film. In a low pressure environment (such as 0.1Pa-1Pa), the mean free path of metal atoms is longer, which is conducive to the formation of a dense film structure, but too low a pressure (such as <0.3Pa) may lead to uneven film growth. The precise control of the deposition rate can be achieved by adjusting the power, gas flow rate and other parameters of the PVD equipment. Generally, it is between a few nanometers per second and tens of nanometers per second, and a reasonable selection is made according to the film thickness requirements and process stability. For example, for thinner metal films (thickness < 500nm), the deposition rate can be controlled at 2nm / s - 5nm / s to ensure the quality of the film; for thicker films, the deposition rate can be appropriately increased, but care should be taken to avoid defects inside the film due to excessively fast rates. At the same time, real-time monitoring technology (such as reflection high-energy electron diffraction, RHEED) is used to monitor the changes in the crystal structure during the film growth process to ensure that the metal film maintains a uniform crystal state and good orientation throughout the deposition process, thereby obtaining a high-quality metallized epitaxial layer2. Through the analysis of RHEED patterns, the growth mode of the film (such as layered growth, island growth, etc.) and crystal structure information (such as lattice constant, crystal plane orientation, etc.) can be understood in real time, and the deposition parameters can be adjusted in time to ensure the quality of the film.

[0044] Step 3: Test electrode preparation

[0045] Step 3.1: Design and make the test electrode. The design of the test electrode needs to consider the compatibility with the test equipment and the accuracy of the test. The test electrode can be connected to the test equipment by welding, pasting or other means. When welding, care should be taken to avoid thermal damage to the equipment; when pasting, it is necessary to select a suitable adhesive to ensure a firm connection without affecting the test results. For example, when using conductive silver glue for pasting, it is necessary to ensure that the silver glue has good conductivity, bonding strength, and a suitable curing temperature and time to ensure a stable and reliable electrical connection between the electrode and the test equipment.

[0046] Step 3.2: Perform necessary treatment on the test electrode, such as deoxidation and cleaning, to ensure good contact between it and the metallized epitaxial layer 2. The oxide layer or impurities on the electrode surface will increase the contact resistance and affect the accuracy of current transmission and voltage measurement. Removing the surface oxide layer by chemical cleaning or physical polishing, and then cleaning the impurities with an appropriate solvent can significantly reduce the contact resistance and improve the accuracy and reliability of the test. For example, use a dilute acid solution to remove the oxide on the surface of the metal electrode, and then use a high-purity organic solvent to clean the residual acid and impurities to restore the electrode surface to cleanliness, ensuring a close, low-resistance contact with the metallized epitaxial layer 2, thereby providing good electrical connection conditions for accurately measuring the Rdson value.

[0047] Step 4: Rdson test

[0048] Step 4.1: Connect the drain end of the test equipment to the metallized epitaxial layer 2 at the edge of the wafer through the test electrode, as the source access point and gate access point respectively; the source end and gate end are connected to the source 1-1 (source pad) and gate 1-2 (gate pad) of the chip in the conventional way. When connecting, pay attention to ensure the reliability and stability of the electrical connection. For example, use high-precision probe cards and connectors to ensure that the connection between the source pad and gate pad and the test equipment is tight and the resistance is stable; for the connection between the drain end and the metallized epitaxial layer 2, check whether the welding point or the adhesive is firm to avoid poor contact during the test process, ensure that the current can pass through the test structure smoothly, and lay the foundation for accurate voltage measurement and Rdson value calculation.

[0049] The selection of probes needs to be optimized according to the size and material properties of the pad to ensure stable electrical contact and low wear. For small-sized pads, micro-tip probes are used, and the tip radius can be as small as a few microns (such as 2μm - 5μm), which can achieve good point contact without damaging the pad surface. The material of the micro-tip probe is generally selected from materials with high hardness and good conductivity, such as tungsten (W) or beryllium copper (BeCu).

[0050] Step 4.2: Apply appropriate voltage and current, measure and record the Rdson value through the test equipment. During the test, the consistency of the test conditions must be ensured, such as the control of environmental factors such as temperature and humidity, to eliminate test errors. Changes in ambient temperature and humidity may affect the electrical properties of wafer materials, the resistance of metal connections, and the measurement accuracy of test equipment. For example, an increase in temperature may cause the resistivity of semiconductor materials to decrease, thereby affecting the measurement of Rdson values; changes in humidity may cause oxidation or adsorption of water vapor on the metal surface, increasing contact resistance. Therefore, the test is usually carried out in a constant temperature and humidity environment, and the test equipment is calibrated before measurement to ensure the accuracy and repeatability of the measurement.

[0051] Step 4.3: Analyze and process the test results to obtain the Rdson value of the thick-chip power device and its performance evaluation. and current Data, using Ohm's law The Rdson value is calculated using relevant electrical formulas such as . At the same time, a comprehensive performance evaluation is performed on the device in combination with the design specifications and performance requirements to determine whether the device meets the expected performance indicators. For example, if the calculated Rdson value is within the design allowable range and consistent with the expected performance, it means that the thick-chip power device performs normally in terms of on-resistance; if the Rdson value exceeds the expected range, further analysis of the cause is required, which may involve factors such as wafer material quality, manufacturing process deviation, and errors in the test process, so that corresponding improvement measures can be taken to optimize device performance or test methods.

[0052] By actually implementing the above steps, multiple thick-chip power device samples were tested and compared with traditional test methods. The results show that the test method of the present invention can accurately measure the Rdson value of thick-chip power devices, effectively solving the problem of testing difficulties caused by thickness limitations. At the same time, it improves the utilization rate of the inactive area at the edge of the wafer, reduces the test cost and complexity, and provides an efficient and reliable solution for the production and performance evaluation of thick-chip power devices. In practical applications, this test method can help semiconductor manufacturers better control product quality, optimize device design, improve production efficiency, and meet the market demand for high-performance and high-reliability power devices. In addition, through further research and optimization of different process parameters and material selection, the accuracy and adaptability of the test method can be further improved, providing strong support for the development of semiconductor manufacturing technology.

[0053] Through the detailed arrangement of the above embodiments, the specific operation process, technical points and the effects achieved in the actual application of the present invention can be clearly demonstrated, which provides specific practical guidance and reference basis for relevant technical personnel, and helps to promote the widespread application and further development of the invention in the field of semiconductor manufacturing.

[0054] The present invention provides an efficient, accurate and economical Rdson test solution for the semiconductor power device manufacturing field, which is expected to be widely used in the production process and performance evaluation of various thick-chip power devices, promote the further development of semiconductor power device technology, and meet the growing market demand for high-performance power devices. In the future, with the continuous advancement of semiconductor technology, the test method and structure of the present invention can also be used as a basis for further optimization and expansion, providing strong support for the research and development and manufacturing of more advanced power devices.

[0055] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A thick chip power device on-resistance test structure, characterized in that It comprises a wafer after edge cleaning, and a metallized epitaxial layer; the metallized epitaxial layer is located on the substrate area exposed after edge cleaning of the wafer; During the test, the metallized epitaxial layer is used as a drain access point, and the source and gate of each chip on the wafer are used as a source access point and a gate access point respectively; The substrate material is silicon; The metallized epitaxial layer is deposited on the substrate area exposed after the edge cleaning of the wafer by physical vapor deposition technology, specifically with a titanium layer as the bottom layer, a nickel layer as the middle layer, and a silver layer as the top layer, wherein the titanium layer realizes ohmic contact with the substrate.

2. The on-resistance test structure of a thick power device according to claim 1, characterized in that: The thickness of the metallized epitaxial layer is 1-2 μm.

3. The on-resistance test structure of a thick power device according to claim 1, characterized in that: The metallized epitaxial layer is in a ring shape.

4. The on-resistance test structure of a thick power device according to claim 1, characterized in that: The wafer of the thick-chip power device is 8 inches or 12 inches.

5. A method for testing on-resistance using the structure according to any one of claims 1 to 4, characterized in that: The method is specifically: Connect the drain terminal of the test equipment to the metallized epitaxial layer at the edge of the wafer through the test electrode, and connect the source and gate of the test chip to the source and gate terminals of the test equipment using a probe card; During the test, the source and gate of the test chip are connected to the high and low ends of the voltage source and a negative voltage is provided to turn on the thick power device. Then the source of the test chip is connected to the low end of the current source and a forward current is provided to the metallized epitaxial layer. At the same time, the voltage across the source and drain is measured to obtain the on-resistance value.

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