Driver circuit for bypassing power transistor comprising secondary driver circuit supply path from set of battery cells

Abstract

Embodiments of the present disclosure relate to a driver circuit for bypassing a power transistor including a secondary driver circuit supply path from a set of battery cells. A driver circuit is configured to control one or more bypass transistors. The driver circuit includes one or more supply connections configured to supply power from a set of battery cells. The set of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit is configured to receive information indicating whether an error condition exists in the set of battery cells that prevents the driver circuit from receiving power from the primary driver circuit supply path across the set of battery cells via the one or more supply connections. The driver circuit is further configured to receive power from a secondary driver circuit supply path across one or more battery cells of the set of battery cells via one or more supply connections. Current flows through the secondary driver circuit supply path without reaching an error condition.

Description

Technical Field

[0001] The present disclosure relates to circuits for controlling current across semiconductor devices. Background Art

[0002] Driver circuits are often used to control voltage, current, or power at a load. For example, a group of semiconductor devices may be part of one or more circuits that provide electrical signals to a load such as a motor. The group of semiconductor devices may be part of a power converter, a supply device, a bypass circuit, or other type of circuit. In some cases, a gate driver circuit may control the group of semiconductor devices by delivering electrical signals to corresponding gate terminals of the group of semiconductor devices. Summary of the invention

[0003] In general, the present disclosure relates to devices, systems, and techniques for supplying power sufficient to a gate driver to control one or more bypass transistors when an error condition occurs in a circuit that supplies power to a load. For example, a system may include a group of circuits, each circuit including a group of battery cells, and the group of battery cells is configured to supply power to a load via a power delivery circuit. When an error condition occurs in the circuit, the bypass gate driver can control one or more bypass transistors to prevent the power delivery circuit or other components of the circuit from being damaged. In some examples, the bypass gate driver can turn on one or more bypass transistors to create a bypass current path. The bypass current path can prevent power surges caused by error conditions from damaging components of a circuit used to deliver power to a load via a power delivery circuit.

[0004] The bypass gate driver may include one or more supply connections and circuit supply paths, which are configured to supply power to the bypass gate driver to control one or more bypass transistors. In some examples, when the circuit for supplying power to the load operates normally without an error condition, the bypass gate driver may receive power from the primary supply connection or circuit supply path. In response to an error condition occurring in the circuit supplying power to the load, the bypass gate driver may control one or more bypass transistors to define a bypass current path. In order to control one or more bypass transistors to define the bypass current path, the bypass gate driver may deliver a power greater than a gate power threshold to one or more bypass transistors. The system may ensure that the bypass gate driver receives sufficient power for controlling one or more bypass transistors when an error condition occurs. For example, when there is an error condition, the system may enable the bypass gate driver to receive power from the secondary supply connection or circuit supply path, thereby enabling the bypass gate driver to receive sufficient power for controlling one or more bypass transistors even when the primary supply connection or circuit supply path does not deliver sufficient power to the bypass gate driver.

[0005] In some examples, the primary supply connection or circuit supply path of the bypass gate driver can deliver power from a group of battery cells to the bypass gate driver. For example, the supply connection of the bypass gate driver can be connected to a node that receives power from the group of battery cells. When there is no error condition in the group of battery cells or the power delivery circuit, the bypass gate driver can receive power from the group of battery cells via the primary supply connection or circuit supply path. However, when an error condition occurs in the group of battery cells or the power delivery circuit, the power delivered to the bypass gate driver may not be sufficient to control one or more bypass transistors to define a bypass current path. This means that when an error condition occurs in the group of battery cells or the power delivery circuit, it may be beneficial for the system to deliver power to the bypass gate driver via a secondary supply connection or circuit supply path.

[0006] The technology of the present disclosure can provide one or more advantages. For example, when an error condition occurs in the power delivery circuit and when the bypass gate driver controls one or more bypass transistors to define a bypass current path, the bypass gate driver can receive power via one or more secondary supply connectors connected to the bypass current path. That is, the bypass gate driver can receive power from the bypass current path created by the bypass gate driver when the error condition occurs. In some examples, when an error condition exists in the group of battery cells, the bypass gate driver can receive power from a secondary driver circuit supply path that delivers power from the group of battery cells without reaching the error condition present in the group of battery cells. In any case, when an error condition occurs, supplying power to the gate driver circuit via a secondary supply connector or a secondary driver circuit supply path can better ensure that the gate driver circuit receives sufficient power when the error condition occurs, compared to a system that does not include a secondary supply of the bypass gate driver.

[0007] In some examples, a driver circuit is configured to control one or more bypass transistors. The driver circuit includes a primary supply input connector configured to supply power to the driver circuit from a group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit also includes one or more secondary supply input connectors. The driver circuit is configured to receive information indicating whether an error condition exists in the power delivery circuit and control one or more bypass transistors based on the error condition existing in the power delivery circuit to define a bypass current path between the one or more bypass transistors and the load. The driver circuit is also configured to receive power from the bypass current path via a secondary supply input connector in one or more secondary supply input connectors, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0008] In some examples, a method for controlling one or more bypass transistors includes: supplying power from a group of battery cells to the driver circuit via a primary supply input connector of the driver circuit, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit and receiving information indicating whether an error condition exists in the power delivery circuit by the driver circuit, and defining one or more bypass transistors for bypassing a bypass current path of the power delivery circuit based on the error condition existing in the power delivery circuit by the driver circuit. The method also includes: receiving power from the bypass current path via a secondary supply input connector of one or more secondary supply input connectors by the driver circuit, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0009] In some examples, a system includes a group of battery cells and a power delivery circuit, the power delivery circuit including four power transistors arranged in an H-bridge. The power delivery circuit is configured to deliver power from the group of battery cells to a load. The system also includes: an H-bridge driver circuit configured to control the four power transistors arranged in the H-bridge; one or more bypass transistors; and a bypass driver circuit configured to control the one or more bypass transistors. The bypass driver circuit includes: a primary supply input connector configured to supply power from the group of battery cells to the bypass driver circuit; and one or more secondary supply input connectors. The bypass driver circuit is configured to receive information indicating whether an error condition exists in the power delivery circuit, control the one or more bypass transistors based on the error condition existing in the power delivery circuit to define a bypass current path for bypassing the power delivery circuit, and receive power from the bypass current path via a secondary supply input connector of the one or more secondary supply input connectors, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0010] In some examples, a driver circuit is configured to control one or more bypass transistors. The driver circuit includes one or more supply connections, the one or more supply connections being configured to supply power from a group of battery cells. The group of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit is configured to receive information indicating whether an error condition exists in the group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via the one or more supply connections, activating one or more bypass transistors based on the error condition present in the group of battery cells to define a bypass current path for bypassing the power delivery circuit, and receiving power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows across the secondary driver circuit supply path without reaching the error condition.

[0011] In some examples, a method includes: receiving, by a driver circuit including one or more supply connections configured to supply power from a group of battery cells, information indicating whether an error condition exists in a group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit; activating, by the driver circuit based on the error condition existing in the group of battery cells, one or more bypass transistors to define a bypass current path for bypassing the power delivery circuit; and receiving, by the driver circuit via the one or more supply connections, power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells, wherein current flows across the secondary driver circuit supply path without reaching the error condition.

[0012] In some examples, a system includes a group of battery cells and a power delivery circuit, the power delivery circuit including four power transistors arranged in an H-bridge. The power delivery circuit is configured to deliver power from the group of battery cells to a load. The system also includes: an H-bridge driver circuit configured to control the four power transistors arranged in the H-bridge; one or more bypass transistors; and a bypass driver circuit configured to control the one or more bypass transistors, the bypass driver circuit including one or more supply connections configured to supply power from the group of battery cells. The bypass driver circuit is configured to: receive information indicating whether an error condition exists in the group of battery cells, the error condition preventing the bypass driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via the one or more supply connections; based on the error condition existing in the group of battery cells, activate the one or more bypass transistors to define a bypass current path for bypassing the power delivery circuit; and receive power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows across the secondary driver circuit supply path without reaching the error condition.

[0013] This summary of the invention is intended to provide an overview of the subject matter described in the present disclosure. It is not intended to provide an exclusive or exhaustive explanation of the systems, devices, and methods described in detail in the drawings and the following description. Further details of one or more examples of the present disclosure are set forth in the drawings and the following description. Other features, objects, and advantages will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram illustrating a system for controlling a bypass current path of a circuit delivering power to a load, in accordance with one or more techniques of this disclosure.

[0015] FIG. 2A to FIG. 2D is a circuit diagram illustrating an example configuration of a power delivery circuit in accordance with one or more techniques of this disclosure.

[0016] Figure 3 is a circuit diagram illustrating a first example circuit for supplying power to a bypass driver circuit in accordance with one or more techniques of this disclosure.

[0017] Figure 4 is a circuit diagram illustrating a second example circuit for supplying power to a bypass driver circuit, in accordance with one or more techniques of this disclosure.

[0018] Figure 5 is a circuit diagram illustrating a system including a set of circuits, each circuit configured to supply power to a power cell in a set of power cells that supply power to a common load.

[0019] Figure 6 is a graph illustrating a graph of voltage output from a group of power cells to a common load, in accordance with one or more techniques of this disclosure.

[0020] Figure 7 is a flow chart illustrating example operations for supplying power to a bypass gate driver when an error condition occurs in a power delivery circuit, in accordance with one or more techniques of this disclosure.

[0021] Figure 8 is a flow chart illustrating example operations for supplying power to a bypass gate driver when an error condition exists in a group of battery cells, in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION

[0022] Figure 1 1 is a block diagram illustrating a system 100 for controlling a bypass current path of a circuit delivering power to a load in accordance with one or more techniques of the present disclosure. Figure 1 As shown, the system 100 includes a controller 110, a battery cell 116, a power delivery circuit 120, (one or more) bypass transistors 132, a load 130, a power delivery circuit gate driver 140, and a bypass gate driver 150. The controller 110 includes a processing circuit device 112, a memory 114, and a battery management circuit 115. The power delivery circuit 120 includes (one or more) power transistors 122. The controller 110 can be configured to control the battery cell 116 to deliver power to the load 130 via the power delivery circuit 120.

[0023] Controller 110 may include processing circuitry 112. Processing circuitry 112 may include, for example, one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or equivalent discrete or integrated logic circuitry, or a combination of any of the foregoing devices or circuitry. Thus, processing circuitry 112 may include any suitable structure, whether hardware, software, firmware, or any combination thereof, to perform the functions attributed herein to controller 110.

[0024] The controller 110 may include a memory 114 in communication with the processing circuit device 112. In some examples, the memory 114 in communication with the processing circuit device 112 includes computer-readable instructions that, when executed by the processing circuit device 112, cause the system 100 to perform various functions pertaining to the first system 100 herein. The memory 114 may include any volatile medium, non-volatile medium, magnetic medium, optical medium, or electrical medium capable of storing information, such as a random access memory (RAM), a read-only memory (ROM), a non-volatile RAM (NVRAM), an electrically erasable programmable ROM (EEPROM), a flash memory, or any other digital medium.

[0025] The processing circuit device 112 can communicate with the battery management circuit 115. The battery management circuit 115 can be configured to control and / or monitor the group of battery cells 116. For example, the battery management circuit 115 can output one or more instructions to the group of battery cells 116. Additionally or alternatively, the battery management circuit 115 can receive information from the battery cells 116. In some examples, the battery management circuit 115 can control the battery cells 116 based on the information received from the battery cells 116. In some examples, the battery management circuit 115 can control the battery cells 116 based on the instructions received from the processing circuit device 112.

[0026] In some examples, the battery management circuit 115 is part of a battery management system (BMS) that includes the battery management circuit 115, the processing circuit device 112 of the controller 110, and the battery cells 116. The BMS may include multiple battery management circuits, each of which manages a subset of battery cells of the battery cells 116. For example, the battery management circuit 115 may include multiple battery management circuits, each of which manages a subset of battery cells of the battery cells 116. For example, a first battery management circuit of the multiple battery management circuits may manage a first subset of battery cells 116, a second battery management circuit of the multiple battery management circuits may manage a second subset of battery cells 116, and so on. That is, the battery cells 116 may include multiple subsets of battery cells, each of which is managed by a battery management circuit of the battery management circuit 115. The BMS may include processing circuit devices to balance the subsets of battery cells 116 relative to each other. For example, the processing circuit device 112 may serve as a processing circuit device of the BMS that includes the battery management circuit 115.

[0027] The battery cells 116 may include a group of battery cells connected in series, a group of battery cells connected in parallel, or a group of battery cells connected to each other via both parallel connection and series connection. In some examples, each battery cell of the battery cells 116 may include a lithium ion cell. In other examples, the battery cells 116 may include a lead-acid cell, a nickel-metal hydride cell, or other materials. In some examples, the output of the battery cells 116 is 24 volts (V), but this is not required. The output of the battery cells 116 may include any amount of voltage or current. In some examples, each battery cell of the battery cells 116 may include a positive terminal and a negative terminal. In some examples, the battery cells 116 may be a unit including a positive terminal and a negative terminal. For example, the positive terminal of the battery cell 116 may include the positive terminal of the first battery cell of the battery cell 116 and the negative terminal of the battery cell 116 may include the negative terminal of the last battery cell of the battery cell 116. In some examples, the battery cells 116 may include 12 battery cells, 16 battery cells, or any number of battery cells. The battery management circuit 115 may be designed or configured to manage 12 or fewer cells, or possibly 16 or fewer cells.

[0028] The power delivery circuit 120 may include (one or more) power transistors 122. In some examples, the power delivery circuit 120 may be configured to deliver power from the battery cell 116 to the load 130 according to one or more operating modes. For example, the power delivery circuit 120 may deliver a positive voltage to the load 130 according to a first one or more operating modes, the power delivery circuit 120 may deliver a negative voltage to the load 130 according to a second one or more operating modes, and the power delivery circuit 120 may deliver a zero voltage to the load 130 according to a third one or more operating modes. In some examples, current may flow from the battery cell 116 to the load 130 according to the current path 123. For example, the current may flow clockwise from the first end of the battery cell 116 to the power delivery circuit 120, from the power delivery circuit 120 to the load 1430, from the load 130 back to the power delivery circuit 120, and from the power delivery circuit 120 to the second end of the battery cell 116. The system 100 is not limited to current flowing clockwise according to the current path 123. In some examples, the current may flow counterclockwise according to the current path 123.

[0029] (One or more) power transistors 122 may represent semiconductor devices or other types of switches. In some cases, each power transistor of (one or more) power transistors 122 may include a power switch, such as but not limited to any type of field effect transistor (FET), including metal oxide semiconductor field effect transistor (MOSFET), bipolar junction transistor (BJT), insulated gate bipolar transistor (IGBT), junction field effect transistor (JFET), high electron mobility transistor (HEMT) or any other type of element controlled using voltage or current or a combination thereof. In addition, each power transistor of (one or more) power transistors 122 may include any one or a combination of N-type transistors, p-type transistors, and other types of power transistors. In some examples, each power transistor of (one or more) power transistors 122 includes a vertical transistor, a lateral transistor, and / or a horizontal transistor. In some examples, each power transistor of (one or more) power transistors 122 includes other analog devices, such as diodes and / or thyristors. In some examples, each power transistor of (one or more) power transistors 122 may operate as a switch and / or operate as an analog device.

[0030] In some examples, each power transistor of (one or more) power transistors 122 includes three terminals: two load terminals and a control terminal. When the power transistor represents a MOSFET, the power transistor may include a drain terminal, a source terminal, and at least one gate terminal, wherein the control terminal is a gate terminal. When the power transistor represents a BJT switch, the control terminal may represent a base terminal. Based on the voltage at the corresponding control terminal, a current may flow between the two load terminals of the power transistor. Therefore, based on the control signal transmitted to the control terminal of the power transistor, a current may flow across the power transistor. In one example, if the voltage applied to the control terminal of the power transistor is greater than or equal to a voltage threshold, the power transistor may be activated, thereby allowing the power transistor to conduct. In addition, when the voltage applied to the control terminal of the power transistor is lower than a threshold voltage, the power transistor may be deactivated, thereby preventing the power transistor from conducting. The controller 110 may be configured to control each power transistor in (one or more) power transistors 122.

[0031] Each of the power transistors 122 may include various material compounds, such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials. In some examples, silicon carbide switches may experience lower switching power losses. Improvements in magnetics and faster switches (such as gallium nitride switches) may enable power transistors to generate short pulses of current. These high-frequency devices may need to send control signals (e.g., voltage signals delivered to the control terminals of the power transistors) with more precise timing than low-frequency devices.

[0032] In some examples, (one or more) power transistors 122 may be arranged so that the power delivery circuit 120 forms an H-bridge circuit. In some cases, the H-bridge circuit may be configured as a stepper inverter circuit. In this example, (one or more) power transistors 122 may include a first power transistor, a second power transistor, a third power transistor, and a fourth power transistor. In some examples, the first power transistor and the second power transistor may represent high-side power transistors connected to the positive terminal of the battery cell 116. In some examples, the third power transistor and the fourth power transistor may represent low-terminal power transistors connected to the negative terminal of the battery cell 116. The (one or more) power transistors 122 of the H-bridge circuit may be arranged so that the H-bridge circuit is configured to pass a positive output, a negative output, or a zero output. This may allow the controller 110 to control whether the load 130 receives a positive output, a negative output, or a zero output from the battery cell 116.

[0033] When both the first power transistor and the second power transistor of the H-bridge are turned on and both the third power transistor and the fourth power transistor are turned off, the power delivery circuit 120 may output zero voltage to the load 130. When both the first power transistor and the second power transistor of the H-bridge are turned off and both the third power transistor and the fourth power transistor are turned on, the power delivery circuit 120 may output zero voltage to the load 130. When the first power transistor and the fourth power transistor are turned on and the second power transistor and the third power transistor are turned off, the power delivery circuit 120 may output a positive voltage to the load 130. When the first power transistor and the fourth power transistor are turned off and the second power transistor and the third power transistor are turned on, the power delivery circuit 120 may output a negative voltage to the load 130.

[0034] In some examples, bypass transistor(s) 132 may represent semiconductor devices or other types of power switches. Bypass transistor(s) 132 may be substantially similar to power transistor(s) 122 in structure and size, but this is not required. In some examples, bypass transistor(s) 132 may include different materials, different sizes or ratings than power transistor(s) 122, and / or may include different types of power switches than power transistor(s) 122. In any case, each bypass transistor of bypass transistor(s) 132 may be turned off or turned on. When bypass transistor(s) 132 are turned on, current may flow across bypass transistor(s) 132. When one or more of bypass transistor(s) 132 are turned off, current may not flow across bypass transistor(s) 132.

[0035] When the bypass transistor(s) 132 are turned on, current may flow along the bypass current path 133 between the bypass transistor(s) 132 and the load 130. Figure 1As shown, the bypass current path 133 can flow clockwise from the first end of the bypass transistor (one or more) 132 to the load 130, and from the load 130 to the second end of the bypass transistor (one or more) 132. The bypass current path 133 is not limited to clockwise flow. In some examples, the bypass current path 133 may flow counterclockwise from the second end of the bypass transistor (one or more) 132 to the load 130, and from the load 130 to the first end of the bypass transistor (one or more) 132. In some examples, when the bypass transistor (one or more) 132 is turned on, the current may not flow between the battery cell 116 and the load 130 according to the current path 123. That is, the bypass current path 133 can prevent the current associated with the load 130 from flowing to the power delivery circuit 120 and damaging the components of the power delivery circuit 120 (e.g., the power transistor (one or more) 122).

[0036] In some examples, when the bypass transistor(s) 132 are turned off, current may not flow according to the bypass current path 133. In some examples, when the bypass transistor(s) 132 are turned off, current may flow from the battery cell 116 to the load 130 according to the bypass current path 133. In some examples, when there is no error condition in the battery cell 116 and / or the power delivery circuit 120, the bypass transistor(s) 132 may be turned off and current may flow according to the current path 123, rather than according to the bypass current path 133. In some examples, when there is one or more error conditions in the battery cell 116 and / or the power delivery circuit 120, the bypass transistor(s) 132 may be turned on and current may flow according to the bypass current path 133, rather than according to the current path 123.

[0037] The controller 110 may be configured to output one or more commands to the power delivery circuit gate driver 140 to control the (one or more) power transistors 122 of the power delivery circuit 120. For example, the controller 110 may output commands to the power delivery circuit gate driver 140 to control whether each of the (one or more) power transistors 122 is turned on or off. This means that the controller 110 is configured to control the operation mode of the power delivery circuit 120. In an example where the power delivery circuit 120 includes an H-bridge, the controller 110 may output one or more commands to the power delivery circuit gate driver 140 to control the (one or more) power transistors 122 so that the power delivery circuit 120 outputs a positive voltage, a negative voltage, or a zero voltage.

[0038] The controller 110 may be configured to output one or more commands to the bypass gate driver 150 to control the bypass transistor(s) 132. For example, the controller 110 may output commands to the bypass gate driver 150 to control whether each of the bypass transistor(s) 132 is turned on or off. When one or more error conditions exist in the battery cell 116 and / or the power delivery circuit 120, the controller 110 may output one or more commands for the bypass gate driver 150 to turn on the bypass transistor(s) 132. When there are no error conditions in the battery cell 116 and / or the power delivery circuit 120, the controller 110 may output one or more commands to the bypass gate driver 150 to control the bypass transistor(s) 132 to remain turned off.

[0039] In some examples, the commands output from the controller 110 to the power delivery circuit gate driver 140 and the commands output from the controller 110 to the bypass gate driver 150 may include switching commands for controlling the respective transistors. For example, the commands may include a pulse width modulation (PWM) signal containing a duty cycle and a switching frequency. The duty cycle may represent the percentage of each switching cycle that the transistor is turned on, and the switching frequency may represent the frequency at which the transistor completes the switching cycle. The power delivery circuit gate driver 140 and / or the bypass gate driver 150 may generate a PWM drive signal to be output to the gate terminal of the transistor based on receiving a PWM signal for controlling the transistor.

[0040] In some examples, the bypass gate driver 150 includes a primary supply input connection configured to supply power from the battery cell 116 to the bypass gate driver 150. In some examples, the primary supply input connection can be connected to a node that is connected to a first side of the battery cell 116. In some examples, the bypass gate driver 150 includes one or more secondary supply input connections. These one or more secondary supply input connections can be connected to one or more locations along the bypass current path 133. This means that when the bypass transistor (s) 132 are activated and current flows along the bypass current path 133, the bypass gate driver 150 can receive power from the bypass current path 133 via the one or more secondary supply input connections.

[0041] During normal operation of the system 100, when no error conditions exist in the battery cells 116 and / or the power delivery circuit 120, the bypass gate driver 150 may receive sufficient power via the primary supply input to control the bypass transistor(s) 132. However, when one or more error conditions exist in the power delivery circuit 120, the amount of power received by the bypass gate driver 150 via the primary supply input may be insufficient to control the bypass transistor(s) 132 to form the bypass current path 133. When one or more error conditions exist in the power delivery circuit 120, the amount of power received by the bypass gate driver 150 via the one or more secondary supply input connections may be sufficient for the bypass gate driver 150 to control the bypass transistor(s) 132 to form the bypass current path 133.

[0042] In some examples, bypass gate driver 150 may receive information indicating whether an error condition exists in power delivery circuit 120. In some examples, the information indicating whether an error condition exists in power delivery circuit 120 may include a command from controller 110 to turn on bypass transistor(s) 132. That is, controller 110 may identify an error condition existing in power delivery circuit 120 and output a command to bypass gate driver 150 to turn on bypass transistor(s) 132. In some examples, bypass gate driver 150 may determine whether an error condition exists in power delivery circuit 120 based on the information received from power delivery circuit 120.

[0043] An error condition present in the power delivery circuit 120 may cause a current avalanche. For example, an error condition present in one or more of the power transistors 122 may cause a current avalanche. In some examples, the current avalanche caused by the error condition present in one or more of the power transistors 122 may be associated with the load 130. If the current avalanche reaches the power delivery circuit 120, the current avalanche may damage one or more components of the power delivery circuit 120. When the bypass transistors 132 are turned on, the current avalanche caused by the error condition present in one or more of the power transistors 122 may be limited to the bypass current path 133. That is, the current associated with the current avalanche may flow through the bypass current path 133 without reaching the power delivery circuit 120.

[0044] Based on the error condition present in the power delivery circuit 120, the bypass gate driver 150 may control the bypass transistor(s) 132 to define the bypass current path 133 between the bypass transistor(s) 132 and the load 130. In some examples, the bypass gate driver 150 may control the bypass transistor(s) 132 to conduct to define the bypass current path 133. The bypass gate driver 150 may receive power from the bypass current path 133 via a secondary supply input connection of the one or more secondary supply input connections. The power received from the bypass current path 133 may exceed a power threshold for controlling the bypass transistor(s) 132 to define the bypass current path 133. In some examples, when the error condition is present in the power delivery circuit 160, the bypass gate driver 150 also receives power from the battery cell 116 via the primary supply input, but the power received via the primary supply input may not exceed the power threshold for controlling the bypass transistor(s) 132 to define the bypass current path 133.

[0045] In some examples, based on the absence of an error condition in the power delivery circuit 120, the controller 110 may be configured to output one or more commands to the bypass gate driver 150 to control the bypass transistor(s) 132 to not define the bypass current path 133. The bypass gate driver 150 is configured to receive power exceeding a power threshold from the group of battery cells 116 via the primary supply input for controlling the bypass transistor(s) 132 to not define the bypass current path 133. In some examples, the power threshold at which the bypass gate driver 150 controls the bypass transistor(s) 132 to define the bypass current path 133 is different from the power threshold at which the bypass gate driver 150 controls the bypass transistor(s) 132 to not define the bypass current path 133. For example, the power threshold at which the bypass gate driver 150 turns on the bypass transistor(s) 132 may be greater than the power threshold at which the bypass gate driver 150 keeps the bypass transistor(s) 132 off.

[0046] In some examples, the bypass gate driver 150 can include one or more supply connections that supply power from the battery cells 116. In some examples, the battery cells 116 supply power to the bypass gate driver 150 via a primary driver circuit supply path via the one or more supply connections. In some examples, the battery cells 116 supply power to the bypass gate driver 150 via one or more secondary driver circuit supply paths via the one or more supply connections. In some examples, the one or more secondary driver circuit supply paths can be configured to supply power to the bypass gate driver 150 even when an error condition exists in the battery cells 116 that prevents current from flowing across the battery cells 116 from a first side of the battery cells 116 to a second side of the battery cells 116.

[0047] The bypass gate driver 150 may receive information indicating whether an error condition exists in the battery cell 116 that prevents the bypass gate driver 150 from receiving power from the primary driver circuit supply path via one or more supply connections. In some examples, the primary driver circuit supply path includes a current flowing across the battery cell 116 from a first side of the battery cell 116 to a second side of the battery cell 116. In some examples, each secondary driver circuit supply path includes a current flowing across a portion of the battery cells 116 but not across all of the battery cells 116 from a first side of the battery cell 116 to a second side of the battery cell 116. In some examples, the information indicating whether an error condition exists in the battery cell 116 includes a message and / or command from the controller 110. In some examples, the bypass gate driver 150 identifies the error condition based on the information received from the battery cell 116.

[0048] The bypass gate driver 150 may activate the bypass transistor(s) 132 based on an error condition present in the battery cell 116 to define the bypass current path 133. When an error condition occurs in the battery cell 116, this may result in a current surge associated with the load 130. Beneficially, the bypass gate driver 150 activates the bypass transistor(s) 132 based on the error condition present in the battery cell 116 to prevent this current surge from damaging components of the power delivery circuit 120. For example, current associated with the load 130 may flow according to the bypass current path 133 without reaching the power delivery circuit 120. However, as explained in more detail below, the ability to activate the bypass transistor(s) 132 may sometimes be compromised by the error condition itself.

[0049] When bypass gate driver 150 activates bypass transistor(s) 132 to define bypass current path 133, bypass gate driver 150 is configured to receive power from the secondary driver circuit supply path via the secondary driver circuit supply path via one or more supply connections. In some examples, current can flow through the secondary driver circuit supply path across one or more of battery cells 116 without reaching an error condition present in battery cells 116. In some examples, the power received by bypass gate driver 150 via the secondary driver circuit supply path exceeds a power threshold for controlling bypass transistor(s) 132 to define bypass current path 133.

[0050] In some examples, when there is no error condition in the battery cell 116, the bypass gate driver 150 can control the bypass transistor(s) 132 to not form the bypass current path 133. For example, the bypass gate driver 150 can control the bypass transistor(s) 132 to remain off, allowing current to flow from the battery cell 116 to the load 130 according to the current path 123. When there is no error condition in the battery cell 116, the bypass gate driver 150 can receive power via the primary driver circuit supply path. In some examples, the power received via the primary driver circuit supply path satisfies a power threshold for controlling the bypass transistor(s) 132 to not form the bypass current path 133.

[0051] In some cases, the load 130 may include a power cell for an electric motor, such as a brushless direct current (BLDC) motor, a brushed direct current (DC) motor, an alternating current (AC) induction motor, or other types of electric motors. In the case where the load 130 represents a power cell for a BLDC motor, the BLDC motor may be operated according to any one of a set of phases, wherein each phase in the set of phases is associated with a corresponding input of the load 130. For example, when the power delivery circuit 120 may be configured to operate according to one or more operating modes that cause the power delivery circuit 120 to deliver a positive voltage, operate according to one or more operating modes that cause the power delivery circuit 120 to deliver a negative voltage, and operate according to one or more operating modes that cause the power delivery circuit 120 to deliver a zero voltage. Based on the operating mode of the power delivery circuit 120, the power cell for the electric motor may operate in one or more corresponding phases of the set of phases. In some examples, the electric motor corresponding to the load 130 may include an electric motor of a vehicle. Example vehicles include automobiles, trucks, buses, motorcycles, golf carts, all-terrain vehicles (ATVs), snowmobiles, aircraft, and watercraft.

[0052] The motor for load 130 is just one example. However, more generally, load 130 is not limited to a motor. Load 130 can define a collection of electrical components that consume power. In some examples, load 130 includes a collection of circuit components (such as resistors, inductors, capacitors, diodes, and other semiconductor components). Load 130 may include one or more post-regulator circuits that increase or decrease the output voltage delivered by power delivery circuit 120. In some examples, load 130 is an electrical component of a vehicle (e.g., an instrument panel, a control panel, a heating / cooling system, and lights). In other examples, load 130 includes a motor and / or electrical components used in applications other than a vehicle.

[0053] In some examples, the load 130 includes a power cell in a group of power cells for supplying power to a common load (such as a motor). For example, the group of power cells can be connected in series so that the output voltage from the group of power cells can include the sum of the voltages of the group of power cells. Since the power delivery circuit 120 can be configured to deliver a positive voltage, a negative voltage, or a zero voltage to the load 130, the voltage output from the power delivery circuit 120 can affect the voltage output from the group of power cells including the power cell corresponding to the load 130. For example, when the power delivery circuit 120 outputs a positive voltage to the load 130, the voltage output from the group of power cells may be higher than when the power delivery circuit 120 outputs a zero voltage to the load 130.

[0054] FIG. 2A to FIG. 2D 2 is a circuit diagram illustrating example configurations 200A-200D of power delivery circuits according to one or more techniques of the present disclosure. In some examples, each of the configurations 200A-200D is similar to Figure 1 The power delivery circuit 120 corresponds to one of a set of operating modes. For example, Figure 2A Configuration 200A may represent a first operating mode of the power delivery circuit 120, Figure 2B Configuration 200B may represent a second operating mode of the power delivery circuit 120, Figure 2C Configuration 200C may represent a third operating mode of the power delivery circuit 120, while Figure 2D Configuration 200D may represent a fourth operating mode of the power delivery circuit 120 .

[0055] like Figure 2A As shown, configuration 200A includes (one or more) power transistors 203A-203D (collectively referred to as "power transistors 203") and (one or more) bypass transistors 213A, 213B (collectively referred to as "bypass transistors 213"). Power transistor 203 may be Figure 1The bypass transistor 213 may be an example of a power transistor (or transistors) 222. Figure 1 2. The bypass transistor 132 of the embodiment of the present invention is an example of a bypass transistor 132 of the embodiment of the present invention. In the configuration 200A, the power transistors 203A, 203B are turned on, while the power transistors 203C, 203D are turned off. Since both the power transistors 203C, 203D are turned off, the configuration 200A does not include any connection between the positive terminal of the battery cell 116 and the negative terminal of the battery cell 116 via the power transistor 203 of the power delivery circuit 120. Since there is no connection between the positive terminal of the battery cell 116 and the negative terminal of the battery cell 116 via the power transistor 203, current cannot flow through the power delivery circuit 120. This means that when operating according to the operating mode corresponding to the configuration 200A, the power delivery circuit 120 can output zero volts to the load 130.

[0056] like Figure 2B As shown, configuration 200B includes (one or more) power transistors 223A-223D (collectively referred to as "power transistors 223") and (one or more) bypass transistors 233A, 233B (collectively referred to as "bypass transistors 233"). Power transistor 223 may be Figure 1 The bypass transistor 233 may be an example of a power transistor (or transistors) 222. Figure 1 200B, the power transistors 223A and 223D are turned on, while the power transistors 223B and 223C are turned off. Since the power transistor 223A is turned on, the current can flow from the positive terminal of the battery cell 116 through the high side of the power delivery circuit 120 via the power transistor 223A. Since the power transistor 223D is turned on, the current can flow to the negative terminal of the battery cell 116 via the power transistor 223D via the low terminal of the power delivery circuit 120. Since according to the configuration 200B, the current flows from the positive terminal of the battery cell 116 through the high side of the power delivery circuit 120 to the load 130 and the current flows from the load 130 through the low side of the power delivery circuit 120 to the negative terminal of the battery cell 116, when operating in the operation mode corresponding to the configuration 200B, the power delivery circuit 120 can deliver a positive voltage to the load 130.

[0057] like Figure 2C As shown, configuration 200C includes (one or more) power transistors 243A-243D (collectively referred to as "power transistors 243") and (one or more) bypass transistors 253A, 253B (collectively referred to as "bypass transistors 253"). Power transistor 243 may be Figure 1 The bypass transistor 253 may be an example of a power transistor (or transistors) 222. Figure 1200A, the power transistors 243A and 243B are turned off, and the power transistors 243C and 243D are turned on. Since both the power transistors 243A and 243B are turned off, the configuration 200C does not include any connection between the positive terminal of the battery cell 116 and the negative terminal of the battery cell 116 via the power transistor 243 of the power delivery circuit 120. Since there is no connection between the positive terminal of the battery cell 116 and the negative terminal of the battery cell 116 via the power transistor 243, current cannot flow through the power delivery circuit 120. This means that when operating according to the operating mode corresponding to the configuration 200C, the power delivery circuit 120 can output zero volts to the load 130.

[0058] like Figure 2D As shown, configuration 200D includes (one or more) power transistors 263A-263D (collectively referred to as "power transistors 263") and (one or more) bypass transistors 273A, 273B (collectively referred to as "bypass transistors 273"). Power transistor 263 may be Figure 1 The bypass transistor 273 may be an example of a power transistor (or transistors) 222. Figure 1 200D. In the configuration 200D, the power transistors 263A, 263D are turned off, and the power transistors 263C, 263D are turned on. Since the power transistor 263B is turned on, the current can flow from the positive terminal of the battery cell 116 through the high side of the power delivery circuit 120 via the power transistor 263B. Since the power transistor 263C is turned on, the current can flow through the low side of the power delivery circuit 120 to the negative terminal of the battery cell 116 via the power transistor 263C. Since according to the configuration 200D, the current flows from the positive terminal of the battery cell 116 through the high side of the power delivery circuit 120 to the load 130 and the current flows from the load 130 through the low side of the power delivery circuit 120 to the negative terminal of the battery cell 116, when operating in the operation mode corresponding to the configuration 200D, the power delivery circuit 120 can deliver a negative voltage to the load 130.

[0059] Figure 3 is a circuit diagram illustrating a first example circuit 300 for supplying power to a bypass gate driver 350 in accordance with one or more techniques of this disclosure. Figure 3As shown, circuit 300 includes controller 310, power delivery circuit 320, bypass transistors 332A-332B (collectively referred to as "bypass transistors 332"), load 330, power delivery circuit gate driver 340, and bypass gate driver 350. Controller 310 includes processing circuit device 312, memory 314, and battery management circuit 315. Power delivery circuit 320 includes power transistors 322A-322D (collectively referred to as "power transistors 322"). Bypass gate driver 350 may include primary supply input connection 351, first diode 352, first secondary supply input connection 353, second diode 354, second secondary supply input connection 355, third diode 356, and internal supply unit 258.

[0060] The circuit 300 may be Figure 1 Controller 310 may be an example of system 100. Figure 1 The processing circuit device 312 may be an example of a controller 110 of FIG. Figure 1 An example of processing circuit device 112 of FIG. 314 may be Figure 1 The battery management circuit 315 may be an example of a memory 114. Figure 1 An example of a battery management circuit 115 is shown in FIG. 31 . The battery cell 316 may be Figure 1 An example of a battery cell 116 of FIG. 1 is shown in FIG. 1 . The power delivery circuit 320 may be Figure 1 An example of a power delivery circuit 120 of FIG. 1 is shown in FIG. 1 . The power transistor 322 may be Figure 1 The bypass transistor 332 may be an example of the bypass transistor 132 of FIG. 2 . The load 330 may be an example of the bypass transistor 132 of FIG. 2 . Figure 1 The power delivery circuit gate driver 340 may be Figure 1 The bypass gate driver 350 may be an example of a power delivery circuit gate driver 140. Figure 1 1. Although six cells are illustrated, in some examples, the battery cells 316 may include 12 battery cells, 16 battery cells, or any number of battery cells. The battery management circuit 315 may be designed or configured to manage 12 or fewer cells, or possibly 16 or fewer cells.

[0061] In some examples, bypass gate driver 350 can receive information indicating whether an error condition exists in power delivery circuit 320. In some examples, the information indicating whether an error condition exists in power delivery circuit 320 includes a command, message, or instruction from controller 310. For example, controller 310 can identify an error condition existing in power delivery circuit 320 and output a command to bypass gate driver 350 to control bypass transistor 332 to form bypass current path 333. In some examples, bypass gate driver 350 can identify the error condition based on the information received from power delivery circuit 320.

[0062] Bypass gate driver 350 may control bypass transistor 332 to define bypass current path 333 between bypass transistor 332 and load 330 based on an error condition present in power delivery circuit 320. For example, bypass gate driver 350 may output a signal to a gate terminal of bypass transistor 332A sufficient to turn on bypass transistor 332A and bypass gate driver 350 may output a signal to a gate terminal of bypass transistor 332B sufficient to turn on bypass transistor 332B. In some examples, to turn on bypass transistor 332A and bypass transistor 332B, bypass gate driver 350 may output a voltage greater than a threshold voltage to a gate terminal of bypass transistor 332A and bypass gate driver 350 may output a voltage greater than a threshold voltage to a gate terminal of bypass transistor 332B. Figure 3 As shown, the body diode of bypass transistor 332A faces in the opposite direction from the body diode of bypass transistor 332B. That is, bypass transistors 332 may be placed in an anti-series arrangement.

[0063] The bypass gate driver 350 includes a primary supply input connection 351 connected to a first diode 352, a first secondary input supply connection 353 connected to a second diode 354, and a second secondary supply input connection 355 connected to a third diode 356. In some examples, the first diode 352, the second diode 354, and the third diode 356 can represent independent diodes within the bypass gate driver 350. In some examples, one or more of the first diode 352, the second diode 354, and the third diode 356 can represent the body diode of a semiconductor device. For example, when a transistor (such as a MOSFET) operates as an active diode, the body diode of the MOSFET can act as a diode when the MOSFET is turned off, but when the MOSFET is turned on, the body diode of the MOSFET can be removed. This means that whether the MOSFET is turned on or off controls whether the body diode of the MOSFET affects the operation of the circuit. The internal supply unit 358 can receive an electrical signal from one or more of the first diode 352, the second diode 354, and the third diode 356. In some examples, internal supply unit 358 can generate one or more output signals for sending to bypass transistor 332 .

[0064] In the field of circuit electronics, a diode includes a semiconductor component that allows current to flow across the diode in a first direction (e.g., "forward") and prevents current from flowing across the diode in a second direction (e.g., "reverse"). A diode may include an anode and a cathode, and current may pass through the diode in the forward direction from the anode to the cathode. However, current may not pass through the diode in the reverse direction from the cathode to the anode.

[0065] In some examples, the primary supply input connector 351 can supply power from the battery cell 316 to the bypass gate driver 350. For example, the primary supply input connector 351 can be connected to a node 362. The node 362 can be connected to a first side (e.g., a positive terminal) of the battery cell 316. This means that the primary supply input connector 351 can receive a signal having a voltage substantially the same as the voltage at the node 362. When the circuit 300 operates normally and the battery cell 316 supplies power to the load 330 via the power delivery circuit 320, the voltage at the node 362 can be equal to the voltage output from the battery cell 316. When there is no error condition in the battery cell 316 and / or the power delivery circuit 320, the power received by the bypass gate driver 350 via the primary supply input connector 351 may exceed the power threshold for controlling the bypass transistor 332 to not form the bypass current path 333.

[0066] The first secondary supply input connection 353 and / or the second secondary supply input connection 355 may supply power to the bypass gate driver 350 from the bypass current path 333. For example, when the bypass gate driver 350 activates the bypass transistor 332 to define the bypass current path 333 based on an error condition present in the power delivery circuit 320, current may flow based on the bypass current path 333. That is, the current may flow clockwise from the first side of the bypass transistor 332 to the first side of the load 330, flow through the load 330, flow from the second side of the load 330 to the second side of the bypass transistor 332, and flow through the bypass transistor 332. Alternatively, the current may flow counterclockwise from the second side of the bypass transistor 332 to the second side of the load 330, flow through the load 330, flow from the second side of the load 330 to the second side of the bypass transistor 332, and flow through the bypass transistor 332. In any event where the bypass transistor 332 is activated and current flows according to the bypass current path 333 , the first secondary supply input connection 353 and / or the second secondary supply input connection 355 may supply power to the bypass gate driver 350 .

[0067] The bypass gate driver 350 may automatically receive power sufficient to control the bypass transistor 332 to define the bypass current path 333. For example, when an error condition present in the power delivery circuit 320 causes the voltage at the node 364 and / or the node 366 to increase, the bypass gate driver 350 may automatically receive power via the first secondary supply input connection 353 and / or the second secondary supply input connection 355 so that the bypass gate driver 350 receives sufficient power for controlling the bypass transistor 332 to define the bypass current path 333. In other words, since the first secondary supply input connection 353 and the second secondary supply input connection 355 connect the bypass gate driver 350 to nodes along the bypass current path 333, the bypass gate driver 350 may automatically receive power from the bypass current path 333 under the condition that an error condition present in the power delivery circuit 320 causes the current and / or voltage at the node 364 and / or the node 366 to increase. In some examples, the increase in current and / or voltage at node 364 and / or node 366 may occur before gate driver circuit 350 receives a command to activate bypass transistor 332. This means that gate driver circuit 350 may automatically receive power via first secondary supply input connection 353 and / or second secondary supply input connection 355 such that when bypass gate driver 350 receives a command to turn on bypass transistor 332, bypass gate driver 350 receives sufficient power to turn on bypass transistor 332.

[0068] like Figure 3As shown, the power transistors 322 of the power delivery circuit 320 can form an H-bridge circuit. The error conditions present in the power delivery circuit 320 may include error conditions present in one or more power transistors 322. For example, an error condition may exist in any one or combination of power transistors 322A, power transistors 322B, power transistors 322C, and power transistors 322D. The error conditions present in the power transistors 322 may include a power transistor failure that prevents current from flowing across the power transistors. For example, a power transistor failure at power transistor 322A may prevent current from flowing across power transistor 322A, a power transistor failure at power transistor 322B may prevent current from flowing across power transistor 322B, and so on. Other error conditions include a short circuit across the power transistors, a component failure that attenuates the amount of current that can flow across the power transistors, other types of error conditions, or any combination thereof. In some examples, the error conditions present in one or more power transistors 322 may prevent the H-bridge circuit formed by the power transistors 322 from operating according to one or more operating modes.

[0069] In some examples, when an error condition occurs at power transistor 322A and bypass gate driver 350 activates bypass transistor 332, current may flow counterclockwise according to bypass current path 333. In some examples, when an error condition occurs at power transistor 322B and bypass gate driver 350 activates bypass transistor 332, current may flow clockwise according to bypass current path 333. When bypass gate driver 350 activates bypass transistor 332 based on the error condition present at power transistor 322B, bypass gate driver 350 may receive power from first secondary supply input connection 353 connected to node 364. When bypass gate driver 350 activates bypass transistor 332 based on the error condition present at power transistor 322A, bypass gate driver 350 may receive power from second secondary supply input connection 355 connected to node 366. In some examples, bypass gate driver 350 can receive power from first secondary supply input connection 353 and / or second secondary supply input connection 355 when an error condition occurs at one or more locations other than power transistor 322A and power transistor 322B.

[0070] The power received via the first secondary supply input connection 353 and / or the second secondary supply input connection 355 may exceed a power threshold for controlling the bypass transistor 332 to define the bypass current path 333. As used herein, the term "power threshold" may refer to a current threshold and / or a voltage threshold. That is, when the bypass gate driver 350 receives a voltage exceeding the voltage threshold and / or a current greater than the current threshold, the bypass gate driver 350 may be configured to control the bypass transistor 332 to define the bypass current path 333. When the bypass gate driver 350 receives a voltage that does not exceed the voltage threshold and / or a current that does not exceed the current threshold, the bypass gate driver 350 may not receive enough power to control the bypass transistor 332 to define the bypass current path 333.

[0071] In some examples, when an error condition exists in the power delivery circuit 320, the bypass gate driver 350 can receive power from the battery cell 316 via the primary supply input connection 351. However, when an error condition exists in the power delivery circuit 320, the power received by the bypass gate driver 350 via the primary supply input connection 351 may not exceed the power threshold used to control the bypass transistor 332 to define the bypass current path 333. In some examples, the power received from the first secondary supply input connection 353 and / or the second secondary supply input connection 355 can supplement the power received from the primary supply input connection 351, so that the total power received by the bypass gate driver 350 exceeds the power threshold used to control the bypass transistor 332 to define the bypass current path 333.

[0072] Figure 4 is a circuit diagram illustrating a second example circuit 400 for supplying power to a bypass driver circuit 450 in accordance with one or more techniques of this disclosure. Figure 4As shown, circuit 400 includes controller 410, battery cells 416A-416F (collectively referred to as "battery cells 416"), power delivery circuit 420, bypass transistors 432A-432B (collectively referred to as "bypass transistors 432"), load 430, power delivery circuit gate driver 440, and bypass gate driver 450. Controller 410 includes processing circuit device 412, memory 414, and battery management circuit 415. Power delivery circuit 420 includes power transistors 422A-422D (collectively referred to as "power transistors 422"). Bypass gate driver 450 may include a first supply connection 451, a first diode 452, a second supply connection 453, a second diode 454, a third diode 456, a fourth diode 457, and an internal supply and boost unit 458. Although six cells are illustrated, in some examples, battery cell 416 may include 12 battery cells, 16 battery cells, or any number of battery cells. The battery management circuit 415 may be designed or configured to manage 12 or fewer cells, or possibly 16 or fewer cells.

[0073] Circuit 400 may be Figure 1 Controller 410 may be an example of system 100. Figure 1 The processing circuit device 412 may be Figure 1 An example of processing circuit device 112 of FIG. 414 may be Figure 1 The battery management circuit 415 may be an example of a memory 114. Figure 1 An example of a battery management circuit 115 is shown in FIG. 4 . The battery cell 416 may be Figure 1 An example of a battery cell 116 of FIG. 4 is shown in FIG. 4B . The power delivery circuit 420 may be Figure 1 An example of a power delivery circuit 120 of FIG. 4 is shown in FIG. 4 . The power transistor 422 may be Figure 1 The bypass transistor 432 may be an example of the bypass transistor 132 of FIG. 2 . The load 430 may be an example of the bypass transistor 132 of FIG. 2 . Figure 1 The power delivery circuit gate driver 440 may be an example of a load 130. Figure 1 An example of a power delivery circuit gate driver 140. The bypass gate driver 450 may be Figure 1 An example of a bypass gate driver 150 .

[0074] In some examples, bypass gate driver 450 can receive information indicating whether an error condition exists in battery cell 416. In some examples, the information indicating whether an error condition exists in battery cell 416 includes a command, message, or instruction from controller 410. For example, controller 410 can identify an error condition existing in battery cell 416 and output a command to bypass gate driver 450 to control bypass transistor 432 to form bypass current path 433. In some examples, bypass gate driver 450 can identify the error condition based on the information received from battery cell 416.

[0075] Bypass gate driver 450 may control bypass transistor 432 based on an error condition present in battery cell 416 to define a bypass current path 433 between bypass transistor 432 and load 430. For example, bypass gate driver 450 may output a signal to a gate terminal of bypass transistor 432A sufficient to turn on bypass transistor 432A and bypass gate driver 450 may output a signal to a gate terminal of bypass transistor 432B sufficient to turn on bypass transistor 432B. In some examples, to turn on bypass transistor 432A and bypass transistor 432B, bypass gate driver 450 may output a voltage greater than a threshold voltage to a gate terminal of bypass transistor 432A and bypass gate driver 450 may output a voltage greater than a threshold voltage to a gate terminal of bypass transistor 432B. Figure 4 As shown, the body diode of bypass transistor 432A faces in the opposite direction to the body diode of bypass transistor 432B. That is, bypass transistors 432 may be placed in an anti-series arrangement.

[0076] In some examples, the battery cells 416A-416F can be connected in series so that the output voltage from the battery cells 416A-416F is the sum of the voltage outputs from each of the battery cells 416A-416F. When the circuit 400 operates normally under the condition that there is no error condition in the battery cells 416, current can flow across each of the battery cells 416A-416F and the battery cells 416 can supply power to the load 430 via the power delivery circuit 420. However, when one or more error conditions exist in the battery cells 416, this can prevent current from flowing across each of the battery cells 416A-416F from the first side of the battery cells 416 to the second side of the battery cells 416. The battery cells 416 are not limited to including six cells. In some examples, the battery cells 416 can include more than six cells or less than six cells.

[0077] When no error condition exists in the battery cell 416, the bypass gate driver 450 may receive power via the primary driver circuit supply path 472. Figure 4 As shown, the first supply connection 451 is connected to the node 462. The node 462 is connected to one side of the battery cell 416. In some examples, the node 462 is connected to one side of the battery cell 416 corresponding to the positive terminal of the battery cell 416. The primary driver circuit supply path 472 delivers power to the bypass gate driver 450 by delivering power from the node 462 to the first supply connection 451. In some examples, according to the primary driver circuit supply path 472, current can flow from the node 462 to the first supply connection 451, from the first supply connection 451 through the first diode 452, through the internal supply and boost unit 458, and through the fourth diode 457 to ground. In some examples, the bypass gate driver 450 may not include the fourth diode 457. In these examples, current can flow from the internal supply and boost unit 458 to ground without flowing through the fourth diode 457.

[0078] When an error condition is not present in the battery cell 416, current may flow from the positive terminal of the battery cell 416 through the node 462, and from the node 462 to the power delivery circuit 420. At least some of the current flowing from the battery cell 416 through the node 462 may flow to the bypass gate driver 450, and at least some of the current flowing from the battery cell 416 through the node 462 may flow to the power delivery circuit 420. When an error condition is not present in the battery cell 416, the power received by the bypass gate driver 450 via the primary driver circuit supply path 472 may exceed a power threshold for controlling the bypass transistor 432 to not form a bypass current path.

[0079] When an error condition exists in the battery cell 416, this may prevent current from flowing across each of the battery cells 416A-416F. The error condition present in the battery cell 416 may include one or more broken connections between consecutive cells of the battery cells 416A-416F, one or more broken connections within one of the battery cells 416A-416F, one or more short connections, or any combination thereof. In some examples, the presence of an error condition in the battery cell 416 may prevent current from flowing across each of the battery cells 416A-416F and prevent the battery cell 416 from supplying power to the load 430 via the power delivery circuit 420 according to the circuit across each of the battery cells 416A-416F. For example, when the error condition prevents current from flowing across each of the battery cells 416A-416F, this may disconnect the circuit connecting the positive terminal of the battery cell 416 and the negative terminal of the battery cell 416.

[0080] The bypass gate driver 450 may be configured to receive power via the secondary driver circuit supply path 474 in response to one or more error conditions present in the battery cells 416. The secondary driver circuit supply path 474 may allow current to pass through one or more battery cells 416A-416F even when an error connection prevents current from passing through all of the battery cells 416A-416F. For example, when an error condition at battery cell 416E prevents current from flowing from battery cell 416F across battery cells 416A-416F to battery cell 416A, current may still be able to flow from battery cell 416D to battery cell 416A without reaching the error condition at battery cell 416E. The secondary driver circuit supply path 474 may create a circuit that allows the bypass gate driver 450 to receive power from the battery cells 416 even when an error condition interrupts the circuit across the battery cells 416.

[0081] For example, secondary driver circuit supply path 474 may extend from one or more cells of battery cells 416A-416F across nodes within the cells of battery cells 416A-416F to a positive terminal of battery cell 416 (e.g., a positive terminal at an end of battery cell 416A). Nodes within the cells of battery cells 416A-416F may be located between consecutive nodes of battery cells 416A-416F. In some examples, nodes within the cells within battery cells 416A-416F may be located between battery cell 416A and battery cell 416B. In some examples, nodes within the cells within battery cells 416A-416F may be located between battery cell 416B and battery cell 416C. In some examples, nodes within the cells within battery cells 416A-416F may be located between battery cell 416C and battery cell 416D. In some examples, the intra-cell node within battery cells 416A-416F may be located between battery cell 416D and battery cell 416E. In some examples, the intra-cell node within battery cells 416A-416F may be located between battery cell 416E and battery cell 416F. In any case, secondary driver circuit supply path 474 may extend across one or more of battery cells 416A-416F without extending across one or more other of battery cells 416A-416F.

[0082] When the bypass gate driver 450 receives power according to the secondary driver circuit supply path 474, current can flow from the positive terminal of the battery cell 416 to the node 462, from the node 462 to the first supply connection 451, from the first supply connection 451 through the first diode 452, from the first diode 452 through the internal supply and boost cell 458, from the internal supply and boost cell 458 through the third diode 456, from the third diode 456 to the node 459, from the node 459 to the second supply connection 453, and from the second supply connection 453 to a node within the battery cell 416. In some examples, when there is no faulty connection between a node within battery cell 416 and the positive terminal of battery cell 416 (e.g., the positive terminal of battery cell 416A), one or more battery cells 416A-416F located between a node within battery cell 416 and the positive terminal of battery cell 416 may supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even if one or more faulty conditions exist between a node within battery cell 416 and the negative terminal of battery cell 416 (e.g., the negative terminal of battery cell 416F).

[0083] The bypass gate driver 450 may automatically receive power sufficient to control the bypass transistor 432 to define the bypass current path 433. For example, in response to an error condition present in the battery cell 416 that causes a short circuit that prevents current from flowing across the battery cell 416, the bypass gate driver 450 may automatically receive power via the secondary driver circuit supply path 474 so that the bypass gate driver 450 receives sufficient power for controlling the bypass transistor 432 to define the bypass current path 433. In other words, because the secondary driver circuit supply path 474 may span one or more of the battery cells 416 without spanning the error condition, the bypass gate driver 450 may automatically receive power via the secondary driver circuit supply path 474 under the condition that an error condition exists in the battery cell 416 that prevents the bypass gate driver 450 from receiving power via the primary driver circuit supply path 472. In some examples, the error condition in the battery cell 416 may occur before the gate driver circuit 450 receives a command to activate the bypass transistor 432. This means that the gate driver circuit 450 can automatically receive power via the secondary driver circuit supply path 474 so that when the bypass gate driver 450 receives a command to turn on the bypass transistor 432, the bypass gate driver 450 receives sufficient power to turn on the bypass transistor 432.

[0084] In some examples, the first diode 452, the second diode 454, the third diode 456, and the fourth diode 457 can represent independent diodes within the bypass gate driver 450. In some examples, one or more of the first diode 452, the second diode 454, the third diode 456, and the fourth diode 457 can represent a body diode of a semiconductor device. For example, when a transistor (such as a MOSFET) operates as an active diode, the body diode of the MOSFET can act as a diode when the MOSFET is turned off, but when the MOSFET is turned on, the body diode of the MOSFET can be removed. This means that whether the MOSFET is turned on or off controls whether the body diode of the MOSFET affects the operation of the circuit.

[0085] For example, when a node within battery cell 416 of secondary driver circuit supply path 474 is located between battery cell 416A and battery cell 416B, battery cell 416A may supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even when an error condition exists between the node and the negative terminal of battery cell 416F. When a node within battery cell 416 of secondary driver circuit supply path 474 is located between battery cell 416B and battery cell 416C, battery cells 416A and 416B may supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even when an error condition exists between the node and the negative terminal of battery cell 416F. When a node within battery cells 416 of secondary driver circuit supply path 474 is between battery cells 416C and battery cells 416D, battery cells 416A-416C may supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even when an error condition exists between the node and the negative terminal of battery cell 416F. When a node within battery cells 416 of secondary driver circuit supply path 474 is between battery cells 416D and battery cells 416E, battery cells 416A-416D may supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even when an error condition exists between the node and the negative terminal of battery cell 416F. When a node within battery cell 416 of secondary driver circuit supply path 474 is between battery cell 416E and battery cell 416F, battery cells 416A-416E can supply power to bypass gate driver 450 via secondary driver circuit supply path 474 even when an error condition exists between the node and the negative terminal of battery cell 416F.

[0086] The bypass gate driver 450 may receive power from the secondary driver circuit supply path 474 based on the error condition present in the battery cell 416. In some examples, the power received by the bypass gate driver 450 from the secondary driver circuit supply path 474 may exceed a power threshold for controlling the bypass transistor 432 to define the bypass current path 433. Current may flow through the secondary driver circuit supply path 474 without reaching the error condition present in the battery cell 416. That is, current may flow through one or more of the battery cells 416A-416F according to the secondary driver circuit supply path 474 without reaching the error condition present in the battery cells 416A-416F.

[0087] Figure 5 5 is a circuit diagram illustrating a system 500 including a set of circuits 502A-502N (collectively referred to as "circuit 502"), each circuit configured to supply power to a power cell in a set of power cells 504A-504N that supply power to a common load 506. Each circuit in circuit 502 may include a battery cell, a power delivery circuit, and a bypass transistor. For example, circuit 502A includes battery cell 516A, power delivery circuit 520A including power transistors 522A-522D, and bypass transistors 532A, 532B. Circuit 502B includes battery cell ( Figure 5 Not shown), including power transistors ( Figure 5 The power transmission circuit (not shown) Figure 5 not shown) and a bypass transistor ( Figure 5 Circuit 502N includes battery cell 516N, power delivery circuit 520N including power transistors 552A-552D, and bypass transistors 562A, 562B. In some examples, circuit 502 may include Figure 5 One or more components not shown in the figure, such as a controller and a gate driver.

[0088] In some examples, each circuit in circuit 502 may be Figure 1 System 100, Figure 3 The circuit 300 or Figure 4 Each group of battery cells 516A-516N may be Figure 1 Battery cells 116, Figure 3 Battery cells 316 or Figure 4 Each of the power delivery circuits 520A-520N may be an example of a battery cell 416. Figure 1 The power delivery circuit 120, Figure 3 The power delivery circuit 320 or Figure 4Each of the power cells 504A-504N may be Figure 1 Load 130, Figure 3 The load is 330 or Figure 4 An example of a load 430.

[0089] The power delivery circuit of each circuit in circuit 502 can be configured to supply a positive voltage, a negative voltage, or a zero voltage to the corresponding power cell of power cell 504. For example, power delivery circuit 520A can be configured to supply a positive voltage, a negative voltage, or a zero voltage to power cell 504A, and the power delivery circuit of circuit 504B can be configured to supply a positive voltage, a negative voltage, or a zero voltage to power cell 504B, and so on. In some examples, when the power delivery circuit delivers a positive voltage or a negative voltage, the voltage has a constant amplitude. For example, power delivery circuit 520A can deliver positive 24 volts (+24V), negative 24 volts (-24V), or zero volts (0V). The power output from the power delivery circuit is not limited to 24V. The constant amplitude may include any number of volts.

[0090] In some examples, circuit 502 can control the voltage delivered to each of power cells 504A-504N in order to control the voltage delivered to common load 506. In some examples, the voltage delivered to common load 506 can represent the sum of the voltages delivered to each of power cells 504A-504N. For example, power cells 504 can deliver 48V to common load 506 when power delivery circuit 520A delivers 24V to power cell 504A and power delivery circuit 520B delivers 24V to power cell 504B but each other power delivery circuit delivers 0V to the corresponding power cell.

[0091] Figure 6 is a graph illustrating a graph 602 of voltage output from a group of power cells to a common load, in accordance with one or more techniques of this disclosure. In some examples, the graph 602 may indicate a voltage output from the group of power cells 504 to the common load 506.

[0092] like Figure 6As shown, curve 602 indicates that the voltage output from the power unit 504 to the common load 506 oscillates between the positive maximum voltage 604 and the negative minimum voltage 606. In some examples, when each power unit of the power unit 504 receives a positive voltage, the group of power units 504 can output the positive maximum voltage 604. In some examples, when each power unit in the power unit 504 receives a negative voltage, the group of power units 504 can output the negative minimum voltage 606. The circuit 502 can control the power delivery circuit 520 to output a positive voltage, a negative voltage, or a zero voltage so that the voltage output from the group of power units 504 to the common load 506 oscillates according to the curve 602.

[0093] Figure 7 is a flow chart illustrating example operations for supplying power to a bypass gate driver when an error condition occurs in a power delivery circuit, in accordance with one or more techniques of this disclosure. Figure 7 It is for Figure 3 However, Figure 7 The techniques may be performed by different components of circuit 300 or by additional or alternative systems.

[0094] Bypass gate driver 350 may receive information indicating whether an error condition exists in power delivery circuit 320 (702). In some examples, the information indicating whether an error condition exists includes a command from controller 310 to control bypass transistor 332 to define bypass current path 333. In some examples, bypass gate driver 350 is configured to identify the error condition based on the information received from power delivery circuit 320. In some examples, controller 310 may identify the error condition existing in power delivery circuit 320 based on the information received from power delivery circuit 320, and output a command to bypass gate driver 350 to define bypass current path 333.

[0095] The bypass gate driver 350 may control the bypass transistor 332 based on the error condition present in the power delivery circuit 320 to define the bypass current path 333 between the bypass transistor 332 and the load 330 (704). In some examples, when the bypass gate driver 350 controls the bypass transistor 332 to define the bypass current path 333, current may flow according to the bypass current path 333 without reaching the power delivery circuit 320. In some examples, when the bypass gate driver 350 receives power exceeding a power threshold for controlling the bypass transistor 332 to define the bypass current path 333, the bypass gate driver 350 may be configured to control the bypass transistor 332 to define the bypass current path 333. In some examples, when the bypass gate driver 350 receives power not exceeding the power threshold for controlling the bypass transistor 332 to define the bypass current path 333, the bypass gate driver 350 may not be configured to control the bypass transistor 332 to define the bypass current path 333.

[0096] The bypass gate driver 350 may receive power from the bypass current path 333 that exceeds a power threshold for controlling the bypass transistor 332 to define the bypass current path 333 (706). By receiving power from the bypass current path 333, the bypass gate driver 350 may receive power that exceeds a power threshold for controlling the bypass transistor 332 to define the bypass current path 333. For example, the bypass gate driver 350 may be configured to receive power from the battery cell 316 via the primary supply input connection 351, receive power from the bypass current path 333 via the first secondary supply input connection 353, receive power from the bypass current path 333 via the second secondary supply input connection 355, or any combination thereof.

[0097] In some examples, when an error condition exists in the power delivery circuit 320, the power received by the bypass gate driver 350 may not exceed the power threshold used to control the bypass transistor 332 to define the bypass current path 333. However, when an error condition occurs in the power delivery circuit 320 and the bypass gate driver 350 controls the bypass transistor 332 to define the bypass current path 333, the bypass gate driver 350 may receive power via the first secondary supply input connection 353 and / or the second secondary supply input connection 355, so that the power received by the bypass gate driver 350 exceeds the power threshold used to control the bypass transistor 332 to define the bypass current path 333.

[0098] Figure 8 is a flow chart illustrating example operations for supplying power to a bypass gate driver when an error condition exists in a group of battery cells, in accordance with one or more techniques of this disclosure. Figure 8 It is for Figure 4The circuit 400 is described. However, Figure 8 The techniques may be performed by different components of circuit 400 or by additional or alternative systems.

[0099] The bypass gate driver 450 may receive information indicating whether an error condition exists in the battery cell 416 that prevents the bypass gate driver circuit 450 from receiving power from the primary driver circuit supply path 472 across the battery cell 416 via one or more supply connections (802). This may prevent current from flowing across the battery cell 416 when an error condition exists in the battery cell 416, for example. The bypass gate driver 450 may activate the bypass transistor 432 based on the error condition existing in the battery cell 416 to define a bypass current path 433 to bypass the power delivery circuit 420 (804). The bypass gate driver 450 may receive power from the secondary driver circuit supply path 474 across the battery cell 416 via one or more supply connections, wherein current flows through the secondary driver circuit supply path 474 without reaching the error condition (806).

[0100] The following numbered clauses may demonstrate one or more aspects of the present disclosure.

[0101] Clause 1: A driver circuit configured to control one or more bypass transistors, the driver circuit comprising: a primary supply input connection configured to supply power to the driver circuit from a group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit; and one or more secondary supply input connections. The driver circuit is configured to: receive information indicating whether an error condition exists in the power delivery circuit; based on the error condition existing in the power delivery circuit, control the one or more bypass transistors to define a bypass current path between the one or more bypass transistors and the load; and receive power from the bypass current path via a secondary supply input connection of the one or more secondary supply input connections, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0102] Item 2: A driver circuit according to item 1, wherein the driver circuit is further configured to: receive power from the group of battery cells via the primary supply input connection when the error condition exists in the power delivery circuit, and wherein the power from the group of battery cells does not exceed a power threshold used to control the one or more bypass transistors to define the bypass current path.

[0103] Clause 3: A driver circuit according to any one of clauses 1 to 2, wherein the power threshold is a first power threshold, and wherein the driver circuit is further configured to: control the one or more bypass transistors to not define the bypass current path based on an error condition not existing in the power delivery circuit; and receive power exceeding a second power threshold for controlling the one or more bypass transistors to not define the bypass current path from the group of battery cells via the primary supply input connection.

[0104] Clause 4: A driver circuit according to any one of clauses 1 to 3, wherein the one or more secondary supply input connectors include: a first secondary supply input connector configured to supply power to the driver circuit from a first node of the bypass current path when an error condition occurs at a first node of the power delivery circuit; and a second secondary supply input connector configured to supply power to the driver circuit from a second node of the bypass current path when an error condition occurs at a second node of the power delivery circuit.

[0105] Clause 5: A driver circuit as described in clause 4, wherein the power delivery circuit includes two or more power transistors, wherein a first node of the power delivery circuit includes a first power transistor of the two or more power transistors, and wherein a second node of the power delivery circuit includes a second power transistor of the two or more power transistors.

[0106] Clause 6: A driver circuit according to any one of clauses 1 to 5, wherein the power delivery circuit includes an H-bridge circuit, the H-bridge circuit includes a first power transistor, a second power transistor, a third power transistor and a fourth power transistor, and wherein the error condition includes a failure of one or more of the first power transistor, the second power transistor, the third power transistor and the fourth power transistor.

[0107] Clause 7: A driver circuit according to clause 6, wherein the H-bridge circuit is configured to: supply zero voltage to the load according to a first operating mode when the first power transistor and the second power transistor are turned on and the third power transistor and the fourth power transistor are turned off; supply a positive voltage to the load according to a second operating mode when the first power transistor and the fourth power transistor are turned on and the second power transistor and the third power transistor are turned off; supply zero voltage to the load according to a third operating mode when the first power transistor and the second power transistor are turned off and the third power transistor and the fourth power transistor are turned on; and supply a negative voltage to the load according to a fourth operating mode when the first power transistor and the fourth power transistor are turned off and the second power transistor and the third power transistor are turned on, wherein an error condition including a failure of one or more of the first power transistor, the second power transistor, the third power transistor and the fourth power transistor prevents the H-bridge circuit from operating according to one or more of the first operating mode, the second operating mode, the third operating mode and the fourth operating mode.

[0108] Clause 8: A driver circuit as described in any of clauses 1 to 7, wherein the one or more bypass transistors include a first bypass transistor and a second bypass transistor placed in an anti-series arrangement such that a body diode of the first bypass transistor and a body diode of the second bypass transistor face in opposite directions.

[0109] Clause 9: A driver circuit according to any one of clauses 1 to 8, wherein in order to control the one or more bypass transistors to define a bypass current path, the driver circuit is configured to: apply a voltage sufficient to turn on the one or more bypass transistors to the gate terminal of each of the one or more bypass transistors so that current flows across the one or more bypass transistors, wherein the voltage sufficient to turn on the one or more bypass transistors corresponds to a power threshold used to control the one or more bypass transistors to define the bypass current path.

[0110] Clause 10: A driver circuit as described in any of clauses 1 to 9, wherein an error condition present in the power delivery circuit causes a current avalanche, and wherein the current avalanche causes the driver circuit to receive power from the bypass current path that exceeds a power threshold used to control the one or more bypass transistors to define the bypass current path.

[0111] Clause 11: A driver circuit as described in any one of clauses 1 to 9, wherein the load comprises an electric motor of a vehicle.

[0112] Clause 12: The driver circuit of clause 11, wherein the power delivery circuit comprises an H-bridge circuit configured as a stepper inverter circuit for controlling an electric motor of the vehicle.

[0113] Item 13: A method for controlling one or more bypass transistors, the method comprising: supplying power from a group of battery cells to a driver circuit via a primary supply input connector of a driver circuit, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit; receiving information indicating whether an error condition exists in the power delivery circuit by the driver circuit; controlling one or more bypass transistors by the driver circuit to define a bypass current path for bypassing the power delivery circuit based on the error condition existing in the power delivery circuit; and receiving power from the bypass current path via a secondary supply input connector in one or more secondary supply input connectors by the driver circuit, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0114] Clause 14: The method according to clause 13 further includes: when the error condition exists in the power delivery circuit, the driver circuit receives power from the group of battery cells through the primary supply input connection, wherein the power from the group of battery cells does not exceed a power threshold used to control the one or more bypass transistors to define the bypass current path.

[0115] Clause 15: A method according to any one of clauses 13 to 14, wherein the power threshold is a first power threshold, and wherein the method further comprises: the driver circuit controlling the one or more bypass transistors to not define the bypass current path based on an error condition not existing in the power delivery circuit; and the driver circuit receiving power exceeding a second power threshold for controlling the one or more bypass transistors to not define the bypass current path from the group of battery cells via the primary supply input connection.

[0116] Clause 16: The method according to any one of clauses 13 to 15 further includes: when an error condition occurs at a first node of the power delivery circuit, power is supplied to the driver circuit from a first node of the bypass current path by a first secondary supply input connector among the one or more secondary supply input connectors; when an error condition occurs at a second node of the power delivery circuit, power is supplied to the driver circuit from a second node of the bypass current path by a second secondary supply input connector.

[0117] Clause 17: The method of clause 16, wherein the power delivery circuit comprises two or more power transistors, wherein a first node of the power delivery circuit comprises a first power transistor of the two or more power transistors, and wherein a second node of the power delivery circuit comprises a second power transistor of the two or more power transistors.

[0118] Clause 18: A method according to any one of clauses 13 to 17, wherein the power delivery circuit comprises an H-bridge circuit, the H-bridge circuit comprising a first power transistor, a second power transistor, a third power transistor and a fourth power transistor, wherein the error condition comprises a failure of one or more of the first power transistor, the second power transistor, the third power transistor and the fourth power transistor.

[0119] Item 19: A method according to Item 18, wherein controlling the one or more bypass transistors to define a bypass current path includes: applying a voltage sufficient to turn on the one or more bypass transistors to the gate terminal of each of the one or more bypass transistors by the driver circuit so that current flows across the one or more bypass transistors, wherein the voltage sufficient to turn on the one or more bypass transistors corresponds to a power threshold used to control the one or more bypass transistors to define the bypass current path.

[0120] Clause 20: A system comprising: a group of battery cells; a power delivery circuit including four power transistors arranged in an H-bridge, wherein the power delivery circuit is configured to deliver power from the group of battery cells to a load; an H-bridge driver circuit configured to control the four power transistors arranged in the H-bridge; one or more bypass transistors; and a bypass driver circuit configured to control the one or more bypass transistors. The bypass driver circuit includes: a primary supply input connection configured to supply power from the group of battery cells to the bypass driver circuit; and one or more secondary supply input connections. The bypass driver circuit is configured to: receive information indicating whether an error condition exists in the power delivery circuit; based on the error condition existing in the power delivery circuit, control the one or more bypass transistors to define a bypass current path for bypassing the power delivery circuit; and receive power from the bypass current path via a secondary supply input connection of the one or more secondary supply input connections, wherein the power from the bypass current path exceeds a power threshold for controlling the one or more bypass transistors to define the bypass current path.

[0121] Clause 21: The system of clause 20, wherein the system further comprises a load, and wherein the four power transistors arranged in the H-bridge are configured as a stepper inverter circuit for controlling an electric motor of a vehicle.

[0122] Clause 22: A driver circuit configured to control one or more bypass transistors, the driver circuit comprising: one or more supply connections configured to supply power from a group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit. The driver circuit is configured to: receive information indicating whether an error condition exists in the group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via the one or more supply connections; based on the error condition existing in the group of battery cells, activate the one or more bypass transistors to define a bypass current path for bypassing the power delivery circuit; and receive power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows through the secondary driver circuit supply path without reaching the error condition.

[0123] Clause 23: A driver circuit according to clause 22, wherein the one or more supply connectors include: a first supply connector connected to a first node located on one side of the group of battery cells; and a second supply connector connected to a second node located within the group of battery cells, wherein the one or more battery cells of the group of battery cells include each battery cell of the group of battery cells between the first node and the second node, and wherein the driver circuit is configured to receive power from a secondary driver circuit supply path via the first supply connector and the second supply connector.

[0124] Clause 24: A driver circuit as described in clause 23, wherein the driver circuit is configured to receive power from the secondary driver circuit supply path when current flows from the second node through the one or more battery cells to the first node, from the first node to the first supply connection, from the first supply connection through the driver circuit to the second supply connection, and from the second supply connection to the second node.

[0125] Clause 25: A driver circuit according to any one of clauses 23 to 24, wherein the driver circuit further comprises: a first diode, wherein the anode of the first diode is connected to the first supply connection; a second diode, wherein the anode of the second diode is connected to the second supply connection; an internal supply unit, connected to the cathode of the first diode and the cathode of the second diode; and a third diode, wherein the anode of the third diode is connected to the internal supply unit and the cathode of the third diode is connected to a third node between the second supply connection and the second diode.

[0126] Clause 26: A driver circuit according to clause 25, wherein the driver circuit is configured to receive power from the secondary driver circuit supply path when current flows from the first supply connection to the first diode, from the internal supply unit to the third diode, and from the third diode to the second supply connection.

[0127] Clause 27: A driver circuit according to any one of clauses 22 to 26, wherein the one or more supply connectors include: a supply connector connected to a node located on a first side of the group of battery cells, wherein the primary driver circuit supply path spans the group of battery cells between the first side of the group of battery cells and the second side of the group of battery cells, wherein the driver circuit is further configured to: disable one or more bypass transistors based on an error condition not present in one or more battery cells; and receive power from the primary driver circuit supply path via the supply connector.

[0128] Clause 28: A driver circuit as described in clause 27, wherein the driver circuit is configured to receive power from the primary driver circuit supply path when current flows across the second side of the group of battery cells to the first side, flows across the node from the first side to the power delivery circuit, flows from the power delivery circuit to the load, flows from the load to the power delivery circuit, and flows from the power delivery circuit to the second side of the group of battery cells.

[0129] Clause 29: A driver circuit as described in any of clauses 22 to 28, wherein the one or more bypass transistors include a first bypass transistor and a second bypass transistor placed in an anti-series arrangement such that a body diode of the first bypass transistor and a body diode of the second bypass transistor face in opposite directions.

[0130] Clause 30: A driver circuit according to any one of clauses 22 to 29, wherein in order to activate one or more bypass transistors to define a bypass current path, the driver circuit is configured to: apply a voltage sufficient to activate the one or more bypass transistors to the gate terminal of each bypass transistor of the one or more bypass transistors so that current flows across the one or more bypass transistors, wherein the power received from the secondary driver circuit supply path exceeds a power threshold for activating the one or more bypass transistors.

[0131] Clause 31: A driver circuit as described in any of clauses 22 to 30, wherein the load comprises one or more electrical systems of a vehicle.

[0132] Item 32: A method comprising: receiving, by a driver circuit including one or more supply connections configured to supply power from a group of battery cells, information indicating whether an error condition exists in a group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit; activating, by the driver circuit based on the error condition existing in the group of battery cells, one or more bypass transistors to define a bypass current path for bypassing the power delivery circuit; and receiving, by the driver circuit via the one or more supply connections, power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells, wherein current flows across the secondary driver circuit supply path without reaching the error condition.

[0133] Clause 33: A method according to clause 32, wherein the one or more supply connectors include: a first supply connector connected to a first node located on one side of a group of battery cells; and a second supply connector connected to a second node located within the group of battery cells, wherein one or more battery cells of the group of battery cells include each battery cell of the group of battery cells between the first node and the second node, and wherein the method includes receiving power from a secondary driver circuit supply path by the driver circuit via the first supply connector and the second supply connector.

[0134] Clause 34: A method according to clause 33, wherein the method includes: receiving power from the secondary driver circuit supply path when current flows from the second node through one or more battery cells to the first node, from the first node to the first supply connection, from the first supply connection through the driver circuit to the second supply connection, and from the second supply connection to the second node.

[0135] Clause 35: A method according to any one of clauses 33 to 34, wherein the driver circuit further comprises: a first diode, wherein the anode of the first diode is connected to the first supply connection; a second diode, wherein the anode of the second diode is connected to the second supply connection; an internal supply unit, connected to the cathode of the first diode and the cathode of the second diode; and a third diode, wherein the anode of the third diode is connected to the internal supply unit and the cathode of the third diode is connected to a third node between the second supply connection and the second diode.

[0136] Clause 36: The method of clause 35, wherein the method further comprises: receiving power by the driver circuit from the secondary driver circuit supply path when current flows from the first supply connection to the first diode, from the internal supply unit to the third diode, and from the third diode to the second supply connection.

[0137] Clause 37: A method according to any one of clauses 32 to 36, wherein the one or more supply connectors include a supply connector connected to a node located on a first side of the group of battery cells, wherein the primary driver circuit supply path spans the group of battery cells between the first side of the group of battery cells and the second side of the group of battery cells, and wherein the method further includes: deactivating one or more bypass transistors by the driver circuit based on the absence of an error condition in one or more cells; and receiving power from the primary driver circuit supply path by the driver circuit via the supply connector.

[0138] Clause 38: A method according to clause 37, wherein the method also includes receiving power from the primary driver circuit supply path by the driver circuit when current flows from the second side to the first side across a group of battery cells, from the first side to the power delivery circuit of the node, from the power delivery circuit to the load, from the load to the power delivery circuit, and from the power delivery circuit to the second side of the group of battery cells.

[0139] Clause 39: A method according to any one of clauses 32 to 38, wherein activating one or more bypass transistors to define a bypass current path includes: applying a voltage sufficient to activate the one or more bypass transistors to the gate terminal of each bypass transistor of the one or more bypass transistors by a driver circuit so that current flows across the one or more bypass transistors, wherein power received from a secondary driver circuit supply path exceeds a power threshold for activating the one or more bypass transistors.

[0140] Clause 40: The method of any one of clauses 32 to 39, wherein the load comprises an electric motor of a vehicle.

[0141] Clause 41: A system comprising: a group of battery cells; a power delivery circuit including four power transistors arranged in an H-bridge, wherein the power delivery circuit is configured to deliver power from the group of battery cells to a load; an H-bridge driver circuit configured to control the four power transistors arranged in the H-bridge; one or more bypass transistors; and a bypass driver circuit configured to control the one or more bypass transistors, the bypass driver circuit including one or more supply connections configured to supply power from the group of battery cells. The bypass driver circuit is configured to: receive information indicating whether an error condition exists in the group of battery cells, the error condition preventing the bypass driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via the one or more supply connections; based on the error condition existing in the group of battery cells, activate the one or more bypass transistors to define a bypass current path to bypass the power delivery circuit; and receive power from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows across the secondary driver circuit supply path without reaching the error condition.

[0142] The techniques described in this disclosure may be implemented at least in part in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented in one or more processors (including one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuit devices, and any combination of such components). The term "processor" or "processing circuit device" may generally refer to the aforementioned logic circuits, alone or in combination with other logic circuit devices, or any other equivalent circuit devices. A control unit including hardware may also perform one or more techniques of the present disclosure.

[0143] Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various operations and functions described in this disclosure. In addition, any of the described units, modules, or components may be implemented together or separately as discrete but interoperable logic devices. Depicting different features as modules or units is intended to emphasize different feature aspects and does not necessarily mean that such modules or units must be implemented by separate hardware or software components. Instead, the functions associated with one or more modules or units may be performed by separate hardware or software components, or integrated in common or separate hardware or software components.

[0144] The techniques described in the present disclosure may also be implemented or encoded in a computer-readable medium containing instructions, such as a computer-readable storage medium. For example, when the instructions are executed, the instructions embedded or encoded in the computer-readable storage medium may cause a programmable processor or other processor to perform the method. The computer-readable storage medium may include RAM, ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), EEPROM, flash memory, hard disk, compact disk read-only memory (CD-ROM), floppy disk, tape, magnetic medium, optical medium, or other computer-readable medium.

[0145] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A driver circuit configured to control one or more bypass power transistors, the driver circuit comprising: one or more supply connections configured to supply power from a group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit, The driver circuit is configured as follows: receiving information indicating whether an error condition exists in the group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via the one or more supply connections; activating the one or more bypass power transistors to define a bypass current path for bypassing the power delivery circuit based on the error condition existing in the group of battery cells; as well as Power is received from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows through the secondary driver circuit supply path without reaching the fault condition.

2. The driver circuit of claim 1 , wherein the one or more supply connections comprise: a first supply connector connected to a first node located on one side of the group of battery cells; as well as a second supply connection connected to a second node within the group of battery cells, wherein the one or more battery cells of the group of battery cells include each battery cell of the group of battery cells between the first node and the second node, and Wherein the driver circuit is configured to receive power from the secondary driver circuit supply path via the first supply connection and the second supply connection.

3. A driver circuit according to claim 2, wherein the driver circuit is configured to receive the power from the secondary driver circuit supply path when current flows from the second node through the one or more battery cells to the first node, from the first node to the first supply connection, from the first supply connection through the driver circuit to the second supply connection, and from the second supply connection to the second node.

4. The driver circuit according to claim 2, wherein the driver circuit further comprises: a first diode, wherein an anode of the first diode is connected to the first supply connection; a second diode, wherein an anode of the second diode is connected to the second supply connection; an internal supply unit connected to a cathode of the first diode and a cathode of the second diode; as well as A third diode, wherein an anode of the third diode is connected to the internal supply unit and a cathode of the third diode is connected to a third node between the second supply connection and the second diode.

5. A driver circuit according to claim 4, wherein the driver circuit is configured to receive power from the secondary driver circuit supply path when current flows from the first supply connection to the first diode, from the internal supply unit to the third diode, and from the third diode to the second supply connection.

6. The driver circuit of claim 1 , wherein the one or more supply connections comprise: a supply connection connected to a node on a first side of the group of battery cells, wherein the primary driver circuit supply path spans the group of battery cells between the first side of the group of battery cells and a second side of the group of battery cells, The driver circuit is further configured to: deactivating the one or more bypass power transistors based on the error condition not being present in the one or more battery cells; as well as The power is received from the primary driver circuit supply path via the supply connection.

7. A driver circuit according to claim 6, wherein the driver circuit is configured to receive the power from the primary driver circuit supply path when current flows from the second side to the first side across the group of battery cells, flows from the first side to the power delivery circuit across the node, flows from the power delivery circuit to the load, flows from the load to the power delivery circuit, and flows from the power delivery circuit to the second side of the group of battery cells.

8. The driver circuit of claim 1 , wherein the one or more bypass power transistors include a first bypass power transistor and a second bypass power transistor placed in an anti-series arrangement such that a body diode of the first bypass power transistor and a body diode of the second bypass power transistor face in opposite directions.

9. The driver circuit of claim 1 , wherein to activate the one or more bypass power transistors to define a bypass current path, the driver circuit is configured to: applying a voltage to a gate terminal of each of the one or more bypass power transistors sufficient to activate the one or more bypass power transistors so that current flows across the one or more bypass power transistors, Wherein the power received from the secondary driver circuit supply path exceeds a power threshold for activating the one or more bypass power transistors.

10. The driver circuit of claim 1, wherein the load comprises one or more electrical systems of a vehicle.

11. A method comprising: receiving, by a driver circuit including one or more supply connections configured to supply power from a group of battery cells, information indicating whether an error condition exists in a group of battery cells, the error condition preventing the driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells, wherein the group of battery cells is configured to supply power to a load via a power delivery circuit; activating, by the driver circuit, the one or more bypass power transistors based on the error condition present in the group of battery cells to define a bypass current path for bypassing the power delivery circuit; as well as Power is received by the driver circuit via the one or more supply connections from a secondary driver circuit supply path across one or more battery cells in the group of battery cells, wherein current flows across the secondary driver circuit supply path without reaching the fault condition.

12. The method of claim 11, wherein the one or more supply connections comprise: a first supply connector connected to a first node located on one side of the group of battery cells; as well as a second supply connection connected to a second node within the group of battery cells, wherein the one or more battery cells of the group of battery cells include each battery cell of the group of battery cells between the first node and the second node, and Wherein the method comprises receiving, by the driver circuit, power from the secondary driver circuit supply path via the first supply connection and the second supply connection.

13. The method according to claim 12, wherein the method comprises: Power is received from the secondary driver circuit supply path when current flows from the second node through the one or more battery cells to the first node, from the first node to the first supply connection, from the first supply connection through the driver circuit to the second supply connection, and from the second supply connection to the second node.

14. The method of claim 12, wherein the driver circuit further comprises: a first diode, wherein an anode of the first diode is connected to the first supply connection; a second diode, wherein an anode of the second diode is connected to the second supply connection; an internal supply unit connected to a cathode of the first diode and a cathode of the second diode; as well as A third diode, wherein an anode of the third diode is connected to the internal supply unit and a cathode of the third diode is connected to a third node between the second supply connection and the second diode.

15. The method according to claim 14, wherein the method further comprises: Power is received by the driver circuit from the secondary driver circuit supply path when current flows from the first supply connection to the first diode, from the internal supply unit to the third diode, and from the third diode to the second supply connection.

16. The method of claim 11, wherein the one or more supply connections include a supply connection connected to a node located on a first side of the group of battery cells, wherein the primary driver circuit supply path spans the group of battery cells between the first side of the group of battery cells and the second side of the group of battery cells, and The method further comprises: deactivating, by the driver circuit, the one or more bypass power transistors based on the absence of an error condition in the one or more battery cells; as well as Power is received by a driver circuit from the primary driver circuit supply path via the supply connection.

17. The method of claim 16, wherein the method further comprises receiving power from the primary driver circuit supply path by the driver circuit when current flows from the second side to the first side across the group of battery cells, from the first side to a power delivery circuit of the node, from the power delivery circuit to the load, from the load to the power delivery circuit, and from the power delivery circuit to the second side of the group of battery cells.

18. The method of claim 11, wherein activating the one or more bypass power transistors to define the bypass current path comprises: applying, by the driver circuit, to a gate terminal of each of the one or more bypass power transistors a voltage sufficient to activate the one or more bypass power transistors so that current flows across the one or more bypass power transistors, Wherein power received from the secondary driver circuit supply path exceeds a power threshold for activating the one or more bypass power transistors.

19. The method of claim 11, wherein the load comprises an electric motor of a vehicle.

20. A system comprising: A set of battery cells; a power delivery circuit comprising four power transistors arranged in an H-bridge, wherein the power delivery circuit is configured to deliver power from the group of battery cells to a load; an H-bridge driver circuit configured to control the four power transistors arranged in the H-bridge; one or more bypass power transistors; as well as a bypass driver circuit configured to control the one or more bypass power transistors, the bypass driver circuit comprising one or more supply connections configured to supply power from the group of battery cells; Wherein the bypass driver circuit is configured as: receiving information indicating whether an error condition exists in the group of battery cells, the error condition preventing the bypass driver circuit from receiving power from a primary driver circuit supply path across the group of battery cells via one or more supply connections; activating the one or more bypass power transistors to define a bypass current path for bypassing the power delivery circuit based on an error condition existing in the group of battery cells; as well as Power is received from a secondary driver circuit supply path across one or more battery cells in the group of battery cells via the one or more supply connections, wherein current flows across the secondary driver circuit supply path without reaching the fault condition.

Images