A Hall signal amplifying circuit and a Hall sensing device

Abstract

The invention discloses a Hall signal amplifying circuit and a Hall sensing device, which relate to the technical field of Hall signal amplification, and aim to solve the problem in the related art that the Hall sensing voltage amplifying circuit cannot completely eliminate the offset voltage of the operational amplifier. The invention discloses a Hall signal amplifying circuit and a Hall sensing device, which relate to the technical field of Hall signal amplification, and aim to solve the problem that the Hall sensing voltage amplifying circuit in the related art cannot completely eliminate the offset voltage of the operational amplifier. The invention discloses a Hall signal amplifying circuit, which is connected to the Hall sensor, and comprises a reference module, an offset calibration module and an integral amplifying module, wherein the reference module can clamp the DC level of the first output end of the Hall sensor at 1 / 2 of the power supply voltage; the offset calibration module can compensate for the offset voltage of the integral operational amplifier module and the offset voltage of the Hall sensor itself; the integral amplifying module can amplify the compensated Hall sensing signal and output the final Hall sensing signal; and also comprises a Hall sensing device comprising a Hall signal amplifying circuit; the Hall signal amplifying circuit and the Hall sensing device can eliminate the offset of the Hall signal.

Description

Technical Field

[0001] The present invention relates to the technical field of Hall signal amplification, and in particular to a Hall signal amplification circuit and a Hall sensing device. Background Art

[0002] The Hall sensor is a magnetoelectric sensor based on the Hall effect. It captures the magnetic field generated by the current and converts it into an output voltage. It can measure physical quantities such as position, speed, angle and current. It has been widely used in the automotive, automation industry and new energy fields. Generally speaking, the induced voltage generated by the Hall sensor is proportional to the current it detects. Since the Hall sensor usually uses silicon-based devices, the Hall induced voltage generated is relatively small, and an amplifier circuit is needed to amplify the induced voltage for use by the next level system.

[0003] The Hall-effect voltage amplifier circuit of the related art is as follows Figure 4 As shown, there are two identical operational amplifiers. Although this symmetrical structure can reduce the impact of the operational amplifier offset voltage on the accuracy of the final sensing output voltage, it cannot completely eliminate the offset voltage of the operational amplifier. In addition, the offset of the Hall sensor itself will affect the sensing voltage output by the Hall sensor, and the offset is an uncontrollable quantity. When the Hall signal increment is relatively small, the offset error has a greater impact on the result and may even cause logical errors. Summary of the invention

[0004] The present invention solves the problem in the related art that the Hall sensing voltage amplifier circuit cannot completely eliminate the offset voltage of the operational amplifier, and proposes a Hall signal amplifier circuit and a Hall sensing device, which can eliminate the offset of the Hall signal.

[0005] In order to achieve the above object, the present invention adopts the following technical solution: a Hall signal amplifying circuit connected to the Hall sensor, comprising:

[0006] A reference module, whose control end is connected to the first output end of the Hall sensor, and the reference module can clamp the DC level of the first output end of the Hall sensor to 1 / 2 of the power supply voltage;

[0007] An offset calibration module, whose output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module, and the offset calibration module can compensate for the offset voltage of the integral operational amplifier module and the offset voltage of the Hall sensor itself;

[0008] The second input end of the integral amplifier module is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

[0009] The Hall signal amplification circuit of the present technical solution mainly includes a reference module, an offset calibration module and an integral amplifier module. The weak Hall sensing signal initially output by the initial Hall sensor is sent to the integral amplifier module after passing through the offset calibration module and the reference module. The weak original Hall sensing signal can be accurately amplified, and the amplification factor can be adjusted over a wide range, which can eliminate the offset voltage of the Hall sensor and the integral operational amplifier module.

[0010] The present invention is further configured as follows: the reference module includes a first operational amplifier and a second operational amplifier, the output end of the first operational amplifier is connected to the same-direction input end of the second operational amplifier, the output end of the second operational amplifier is connected to the power supply end of the Hall sensor, and the reverse input end of the second operational amplifier is connected to the first output end of the Hall sensor; the output end of the second operational amplifier serves as the output end of the reference module, and the reverse input end of the second operational amplifier serves as the control end of the reference module.

[0011] In this technical solution, the output end and the control end of the reference module are both connected to the Hall sensor.

[0012] The present invention is further configured as follows: the same-direction input terminal of the first operational amplifier is respectively connected to one end of the first resistor and one end of the second resistor, the reverse input terminal of the first operational amplifier is connected to its output terminal, the other end of the first resistor is connected to a power supply, which serves as the power supply terminal of the reference module, and the other end of the second resistor is grounded, which serves as the ground terminal of the reference module.

[0013] In this technical solution, the resistance values ​​of the first resistor and the second resistor are the same.

[0014] The present invention is further configured as follows: the integral amplification module includes a third operational amplifier, the same-direction input terminal of the third operational amplifier is connected to the second output terminal of the Hall sensor, the reverse input terminal of the third operational amplifier is connected to one end of a fifth resistor, and the other end of the fifth resistor is connected to the reverse input terminal of the second operational amplifier and the first output terminal of the Hall sensor; the reverse input terminal of the third operational amplifier serves as the first input terminal of the integral amplification module, the positive input terminal of the third operational amplifier serves as the second input terminal of the integral amplification module, and the output terminal of the third operational amplifier serves as the output terminal of the integral amplification module.

[0015] In the technical solution, one end of the fifth resistor is connected to the first input end of the integral amplifier module, and the other end thereof is respectively connected to the control end of the reference module and the first output end of the Hall sensor.

[0016] The present invention is further configured as follows: the reverse input end of the third operational amplifier is respectively connected to one end of the third resistor and one end of the capacitor, the third resistor and the capacitor are connected in parallel, and the other end of the third resistor and the other end of the capacitor are both connected to the output end of the third operational amplifier.

[0017] In this technical solution, the type of the third resistor is consistent with that of the first resistor and the second resistor.

[0018] The present invention is further configured as follows: the offset calibration module includes a digital-to-analog converter, one end of the digital-to-analog converter is connected to one end of a fourth resistor, the other end of the fourth resistor is connected to the reverse input end of the third operational amplifier, and the output end of the digital-to-analog converter serves as the output end of the offset calibration module.

[0019] In the technical solution, the offset voltage is compensated specifically by a digital-to-analog converter.

[0020] The present invention is further configured as follows: the offset voltage of the third operational amplifier and the offset voltage of the Hall sensor are cumulatively expressed as an offset voltage V OS , the DAC has an offset voltage V OS The calibration range is:

[0021] ,

[0022] Among them, A C is the Hall signal amplification factor, AVDD is the power supply voltage, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and q is the number of bits of the digital-to-analog converter.

[0023] In this technical solution, the offset calibration range changes with the change of the Hall signal amplification factor and the power supply voltage.

[0024] The present invention is further configured as follows: the Hall signal amplification factor A C Specifically:

[0025] ,

[0026] Wherein, R5 is the resistance value of the fifth resistor.

[0027] The present invention is further configured as follows: the offset voltage V OS Superimposed on the inverting input terminal of the third operational amplifier OPA1.

[0028] In this technical solution, since the third resistor and the fourth resistor are both fixed value resistors, the magnitude of the Hall signal amplification factor depends on The size of the value.

[0029] The present invention is further configured such that: the fifth resistor is an editable resistor.

[0030] A Hall sensing device comprises the above-mentioned Hall signal amplifying circuit and a Hall sensor, wherein the Hall signal amplifying circuit comprises:

[0031] A reference module, whose control end is connected to the first output end of the Hall sensor, and the reference module can clamp the DC level of the first output end of the Hall sensor to 1 / 2 of the power supply voltage;

[0032] An offset calibration module, whose output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module, and the offset calibration module can compensate for the offset voltage of the integral amplifier module and the offset voltage of the Hall sensor itself;

[0033] The second input end of the integral amplifier module is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

[0034] The technical solution also relates to a Hall sensing device, which is provided with the above-mentioned Hall signal amplifying circuit and Hall sensor, and also plays the role of eliminating Hall signal imbalance.

[0035] The present invention can bring the following beneficial effects:

[0036] The present invention relates to a Hall signal amplifying circuit, which adopts a reference module to fix the final Hall induction signal output common mode level to 1 / 2*AVDD, and can provide power for the Hall element at the same time, and uses an offset calibration module to adjust the influence of the offset voltage on the output common mode level and the interference of the offset voltage on the output Hall induction signal after being amplified, and the adjustment range of the offset voltage is large and the adjustment accuracy is high; and the amplification of the weak induction voltage is realized by the integral amplification module. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram of a Hall signal amplification circuit of the present application.

[0038] Figure 2 It is a schematic diagram of a reference module of a Hall signal amplification circuit of the present application.

[0039] Figure 3 It is a schematic diagram of an integral amplification module of a Hall signal amplification circuit of the present application.

[0040] Figure 4 It is a schematic diagram of a Hall-induced voltage amplifier circuit of the related art. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific implementation method described herein is only an optimal embodiment of the present invention, which is only used to explain the present invention and does not limit the scope of protection of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0042] refer to Figure 4 The common Hall-induced voltage amplifier circuit in the related art mainly includes two identical operational amplifiers and a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8.

[0043] More specifically, the non-inverting input terminal of the first operational amplifier is connected to the second output terminal of the Hall device, the reverse input terminal of the first operational amplifier is respectively connected to one end of the sixth resistor R6 and one end of the seventh resistor R7, the other end of the sixth resistor R6 is connected to the output terminal of the first operational amplifier, the other end of the seventh resistor R7 is respectively connected to the reverse input terminal of the second operational amplifier and one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected to the output terminal of the second operational amplifier, and the non-inverting input terminal of the second operational amplifier is connected to the first output terminal of the Hall device. For more specific content of this common Hall induction voltage amplifier circuit, please refer to Figure 4 .

[0044] Although this symmetrical structure can reduce the impact of the op amp offset voltage on the final induced output voltage accuracy to a certain extent, it cannot completely eliminate the op amp offset voltage. In addition, the Hall sensor itself is offset (the static output voltage is not at the midpoint potential under zero magnetic field conditions), which will affect the final induced voltage output by the Hall sensor. The offset is an uncontrollable quantity. When the Hall signal increment is relatively small, the impact of the offset error on the result will be even more significant and may even cause logical errors.

[0045] Example 1

[0046] In view of the problems existing in the prior art, this embodiment discloses a Hall signal amplification circuit. Figure 1 The amplifier circuit is connected to the Hall sensor and mainly includes a reference module, an offset calibration module and an integral amplifier module.

[0047] For the reference module, a control terminal thereof is connected to the first output terminal of the Hall sensor, and the reference module can clamp the DC level of the first output terminal of the Hall sensor to 1 / 2 of the power supply voltage.

[0048] In addition, an input terminal of the reference module is connected to a power supply AVDD, and a ground terminal of the reference module is grounded.

[0049] For the offset calibration module, its output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module. The offset calibration module can compensate for the offset voltage of the integral operational amplifier module and the offset voltage of the Hall sensor.

[0050] For the integral amplifier module, the second input end thereof is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

[0051] In this technical solution, the weak Hall sensing signal initially output by the initial Hall sensor is sent to the integral amplifier module after passing through the offset calibration module and the reference module. The weak original Hall sensing signal can be accurately amplified, and the amplification factor can be adjusted over a wide range. The offset voltage of the Hall sensor and the third operational amplifier can be eliminated. At the same time, power can be provided for the Hall sensor, reducing the peripheral power supply configuration, and can be adapted to most Hall sensors.

[0052] refer to Figure 1 and Figure 2 The reference module mainly includes a first operational amplifier OPA1 and a second operational amplifier OPA2. The output end of the first operational amplifier OPA1 is connected to the same-direction input end of the second operational amplifier OPA2, the output end of the second operational amplifier OPA2 is connected to the power supply end of the Hall sensor, and the reverse input end of the second operational amplifier OPA2 is connected to the first output end of the Hall sensor; the output end of the second operational amplifier OPA2 serves as the output end of the reference module, and the reverse input end of the second operational amplifier OPA2 serves as the control end of the reference module.

[0053] Furthermore, the same-direction input terminal of the first operational amplifier OPA1 is respectively connected to one end of the first resistor R1 and one end of the second resistor R2, the reverse input terminal of the first operational amplifier OPA1 is connected to its output terminal, the other end of the first resistor R1 is connected to the power supply AVDD, and the other end of the first resistor R1 is used as the power supply terminal of the reference module, the other end of the second resistor R2 is grounded, and the other end of the second resistor R2 is used as the ground terminal of the reference module.

[0054] Furthermore, the reference module mainly includes a first resistor R1, a second resistor R2, a first operational amplifier OPA1 and a second operational amplifier OPA2, wherein the first resistor R1 and the second resistor R2 have the same resistance value, one end of the first resistor R1 is connected to the power supply AVDD, the other end of the resistor R1 is simultaneously connected to one end of the resistor R2 and the same-direction input end of the first operational amplifier OPA1, the other end of the second resistor R2 is grounded, the reverse input end of the first operational amplifier OPA1 is connected to its output end, the reverse input end of the second operational amplifier OPA2 is connected to the first output end of the Hall sensor, and the output end of the second operational amplifier OPA2 is connected to the power supply end of the Hall sensor.

[0055] refer to Figure 1 and Figure 3 The integral amplification module includes a third operational amplifier OPA3, the same-direction input terminal of the third operational amplifier OPA3 is connected to the second output terminal of the Hall sensor, the reverse input terminal of the third operational amplifier OPA3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the reverse input terminal of the second operational amplifier OPA3 and the first output terminal of the Hall sensor; the reverse input terminal of the third operational amplifier OPA3 serves as the first input terminal of the integral amplification module, the positive input terminal of the third operational amplifier OPA3 serves as the second input terminal of the integral amplification module, and the output terminal of the third operational amplifier OPA3 serves as the output terminal of the integral amplification module.

[0056] The reverse input terminal of the third operational amplifier OPA3 is respectively connected to one end of the third resistor R3 and one end of the capacitor, wherein the third resistor R3 and the capacitor are connected in parallel, and the other end of the third resistor R3 and the other end of the capacitor are both connected to the output terminal of the third operational amplifier OPA3.

[0057] The offset calibration module includes a digital-to-analog converter DAC, one end of the digital-to-analog converter DAC is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the reverse input end of the third operational amplifier OPA3, and the output end of the digital-to-analog converter DAC serves as the output end of the offset calibration module.

[0058] Furthermore, the fifth resistor R5 is an editable resistor, and the size of the fifth resistor R5 can determine the size of the Hall signal amplification factor.

[0059] Furthermore, the integral amplifier module mainly includes a capacitor, a third resistor R3 and a third operational amplifier OPA3, and the fourth resistor R4 is arranged between the offset calibration module and the integral amplifier module, one end of the fifth resistor R5 is connected to the integral amplifier module, and the other end thereof is respectively connected to the reference module and the Hall sensor.

[0060] Furthermore, one end of the fourth resistor R4 is connected to the output end of the digital-to-analog converter DAC, the other end of the fourth resistor R4 is connected to the reverse input end of the third operational amplifier OPA3, one end of the third resistor R3 is connected to the reverse input end of the third operational amplifier OPA3, the other end of the third resistor R3 is connected to the output end of the third operational amplifier OPA3, one end of the capacitor is connected to the reverse input end of the third operational amplifier OPA3, the other end of the capacitor is connected to the output end of the third operational amplifier OPA3, one end of the fifth resistor R5 is connected to the first output end of the Hall sensor, the other end of the fifth resistor R5 is connected to the reverse input end of the third operational amplifier OPA3, and the output end of the third operational amplifier OPA3 is connected to the next level Hall signal processing circuit.

[0061] In this embodiment, the first resistor R1 , the second resistor R2 , the third resistor R3 , the fourth resistor R4 , and the fifth resistor R5 are of the same type.

[0062] Specifically, the offset voltage of the third operational amplifier and the offset voltage of the Hall sensor are accumulated to represent the offset voltage V OS , the digital-to-analog converter DAC has an offset voltage V OS The calibration range is expressed as:

[0063] ,

[0064] In the above formula, A C is the Hall signal amplification factor, AVDD is the power supply voltage, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and q is the number of bits of the digital-to-analog converter. The offset calibration range of the digital-to-analog converter DAC changes with the change of the Hall signal amplification factor and the power supply voltage.

[0065] During the process of losing regulation, the offset voltage V OS Superimposed on the inverting input terminal of the third operational amplifier OPA1.

[0066] Hall signal amplification factor A C Specifically expressed as:

[0067] ,

[0068] In the above formula, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and R5 is the resistance value of the fifth resistor.

[0069] Example 2

[0070] Based on Example 1, this embodiment further discloses a Hall sensing device, which mainly includes a Hall signal amplifying circuit and a Hall sensor. The Hall signal amplifying circuit is connected to the Hall sensor, and the amplifying circuit mainly includes a reference module, an offset calibration module and an integral amplifying module.

[0071] For the reference module, a control terminal thereof is connected to the first output terminal of the Hall sensor, and the reference module can clamp the DC level of the first output terminal of the Hall sensor to 1 / 2 of the power supply voltage.

[0072] In addition, an input terminal of the reference module is connected to a power supply AVDD, and a ground terminal of the reference module is grounded.

[0073] For the offset calibration module, its output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module. The offset calibration module can compensate for the offset voltage of the integral operational amplifier module and the offset voltage of the Hall sensor.

[0074] For the integral amplifier module, the second input end thereof is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

[0075] In this technical solution, the weak Hall sensing signal initially output by the initial Hall sensor is sent to the integral amplifier module after passing through the offset calibration module and the reference module. The weak original Hall sensing signal can be accurately amplified, and the amplification factor can be adjusted over a wide range. The offset voltage of the Hall sensor and the third operational amplifier can be eliminated. At the same time, power can be provided for the Hall sensor, reducing the peripheral power supply configuration, and can be adapted to most Hall sensors.

[0076] refer to Figure 1 and Figure 2 The reference module mainly includes a first operational amplifier OPA1 and a second operational amplifier OPA2. The output end of the first operational amplifier OPA1 is connected to the same-direction input end of the second operational amplifier OPA2, the output end of the second operational amplifier OPA2 is connected to the power supply end of the Hall sensor, and the reverse input end of the second operational amplifier OPA2 is connected to the first output end of the Hall sensor; the output end of the second operational amplifier OPA2 serves as the output end of the reference module, and the reverse input end of the second operational amplifier OPA2 serves as the control end of the reference module.

[0077] Furthermore, the same-direction input terminal of the first operational amplifier OPA1 is respectively connected to one end of the first resistor R1 and one end of the second resistor R2, the reverse input terminal of the first operational amplifier OPA1 is connected to its output terminal, the other end of the first resistor R1 is connected to the power supply AVDD, and the other end of the first resistor R1 is used as the power supply terminal of the reference module, the other end of the second resistor R2 is grounded, and the other end of the second resistor R2 is used as the ground terminal of the reference module.

[0078] Furthermore, the reference module mainly includes a first resistor R1, a second resistor R2, a first operational amplifier OPA1 and a second operational amplifier OPA2, wherein the first resistor R1 and the second resistor R2 have the same resistance value, one end of the first resistor R1 is connected to the power supply AVDD, the other end of the resistor R1 is simultaneously connected to one end of the resistor R2 and the same-direction input end of the first operational amplifier OPA1, the other end of the second resistor R2 is grounded, the reverse input end of the first operational amplifier OPA1 is connected to its output end, the reverse input end of the second operational amplifier OPA2 is connected to the first output end of the Hall sensor, and the output end of the second operational amplifier OPA2 is connected to the power supply end of the Hall sensor.

[0079] refer to Figure 1 and Figure 3 The integral amplification module includes a third operational amplifier OPA3, the same-direction input terminal of the third operational amplifier OPA3 is connected to the second output terminal of the Hall sensor, the reverse input terminal of the third operational amplifier OPA3 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the reverse input terminal of the second operational amplifier OPA3 and the first output terminal of the Hall sensor; the reverse input terminal of the third operational amplifier OPA3 serves as the first input terminal of the integral amplification module, the positive input terminal of the third operational amplifier OPA3 serves as the second input terminal of the integral amplification module, and the output terminal of the third operational amplifier OPA3 serves as the output terminal of the integral amplification module.

[0080] The reverse input terminal of the third operational amplifier OPA3 is respectively connected to one end of the third resistor R3 and one end of the capacitor, wherein the third resistor R3 and the capacitor are connected in parallel, and the other end of the third resistor R3 and the other end of the capacitor are both connected to the output terminal of the third operational amplifier OPA3.

[0081] The offset calibration module includes a digital-to-analog converter DAC, one end of the digital-to-analog converter DAC is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the reverse input end of the third operational amplifier OPA3, and the output end of the digital-to-analog converter DAC serves as the output end of the offset calibration module.

[0082] Furthermore, the fifth resistor R5 is an editable resistor, and the size of the fifth resistor R5 can determine the size of the Hall signal amplification factor.

[0083] Furthermore, the integral amplifier module mainly includes a capacitor, a third resistor R3 and a third operational amplifier OPA3, and the fourth resistor R4 is arranged between the offset calibration module and the integral amplifier module, one end of the fifth resistor R5 is connected to the integral amplifier module, and the other end thereof is respectively connected to the reference module and the Hall sensor.

[0084] Furthermore, one end of the fourth resistor R4 is connected to the output end of the digital-to-analog converter DAC, the other end of the fourth resistor R4 is connected to the reverse input end of the third operational amplifier OPA3, one end of the third resistor R3 is connected to the reverse input end of the third operational amplifier OPA3, the other end of the third resistor R3 is connected to the output end of the third operational amplifier OPA3, one end of the capacitor is connected to the reverse input end of the third operational amplifier OPA3, the other end of the capacitor is connected to the output end of the third operational amplifier OPA3, one end of the fifth resistor R5 is connected to the first output end of the Hall sensor, the other end of the fifth resistor R5 is connected to the reverse input end of the third operational amplifier OPA3, and the output end of the third operational amplifier OPA3 is connected to the next level Hall signal processing circuit.

[0085] In this embodiment, the first resistor R1 , the second resistor R2 , the third resistor R3 , the fourth resistor R4 , and the fifth resistor R5 are of the same type.

[0086] Specifically, the offset voltage of the third operational amplifier and the offset voltage of the Hall sensor are accumulated to represent the offset voltage V OS , the digital-to-analog converter DAC has an offset voltage V OS The calibration range is expressed as:

[0087] ,

[0088] In the above formula, A C is the Hall signal amplification factor, AVDD is the power supply voltage, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and q is the number of bits of the digital-to-analog converter. The offset calibration range of the digital-to-analog converter DAC changes with the change of the Hall signal amplification factor and the power supply voltage.

[0089] During the process of losing regulation, the offset voltage V OS Superimposed on the inverting input terminal of the third operational amplifier OPA1.

[0090] Hall signal amplification factor A C Specifically expressed as:

[0091] ,

[0092] In the above formula, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and R5 is the resistance value of the fifth resistor.

[0093] Example 3

[0094] refer to Figures 1 to 3 Based on Example 1, the voltage at the non-inverting input terminal of the first operational amplifier OPA1 is 1 / 2*AVDD. Due to the virtual short characteristic of the ideal operational amplifier, the VREF voltage is also 1 / 2*AVDD. The voltage at the first output terminal of the Hall sensor is VIN, the voltage at the second output terminal of the Hall sensor is VIP, and the output terminal voltage of the third operational amplifier OPA3 is V OUT The output of the digital-to-analog converter DAC is V DAC , assuming that the cumulative offset voltage of the Hall sensor and the third operational amplifier OPA3 is V OS , the offset voltage V OS Superimposed on the inverting input terminal of the third operational amplifier OPA3, from the virtual short characteristic of the ideal operational amplifier, it can be known that the voltage at the inverting input terminal of the operational amplifier OPA3 is VIP.

[0095] Furthermore, the current flowing through the third resistor R3 can be calculated, which is specifically expressed as:

[0096] ,

[0097] Furthermore, the current flowing through the fourth resistor R4 can be calculated, which is specifically expressed as:

[0098] ,

[0099] Furthermore, the current flowing through the fifth resistor R5 can be calculated, which is specifically expressed as:

[0100]

[0101] According to the virtual-off characteristic of the ideal op amp, that is, the current flowing through the input terminal is 0, the following relationship can be obtained:

[0102] ,

[0103] Substituting the calculation formulas of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 into the above formula, the following relationship can be obtained:

[0104] .

[0105] After sorting, we can get the following relationship:

[0106] .

[0107] In the above-arranged relationship, VIN is the DC bias, VIN=VREF=1 / 2*AVDD, so VIP-VIN does not contain a DC component. This is the signal that really needs to be differentially amplified, and the amplification factor is A. C (Closed-loop gain) can be expressed as:

[0108] ,

[0109] The fifth resistor R5 is an editable resistor, and its resistance value has 16 coding modes. Moreover, the fifth resistor R5, the third resistor R3, and the fourth resistor R4 are all based on the same unit resistor, so the amplification factor is adjustable.

[0110] In this embodiment, the digital-to-analog converter DAC is an 8-bit digital-to-analog converter, the power supply is AVDD, and the output range is specifically , its resolution 1LSB is , output voltage V DAC The expression is ,in, .

[0111] The above-mentioned eight-bit D / A converter is only an example. When used, it is not limited to an eight-bit D / A converter, and a D / A converter with other bits may also be used.

[0112] The output voltage V of the third operational amplifier OPA3 OUT The expression shows that the offset voltage V OS Like the signal VIP-VIN that needs to be amplified, it is amplified by the same multiple. Under normal circumstances, V OUT The output common-mode level is VIN. If the offset voltage V OS is eliminated and finally reflected at the output terminal V OUT This will manifest as an output common-mode level shift. If the amplification factor is large enough, the output signal of the final amplifier can easily be clipped (greater than the power supply voltage or lower than the ground voltage).

[0113] If the offset voltage is 0, that is, , then as long as the output V of the digital-to-analog converter DAC DAC =1 / 2*AVDD, then is eliminated, and the output common-mode voltage is exactly at VIN, so the input of the digital-to-analog converter DAC needs to be configured to 10000000.

[0114] If the offset voltage is negative, that is, , then the output of the digital-to-analog converter DAC is V DAC must be increased to offset the offset term and item , then the input of the digital-to-analog converter DAC can be configured to a value greater than 10000000. Similarly, if the offset voltage is positive, that is , the DAC input can be configured to a value less than 10000000.

[0115] According to the above analysis process, It is to eliminate .Bundle This term is split into offset and offset , offset The item is that the digital-to-analog converter DAC input configuration is greater than 10000000 or less than 10000000.

[0116] make ,

[0117] (1) When the offset voltage hour

[0118] The maximum negative adjustment range can be achieved when the DAC output is at its maximum, and the maximum DAC output is ,at this time , so we have the following expression:

[0119] ,

[0120] And because VIN=1 / 2*AVDD3, so:

[0121] ,

[0122] Finally, we get V OS The negative maximum value of is:

[0123] ,

[0124] If V OS If this value is exceeded, the digital-to-analog converter DAC will not be able to adjust the output common mode point to VIN, which is 1 / 2*AVDD.

[0125] (2) When the offset voltage hour

[0126] The maximum positive adjustment range can be achieved when the DAC output is at its minimum, and the minimum DAC output is 0. , so we have the following expression:

[0127] ,

[0128] Because VIN=1 / 2*AVDD3, then:

[0129] ,

[0130] Finally, we get V OS The positive maximum value of is expressed as:

[0131] ,

[0132] If V OS If the calculated value is exceeded, the DAC will not be able to adjust the output common mode point to VIN, which is 1 / 2*AVDD.

[0133] In summary, the digital-to-analog converter DAC has a high sensitivity to the offset voltage V OS The calibration range can be expressed as:

[0134] .

[0135] From the above formula, it can be seen that with the supply voltage AVDD and the closed-loop gain A C As the offset voltage V OS If the output common mode point of the digital-to-analog converter DAC is fixed, the difference from VIN after adjustment (i.e., adjustment accuracy) is:

[0136] ,

[0137] For the digital-to-analog converter DAC, any offset voltage V within the calibration range can be OS , the maximum value of this difference △ is expressed as:

[0138] ,

[0139] , the minimum value is 0, so by controlling the ratio of the third resistor R3 and the fourth resistor R4, and using a higher resolution digital-to-analog converter DAC, a higher adjustment accuracy can be obtained. In this embodiment, R3=R4, so the final adjustment accuracy will depend on the resolution of the digital-to-analog converter DAC. Further, due to the amplification factor of the Hall signal , so it will depend on size.

[0140] It can be seen that by using the reference module and the offset calibration module, the influence of the offset of the Hall sensor itself and the offset of the third operational amplifier OPA3 on the final Hall sensing signal can be eliminated at the same time. The Hall signal amplification factor can be adjusted through the integral amplifier module to adapt to the next level of Hall signal processing circuit. At the same time, the Hall signal amplification circuit can also provide power supply for the Hall sensor, reducing the configuration of peripheral power supply.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A Hall signal amplifier circuit, characterized in that: Connect with Hall sensor, including: A reference module, whose control end is connected to the first output end of the Hall sensor, and the reference module can clamp the DC level of the first output end of the Hall sensor to 1 / 2 of the power supply voltage; An offset calibration module, whose output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module, and the offset calibration module can compensate for the offset voltage of the integral operational amplifier module and the offset voltage of the Hall sensor itself; The second input end of the integral amplifier module is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

2. A Hall signal amplifying circuit according to claim 1, characterized in that: The reference module includes a first operational amplifier and a second operational amplifier, the output end of the first operational amplifier is connected to the same-direction input end of the second operational amplifier, the output end of the second operational amplifier is connected to the power supply end of the Hall sensor, and the reverse input end of the second operational amplifier is connected to the first output end of the Hall sensor; the output end of the second operational amplifier serves as the output end of the reference module, and the reverse input end of the second operational amplifier serves as the control end of the reference module.

3. A Hall signal amplifying circuit according to claim 2, characterized in that: The same-direction input terminal of the first operational amplifier is respectively connected to one end of the first resistor and one end of the second resistor, the inverting input terminal of the first operational amplifier is connected to its output terminal, the other end of the first resistor is connected to a power supply, which serves as the power supply terminal of the reference module, and the other end of the second resistor is grounded, which serves as the ground terminal of the reference module.

4. A Hall signal amplifying circuit according to any one of claims 1 to 3, characterized in that: The integral amplification module includes a third operational amplifier, the same-direction input terminal of the third operational amplifier is connected to the second output terminal of the Hall sensor, the reverse input terminal of the third operational amplifier is connected to one end of a fifth resistor, and the other end of the fifth resistor is connected to the reverse input terminal of the second operational amplifier and the first output terminal of the Hall sensor; the reverse input terminal of the third operational amplifier serves as the first input terminal of the integral amplification module, the positive input terminal of the third operational amplifier serves as the second input terminal of the integral amplification module, and the output terminal of the third operational amplifier serves as the output terminal of the integral amplification module.

5. A Hall signal amplifying circuit according to claim 4, characterized in that: The inverting input terminal of the third operational amplifier is respectively connected to one end of a third resistor and one end of a capacitor, the third resistor and the capacitor are connected in parallel, and the other end of the third resistor and the other end of the capacitor are both connected to the output terminal of the third operational amplifier.

6. A Hall signal amplifying circuit according to claim 5, characterized in that: The offset calibration module includes a digital-to-analog converter, one end of the digital-to-analog converter is connected to one end of a fourth resistor, the other end of the fourth resistor is connected to the inverting input end of the third operational amplifier, and the output end of the digital-to-analog converter serves as the output end of the offset calibration module.

7. A Hall signal amplifying circuit according to claim 6, characterized in that: The offset voltage of the third operational amplifier and the offset voltage of the Hall sensor are cumulatively expressed as an offset voltage V OS , the DAC has an offset voltage V OS The calibration range is: ， Among them, A C is the Hall signal amplification factor, AVDD is the power supply voltage, R3 and R4 are the resistance values ​​of the third resistor and the fourth resistor respectively, and q is the number of bits of the digital-to-analog converter.

8. A Hall signal amplifying circuit according to claim 7, characterized in that: The Hall signal amplification factor A C Specifically: ， Wherein, R5 is the resistance value of the fifth resistor.

9. The Hall signal amplifying circuit according to claim 4, characterized in that: The fifth resistor is an editable resistor.

10. A Hall sensor device, characterized in that: A Hall signal amplifying circuit and a Hall sensor comprising any one of claims 1 to 9, wherein the Hall signal amplifying circuit is connected to the Hall sensor, and the Hall signal amplifying circuit comprises: A reference module, whose control end is connected to the first output end of the Hall sensor, and the reference module can clamp the DC level of the first output end of the Hall sensor to 1 / 2 of the power supply voltage; An offset calibration module, whose output end is respectively connected to the first output end of the Hall sensor and the first input end of the integral amplifier module, and the offset calibration module can compensate for the offset voltage of the integral amplifier module and the offset voltage of the Hall sensor itself; The second input end of the integral amplifier module is connected to the second output end of the Hall sensor. The integral amplifier module can amplify the compensated Hall sensing signal and output the final Hall sensing signal.

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