Isolation amplification circuit

Abstract

The application discloses an isolation amplification circuit. The isolation amplification circuit comprises a modulation circuit, an isolation circuit and a demodulation circuit. The modulation circuit receives an input signal and a first clock signal and generates a first modulation signal and a second modulation signal according to the first clock signal and the input signal. The isolation amplification circuit receives a second clock signal, the first modulation signal and the second modulation signal, and generates the first clock signal according to the second clock signal, a first demodulation signal according to the first modulation signal and a second demodulation signal according to the second modulation signal. The demodulation circuit receives the first demodulation signal, the second demodulation signal and the second clock signal, and generates an output signal according to the second clock signal, the first demodulation signal and the second demodulation signal. The application realizes low noise of the isolation amplification circuit by weighting and summing the second demodulation signal generated according to the second modulation signal in the demodulation circuit and the demodulated first modulation signal to offset quantization noise generated by the first modulation circuit.

Description

Technical Field

[0001] The present application relates to the technical field of isolation amplifier circuits, and in particular to an isolation amplifier circuit. Background Art

[0002] Isolation amplifier circuits are widely used in the field of current and voltage detection. Actual drive systems in the industrial and automotive fields, such as motor drive systems, typically have two voltage domains: a "high voltage" domain and a "low voltage" domain. A microcontroller or digital signal processor, typically located in the low-voltage domain, receives feedback signals (voltage, current, etc.) from the three-phase IGBT power stage and generates digital signals to control the power switching transistors and other high-voltage circuits. This requires reliable electrical isolation between the two voltage domains to isolate the high-voltage circuit from the low-voltage circuit, ensuring the reliable operation of the motor drive system. By breaking the ground loop between the high- and low-voltage circuits, damage to expensive circuits is prevented and operators are protected from high voltage injuries.

[0003] An isolation amplifier circuit is required to protect the digital control circuit. However, existing isolation amplifier circuits often cannot achieve both high bandwidth and fast response and high precision when implementing the isolation amplification function. The precision of the isolation amplifier circuit is mainly affected by system noise. If the measurement accuracy is to be improved, the response speed will be sacrificed. Summary of the Invention

[0004] This application provides an isolation amplifier circuit, which aims to solve the problems of low signal transmission accuracy and low signal-to-noise ratio in isolation amplifier circuits in the prior art. To achieve the above technical objectives, this application adopts the following technical solutions:

[0005] According to a first aspect of the present application, an embodiment of the present application provides an isolation amplifier circuit, including: a modulation circuit 10, having an input end receiving an input signal VIN, a control end receiving a first clock signal CLK_rx, a first output end providing a first modulation signal D1_tx, and a second output end providing a second modulation signal D2_tx, wherein the modulation circuit 10 generates a first modulation signal D1_tx and a second modulation signal D2_tx according to the input signal VIN and the first clock signal CLK_rx; an isolation circuit 20, having a first input end receiving the first modulation signal D1_tx, a second input end receiving the second modulation signal D2_tx, a control end receiving the second clock signal, and generating a first clock signal CLK_rx according to the second clock signal CLK_tx, and generating a first demodulated signal D1_tx according to the first modulation signal D1_tx. _rx, generates a second demodulated signal D2_rx according to the second modulation signal D2_tx, wherein the first clock signal CLK_tx and the second clock signal CLK_rx have the same frequency and amplitude, the first demodulated signal D1_rx and the first modulation signal D1_tx have the same frequency and amplitude, and the second demodulated signal D2_rx and the second modulation signal D2_tx have the same frequency and amplitude; and a demodulation circuit 30, having a first input end receiving the first demodulated signal D1_rx, a second input end receiving the second demodulated signal D2_rx, and a control end receiving the second clock signal CLK_tx, the demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulated signal D1_rx and the second demodulated signal D2_rx, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0006] According to the second aspect of the present application, an embodiment of the present application provides an isolation amplifier circuit, including: a modulation circuit 10, having an input end receiving an input signal VIN, a control end receiving a first clock signal CLK_tx, a first output end providing a first modulation signal D1_tx, and a second output end providing a second modulation signal D2_tx, wherein the modulation circuit 10 samples the input signal VIN at the frequency of the first clock signal CLK_tx and modulates it into a first modulation signal D1_tx and a second modulation signal D2_tx; an isolation circuit 20, having a first input end receiving the first modulation signal D1_tx, a second input end receiving the second modulation signal D2_tx, a control end receiving the first clock signal CLK_tx, and generating a first demodulation signal D1_rx according to the first modulation signal D1_tx, and generating a first demodulation signal D1_rx according to the first demodulation signal D1_tx. The second modulation signal D2_tx generates a second demodulation signal D2_rx, and a second clock signal is generated according to the first clock signal, wherein the frequency and amplitude of the first clock signal CLK_tx and the second clock signal CLK_rx are the same, the frequency and amplitude of the first demodulation signal D1_rx and the first modulation signal D1_tx are the same, and the frequency and amplitude of the second demodulation signal D2_rx and the second modulation signal D2_tx are the same; and the demodulation circuit 30 has a first input end for receiving the first demodulation signal D1_rx, a second input end for receiving the second demodulation signal D2_rx, and a control end for receiving the second clock signal CLK_tx, and the demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx and the second demodulation signal D2_rx.

[0007] Through one or more of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0008] The present application obtains a second modulation signal through a modulation circuit, and transmits the second modulation signal and the first modulation signal to a demodulation circuit together through an isolation circuit. The isolation circuit generates a second demodulation signal according to the second modulation signal, and generates a first demodulation signal according to the first modulation signal. The demodulation circuit receives the first demodulation signal and the second demodulation signal, and performs a weighted summation on the two to offset the quantization noise introduced by the modulation circuit during the modulation process, thereby improving the signal-to-noise ratio during the signal transmission process of the isolation circuit and ensuring the signal transmission accuracy during the high-bandwidth fast response process. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0010] Figure 1A A circuit structure diagram of an isolation amplifier circuit 100 according to an embodiment of the present application is provided;

[0011] Figure 1B A circuit structure diagram of an isolation amplifier circuit 100 according to an embodiment of the present application is provided;

[0012] Figure 2 A schematic diagram of the circuit structure of a modulation circuit 10 according to an embodiment of the present application is provided;

[0013] Figure 3A A schematic diagram of the circuit structure of the first modulation circuit 11 according to an embodiment of the present application is provided;

[0014] Figure 3B A schematic diagram of signal waveforms of the first modulation circuit 11 according to an embodiment of the present application is provided;

[0015] Figure 4A A circuit structure diagram of the second modulation circuit 12 according to an embodiment of the present application is provided;

[0016] Figure 4B A schematic diagram of signal waveforms of the second modulation circuit 12 according to an embodiment of the present application is provided;

[0017] Figure 5 A schematic diagram of the circuit structure of a demodulation circuit 30 according to an embodiment of the present application is provided;

[0018] Figure 6 A circuit structure diagram of a demodulation circuit 30 according to another embodiment of the present application is provided;

[0019] Figure 7 A circuit structure diagram of a first demodulation circuit 31 according to an embodiment of the present application is provided;

[0020] Figure 8 A circuit structure diagram of the second demodulation circuit 32 according to an embodiment of the present application is provided;

[0021] Figure 9 A schematic diagram of the circuit structure of the isolation circuit 20 according to an embodiment of the present application is provided;

[0022] Figure 10 A circuit structure diagram of an isolation amplifier circuit 100 according to another embodiment of the present application is provided;

[0023] Figure 11 A schematic diagram of the circuit structure of an isolation circuit 20 according to another embodiment of the present application is provided. DETAILED DESCRIPTION

[0024] In describing the present invention, it should be noted that throughout the specification and claims, "coupled" is defined as a connection, either directly or indirectly, electrically or non-electrically. When an element is described as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, no intervening elements are present. Throughout this specification, references to "one embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, appearances of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, particular features, structures, or characteristics may be combined in any suitable combination and / or subcombination in one or more embodiments or examples. Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes only and are not necessarily drawn to scale. Identical reference numbers indicate identical components. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0025] Figure 1A A schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to an embodiment of the present application is provided. The isolation amplifier circuit 100 includes a modulation circuit 10, an isolation circuit 20, and a demodulation circuit 30. The modulation circuit 10 has an input terminal for receiving an input signal VIN, a control terminal for receiving a first clock signal CLK_rx, a first output terminal for providing a first modulation signal D1_tx, and a second output terminal for providing a second modulation signal D2_tx. The modulation circuit 10 generates the first modulation signal D1_tx and the second modulation signal D2_tx based on the input signal VIN and the first clock signal CLK_rx. In one embodiment, the first modulation signal D1_tx represents the input signal VIN, and the second modulation signal D2_tx represents the quantization noise generated when the input signal VIN generates the first modulation signal D1_tx. In one embodiment, the input signal VIN can be a square wave or a sine wave with a frequency between 100 kHz and 2 MHz. In one embodiment, the frequency range of the first clock signal CLK_rx is between 10 MHz and 30 MHz.

[0026] The isolation circuit 20 has a first input end for receiving a first modulation signal D1_tx, a second input end for receiving a second modulation signal D2_tx, and a control end for receiving a second clock signal CLK_tx, and generates a first clock signal CLK_rx based on the second clock signal CLK_tx, generates a first demodulation signal D1_rx based on the first modulation signal D1_tx, and generates a second demodulation signal D2_rx based on the second modulation signal D2_tx, wherein the first clock signal CLK_tx and the second clock signal CLK_rx have the same frequency and amplitude, the first demodulation signal D1_rx and the first modulation signal D1_tx have the same frequency and amplitude, and the second demodulation signal D2_rx and the second modulation signal D2_tx have the same frequency and amplitude.

[0027] The demodulation circuit 30 has a first input terminal for receiving the first demodulation signal D1_rx, a second input terminal for receiving the second demodulation signal D2_rx, and a control terminal for receiving the second clock signal CLK_tx. The demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_tx, the first demodulation signal D1_rx, and the second demodulation signal D2_rx, wherein the amplitude of the output signal is greater than the amplitude of the input signal.

[0028] Figure 1B The circuit structure diagram of the isolation amplifier circuit according to an embodiment of the present application is given. The isolation circuit 20 includes a first isolation circuit, which has an input end receiving a second clock signal CLK_tx and an output end providing a first clock signal CLK_rx. The first isolation circuit generates a first clock signal CLK_rx according to the second clock signal CLK_tx. Figure 1B In the illustrated embodiment, the first isolation circuit may include an isolated coupled first receiving circuit RX1 and a first transmitting circuit TX1, wherein the first transmitting circuit TX1 receives the second clock signal CLK_tx and generates differential signals P2 and N2, which are coupled and output to the first receiving circuit RX1. The first receiving circuit RX1 receives the differential signals P2 and N2 and generates a first clock signal CLK_rx, which is output to the modulation circuit 10. The isolation circuit 20 also includes a second isolation circuit having an input terminal for receiving the first modulation signal D1_tx and an output terminal for providing a first demodulated signal D1_rx. The second isolation circuit generates a first demodulated signal D1_rx based on the first modulation signal D1_tx. Figure 1BIn the illustrated embodiment, the second isolation circuit may include an isolated coupled second receiving circuit RX2 and a second transmitting circuit TX2, wherein the second transmitting circuit TX2 receives the first modulated signal D1_tx and generates differential signals P1 and N1, which are coupled and output to the second receiving circuit RX2. The second receiving circuit RX2 receives the differential signals P1 and N1 and generates a first demodulated signal D1_rx, which is output to the demodulation circuit 30. The isolation circuit 20 also includes a third isolation circuit having an input terminal for receiving the second modulated signal D2_tx and an output terminal for providing a second demodulated signal D2_rx. The third isolation circuit generates a second demodulated signal D2_rx based on the second modulated signal D2_tx. Figure 1B In the illustrated embodiment, the third isolation circuit may include an isolated coupled third receiving circuit RX3 and a third transmitting circuit TX3, wherein the third transmitting circuit TX3 receives the second modulated signal D2_tx and generates differential signals P3 and N3, which are coupled and output to the third receiving circuit RX3. The third receiving circuit RX3 receives the differential signals P3 and N3 and generates a second demodulated signal D2_rx, which is output to the demodulation circuit 30.

[0029] The modulation circuit 10 generates a second modulation signal D2_tx based on the quantization noise signal Vqn_tx. Quantization noise is the noise generated when the modulation circuit 10 converts the analog input signal VIN into the digital first modulation signal D1_tx. In one embodiment, the second modulation signal D2_tx is a pulse-width modulated signal. The isolation circuit 20 generates a second demodulated signal D2_rx based on the second modulation signal D2_tx. The second demodulated signal D2_rx is also a pulse-width modulated signal. The demodulation circuit 30 receives the second demodulated signal D2_rx and generates an output signal VOUT based on the second demodulated signal D2_rx and the first demodulated signal D1_rx to offset the effects of the quantization noise generated in the modulation circuit 10.

[0030] Figure 2A schematic diagram of the circuit structure of a modulation circuit 10 according to an embodiment of the present application is provided. The modulation circuit 10 includes a first modulation circuit 11 and a second modulation circuit 12. The first modulation circuit 11 has an input terminal for receiving an input signal VIN, a control terminal for receiving a first clock signal CLK_rx, a first output terminal for providing a first modulation signal D1_tx, and a second output terminal for providing a quantization noise signal Vqn_tx. Under the control of the first clock signal CLK_rx, the first modulation circuit 11 generates the first modulation signal D1_tx and the quantization noise signal Vqn_tx according to the input signal VIN. The quantization noise signal Vqn_tx represents the noise caused by the error introduced by the quantization process when the analog signal (input signal VIN) is converted into a discrete digital signal (first modulation signal D1_tx). The second modulation circuit 12 has an input terminal for receiving a quantization noise signal Vqn_tx, a control terminal for receiving a first clock signal CLK_rx, and a first output terminal for providing a second modulation signal D2_tx. The second modulation circuit 12 generates the second modulation signal D2_tx based on the quantization noise signal Vqn_tx under the control of the first clock signal CLK_rx. In one embodiment, the first modulation circuit 11 includes a delta-sigma modulation circuit (SDM, sigma-delta modulator), which can be a continuous delta-sigma modulation circuit or a discrete delta-sigma modulation circuit. In one embodiment, the first modulation circuit 11 can be a second-order 1-bit feedforward SDM. It should be noted that the SDM modulator is merely an example, and any circuit structure that can generate the first modulation signal D1_tx and the quantization noise signal Vqn_tx based on the input signal VIN under the control of the first clock signal CLK_rx is included in this application. In one embodiment, the second modulation circuit 12 may be a pulse width modulation circuit (PWM), wherein the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that the pulse width modulation circuit is merely an example, and any circuit structure capable of generating the second modulation signal D2_tx based on the quantization noise signal Vqn_tx under the control of the first clock signal CLK_rx is included in this application.

[0031] Figure 3AA schematic diagram of the circuit structure of a first modulation circuit 11 according to an embodiment of the present application is provided. The first modulation circuit 11 includes a first integrator circuit 111, a second integrator circuit 112, a first summing circuit 113, and a first operation circuit 114. The first integrator circuit 111 has a first input terminal for receiving an input signal VIN and a second input terminal for receiving a first modulation signal D1_tx. The first integrator circuit 111 performs a weighted integration operation on the input signal VIN and the first modulation signal D1_tx to generate a first conversion signal TX1. The second integrator circuit 112 has an input terminal for receiving the first conversion signal TX1 and performs an integration operation on the first conversion signal TX1 to generate a quantization noise signal Vqn_tx. The first summing circuit 113 has a first input terminal for receiving a quantization noise signal Vqn_tx, a second input terminal for receiving the first conversion signal TX1, and a third input terminal for receiving the input signal VIN. The first summing circuit 113 performs a weighted summation operation on the quantization noise signal Vqn_tx, the first conversion signal TX1, and the input signal VIN to generate a second conversion signal TX2. The first operation circuit 114 has an input terminal for receiving the second conversion signal TX2 , and generates a first modulation signal D1_tx according to the second conversion signal TX2 .

[0032] exist Figure 3A In the illustrated embodiment, the first modulation circuit 11 is a second-order, 1-bit feedforward Sigma-Delta modulator. A first integrator 111 samples the input voltage VIN at a sampling frequency F and performs a weighted summation on the sampled voltage and the first modulated signal D1_tx. Weighted summation involves multiplying the summed voltage by a corresponding weight coefficient and then adding the products to obtain the sum. In this embodiment, the product of the sampled voltage multiplied by a coefficient and the product of the first modulated signal D1_tx multiplied by a coefficient are added to obtain the sum. This summation is then delayed and integrated to generate the first converted signal TX1. A second integrator 112 integrates the first converted signal TX1 to generate a quantization noise signal Vqn_tx. A first adder 113 performs a weighted summation operation on the quantization noise signal Vqn_tx, the first converted signal TX1, and the input signal VIN to generate a second converted signal TX2. A first operation circuit 114 generates the first modulated signal D1_tx based on the second converted signal TX2.

[0033] exist Figure 3A In the embodiment shown, the transfer function of the first modulated signal D1_tx in the z-domain is expressed as follows:

[0034] D1_tx(z)=VIN(z)+E(z)·(1-z -1 ) 2 (1)

[0035] Where D1_tx(z) is the first modulated signal, and E(z) is the quantization noise contributed by a 1-bit quantizer. The working principle of a 1-bit quantizer is to use oversampling and noise shaping techniques to improve the conversion accuracy. Ideally, the bandwidth quantization noise power of a second-order 1-bit SDM is Where OSR is the oversampling rate, which is equal to half of the sampling frequency divided by the signal bandwidth, e rms is the root mean square value of the quantization noise. When the oversampling rate is fixed, the theoretically obtained quantization noise limits the signal-to-interference plus noise ratio (SNR) performance of the structure. When the sampling frequency is fixed, as the frequency range of the input signal VIN increases, the oversampling rate decreases, and the signal-to-noise ratio gradually decreases. In the embodiment of Figure 3, the quantization noise is provided by the output end of the second integrator circuit 112, that is, the quantization noise signal Vqn_tx, and its z-domain transfer function is shown in the following formula (2):

[0036] V qn_tx (z)=-z -2 E(z) (2)

[0037] As can be seen from the above formula, the quantization noise signal Vqn_tx is the delay of two time units of the quantization noise E(z) (the exponential value of z represents the degree of delay, the -1 power is one time unit delay, and the -2 power is two time unit delay), which can represent the quantization noise in the first modulation circuit 11 when the input signal VIN generates the first modulation signal D1_tx.

[0038] Figure 3B A schematic diagram of the signal waveform of the first modulation circuit 11 according to an embodiment of the present application is given. Figure 3A The structure of the first modulation circuit 11 shown is Figure 3B The waveforms of the signals in the figure are described. Under the control of the first clock signal CLK_tx, the input signal VIN is modulated into the first modulation signal D1_tx. During the modulation process, the influence of the quantization noise signal Vqn_tx is superimposed. It should be noted that Figure 3B The waveform change of the quantization noise signal Vqn_tx shown in FIG is for illustration only, and is only used to indicate that the quantization noise signal has a random distribution in different clock cycles and has no regularity.

[0039] exist Figure 3AIn the illustrated embodiment, the first operation circuit 114 is a dynamic zero-crossing comparator that periodically compares the second conversion signal TX2 with the reference ground voltage GND according to the frequency of the first clock signal CLK_rx. When the second conversion signal TX2 is greater than the reference ground voltage GND, the first modulation signal D1_tx is output as a logic high level. Otherwise, the first modulation signal D1_tx is output as a logic low level.

[0040] Figure 4A A schematic diagram of the circuit structure of the second modulation circuit 12 according to one embodiment of the present application is provided. A differential pair of quantization noise signals, Vqn_tx and -Vqn_tx, is input to the second modulation circuit 12, and a differential pair of first clock signals, CLK_rxP and CLK_rxN, are input to the second modulation circuit 12. Taking a circuit in which one side receives the quantization noise signal Vqn_tx and the first clock signal CLK_rxP, as an example, a first switch S1 and a second switch S2 are turned on or off under the control of a second modulation signal D2_tx. When the first switch S1 is turned on, the second end of the resistor Rf1p receives a first reference voltage, -Vref1. When the second switch S2 is turned on, the second end of the resistor Rf1p receives a second reference voltage, +Vref1. In one embodiment, when the second modulation signal D2_tx is at a logic high level, the first switch S1 is turned off and the second switch S2 is turned on. When the second modulation signal D2_tx is at a logic low level, the first switch S1 is turned on and the second switch S2 is turned off. In one embodiment, the first reference voltage − Vref1 and the second reference voltage + Vref1 have the same absolute value but opposite polarities.

[0041] exist Figure 4A In the embodiment shown, one side of the differential input second modulation circuit 12 is used as an example for explanation. The integrator composed of resistor Rcp, capacitor C1P and operational amplifier provides a triangular wave signal at the input end of the operational amplifier to the subsequent comparison circuit. The triangular wave is used as the carrier of the second modulation circuit 12 to implement pulse width modulation. When the operational amplifier is in a stable state, the output of the integrator must be bounded. Therefore, from the perspective of cycle balance, the average current on capacitor C1P is zero. According to the Thevenin theorem, the output duty cycle of the second modulation signal D2_tx is derived, and its calculation formula is: The bandwidth of the second modulation signal D2_tx is determined by the resistors Rcp, Rf1p, the capacitor C1P, and the carrier frequency, and exhibits a first-order low-pass characteristic. Since the quantization noise does not need to be fully transmitted to the demodulation side, the bandwidth of the second modulation signal D2_tx only needs to be greater than the signal bandwidth. In one embodiment, the bandwidth of the second modulation signal D2_tx is 1 MHz. In other embodiments, the second modulation circuit 12 may also be a non-differential input circuit, for example, it may only include the following: Figure 4AOne side of the circuit shown in FIG, that is, only includes a resistor Rcp, a resistor Rs1p, a capacitor C1P, an operational amplifier, a comparator, and a first switch S1 and a second switch S2, and its working principle is the same as Figure 4A The working principle of the differential single-side in the second modulation circuit 12 shown is similar and will not be described in detail here.

[0042] Figure 4B A schematic diagram of the signal waveform of the second modulation circuit 12 according to an embodiment of the present application is given. Figure 4A The structure of the second modulation circuit 12 shown is Figure 4B The waveforms of the signals in FIG are described. Under the control of the clock signal CLK_rx, the quantization noise signal VIN is modulated into the second modulation signal D2_tx. The second modulation circuit 12 is a pulse width modulation circuit, wherein the pulse width of the second modulation signal D2_tx represents the quantization noise signal Vqn_tx. It should be noted that, Figure 4B The waveform change of the quantization noise signal Vqn_tx shown in FIG is only for illustration. In actual applications, the quantization noise signal has random value fluctuations.

[0043] In some embodiments, the second modulation circuit 12 may include a first-order 1-bit SDM modulator or a first-order pulse width modulator. First-order pulse width modulators have better noise performance. In a first-order pulse width modulator, signal information is encoded in the time domain. Ideally, PWM does not contribute to quantization noise. Using PWM to transfer quantization noise can achieve a better signal-to-noise ratio.

[0044] Figure 5 A circuit structure diagram of a demodulation circuit 30 according to an embodiment of the present application is given. The demodulation circuit 30 includes a first demodulation circuit 31 and a second demodulation circuit 32. The first demodulation circuit 31 has an input end for receiving a second demodulation signal D2_rx, and generates a demodulated quantization noise signal Vqn_rx based on the second demodulation signal D2_rx. The second demodulation circuit 32 has a first input end for receiving a first demodulation signal D1_rx, a second input end for receiving a demodulated quantization noise signal Vqn_rx, and a third input end for receiving a second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT based on the second clock signal CLK_tx, the first demodulation signal D1_rx and the demodulated quantization noise signal Vqn_rx. In one embodiment, the first demodulation signal D1_rx and the demodulation quantization noise signal Vqn_rx are weightedly summed to generate the output signal VOUT. It should be noted that

[0045] Figure 5 The demodulation circuit 30 provided is only an example, and any circuit structure that can generate a demodulated quantization noise signal Vqn_rx according to the second demodulation signal D2_rx is included in the present application.

[0046] Figure 6 A circuit structure diagram of a demodulation circuit 30 according to another embodiment of the present application is given. Figure 5 In the embodiment shown, the first demodulation circuit 31 has an input terminal for receiving the second demodulation signal D2_rx, and generates a demodulated quantization noise signal Vqn_rx according to the second demodulation signal D2_rx. Figure 5 The first demodulation circuit 31 does not receive the second clock signal CLK_tx, and its timing control is only implemented according to the timing information of the second demodulation signal D2_rx. Figure 6 In the illustrated embodiment, the first demodulation circuit 31 has an input terminal for receiving a second demodulated signal D2_rx and a second clock signal CLK_tx, and generates a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx and the second clock signal CLK_tx. The second demodulation circuit 32 has a first input terminal for receiving the first demodulated signal D1_rx, a second input terminal for receiving the demodulated quantization noise signal Vqn_rx, and a third input terminal for receiving the second clock signal CLK_tx. The second demodulation circuit 32 generates an output signal VOUT based on the second clock signal CLK_tx, the first demodulated signal D1_rx, and the demodulated quantization noise signal Vqn_rx. It should be noted that any circuit structure that can generate a demodulated quantization noise signal Vqn_rx based on the second demodulated signal D2_rx under the control of the second clock signal CLK_tx is included in this application.

[0047] Figure 7 A schematic diagram of the circuit structure of a first demodulation circuit 31 according to an embodiment of the present application is provided. The first demodulation circuit 31 includes a fifth switch S5, a sixth switch S6, a fourth resistor R4, a sixth arithmetic circuit 311, a second capacitor C2, a sample-and-hold circuit 312, a seventh arithmetic circuit 313, and a fifth resistor R5.

[0048] The fifth switch S5 has a first terminal for receiving the fourth reference voltage -Vref2 and a third terminal for receiving the second demodulated signal D2_rx. The sixth switch S6 has a first terminal for receiving the third reference voltage +Vref2 and a third terminal for receiving the second demodulated signal D2_rx. The fourth resistor R4 has a first terminal coupled to the second terminal of the fifth switch S5 and the second terminal of the sixth switch S6. The sixth operation circuit 311 has a first input terminal coupled to the second terminal of the fourth resistor R4, a second input terminal coupled to the reference ground, and an output terminal providing the sixth conversion signal TX6. The second capacitor C2 has a first terminal coupled to the first input terminal of the sixth operation circuit 311 and a second terminal coupled to the output terminal of the sixth operation circuit 311. The sample-and-hold circuit 312 has a first input terminal for receiving the sixth conversion signal TX6 and a second input terminal for receiving the second demodulated signal D2_rx. The sample-and-hold circuit 312 generates a seventh conversion signal TX7 based on the sixth conversion signal TX6 and the second demodulated signal D2_rx. The seventh operation circuit 313 has an input terminal for receiving the seventh conversion signal TX7 and generates a demodulated quantization noise signal Vqn_rx based on the seventh conversion signal TX7. The fifth resistor R5 has a first terminal for receiving the demodulated quantization noise signal Vqn_rx and a second terminal coupled to the first input terminal of the sixth operation circuit 311. The fifth switch S5 and the sixth switch S6 are turned on or off under the control of the second demodulation signal D2_rx. When the fifth switch S5 is turned on, the first terminal of the fourth resistor R4 receives the fourth reference voltage -Vref2. When the sixth switch S6 is turned on, the first terminal of the fourth resistor R4 receives the third reference voltage +Vref2. In one embodiment, when the second demodulation signal D2_rx is at a logic high level, the fifth switch S5 is turned off and the sixth switch S6 is turned on. When the second demodulation signal D2_rx is at a logic low level, the fifth switch S5 is turned on and the sixth switch S6 is turned off.

[0049] exist Figure 7 In the embodiment shown, the first demodulation circuit 31 is used for pulse width demodulation to restore the demodulated quantization noise signal Vqn_rx and output it to the second demodulation circuit 32. The voltage of the demodulated quantization noise signal Vqn_rx is And it presents a first-order low-pass characteristic. The sampling and holding circuit 312 can generate a notch at the carrier frequency to suppress the interference signal near the carrier frequency. According to the calculation formula of the second modulation circuit 12, Finally, it is derived It can be seen that when the resistance and reference voltage are equally matched, V qn_rx =V qn_tx .

[0050] In one embodiment, the first demodulation circuit 31 exhibits a low-pass characteristic of PWM, and the cancellation effect of the part above the PWM bandwidth is weakened. In order to suppress high-frequency noise, a low-pass filter can be added in the later stage to further filter out the high-frequency noise to obtain better noise performance.

[0051] Figure 8 A schematic diagram of the circuit structure of the second demodulation circuit 32 according to an embodiment of the present application is provided. The second demodulation circuit 32 includes a third switch S3, a fourth switch S4, a third integration circuit 321, a fourth operation circuit 323, a fourth integration circuit 322, a fifth operation circuit 324, and a second addition circuit 325.

[0052] The third switch S3 has a first terminal, a second terminal, and a third terminal. The first terminal receives a third reference voltage +Vref2, and the third terminal receives the first demodulated signal D1_rx. The third switch is turned on or off under the control of the first demodulated signal D1_rx. The fourth switch S4 has a first terminal, a second terminal, and a third terminal. The first terminal receives a fourth reference voltage -Vref2, and the third terminal receives the first demodulated signal D1_rx. The fourth switch S4 is turned on or off under the control of the first demodulated signal. The fourth operation circuit 323 has an input terminal that receives the output signal VOUT and generates a third conversion signal TX3 based on the output signal VOUT. The third integrator circuit 321 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the second terminal of the third switch S3 and the second terminal of the fourth switch S4, and the second input terminal receives the third conversion signal TX3. The third switch S3 and the fourth switch S4 are turned on or off under the control of the first demodulated signal D1_rx. When the third switch S3 is turned on, the first input terminal of the third integrator circuit 321 receives the third reference voltage +Vref2. When the fourth switch S4 is turned on, the first input terminal of the third integrator circuit 321 receives the fourth reference voltage -Vref2. The third integrator circuit 321 performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate a fourth conversion signal TX4. Alternatively, the third integrator circuit 321 performs a weighted integration operation based on the third reference voltage and the third conversion signal TX3 to generate a fourth conversion signal TX4. The fourth integrator circuit 322 has a first input terminal for receiving the fourth conversion signal TX4 and a second input terminal for receiving the third conversion signal TX3. The fourth integrator circuit 322 performs a weighted integration operation based on the fourth conversion signal TX4 and the third conversion signal TX3 to generate a fifth conversion signal TX5. The fifth arithmetic circuit 324 has an input terminal for receiving the demodulated quantization noise signal Vqn_rx and generates a second noise signal Vqn2 based on the demodulated quantization noise signal Vqn_rx. The second adding circuit 325 has a first input terminal for receiving the fifth conversion signal TX5 and a second input terminal for receiving the second noise signal Vqn2 , and performs a weighted sum operation according to the fifth conversion signal TX5 and the second noise signal Vqn2 to generate an output signal VOUT.

[0053] In one embodiment, when the first demodulated signal D1_rx is at a logic low level, the third switch S3 is turned off and the fourth switch S4 is turned on. When the first demodulated signal D1_rx is at a logic high level, the third switch S3 is turned on and the fourth switch S4 is turned off.

[0054] exist Figure 8 In the illustrated embodiment, the second demodulation circuit 32 converts the digital first demodulation signal D1_rx into an analog output signal VOUT, while simultaneously achieving weighted cancellation of the quantization noise generated by the first modulation circuit 10. The output signal VOUT is expressed in the z-domain as follows:

[0055]

[0056] Where D(z) = 10-15z -1 +6z -2

[0057] Each operation circuit, integration circuit and addition circuit in the first demodulation circuit 31 and the second demodulation circuit 32 needs to perform operations according to the frequency of the first clock signal. -1 " means delay for one time period, "z -2 " indicates a delay of two time periods. The setting of the time period is related to the frequency period of the clock signal.

[0058] In summary, combined with formulas (1), (2), and (3), the expression of the output signal VOUT can be derived as:

[0059]

[0060] Figure 9 A schematic diagram of the circuit structure of an isolation circuit 20 according to an embodiment of the present application is provided. The isolation circuit 20 includes a first isolation circuit 21 , a second isolation circuit 22 and a third isolation circuit 23 .

[0061] The first isolation circuit 21 has an input terminal for receiving the second clock signal CLK_tx and an output terminal for providing the first clock signal CLK_rx. The first isolation circuit 21 generates the first clock signal CLK_rx based on the second clock signal CLK_tx. The second isolation circuit 22 has an input terminal for receiving the first modulated signal D1_tx and an output terminal for providing the first demodulated signal D1_rx. The second isolation circuit 22 generates the first demodulated signal D1_rx based on the first modulated signal D1_tx. The third isolation circuit 23 has an input terminal for receiving the second modulated signal D2_tx and an output terminal for providing the second demodulated signal D2_rx. The third isolation circuit 23 generates the second demodulated signal D2_rx based on the second modulated signal D2_tx.

[0062] exist Figure 9In the illustrated embodiment, the first isolation circuit 21 includes a first capacitor C1, the second isolation circuit 22 includes a second capacitor C2, and the third isolation circuit 23 includes a third capacitor C3. In other embodiments, the first isolation circuit 21 may include N capacitors connected in series, where N is an integer greater than or equal to 2.

[0063] Figure 10 A schematic diagram of the circuit structure of an isolation amplifier circuit 100 according to another embodiment of the present application is given. The modulation circuit 10 has an input terminal for receiving an input signal VIN, a control terminal for receiving a first clock signal CLK_tx, a first output terminal for providing a first modulation signal D1_tx, and a second output terminal for providing a second modulation signal D2_tx. The modulation circuit 10 samples the input signal VIN at the frequency of the first clock signal CLK_tx and modulates it into the first modulation signal D1_tx and the second modulation signal D2_tx. Figure 10 In the illustrated embodiment, the first clock signal CLK_tx is generated by an oscillator. The isolation circuit 20 has a first input terminal receiving a first modulation signal D1_tx, a second input terminal receiving a second modulation signal D2_tx, and a control terminal receiving the first clock signal CLK_tx. The isolation circuit 20 generates a first demodulated signal D1_rx based on the first modulation signal D1_tx, generates a second demodulated signal D2_rx based on the second modulation signal D2_tx, and generates a second clock signal CLK_rx based on the first clock signal CLK_tx. The first clock signal CLK_tx and the second clock signal CLK_rx have the same frequency and amplitude, the first demodulated signal D1_rx has the same frequency and amplitude as the first modulation signal D1_tx, and the second demodulated signal D2_rx has the same frequency and amplitude as the second modulation signal D2_tx. The demodulation circuit 30 has a first input terminal receiving the first demodulation signal D1_rx, a second input terminal receiving the second demodulation signal D2_rx, and a control terminal receiving the second clock signal CLK_rx. The demodulation circuit 30 generates an output signal VOUT according to the second clock signal CLK_rx, the first demodulation signal D1_rx, and the second demodulation signal D2_rx.

[0064] Figure 11A schematic diagram of the circuit structure of an isolation circuit 20 according to another embodiment of the present application is provided. The isolation circuit 20 includes a first isolation circuit 21, a second isolation circuit 22, and a third isolation circuit 23. The first isolation circuit 21 has an input terminal for receiving a first clock signal CLK_tx and an output terminal for providing a second clock signal CLK_rx. The first isolation circuit 21 generates a second clock signal CLK_rx based on the first clock signal CLK_tx. The second isolation circuit 22 has an input terminal for receiving a first modulation signal D1_tx and an output terminal for providing a first demodulated signal D1_rx. The second isolation circuit 22 generates a first demodulated signal D1_rx based on the first modulation signal D1_tx. The third isolation circuit 23 has an input terminal for receiving a second modulation signal D2_tx and an output terminal for providing a second demodulated signal D2_rx. The third isolation circuit 23 generates a second demodulated signal D2_rx based on the second modulation signal D2_tx.

[0065] exist Figure 11 In the illustrated embodiment, the first isolation circuit 21 includes a first capacitor C1 , the second isolation circuit 22 includes a second capacitor C2 , and the third isolation circuit 23 includes a third capacitor C3 .

[0066] While the present invention has been described with reference to several exemplary embodiments, it should be understood that the terms used are descriptive and illustrative, rather than restrictive. Since the present invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above-described embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope of the appended claims. All changes and modifications that fall within the scope of the claims or their equivalents are intended to be covered by the appended claims.

Claims

1. An isolation amplifier circuit, comprising: a modulation circuit having an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a second modulation signal, wherein the modulation circuit generates the first modulation signal and the second modulation signal according to the input signal and the first clock signal; The first modulation signal represents the input signal, and the second modulation signal represents the quantization noise generated when the input signal generates the first modulation signal; an isolation circuit, wherein a first input terminal receives the first modulation signal, a second input terminal receives the second modulation signal, a control terminal receives a second clock signal, and generates a first clock signal based on the second clock signal, generates a first demodulation signal based on the first modulation signal, and generates a second demodulation signal based on the second modulation signal, wherein the first clock signal and the second clock signal have the same frequency and amplitude, the first demodulation signal and the first modulation signal have the same frequency and amplitude, and the second demodulation signal and the second modulation signal have the same frequency and amplitude; as well as The demodulation circuit has a first input end for receiving the first demodulation signal, a second input end for receiving the second demodulation signal, and a control end for receiving a second clock signal. The demodulation circuit generates an output signal based on the second clock signal, the first demodulation signal, and the second demodulation signal, wherein the amplitude of the output signal is greater than the amplitude of the input signal. 2 . The isolation amplifier circuit according to claim 1 , wherein the input signal is a square wave or a sine wave with a frequency between 100 kHz and 2 MHz. 3 . The isolation amplifier circuit according to claim 1 , wherein a frequency range of the first clock signal CLKtx is between 10 MHz and 30 MHz.

4. The isolation amplifier circuit according to claim 1, wherein the modulation circuit comprises: a first modulation circuit, having an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a quantization noise signal, wherein the first modulation circuit generates the first modulation signal and the quantization noise signal according to the input signal under the control of the first clock signal; as well as The second modulation circuit has an input end for receiving a quantization noise signal, a control end for receiving a first clock signal, and an output end for providing a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal. The isolation amplifier circuit according to claim 4 , wherein the first modulation circuit comprises a delta-sigma modulation circuit. 6 . The isolation amplifier circuit according to claim 4 , wherein the second modulation circuit comprises a pulse width modulation circuit, wherein a pulse width of the second modulation signal represents a quantization noise signal.

7. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: a first demodulation circuit having an input terminal for receiving the second demodulation signal and generating a demodulated quantization noise signal according to the second demodulation signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving the second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulated quantization noise signal.

8. The isolation amplifier circuit according to claim 1, wherein the demodulation circuit comprises: a first demodulation circuit having an input terminal for receiving the second demodulation signal and a second clock signal, and generating a demodulated quantization noise signal according to the second demodulation signal and the second clock signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving the second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulated quantization noise signal. 9 . The isolation amplifier circuit according to claim 7 , wherein the output signal is generated by weighted summing of the first demodulated signal and the demodulated quantization noise signal.

10. The isolation amplifier circuit according to claim 1, wherein the isolation circuit comprises: a first isolation circuit having an input terminal for receiving a second clock signal and an output terminal for providing a first clock signal, wherein the first isolation circuit generates the first clock signal according to the second clock signal; a second isolation circuit having an input end for receiving a first modulation signal and an output end for providing a first demodulation signal, wherein the second isolation circuit generates a first demodulation signal according to the first modulation signal; as well as The third isolation circuit has an input end for receiving the second modulation signal and an output end for providing the second demodulation signal. The third isolation circuit generates a second demodulation signal according to the second modulation signal.

11. An isolation amplifier circuit, comprising: A modulation circuit having an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a second modulation signal, wherein the modulation circuit samples the input signal at a frequency of the first clock signal and modulates the input signal into the first modulation signal and the second modulation signal; The first modulation signal represents the input signal, and the second modulation signal represents the quantization noise generated when the input signal generates the first modulation signal; an isolation circuit, wherein a first input terminal receives the first modulation signal, a second input terminal receives the second modulation signal, a control terminal receives a first clock signal, and generates a first demodulation signal according to the first modulation signal, generates a second demodulation signal according to the second modulation signal, and generates a second clock signal according to the first clock signal, wherein the first clock signal and the second clock signal have the same frequency and amplitude, the first demodulation signal and the first modulation signal have the same frequency and amplitude, and the second demodulation signal and the second modulation signal have the same frequency and amplitude; as well as The demodulation circuit has a first input end for receiving the first demodulation signal, a second input end for receiving the second demodulation signal, and a control end for receiving a second clock signal. The demodulation circuit generates an output signal according to the second clock signal, the first demodulation signal and the second demodulation signal.

12. The isolation amplifier circuit according to claim 11, wherein the modulation circuit comprises: a first modulation circuit, having an input terminal for receiving an input signal, a control terminal for receiving a first clock signal, a first output terminal for providing a first modulation signal, and a second output terminal for providing a quantization noise signal, wherein the first modulation circuit generates the first modulation signal and the quantization noise signal according to the input signal under the control of the first clock signal; as well as The second modulation circuit has an input end for receiving a quantization noise signal, a control end for receiving a first clock signal, and an output end for providing a second modulation signal. The second modulation circuit generates the second modulation signal according to the quantization noise signal under the control of the first clock signal.

13. The isolation amplifier circuit according to claim 11, wherein the isolation circuit comprises: a first isolation circuit having an input terminal for receiving a first clock signal and an output terminal for providing a second clock signal, wherein the first isolation circuit generates the second clock signal according to the first clock signal; a second isolation circuit having an input end for receiving a first modulation signal and an output end for providing a first demodulation signal, wherein the second isolation circuit generates a first demodulation signal according to the first modulation signal; as well as The third isolation circuit has an input end for receiving the second modulation signal and an output end for providing the second demodulation signal. The third isolation circuit generates a second demodulation signal according to the second modulation signal.

14. The isolation amplifier circuit according to claim 11, wherein the demodulation circuit comprises: a first demodulation circuit having an input terminal for receiving the second demodulation signal and generating a demodulated quantization noise signal according to the second demodulation signal; as well as The second demodulation circuit has a first input terminal for receiving the first demodulation signal, a second input terminal for receiving the demodulated quantization noise signal, and a third input terminal for receiving the second clock signal. The second demodulation circuit generates the output signal according to the second clock signal, the first demodulation signal and the demodulated quantization noise signal.

15. The isolation amplifier circuit according to claim 13, wherein: The first isolation circuit includes a first capacitor, the second isolation circuit includes a second capacitor, and the third isolation circuit includes a third capacitor.

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