Burr elimination circuit, burr elimination method and electronic equipment

Abstract

The invention provides a burr eliminating circuit, a burr eliminating method and electronic equipment. The burr eliminating circuit comprises a delay circuit, a trigger and a control circuit, the control circuit adjusts a control signal according to a first signal and a second signal, so that the control signal controls the trigger to work in a reset mode or a sampling mode, the trigger working in the reset mode does not sample the first signal, the trigger continuously outputs low level, and the trigger does not output low level. The trigger working in the sampling mode samples the first signal, and starts to output a high level from the rising edge of the second signal until the falling edge of the second signal appears, so that the signal section with the pulse width smaller than the delay time of the delay circuit in the first signal can be filtered out through the arrangement of the trigger; the signal segment with the pulse width larger than or equal to the delay time of the delay circuit in the first signal can be normally sampled and output by the trigger, so that random burrs of the first signal in the transmission process can be filtered out, and it is guaranteed that the signal is not distorted.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a burr elimination circuit, a burr elimination method and electronic equipment. Background Art

[0002] In the field of integrated circuit design such as digital isolators, isolated gate drive circuits, and wireless communications, the presence of factors such as timing errors and interference signals often causes a large number of narrow random glitches to be generated during the transmission of digital signals. The presence of random glitches will interfere with the normal transmission of digital signals. Therefore, it is usually necessary to add a glitch elimination circuit in the digital signal transmission path to filter out a large number of random glitches and ensure that the transmitted signal is not distorted. Summary of the invention

[0003] The object of the present invention is to provide a burr elimination circuit which can filter out random burrs in the process of signal transmission and ensure that the signal will not be distorted.

[0004] In order to solve the above technical problems, based on one aspect of the present invention, the present invention provides a burr elimination circuit, which includes:

[0005] A delay circuit, used for delaying the first signal and outputting it as a second signal;

[0006] A trigger, wherein the trigger has a reset mode and a sampling mode, and the trigger working in the reset mode continuously outputs a low level; the trigger working in the sampling mode starts to output a high level when the second signal generates a rising edge and the first signal is a high level, and outputs a low level when the second signal generates a falling edge;

[0007] The control circuit is used to output a control signal. When the first signal and the second signal are both at low levels, the control signal controls the trigger to operate in the reset mode; otherwise, the control signal controls the trigger to operate in the sampling mode.

[0008] Optionally, the delay circuit includes a plurality of first inverters connected in cascade, and the number of the first inverters is an even number.

[0009] Optionally, when the first signal and the second signal are both at a low level, the control signal is one of a high level and a low level; otherwise, the control signal is the other of a high level and a low level.

[0010] Optionally, when the first signal and the second signal are both at a low level, the control signal is at a high level; otherwise, the control signal is at a low level.

[0011] Optionally, the control circuit includes a second inverter, a third inverter and an AND gate, the input end of the second inverter receives the first signal, the input end of the third inverter receives the second signal, and the output end of the second inverter and the output end of the third inverter are respectively connected to two input ends of the AND gate.

[0012] Optionally, the trigger includes a D trigger, a data input terminal of the D trigger receives the first signal, a clock pulse input terminal of the D trigger receives the second signal, an output terminal of the D trigger outputs a high level or a low level, and a reset terminal of the D trigger receives the control signal.

[0013] Based on another aspect of the present invention, the present invention further provides an electronic device, which includes the glitch elimination circuit as described above.

[0014] Based on another aspect of the present invention, the present invention also provides a burr elimination method, which comprises:

[0015] Delaying the first signal and outputting it as a second signal;

[0016] When both the first signal and the second signal are at low level, a low level is output; otherwise, a high level is output when the second signal generates a rising edge and the first signal is at a high level, and a low level is output until the second signal generates a falling edge.

[0017] In the glitch elimination circuit as above, the control circuit adjusts the control signal according to the first signal and the second signal, so that the control signal controls the trigger to work in reset mode or sampling mode. The trigger working in reset mode does not sample the first signal, and the trigger continues to output a low level. The trigger working in sampling mode samples the first signal and starts to output a high level from the rising edge of the second signal until the falling edge of the second signal appears. In this way, the signal segment in the first signal whose pulse width is less than the delay time of the delay circuit can be filtered out through the setting of the trigger, and the signal segment in the first signal whose pulse width is greater than or equal to the delay time of the delay circuit can be normally sampled and output by the trigger, thereby filtering out random glitches in the first signal during transmission to ensure that the signal will not be distorted.

[0018] It should be noted that, since the electronic device includes the burr elimination circuit, the burr elimination method and the burr elimination circuit are based on the same inventive concept, and therefore the electronic device and the burr elimination method also have the same technical effects as the burr elimination circuit, which will not be described again here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0020] Figure 1 It is a schematic diagram of a burr elimination circuit in the prior art;

[0021] Figure 2 It is a timing diagram of the input signal, the input signal processed by the delay circuit, and the output signal;

[0022] Figure 3 is a schematic diagram of a glitch elimination circuit according to an embodiment of the present invention;

[0023] Figure 4 is a timing diagram of the first signal, the second signal, the control signal, and the output signal;

[0024] Figure 5 is a schematic diagram of a delay circuit according to an embodiment of the present invention;

[0025] Figure 6 is a schematic diagram of a control circuit according to an embodiment of the present invention.

[0026] In the attached figure:

[0027] 10-delay circuit; 20-trigger; 30-control circuit;

[0028] AND-AND gate; U1-first inverter; U2-second inverter; U3-third inverter. DETAILED DESCRIPTION

[0029] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0030] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] Figure 1 Schematic diagram of a glitch elimination circuit in the prior art. Figure 1 The glitch elimination circuit in the prior art includes a delay circuit 10 and an AND gate AND. The input end of the delay circuit 10 receives the input signal IN. One of the input ends of the AND gate AND is connected to the output end of the delay circuit 10. The other input end of the AND gate AND receives the input signal IN. The AND gate AND logically selects the input signal IN and the input signal IN processed by the delay circuit 10 (that is, the signal IN_delay) to generate an output signal OUT. It can be understood that the delay circuit 10 outputs the input signal IN after delaying it for a certain period of time.

[0032] Figure 2 This is a timing diagram of the input signal, the input signal processed by the delay circuit, and the output signal. Figure 2 , td is the delay time of the delay circuit 10, from Figure 2It can be seen that if the pulse width of the input signal IN is high and is less than td, it will be filtered out; if the pulse width of the input signal IN is high and is greater than td, it will not be filtered out. However, this circuit has some disadvantages. For example, the pulse width of the output signal OUT will become narrower. Figure 2 As shown, if the high level pulse width of the input signal IN is T (T>td), the pulse width of the output signal OUT is (T-td), resulting in a loss in the pulse width of the output signal OUT and signal distortion.

[0033] In view of this, an object of an embodiment of the present invention is to provide a new burr elimination circuit, which can filter out random burrs in the signal transmission process to ensure that the signal will not be distorted.

[0034] Figure 3 FIG. 1 is a schematic diagram of a glitch elimination circuit according to an embodiment of the present invention. Figure 3 An embodiment of the present invention schematically provides a glitch elimination circuit, including a delay circuit 10, a trigger 20 and a control circuit 30. The delay circuit 10 is used to delay a first signal and output it as a second signal. Here, the first signal is equivalent to Figure 1 The signal IN shown in FIG. 1 is equivalent to the second signal Figure 1 The signal IN_delay shown. The trigger 20 has two working modes: reset mode and sampling mode. The output end of the trigger 20 generates an output signal (i.e., signal OUT). The trigger 20 working in the reset mode continuously outputs a low level; the trigger 20 working in the sampling mode starts to output a high level when the second signal generates a rising edge and the first signal is at a high level, and outputs a low level until the second signal generates a falling edge. Specifically, the trigger 20 working in the sampling mode starts to sample the first signal when the second signal generates a rising edge, and when the high level of the first signal is sampled, the trigger 20 starts to output a high level. When the second signal generates a falling edge, the trigger 20 stops outputting a high level, thereby outputting a low level. In this way, the high level pulse of the first signal is sampled and output at the rising and falling edges of the second signal. The control circuit 30 outputs a control signal RST. When the first signal and the second signal are both at a low level, the control signal RST controls the trigger 20 to work in the reset mode. Otherwise, the control signal RST controls the trigger 20 to work in the sampling mode, that is, when either the first signal or the second signal is at a high level, the trigger 20 works in the sampling mode.

[0035] As for the glitch elimination circuit as above, the control circuit 30 adjusts the control signal RST according to the first signal and the second signal, so that the control signal RST controls the trigger 20 to work in the reset mode or the sampling mode. The trigger 20 working in the reset mode does not sample the first signal, and the trigger 20 continues to output a low level. The trigger 20 working in the sampling mode samples the first signal and starts to output a high level from the rising edge of the second signal until the falling edge of the second signal appears. In this way, the signal segment in the first signal whose pulse width is less than the delay time of the delay circuit 10 can be filtered out through the setting of the trigger 20, and the signal segment in the first signal whose pulse width is greater than or equal to the delay time of the delay circuit 10 can be normally sampled and output by the trigger 20, thereby filtering out random glitches in the first signal during transmission to ensure that the signal will not be distorted.

[0036] Further, when the first signal and the second signal are both at low levels, the control signal RST is one of a high level and a low level, thereby controlling the trigger 20 to work in the reset mode; otherwise (that is, when either the first signal or the second signal is at a high level), the control signal RST is the other of a high level and a low level, and the control signal RST controls the trigger 20 to work in the sampling mode. For example, in this embodiment, when both the first signal and the second signal are at low levels, the control signal RST is at a high level; when either the first signal or the second signal is at a high level, the control signal RST is at a low level.

[0037] Figure 4 is a timing diagram of the first signal, the second signal, the control signal, and the output signal. Figure 4 , td is the delay time of the delay circuit 10, from Figure 4 It can be seen that the signal segment of the first signal whose pulse width is less than td is filtered out and does not appear at the output end of the trigger 20, while the signal of the first signal whose pulse width is greater than td is not filtered out and can appear normally at the output end of the trigger 20, that is, the output signal OUT shows a high level, and the pulse width appearing at the output end of the trigger 20 is equal to the pulse width of the first signal, that is, there is no loss in the pulse width and the signal is not distorted.

[0038] Figure 5 FIG. 1 is a schematic diagram of a delay circuit according to an embodiment of the present invention. Figure 5 The delay circuit 10 includes a plurality of first inverters U1 connected in cascade, and the number of the first inverters U1 is an even number.

[0039] Figure 6 FIG. 1 is a schematic diagram of a control circuit according to an embodiment of the present invention. Figure 6The control circuit 30 includes a second inverter U2, a third inverter U3 and an AND gate AND. The input end of the second inverter U2 receives the first signal, the input end of the third inverter U3 receives the second signal, the output end of the second inverter U2 and the output end of the third inverter U3 are respectively connected to the two input ends of the AND gate AND, and the output end of the AND gate AND outputs the control signal RST.

[0040] Optionally, the trigger 20 can be a D trigger, the data input terminal (D terminal) of the D trigger receives the first signal, the clock pulse input terminal (Clk terminal) of the D trigger receives the second signal, and the second signal is used as the clock signal to control the D trigger, the output terminal (Q terminal) of the D trigger outputs a high level or a low level, and the reset terminal (Reset terminal) of the D trigger receives the control signal RST.

[0041] Based on another aspect of the present invention, the present invention also provides an electronic device, which includes the burr elimination circuit as described above, and the electronic device is, for example, a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a camcorder, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device.

[0042] Based on the same inventive concept as the above-mentioned glitch elimination circuit, an embodiment of the present invention further provides a glitch elimination method, the glitch elimination method comprising:

[0043] Delaying the first signal and outputting it as a second signal;

[0044] When both the first signal and the second signal are at low level, a low level is output; otherwise, a high level is output when the second signal generates a rising edge and the first signal is at a high level, and a low level is output until the second signal generates a falling edge.

[0045] It should be noted that those skilled in the art can further understand the glitch elimination method here based on the aforementioned glitch elimination circuit, which will not be described in detail here.

[0046] Although the present invention is disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A glitch elimination circuit, characterized in that: include: A delay circuit, used for delaying the first signal and outputting it as a second signal; A trigger, wherein the trigger has a reset mode and a sampling mode, wherein the trigger working in the reset mode continuously outputs a low level; the trigger working in the sampling mode starts to output a high level when the second signal generates a rising edge and the first signal is a high level, and outputs a low level until the second signal generates a falling edge. The control circuit is used to output a control signal. When the first signal and the second signal are both at low levels, the control signal controls the trigger to operate in the reset mode; otherwise, the control signal controls the trigger to operate in the sampling mode.

2. The glitch elimination circuit according to claim 1, characterized in that: The delay circuit includes a plurality of first inverters connected in cascade, and the number of the first inverters is an even number.

3. The glitch elimination circuit according to claim 1, characterized in that: When both the first signal and the second signal are at a low level, the control signal is one of a high level and a low level; otherwise, the control signal is the other of a high level and a low level.

4. The glitch elimination circuit according to claim 3, characterized in that: When the first signal and the second signal are both at low levels, the control signal is at a high level; otherwise, the control signal is at a low level.

5. The glitch elimination circuit according to claim 1, characterized in that: The control circuit includes a second inverter, a third inverter and an AND gate, the input end of the second inverter receives the first signal, the input end of the third inverter receives the second signal, and the output end of the second inverter and the output end of the third inverter are respectively connected to two input ends of the AND gate.

6. The glitch elimination circuit according to claim 1, characterized in that: The trigger includes a D trigger, a data input terminal of the D trigger receives the first signal, a clock pulse input terminal of the D trigger receives the second signal, an output terminal of the D trigger outputs a high level or a low level, and a reset terminal of the D trigger receives the control signal.

7. An electronic device, characterized in that: The glitch elimination circuit comprises the glitch elimination circuit according to any one of claims 1 to 6.

8. A burr elimination method, characterized in that: include: Delaying the first signal and outputting it as a second signal; When the first signal and the second signal are both at low level, outputting a low level; Otherwise, when the second signal generates a rising edge and the first signal is at a high level, a high level is output, and the low level is output when the second signal generates a falling edge.

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