Level shifting circuit and electronic device

Abstract

The present application proposes a level transfer circuit and an electronic device, which relates to but is not limited to the field of integrated circuit technology, and includes: a level shift module, which is used to output a first level signal according to a first input signal, and output a second level signal according to a second input signal; a duty cycle adjustment module, which is connected to the level shift module, and is used to adjust the duty cycle of the first level signal and output a third level signal, and adjust the duty cycle of the second level signal and output a fourth level signal; a waveform shaping module, which is connected to the duty cycle adjustment module, and is used to invert the third level signal and output a fifth level signal, and invert the fourth level signal and output a sixth level signal. The present application adjusts the waveform duty cycle of the first level signal and the second level signal output by the level shift module through the duty cycle adjustment module, so that the output fifth level signal and sixth level signal can maintain a good duty cycle under different PVTs and different operating frequencies.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a level shifting circuit and an electronic device. Background Art

[0002] In the related art, the existing level conversion circuit is composed of two NMOS tubes, two PMOS tubes and two inverters. Then, the voltage at the input end of the two inverters needs to be changed from the input end voltage of one inverter to a low voltage before the input end voltage of the other unidirectional device can be pulled up. Therefore, the circuit duty cycle will be imbalanced, and the duty cycle will become more significant with changes in process, operating voltage, temperature, operating frequency, etc. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a level shifting circuit and an electronic device, aiming to enable the level shifting circuit to maintain a good duty cycle output.

[0004] In a first aspect, an embodiment of the present application provides a level shifting circuit, comprising:

[0005] A level shift module, configured to output a first level signal according to a first input signal, and output a second level signal according to a second input signal;

[0006] a duty cycle adjustment module, connected to the level shift module, configured to adjust the duty cycle of the first level signal and output a third level signal, and to adjust the duty cycle of the second level signal and output a fourth level signal;

[0007] a waveform shaping module, connected to the duty cycle adjustment module, configured to invert the third level signal and output a fifth level signal, and invert the fourth level signal and output a sixth level signal;

[0008] The delay from the transition edge of the first input signal and the second input signal to the rising edge of the first level signal or the second level signal is constant, and the transition of the fifth level signal and the sixth level signal is triggered at the rising edge of the first level signal or the second level signal.

[0009] According to some embodiments of the present application, the level shift module is provided with a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal is used to input the first input signal, the second input terminal is used to input the second input signal, the first output terminal is used to output the first level signal, and the second output terminal is used to output the second level signal;

[0010] The duty cycle adjustment module is provided with a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal, the third input terminal is connected to the first output terminal, the fourth input terminal is connected to the second output terminal, the third output terminal is used to output the third level signal, and the fourth output terminal is used to output the fourth level signal;

[0011] The waveform shaping module is provided with a fifth input terminal, a sixth input terminal, a fifth output terminal and a sixth output terminal, the fifth input terminal is connected to the third output terminal, the sixth input terminal is connected to the fourth output terminal, the fifth output terminal is used to output the fifth level signal, and the sixth output terminal is used to output the sixth level signal.

[0012] According to some embodiments of the present application, the level shift module includes:

[0013] A first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube;

[0014] The control end of the first NMOS tube is connected to the first input end, the input end of the first NMOS tube is connected to the output end of the first PMOS tube, the control end of the second NMOS tube is connected to the second input end, the input end of the second NMOS tube is connected to the output end of the second PMOS tube, the control end of the first PMOS tube is connected to the input end of the second NMOS tube, the control end of the second PMOS tube is connected to the input end of the first NMOS tube, the output ends of the first NMOS tube and the second NMOS tube are both connected to the ground, and the input ends of the first PMOS tube and the second PMOS tube are both connected to the power supply.

[0015] According to some embodiments of the present application, the first output end is located between the first NMOS tube and the first PMOS tube, and the second output end is located between the second NMOS tube and the second PMOS tube.

[0016] According to some embodiments of the present application, the duty cycle adjustment module includes:

[0017] a third NMOS tube, a fourth NMOS tube, a third PMOS tube and a fourth PMOS tube;

[0018] The control end of the third NMOS tube is connected to the third input end, the input end of the third NMOS tube is connected to the output end of the third PMOS tube, the control end of the fourth NMOS tube is connected to the fourth input end, the input end of the fourth NMOS tube is connected to the output end of the fourth PMOS tube, the control end of the third PMOS tube is connected to the input end of the fourth NMOS tube, the control end of the fourth PMOS tube is connected to the input end of the third NMOS tube, the output ends of the third NMOS tube and the fourth NMOS tube are both connected to the ground, and the input ends of the third PMOS tube and the fourth PMOS tube are both connected to the power supply.

[0019] According to some embodiments of the present application, the duty cycle adjustment module further includes:

[0020] a first capacitor and a second capacitor;

[0021] One end of the first capacitor is connected to the control end of the third NMOS tube, and the other end is connected to the control end of the third PMOS tube; one end of the second capacitor is connected to the control end of the fourth NMOS tube, and the other end is connected to the control end of the fourth PMOS tube.

[0022] According to some embodiments of the present application, the third output end is located between the third NMOS tube and the third PMOS tube, and the fourth output end is located between the fourth NMOS tube and the fourth PMOS tube.

[0023] According to some embodiments of the present application, the waveform shaping module includes:

[0024] A first inverter, wherein an input terminal of the first inverter is connected to the fifth input terminal, and an output terminal of the first inverter is connected to the fifth output terminal.

[0025] According to some embodiments of the present application, the waveform shaping module further includes:

[0026] A second inverter, wherein the input terminal of the second inverter is connected to the sixth input terminal, and the output terminal of the second inverter is connected to the sixth output terminal.

[0027] In a second aspect, an embodiment of the present application provides an electronic device, comprising the level shifting circuit as described in the first aspect.

[0028] According to the technical solution of the embodiment of the present application, at least the following beneficial effects are achieved: the embodiment of the present application proposes a level transfer circuit and an electronic device, the circuit comprising: a level shifting module, used to output a first level signal according to a first input signal, and to output a second level signal according to a second input signal; a duty cycle adjustment module, connected to the level shifting module, used to adjust the duty cycle of the first level signal and output a third level signal, and to adjust the duty cycle of the second level signal and output a fourth level signal; a waveform shaping module, connected to the duty cycle adjustment module, used to invert the third level signal and output a fifth level signal, and invert the fourth level signal and output a sixth level signal; wherein the delay from the transition edge of the first input signal and the second input signal to the rising edge of the first level signal or the second level signal is constant, and the transition of the fifth level signal and the sixth level signal is triggered at the rising edge of the first level signal or the second level signal. Therefore, since the embodiment of the present application can adjust the waveform duty cycle of the first level signal and the second level signal output by the level shift module through the duty cycle adjustment module, the output fifth level signal and the sixth level signal can maintain a good duty cycle under different PVTs and different operating frequencies.

[0029] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0031] Figure 1 is a schematic diagram of the structure of a level shifting circuit provided by an embodiment of the present application;

[0032] Figure 2 It is a waveform diagram of a level shifting circuit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0034] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0035] In the description of this application, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0036] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.

[0037] In some cases, the existing level conversion circuit is composed of two NMOS tubes, two PMOS tubes and two inverters. Then, the voltage at the input end of the two inverters needs to be changed from the input end voltage of one inverter to a low voltage before the input end voltage of the other unidirectional device can be pulled up. Therefore, the circuit duty cycle will be imbalanced, and the duty cycle will become more significant with changes in process, operating voltage, temperature, operating frequency, etc.

[0038] Based on the above situation, the embodiments of the present application provide a level shifting circuit and an electronic device, aiming to enable the level shifting circuit to maintain a good duty cycle output.

[0039] Various embodiments of the level shifting circuit of the present application are further described below in conjunction with the accompanying drawings.

[0040] like Figure 1 As shown, Figure 1 It is a schematic diagram of the structure of a level shifting circuit provided in one embodiment of the present application.

[0041] In one embodiment, the level transfer circuit includes a level shift module 100 , a duty cycle adjustment module 200 and a waveform shaping module 300 .

[0042] It can be understood that the level shift module 100 of the embodiment of the present application is used to output a first level signal according to a first input signal, and to output a second level signal according to a second input signal.

[0043] It can be understood that the duty cycle adjustment module 200 of the embodiment of the present application is connected to the level shift module 100, and is used to adjust the duty cycle of the first level signal and output the third level signal, and adjust the duty cycle of the second level signal and output the fourth level signal.

[0044] It can be understood that the waveform shaping module 300 of the embodiment of the present application is connected to the duty cycle adjustment module 200, and is used to invert the third level signal and output a fifth level signal, and invert the fourth level signal and output a sixth level signal.

[0045] It is worth noting that since the embodiment of the present application can adjust the waveform duty cycle of the first level signal and the second level signal output by the level shift module 100 through the duty cycle adjustment module 200, the output fifth level signal and the sixth level signal can maintain a good duty cycle under different PVTs and different operating frequencies.

[0046] It can be understood that the transition of the fifth level signal and the sixth level signal is triggered by the rising edge of the first level signal or the second level signal. Under a certain PVT condition and input signal frequency, the delay from the transition edge of the first input signal and the second input signal to the rising edge of the first level signal or the second level signal is constant. Therefore, the time difference between the rising edge of the first level signal and the rising edge of the second level signal can be kept consistent with the duty cycle of the first input signal and the second input signal, and is not affected by PVT and the operating frequency, so that the output fifth level signal and the sixth level signal can maintain a good duty cycle under different PVT and different operating frequencies.

[0047] It can be understood that the above-mentioned PVT refers to process, voltage and temperature.

[0048] Specifically, in one embodiment, the level shift module 100 is provided with a first input terminal, a second input terminal, a first output terminal and a second output terminal; the duty cycle adjustment module 200 is provided with a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal; the waveform shaping module 300 is provided with a fifth input terminal, a sixth input terminal, a fifth output terminal and a sixth output terminal.

[0049] Exemplarily, the first input terminal is used to input a first input signal, the second input terminal is used to input a second input signal, the first output terminal is used to output a first level signal, and the second output terminal is used to output a second level signal; the third input terminal is connected to the first output terminal, the fourth input terminal is connected to the second output terminal, the third output terminal is used to output a third level signal, and the fourth output terminal is used to output a fourth level signal; the fifth input terminal is connected to the third output terminal, the sixth input terminal is connected to the fourth output terminal, the fifth output terminal is used to output a fifth level signal, and the sixth output terminal is used to output a sixth level signal.

[0050] Specifically, in one embodiment, the level shift module 100 includes a first NMOS transistor M1 , a second NMOS transistor M2 , a first PMOS transistor M3 , and a second PMOS transistor M4 .

[0051] Exemplarily, the control end of the first NMOS tube M1 is connected to the first input end, the input end of the first NMOS tube M1 is connected to the output end of the first PMOS tube M3, the control end of the second NMOS tube M2 is connected to the second input end, the input end of the second NMOS tube M2 is connected to the output end of the second PMOS tube M4, the control end of the first PMOS tube M3 is connected to the input end of the second NMOS tube M2, the control end of the second PMOS tube M4 is connected to the input end of the first NMOS tube M1, the output ends of the first NMOS tube M1 and the second NMOS tube M2 are both connected to the ground, and the input ends of the first PMOS tube M3 and the second PMOS tube M4 are both connected to the power supply.

[0052] It can be understood that, when the first input signal changes from a high level to a low level and the second input signal changes from a low level to a high level, the first NMOS tube M1 is in an off state, the second NMOS tube M2 is in an on state, the second NMOS tube M2 and the turned-on second PMOS tube M4 are in a competitive state, and the voltage of the second level signal will be gradually lowered. When the voltage of the second level signal is less than the first voltage threshold, the first PMOS tube M3 starts to be turned on, and the voltage of the first level signal is gradually increased, and the second PMOS tube M4 starts to be turned off; thereby obtaining the first level signal and the second level signal with imbalanced duty cycle.

[0053] It can be understood that, when the first input signal changes from a low level to a high level and the second input signal changes from a high level to a low level, the first NMOS tube M1 is in an on state, the second NMOS tube M2 is in an off state, the first NMOS tube M1 and the turned-on first PMOS tube M3 are in a competitive state, and the voltage of the first level signal will be gradually lowered. When the voltage of the first level signal is less than the second voltage threshold, the second PMOS tube M4 starts to turn on, and the voltage of the second level signal is gradually increased, and the first PMOS tube M3 starts to turn off; thereby obtaining the first level signal and the second level signal with imbalanced duty cycles.

[0054] It can be understood that the first output end is located between the first NMOS transistor M1 and the first PMOS transistor M3 , and the second output end is located between the second NMOS transistor M2 and the second PMOS transistor M4 .

[0055] Specifically, in one embodiment, the duty cycle adjustment module 200 includes a third NMOS transistor M5, a fourth NMOS transistor M6, a third PMOS transistor M7 and a fourth PMOS transistor M8.

[0056] Exemplarily, the control end of the third NMOS tube M5 is connected to the third input end, the input end of the third NMOS tube M5 is connected to the output end of the third PMOS tube M7, the control end of the fourth NMOS tube M6 is connected to the fourth input end, the input end of the fourth NMOS tube M6 is connected to the output end of the fourth PMOS tube M8, the control end of the third PMOS tube M7 is connected to the input end of the fourth NMOS tube M6, the control end of the fourth PMOS tube M8 is connected to the input end of the third NMOS tube M5, the output ends of the third NMOS tube M5 and the fourth NMOS tube M6 are both connected to the ground, and the input ends of the third PMOS tube M7 and the fourth PMOS tube M8 are both connected to the power supply.

[0057] It is understandable that the duty cycle adjustment module 200 can adjust the duty cycle of the first level signal and the second level signal with imbalanced duty cycle output by the level shift module 100 to obtain the third level signal and the fourth level signal with good duty cycle.

[0058] Specifically, in one embodiment, the duty cycle adjustment module 200 further includes a first capacitor C1 and a second capacitor C2.

[0059] Exemplarily, one end of the first capacitor C1 is connected to the control end of the third NMOS tube M5, and the other end is connected to the control end of the third PMOS tube M7; one end of the second capacitor C2 is connected to the control end of the fourth NMOS tube M6, and the other end is connected to the control end of the fourth PMOS tube M8.

[0060] It can be understood that the third output end is located between the third NMOS tube M5 and the third PMOS tube M7, and the fourth output end is located between the fourth NMOS tube M6 and the fourth PMOS tube M8.

[0061] It can be understood that, due to the coupling effect between the first capacitor C1 and the second capacitor C2, the transitions of the third level signal and the fourth level signal can occur simultaneously.

[0062] In one embodiment, the waveform shaping module 300 includes a first inverter 310 .

[0063] Exemplarily, the input terminal of the first inverter 310 is connected to the fifth input terminal, and the output terminal of the first inverter 310 is connected to the fifth output terminal.

[0064] It can be understood that the first inverter 310 is used to invert and reshape the third level signal to output a fifth level signal.

[0065] In one embodiment, the waveform shaping module 300 includes a second inverter 320 .

[0066] Exemplarily, the input terminal of the second inverter 320 is connected to the sixth input terminal, and the output terminal of the second inverter 320 is connected to the sixth output terminal.

[0067] It can be understood that the second inverter 320 is used to invert and reshape the fourth level signal to output a sixth level signal.

[0068] like Figure 2 As shown, Figure 2 It is a waveform diagram of a level shifting circuit provided in one embodiment of the present application.

[0069] Exemplarily, when the first input signal vin is at a high level and the second input signal vip is at a low level, the first NMOS tube M1 is in an on state, the second NMOS tube M2 is in an off state, the first level signal vop_1 is at a low level, the second level signal von_1 is at a high level, the fourth NMOS tube M6 is in an on state, the third NMOS tube M5 is in an off state, the fourth level signal vop_2 is pulled low by the fourth NMOS tube M6, the third PMOS tube M7 is turned on, the third level signal von_2 is pulled high, the fourth PMOS tube M8 is turned off, the fifth level signal vop is output as a low level, and the sixth level signal von is output as a high level.

[0070] Exemplarily, when the first input signal vin is at a low level and the second input signal vip is at a high level, the first NMOS tube M1 is in an off state, the second NMOS tube M2 is in an on state, the first level signal vop_1 is at a high level, the second level signal von_1 is at a low level, the fourth NMOS tube M6 is in an off state, the third NMOS tube M5 is in an on state, the third level signal von_2 is pulled low by the third NMOS tube M5, the fourth PMOS tube M8 is turned on, the fourth level signal vop_2 is pulled high, the third PMOS tube M7 is turned off, the fifth level signal vop is output as a high level, and the sixth level signal von is output as a low level.

[0071] Exemplarily, first, when the first input signal vin changes from a high level to a low level and the second input signal vip changes from a low level to a high level, the first NMOS tube M1 is turned off and the second NMOS tube M2 is turned on. Since the second NMOS tube M2 and the turned-on fourth PMOS tube M8 are in a competitive state, the second level signal von_1 will be gradually pulled down. When the voltage of the second level signal von_1 is less than the first voltage threshold, the first PMOS tube M3 starts to be turned on and gradually pulls up the voltage of the first level signal vop_1. At this time, the first level signal vop_1 and the second level signal von_1 present a duty cycle imbalance. Secondly, in the process of the voltage of the second level signal von_1 being pulled down, the fourth NMOS tube M6 is gradually turned off. Since the fourth PMOS tube M8 is also in the off state, the fourth level signal v The voltage of op_2 will not change. When the voltage of the first level signal vop_1 is pulled up, the third NMOS tube M5 is turned on. Since the third NMOS tube M5 and the third PMOS tube M7 are in a competitive state, the voltage of the third level signal von_2 will be gradually pulled down. At the same time, the fourth PMOS tube M8 starts to be turned on and gradually pulls up the voltage of the fourth level signal vop_2. The conduction strength of the third PMOS tube M7 gradually weakens. The voltage of the third level signal von_2 is further quickly pulled down, and the voltage of the fourth level signal vop_2 is also quickly pulled up. Then, the third level signal von_2 is reversely shaped by the first inverter 310 to output the fifth level signal vop of a high level, and the fourth level signal vop_2 is reversely shaped by the second inverter 320 to output the sixth level signal von of a low level.

[0072] It can be understood that, since the fourth NMOS tube M6 is in the off state during the process of gradually lowering the voltage of the third level signal von_2, when the voltage of the third level signal von_2 is less than the third voltage threshold, the fourth level signal vop_2 will be quickly pulled up. At the same time, during the process of the first level signal vop_1 becoming high, due to the coupling effect of the first capacitor C1, the fourth level signal vop_2 will be coupled to the high level at the same time, so that the conduction ability of the third PMOS tube M7 is weakened early, so that the third level signal von_2 is pulled to the low level faster, therefore, the jump of the third level signal von_2 and the fourth level signal vop_2 occurs almost simultaneously during the process of the first level signal vop_1 becoming high, so that the output of the fifth level signal vop and the sixth level signal von also jumps simultaneously, that is, when the fifth level signal vop changes from the low level to the high level, the sixth level signal von changes from the high level to the low level.

[0073] Exemplarily, first, when the first input signal vin changes from a low level to a high level and the second input signal vip changes from a high level to a low level, the first NMOS tube M1 is turned on and the second NMOS tube M2 is turned off. Since the first NMOS tube M1 and the turned-on third PMOS tube M7 are in a competitive state, the first level signal vop_1 will be gradually pulled down. When the voltage of the first level signal vop_1 is less than the second voltage threshold, the second PMOS tube M4 starts to turn on and gradually pulls up the voltage of the second level signal von_1. At this time, the first level signal vop_1 and the second level signal von_1 present a duty cycle imbalance. Secondly, in the process of the voltage of the first level signal vop_1 being pulled down, the third NMOS tube M5 is gradually turned off. Since the third PMOS tube M7 is also in the off state, the third level signal The voltage of von_2 will not change. When the voltage of the second level signal von_1 is pulled up, the fourth NMOS tube M6 is turned on. Since the fourth NMOS tube M6 and the sixth PMOS tube are in a competitive state, the voltage of the fourth level signal vop_2 will be gradually pulled down. At the same time, the third PMOS tube M7 starts to be turned on and gradually pulls up the voltage of the third level signal von_2. The conduction strength of the fourth PMOS tube M8 gradually weakens. The voltage of the fourth level signal vop_2 is further quickly pulled down, and the voltage of the third level signal von_2 is also quickly pulled up. Then, the third level signal von_2 is reversely shaped by the first inverter 310 to output the fifth level signal vop of a low level, and the fourth level signal vop_2 is reversely shaped by the second inverter 320 to output the sixth level signal von of a high level.

[0074] It can be understood that, since the third NMOS tube M5 is in the off state during the process of gradually lowering the voltage of the fourth level signal vop_2, when the voltage of the fourth level signal vop_2 is less than the fourth voltage threshold, the third level signal von_2 will be quickly pulled up. At the same time, during the process of the second level signal von_1 becoming high, due to the coupling effect of the second capacitor C2, the third level signal von_2 will be coupled to the high level at the same time, so that the conduction ability of the fourth PMOS tube M8 is weakened early, so that the fourth level signal vop_2 is pulled to the low level faster, therefore, the jump of the third level signal von_2 and the fourth level signal vop_2 occurs almost simultaneously during the process of the second level signal von_1 becoming high, so that the output of the fifth level signal vop and the sixth level signal von also jumps simultaneously, that is, when the fifth level signal vop changes from the high level to the low level, the sixth level signal von changes from the low level to the high level.

[0075] It can be understood that the first voltage threshold is the difference between the power supply voltage VCC and the threshold voltage of the first PMOS tube M3, the second voltage threshold is the difference between the power supply voltage VCC and the threshold voltage of the second PMOS tube M4, the third voltage threshold is the difference between the power supply voltage VCC and the threshold voltage of the fourth PMOS tube M8, and the fourth voltage threshold is the difference between the power supply voltage VCC and the threshold voltage of the third PMOS tube M7.

[0076] It is worth noting that, since the transition of the fifth level signal vop and the sixth level signal von is triggered by the rising edge of the first level signal vop_1 or the second level signal von_1, and due to the symmetry of the level transfer circuit, under a certain PVT condition and input signal frequency, the delay from the transition edge of the first input signal vin and the second input signal vip to the rising edge of the first level signal vop_1 or the second level signal von_1 is constant. Therefore, the time difference between the rising edge of the first level signal vop_1 and the rising edge of the second level signal von_1 can be kept consistent with the duty cycle of the first input signal vin and the second input signal vip, and is not affected by PVT and the operating frequency, so that the output fifth level signal vop and the sixth level signal von can maintain a good duty cycle under different PVT and different operating frequencies.

[0077] In addition, an embodiment of the present application further provides an electronic device, which includes the level shifting circuit of the above embodiment.

[0078] It is worth noting that since the electronic device of the embodiment of the present application includes the level transfer circuit of the above-mentioned embodiment, the specific implementation manner and technical effects of the electronic device of the embodiment of the present application can refer to the specific implementation manner and technical effects of the level transfer circuit of any of the above-mentioned embodiments.

[0079] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make various equivalent modifications or substitutions under the shared conditions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A level shifting circuit, characterized in that: include: A level shift module is provided with a first output terminal and a second output terminal, and the level shift module is used to output a first level signal according to a first input signal, and output a second level signal according to a second input signal; A duty cycle adjustment module is provided with a third input end and a fourth input end, wherein the third input end is connected to the first output end, and the fourth input end is connected to the second output end. The duty cycle adjustment module comprises a third NMOS tube, a fourth NMOS tube, a third PMOS tube and a fourth PMOS tube. The control end of the third NMOS tube is connected to the third input end, the input end of the third NMOS tube is connected to the output end of the third PMOS tube, the control end of the fourth NMOS tube is connected to the fourth input end, the input end of the fourth NMOS tube is connected to the output end of the fourth PMOS tube, the control end of the third PMOS tube is connected to the input end of the fourth NMOS tube, the control end of the fourth PMOS tube is connected to the input end of the third NMOS tube, the output ends of the third NMOS tube and the fourth NMOS tube are both connected to the ground, and the input ends of the third PMOS tube and the fourth PMOS tube are both connected to the power supply. The duty cycle adjustment module is used to adjust the duty cycle of the first level signal and output a third level signal, and to adjust the duty cycle of the second level signal and output a fourth level signal; a waveform shaping module, connected to the duty cycle adjustment module, configured to invert the third level signal and output a fifth level signal, and invert the fourth level signal and output a sixth level signal; The delay from the transition edge of the first input signal and the second input signal to the rising edge of the first level signal or the second level signal is constant, and the transition of the fifth level signal and the sixth level signal is triggered at the rising edge of the first level signal or the second level signal.

2. A level shifting circuit according to claim 1, characterized in that: The level shift module is further provided with a first input terminal and a second input terminal, the first input terminal is used to input the first input signal, the second input terminal is used to input the second input signal, the first output terminal is used to output the first level signal, and the second output terminal is used to output the second level signal; The duty cycle adjustment module is further provided with a third output terminal and a fourth output terminal, the third output terminal is used to output the third level signal, and the fourth output terminal is used to output the fourth level signal; The waveform shaping module is provided with a fifth input terminal, a sixth input terminal, a fifth output terminal and a sixth output terminal, the fifth input terminal is connected to the third output terminal, the sixth input terminal is connected to the fourth output terminal, the fifth output terminal is used to output the fifth level signal, and the sixth output terminal is used to output the sixth level signal.

3. A level shifting circuit according to claim 2, characterized in that: The level shift module comprises: A first NMOS tube, a second NMOS tube, a first PMOS tube and a second PMOS tube; The control end of the first NMOS tube is connected to the first input end, the input end of the first NMOS tube is connected to the output end of the first PMOS tube, the control end of the second NMOS tube is connected to the second input end, the input end of the second NMOS tube is connected to the output end of the second PMOS tube, the control end of the first PMOS tube is connected to the input end of the second NMOS tube, the control end of the second PMOS tube is connected to the input end of the first NMOS tube, the output ends of the first NMOS tube and the second NMOS tube are both connected to the ground, and the input ends of the first PMOS tube and the second PMOS tube are both connected to the power supply.

4. A level shifting circuit according to claim 3, characterized in that: The first output end is located between the first NMOS tube and the first PMOS tube, and the second output end is located between the second NMOS tube and the second PMOS tube.

5. A level shifting circuit according to claim 1, characterized in that: The duty cycle adjustment module also includes: a first capacitor and a second capacitor; One end of the first capacitor is connected to the control end of the third NMOS tube, and the other end is connected to the control end of the third PMOS tube; one end of the second capacitor is connected to the control end of the fourth NMOS tube, and the other end is connected to the control end of the fourth PMOS tube.

6. A level shifting circuit according to claim 2, characterized in that: The third output end is located between the third NMOS tube and the third PMOS tube, and the fourth output end is located between the fourth NMOS tube and the fourth PMOS tube.

7. A level shifting circuit according to claim 2, characterized in that: The waveform shaping module comprises: A first inverter, wherein an input terminal of the first inverter is connected to the fifth input terminal, and an output terminal of the first inverter is connected to the fifth output terminal.

8. A level shifting circuit according to claim 7, characterized in that: The waveform shaping module also includes: A second inverter, wherein the input terminal of the second inverter is connected to the sixth input terminal, and the output terminal of the second inverter is connected to the sixth output terminal.

9. An electronic device, characterized in that: Comprising the level shifting circuit as claimed in any one of claims 1 to 8.

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