Software phase-locked loop algorithm with trap filter

Abstract

This invention proposes a software phase-locked loop (PLL) algorithm with a notch filter, belonging to the field of power converters. The implementation steps are as follows: Step 1: A multiplicative phase detector is used as the PD stage to perform calculations between the input signal and the feedback signal; Step 2: A notch filter is added to filter out the second harmonic component; Step 3: The phase difference is controlled to zero by a PI control stage; Step 4: The voltage signal passing through the PI (LPF) stage is converted into a frequency signal by a voltage-controlled oscillator (VCO); Step 5: After obtaining the frequency signal, it is fed back to the phase detector via a feedback stage as a feedback signal to perform calculations with the input signal.

Description

Technical Field

[0001] This invention belongs to the field of power converters, specifically relating to a software phase-locked loop algorithm with a notch filter. Background Technology

[0002] A software phase-locked loop (SPLL) is a phase-locked loop algorithm implemented in a digital signal processor (DSP) or microcontroller. It is used to synchronize and track the frequency and phase of an input signal. SPLLs have wide applications in power electronics and communication systems, especially in power converter design, where they are used to accurately estimate the grid phase angle to achieve synchronization between electrical energy and the grid.

[0003] In a software phase-locked loop scenario, the loop filter has low-pass characteristics, which can filter out the high-frequency components of the phase detector output. When the frequency of the locked signal is high, the low-pass characteristics of the PI controller can filter out the existing double-frequency components. However, the frequency of the power grid is very low (50Hz), and the PI controller cannot achieve the ideal filtering effect. The high-frequency components output by the loop filter will affect the final performance of the PLL.

[0004] The low-pass characteristic of the PI controller is not sufficient to fully meet the requirement of filtering out components of twice the grid frequency from the phase detector output. Therefore, a method to linearize the phase detector output must be found. Summary of the Invention

[0005] In view of this, the object of the present invention is to provide a software phase-locked loop algorithm with a notch filter, which can be used to attenuate the second harmonic component of the grid voltage output from the phase detector. An adjustable notch filter can also accurately remove components of the corresponding frequency when the voltage frequency fluctuates within a small range.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] The software phase-locked loop algorithm with notch filter includes the following steps:

[0008] Step 1: Use a multiplier phase detector as the PD stage to perform calculations on the input signal and the feedback signal;

[0009] Step 2: Add a notch filter to remove the second harmonic component;

[0010] Step 3: The phase difference is controlled to be zero by a PI control circuit;

[0011] Step 4: Convert the voltage signal passing through the PI (LPF) stage into a frequency signal using a voltage-controlled oscillator (VCO);

[0012] Step 5: After obtaining the frequency signal, it is fed back to the phase detector via a feedback loop as a feedback signal to perform calculations with the input signal;

[0013] Assume the input signal is The VCO output signal is The inputs and outputs of a multiplier can be represented as:

[0014] .

[0015] .

[0016] In a dynamic situation, the two signals have different frequencies, and their instantaneous phases are:

[0017] Input signal: .

[0018] Output signal: .

[0019] Therefore, PD outputs: ,in: For signal amplitude, angular frequency, ; Output signal amplitude, VCO natural frequency .

[0020] The notch filter's structural transfer function in the s-domain is expressed as:

[0021]

[0022] in, The damping ratio of the system, C2 is the system's natural frequency. To ensure stable system operation, C2 << C1.

[0023] After discretizing the s-domain equations to the z-domain using the zeroth-order preservation method:

[0024]

[0025] T is the sampling period, and the coefficients of the notch filter can be adjusted to follow the fluctuations of the power grid frequency. The corresponding transmission energy consumption can then be expressed as:

[0026] The PI transfer function in the s-domain is expressed as:

[0027]

[0028] Where Kp is the proportional gain, Ki is the integral gain, and T is the sampling period.

[0029] After discretizing the s-domain equations to the z-domain using the zeroth-order preservation method:

[0030]

[0031] The VCO transfer function in the s-domain is expressed as:

[0032]

[0033] in For LPF output, This is the reference frequency.

[0034] After discretizing the s-domain equations to the z-domain using the zeroth-order preservation method:

[0035]

[0036] After the above processing steps, the phase information is as follows:

[0037]

[0038] in The phase is locked to the VCO output; mod is the modulo operation. This is phase information.

[0039] To improve computational speed, the integral method is used to find the sine / cosine values, defined as follows:

[0040]

[0041] For sine or cosine signals, this expression becomes:

[0042]

[0043]

[0044] Compared with existing technologies, the advantages and beneficial effects of this invention are as follows: This invention effectively attenuates the second harmonic interference problem at low frequencies, effectively reduces the amount of computation, effectively improves the computation speed, and effectively accelerates the phase-locked loop speed. Therefore, the method of this invention is well-suited for phase-locked loop tasks at low frequencies compared to traditional phase-locked loop algorithms.

[0045] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0047] Figure 1 This is a block diagram of the software phase-locked loop system of the present invention.

[0048] Figure 2 This is a flowchart of the workflow of the present invention. Detailed Implementation

[0049] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0050] The accompanying drawings are for illustrative purposes only and represent schematic diagrams, not actual physical images. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings. The same or similar reference numerals in the drawings of the embodiments of the invention correspond to the same or similar components.

[0051] This invention provides a software phase-locked loop (PLL) algorithm with a notch filter. The optimization objectives are to minimize computational workload, accurately lock the phase, and filter out second-harmonic interference. The notch filter is used to remove second-harmonic interference, increasing computational speed and phase-locking accuracy. The algorithm includes the following steps:

[0052] Step 1: Use a multiplier phase detector as the PD stage to perform calculations on the input signal and the feedback signal;

[0053] Step 2: Add a notch filter to remove the second harmonic component;

[0054] Step 3: The phase difference is controlled to be zero by a PI control circuit;

[0055] Step 4: Convert the voltage signal passing through the PI (LPF) stage into a frequency signal using a voltage-controlled oscillator (VCO);

[0056] Step 5: After obtaining the frequency signal, it is fed back to the phase detector via a feedback loop as a feedback signal to perform calculations with the input signal;

[0057] Furthermore, this invention uses MATLAB Simulink to simulate the algorithm.

[0058] The system generates a frequency of A sine wave with an initial phase of zero is used as the test signal, and the phase-locked loop algorithm is implemented by calling the MatlabFunction module.

[0059] Define two input signals u1 and u2; and an output signal y.

[0060] Define the output of the PD storage multiplier phase detector.

[0061] Define Notch to store the notch output.

[0062] Define the output of the LPF storage loop filter.

[0063] Define theta to store vector information, cos_out to store cosine, and sin_out to store sine.

[0064] In the phase detection stage of multiplication, PD = u1 * u2.

[0065] In the notch filter stage, the solution is obtained based on the discretized z-domain transfer function:

[0066]

[0067] .

[0068] Notch* represents information at different times, Notch1 represents the current information, and Notch2 represents the Notch* information for the next loop, with an initial value of 0.

[0069] Similarly, in the LPF stage, based on the discretized z-domain equations:

[0070]

[0071] .

[0072] Where LPF* represents information at different times, LPF1 represents the current information, and LPF2 represents the LPF* information for the next cycle, with an initial value of 0.

[0073] In the VCO stage, the phase information is obtained by integrating the sum of the reference signal W0 and the LPF output signal:

[0074]

[0075] Where theta* represents information at different times, theta1 represents the current information, and theta2 represents theta* information for the next cycle, with an initial value of 0.

[0076] Solving for sine and cosine values ​​using integration:

[0077]

[0078] Where cos_out * represents information at different times, cos_out1 is the current information, and cos_out2 is the cos_out* information for the next loop, with an initial value of 1.

[0079] Use within a loop Perform parameter updates and feed cos_out1 back to the multiplication phase detector as feedback input.

[0080] Furthermore, performing a modulo operation outside the loop ensures that the phase θ∈[0, 2π].

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A digital phase-locked loop algorithm with a notch filter, characterized in that: Includes the following steps: Step 1: Use a multiplier phase detector as the PD stage to perform calculations on the input signal and the feedback signal; Step 2: Add a notch filter to remove the second harmonic component; Step 3: The phase difference is controlled to be zero by a PI control circuit; Step 4: The voltage signal controlled by the PI controller is converted into a frequency signal by the voltage-controlled oscillator (VCO). Step 5: After obtaining the frequency signal, it is fed back to the multiplication phase detector via a feedback loop as a feedback signal to perform operations with the input signal; the structure of the multiplication phase detector can be represented as follows: Assume the input signal is The output signal of the voltage-controlled oscillator (VCO) is Therefore, the input and output of the multiplication phase detector can be expressed as: ； ； ； in: For signal amplitude, Angular frequency, Input the instantaneous phase angle; The output signal amplitude, It is the natural frequency of the voltage-controlled oscillator (VCO). To output the instantaneous phase angle; In a dynamic situation, the two signals have different frequencies, and their instantaneous phases are: Input signal: ; Output signal: ; Therefore, PD outputs: 。 2. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that, The transfer function of the notch filter structure in the s-domain is expressed as: ； Among them, is the damping ratio of the system, is the natural frequency of the system. To make the system work stably, it is necessary to make C2 << C1; After discretizing the s-domain equation to the z-domain using the zero-order hold method: ； T is the sampling period, and the coefficient of the notch filter is adjusted according to the fluctuation of the power grid frequency; then the corresponding transmission energy consumption can be expressed as:

3. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that, The PI transfer function in the s-domain is expressed as: ； Where: Kp is the proportional gain, Ki is the integral gain, and T is the sampling period; after discretizing the s-domain equations to the z-domain using the zero-order preservation method: 。 4. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that, The transfer function of the voltage-controlled oscillator (VCO) in the s-domain is expressed as: ； in For PI output, Using the reference frequency; after discretizing the s-domain equations to the z-domain using the zeroth-order preservation method: ； Where T is the sampling period; Phase information is ； in The phase locked to the output of the voltage-controlled oscillator (VCO), where mod represents the modulo operation. For phase information; The integral method is used to find the sine / cosine values, and the definition is: ； For sine or cosine signals, this expression becomes: ； 。

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