Transceiver capacitance reduction

Abstract

Systems, methods, and apparatus are provided for transceiver capacitance reduction. An example apparatus can include a first signal driver of a transceiver, a second signal driver of the transceiver, and an input / output (I / O) pad coupled to the first signal driver and the second signal driver. The apparatus can further include a resistor voltage divider of a plurality of resistor voltage dividers coupled to the first signal driver. The resistor voltage divider, when enabled, is capable of reducing a capacitance of the first signal driver and maintaining the reduced capacitance while the second signal driver is actively driving a signal.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices and methods, and more particularly to devices and methods for transceiver capacitance reduction. Background Art

[0002] Electronic devices (e.g., devices and systems) include various integrated circuits (ICs) (e.g., chips), such as microprocessors, controllers, memory devices, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and system-on-chip (SoC) integrated circuits, as well as various other types of digital and / or analog integrated circuits. Various ICs include input / output (I / O) circuitry that can provide an interface between ICs (e.g., to send and / or receive signals). Thus, the I / O circuitry typically includes physical pins through which signals (e.g., data) can be communicated (e.g., transmitted and / or received). Thus, in some examples, the term "I / O pin" may be used to refer to a physical pin and additional I / O circuitry (e.g., transmit driver circuitry, receiver driver circuitry, etc.) coupled thereto. I / O circuits that are configured to both transmit and receive signals are referred to as bidirectional I / O, and I / O circuits that are configured to only transmit or only receive signals are referred to as unidirectional I / O. Summary of the invention

[0003] In one aspect, the present application provides an apparatus for transceiver capacitance reduction, comprising: a first signal driver for a transceiver; a second signal driver for the transceiver; an input / output (I / O) pad coupled to the first signal driver and the second signal driver; and a resistor divider coupled to the first signal driver, the resistor divider being operable when enabled to reduce the capacitance of the first signal driver and maintain the reduced capacitance when the second signal driver is actively driving a signal.

[0004] On the other hand, the present application provides a system for transceiver capacitance reduction, comprising: an input / output (I / O) component, comprising: a first signal driver for a transceiver; a second signal driver for the transceiver; and one or more resistors coupled to the first signal driver; and control logic coupled to the I / O component, the control logic being configured to: send a first timing signal to the I / O component to enable a first portion of the one or more resistors to maintain a voltage level associated with the first transceiver at a first level when the second transceiver is actively driving a signal; and send a second timing signal to the I / O component to enable a second portion of the one or more resistors to maintain a voltage level associated with the first transceiver at a second level when the second transceiver is actively driving the signal, wherein the second level is higher than the first level.

[0005] On the other hand, the present application provides a method for reducing transceiver capacitance, comprising: enabling a resistor divider of a first signal driver of a transceiver coupled to an input / output (I / O) component to reduce and maintain a voltage level of the first signal driver of the I / O component to a first level when a second signal driver of the transceiver of the I / O component is actively driving a signal; and enabling one or more resistors coupled to the first signal driver to increase the voltage level of the first signal driver to a second level at a first rate and maintain it at the second level when the first signal driver is actively driving the signal, wherein the second level is higher than the first level. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram of a device in the form of a portion of an electronic system for reducing transceiver capacitance in accordance with several embodiments of the present disclosure.

[0007] Figure 2 is a block diagram illustrating example I / O components for reducing transceiver capacitance according to several embodiments of the present disclosure.

[0008] Figure 3 is a block diagram illustrating another example I / O component for reducing transceiver capacitance according to several embodiments of the present disclosure.

[0009] Figure 4 is a flow chart of a method for reducing transceiver capacitance according to several embodiments of the present disclosure. DETAILED DESCRIPTION

[0010] Systems, devices, and methods related to reducing transceiver capacitance are described. In a bidirectional I / O circuit, transceivers (e.g., transmitters, receivers, etc.) are attached to the same I / O pad. In some instances, the transmitter may contribute more capacitance to the I / O pad capacitance than the receiver, which may significantly degrade the performance of the receiver. For example, using a current mode logic (CML) transmitter with a large current load may result in a greater capacitance contribution from the transmitter than from the receiver.

[0011] In some approaches, extensive layout optimizations may be performed to minimize pin capacitance. Tcoil may also be added to I / O pads to separate the capacitance from the pads from the capacitance from the signal driver and enhance signal integrity. However, these approaches do not help reduce the adverse effects of the capacitance of a different signal driver (e.g., the receiver in a transmitter / receiver pair) on one signal driver (e.g., the transmitter in a transmitter / receiver pair, which may be referred to as a transceiver).

[0012] Aspects of the present disclosure address the above and other challenges associated with reducing the capacitance of a signal driver. In an embodiment of the present disclosure, adverse effects on one signal driver that would otherwise be caused by the capacitance of a different signal driver can be reduced; thereby, the performance of one signal driver is improved. The signal driver can be coupled to a resistor divider within an I / O circuit. The gate voltage of the signal driver can be reduced by the resistor divider so as to reduce the capacitance of the signal driver. The reduced capacitance of one signal driver can enhance the performance of another signal driver. For example, the capacitance of the first signal driver can be reduced when a second signal driver coupled to the first signal driver is actively driving a signal. A digital core connected to the I / O circuit can send a timing signal to remind the I / O circuit that the gate voltage of the resistor divider can be reduced.

[0013] As used herein, the singular forms "a", "an", and "the" include singular and plural referents unless the context clearly dictates otherwise. Furthermore, the word "may" is used throughout this application in a permissive sense (i.e., likely, able to) rather than in a mandatory sense (i.e., must). The term "include" and its derivatives mean "including (but not limited to)". The term "coupled" means directly or indirectly connected. Furthermore, as used herein, the terms "reduce", "reduce" and / or "reduce" (or the like) may be used interchangeably to indicate the same meaning.

[0014] The figures herein follow a numbering convention in which the first digit or digits correspond to the figure number and the remaining digits identify the element or component in the figure. Similar elements or components between different figures may be identified by using similar numerals. For example, 104 may refer to Figure 1 Component "04" in , and similar components in Figure 2 It can be marked as 204.

[0015] Similar elements within the drawings may be referenced by a hyphen and an additional number or letter. Figure 1 104-1, ..., 104-T in FIG. Such similar elements may generally be referenced without hyphens and additional numbers or letters. For example, elements 104-1, ..., 104-T may be collectively referred to as element 104. As used herein, the indicator "T" particularly with respect to reference numbers in the drawings indicates that several specific features so designated may be included. It will be appreciated that the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated in order to provide several additional embodiments of the present disclosure. In addition, it should be appreciated that the proportions and relative dimensions of the elements provided in the drawings are intended to illustrate certain embodiments of the present invention and should not be understood in a limiting sense.

[0016] Figure 11 is a block diagram of an apparatus 100 in the form of an electronic system for reducing transceiver capacitance according to several embodiments of the present disclosure. The electronic system may include a memory device and a solid state drive (SSD). The memory device is typically provided as an internal semiconductor integrated circuit system in a computer or other electronic system. There are many different types of memory, including volatile and non-volatile memory. Volatile memory may require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), etc. Non-volatile memory can provide persistent data by retaining stored data when power is not supplied and can include NAND flash memory, NOR flash memory, ferroelectric random access memory (FeRAM), and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), etc.

[0017] The memory device may be coupled to a host (e.g., a host computing device) to store data, commands, and / or instructions for use by the host during operation of a computer or electronic system. For example, during operation of a computing or other electronic system, data, commands, and / or instructions may be transferred between the host and the memory device. A controller (e.g., control logic 102) may be used to manage the transfer of data, commands, and / or instructions between the host and the memory device.

[0018] Device 100 may include control logic 102 and input / output (I / O) components 104-1, ..., 104-T (collectively referred to as "I / O 104"). Control logic 102 may be coupled to I / O 104. As used herein, "control logic" refers to a reusable unit of a processor and / or coprocessor that receives instructions and performs tasks or actions based on the received instructions. Control logic 102 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware to facilitate the operations described herein. For example, control logic 102 may send a timing signal to each I / O component 104 (e.g., may be transmitted via a clock signal). Figure 3 104) to alert the signal driver within I / O 104 of the reduction in capacitance level. In addition, control logic 102 may include dedicated circuitry in the form of an ASIC, FPGA, state machine, and / or other logic circuitry or software and / or firmware that may allow control logic 102 to communicate with I / O 104. Control logic 102 may be coupled to I / O 104 to send and / or receive signals from I / O 104.

[0019] like Figure 3 As further described in , I / O 104 may include one or more signal lines, signal drivers (e.g., transmitters, receivers, etc.), I / O pads, etc., which may receive external signals (e.g., signals received from external devices such as control logic 102), receive internal signals (e.g., signals received from I / O pads within I / O 104), and / or transmit received signals (e.g., to control logic 102 and / or I / O pads). As used herein, a signal driver may be a transmitter (e.g., Figure 3 ) or a receiver (e.g., Figure 3 Receiver 307 described in ).

[0020] Although the embodiment is not limited, the I / O 104 may form various buses (e.g., data bus, address bus, command bus, etc.) and may be placed in various locations of the electronic system. For example, the I / O components may be placed in peripheral devices (e.g., sensors, actuators, displays, etc.) of the electronic system, a host (e.g., a desktop computer, a laptop computer, a network server, a mobile device, or such computing device including a memory and a processing device), a storage system (e.g., including a memory die), etc.

[0021] In some embodiments, one or more of the I / Os 104 may be part of (e.g., form) a “port,” which may be a physical port such as a Serial Advanced Technology Attachment (SATA) port, a Peripheral Component Interconnect Express (PCIe) port, a Universal Serial Bus (USB) port, a Fibre Channel port, a Serial Attached SCSI (SAS) port, a Small Computer System Interface (SCSI) port, a Dual In-line Memory Module (DIMM) port, a NVM Express (NVMe) port, an Open NAND Flash Interface (ONFI) port, etc. Furthermore, in some embodiments, the I / Os 104 may be a (e.g., integrated) part of the controller 102 rather than a separate component independent of the controller 102.

[0022] In addition, as in Figures 2 to 3 As further described in , I / O 104 may include various circuit systems to facilitate reducing transceiver capacitance. For example, I / O 104 may include resistor circuits 108-1, ..., 108-T (collectively referred to as "resistor circuits 108"). Resistor circuits 108 may include a plurality of resistors that may form one or more resistor dividers to reduce the capacitance of a particular signal driver connected to the resistor divider. As described in Figures 2 to 3As further described in , each I / O component 104 may include one or more switches that can be used to selectively couple resistors to form a resistor divider. The switch can be placed in the resistor divider to control the capacitance of a signal driver connected to the resistor divider. The signal driver can be controlled by the output voltage of the resistor divider.

[0023] Figure 2 2 is a block diagram illustrating an example I / O component 204 (alternatively referred to as “I / O 204”) for reducing transceiver capacitance according to several embodiments of the present disclosure. I / O 204 and resistor circuit 208 may be similar to Figure 1 104 and resistor circuit 108 as described in .

[0024] I / O 204 can utilize power supplied by voltage 212 (at Figure 2 As shown in the figure, the power supplied by VVDDIO is used to operate. Figure 2 As illustrated in FIG. 1 , the I / O component 204 includes a first signal driver for a transceiver (e.g., Figure 2 205), a second signal driver of the transceiver (e.g., Figure 2 Receiver 207 shown as "RX" in FIG. 1 ). As used herein, the term 'transceiver' generally refers to an input signal driver (e.g., a receiver) or an output signal driver (e.g., a transmitter) of an I / O component. Furthermore, as used herein, the term "transmitter" may alternatively be referred to as a "transmit driver," "output signal driver," etc. Furthermore, the term "receiver" may alternatively be referred to as a "receiver driver," "input signal driver," etc. As used herein, the term 'transmitter' may alternatively be referred to as a "transmit driver," "output signal driver," etc. Figure 2 , the transmitter 205 as an output signal driver is operable to drive a signal (e.g., received from the outside) to an I / O pad (e.g., I / O pad 206), and the receiver 207 as an input signal driver is operable to drive a signal received from an I / O pad (e.g., I / O pad 206). Tcoils 231-1 and 231-2 (collectively referred to as Tcoil nodes 231) may be connected to the I / O pad 206 to distinguish the capacitance from the I / O pad 206 from the capacitance from the signal drivers 205, 207 and to enhance signal integrity.

[0025] The signal drivers of the I / Os may be coupled to and / or include resistor circuits, such as resistor circuits 208-1 and 208-2, respectively. Figure 2 2 , transmitter 205 is coupled to resistor circuit 208 - 1 , and receiver 207 is coupled to resistor circuit 208 - 2 .

[0026] Each resistor circuit 208 may include a resistor that can form at least one resistor divider (e.g., Figure 3 The resistors (eg, Figure 3 208-3). These resistors, when enabled, are operable to reduce the capacitance of the corresponding signal driver, which can improve the performance of another signal driver when the corresponding signal driver is actively driving a signal. For example, at least when the receiver 207 is actively driving a signal, the resistor circuit 208-1 is operable to reduce the capacitance of the transmitter 205 so as to prevent interference with the performance of the receiver 207, which would otherwise occur due to the capacitance (e.g., parasitic capacitance) of the transmitter 205 being high enough to cause the interference. Vice versa, at least when the transmitter 205 is actively driving a signal, the resistor circuit 208-2 is operable to reduce the capacitance of the receiver 207 so as to prevent interference with the performance of the transmitter 205, which would otherwise occur due to the capacitance (e.g., parasitic capacitance) of the receiver 207 being high enough to cause the interference.

[0027] The voltage level of one signal driver 205 or 207 that has been reduced and / or maintained at a reduced level to cause a reduced capacitance may be restored to an increased level, which may cause an increase in capacitance of the signal driver 205 or 207. For example, the resistor circuit 208-1 may be operable to increase a voltage level associated with the transmitter 205 (which is maintained at a reduced level when the receiver 207 is actively driving a signal) to allow the transmitter 205 to actively drive a signal having an increased voltage level. Vice versa, the resistor circuit 208-2 may be operable to increase a voltage level associated with the receiver 207 (which is maintained at a reduced level when the transmitter 205 is actively driving a signal) to allow the receiver 207 to actively drive a signal having an increased voltage level.

[0028] can be controlled by slave control logic (e.g. Figure 2The control logic 102 in the I / O 204 may control when to reduce (e.g., decrease) the capacitance of the respective signal drivers 205, 207 by using timing signals sent by the control logic 102 in the I / O 204. For example, the control logic may send a first timing signal (e.g., having a first voltage level) to enable resistors (e.g., belonging to the respective resistor circuits 208-1 or 208-2 and forming a resistor voltage divider) to reduce the capacitance of the respective signal drivers 205, 207. Subsequently, the control logic may send a second timing signal (e.g., having a second voltage level) to enable resistors (belonging to the respective resistor circuits 208-1 and 208-2 and including one or more resistors that do form a resistor voltage divider) to increase (e.g., at a faster rate) the voltage level of the respective signal drivers 205, 207. These timing signals may be sent interchangeably to the I / O 204 in a manner that allows for fast switching (alternatively referred to as "turnaround time") between different sets of resistors and activation of different signal drivers 205, 207 without delay.

[0029] In some embodiments, the control logic may completely disable the resistor circuits 208-1, 208-2 to cause the I / O 204 to have additional resistors (eg, Figure 3 208-1 and 208-3) are not selectively enabled or disabled. Thus, in this example, the I / O 204 can operate without further adjusting the voltage levels of the signal drivers 205, 207 via the respective resistor circuits 208-1, 208-2. If operating the I / O 204 with the functionality provided by the resistor circuits 208-1, 208-2 does not allow for rapid switching between activation of the different signal drivers 205, 207 without significant delay, the resistor circuits 208-1, 208-2 can be completely disabled during operation of the I / O 204.

[0030] Figure 3 304 for reducing transceiver capacitance according to several embodiments of the present disclosure. Transmitter 305, receiver 307, I / O pad 306, resistor circuit 308, Tcoil node 331 (shown as "TCOIL"), and VVDDIO 312 may be similar to Figure 2 205, receiver 207, I / O pad 206, resistor circuit 208, Tcoil node 231, and VVDDIO 212 are illustrated in FIG. As used herein, both the transmitter and the receiver may be referred to as “signal drivers,” and the term “first signal driver” may refer to the transmitter and the term “second signal driver” may refer to the receiver (or vice versa).

[0031] As Figure 2Compared to the transmitter 205 described in Figure 3 Transmitter 305 is further described in detail in Figure 3 As described in FIG. 1 , the transmitter 305 includes a termination circuit (in Figure 3 , and the cascode device 325, respectively, for receiving complementary data signals (in Figure 3 305 is a complementary metal oxide semiconductor (CMOS) based transmission gate switch shown as “P TX Data” and “N TX Data” in FIG. 306 . In some embodiments, transmitter 305 may be a current mode logic (CML) buffer. Figure 3 The resistor circuit 308 is further described in detail in FIG. Figure 3 As illustrated in FIG. 3 , resistor circuit 308 includes resistors 321 - 2 , 321 - 3 , a resistor divider 322 , CMOS switches 326 and 327 , and at least a portion of ESD circuit 315 - 1 , such as resistor 321 - 1 .

[0032] As in Figure 3 As illustrated, the transmitter 305 and the receiver 307 are coupled to electrostatic discharge (ESD) circuits 315-1 and 315-2, respectively. Although embodiments are not so limited, the ESD circuits may include ESD protection diodes, transient voltage suppression (TSV) diodes, etc., as shown with respect to the ESD circuit 315-1. The ESD protection circuits 315-1 and 315-2 provide protection to the signal drivers 305, 307, respectively, from damage that occurs due to ESD events.

[0033] I / O component 304 further includes resistors 321-2 and 321-3, which are connected in series or in parallel with resistor 321-1 of ESD protection circuit 315-2, respectively, to transmitter 305. Resistors 321-2 and 321-3 can be selectively enabled along with resistor 321-1 in response to a timing signal, which can be received from control logic (e.g., a controller) coupled to I / O component 304 via timing signal line 320. Figure 1 In other words, the control logic may determine when to send a timing signal to selectively enable resistor 321; thereby, selectively increasing or decreasing the voltage level of transmitter 305.

[0034] Resistors 321-2 and / or 321-3 (collectively, resistors 321) may be selectively enabled to increase and / or decrease the voltage level of transmitter 305. Resistors 321-2 and / or 321-3 may be enabled to switch the voltage level from an operating level (e.g., at which the corresponding signal driver is expected to actively drive the signal) to a reduced voltage level. Enabling resistors 321-2 and / or 321-3 (while resistor 321-1 remains enabled) may reduce the time required for the voltage level to switch between the operating level and the reduced level (e.g., the RC time constant). Some of resistors 321 may form a resistor divider in which the constituent resistors are connected in series. For example, resistors 321-1 and 321-2 connected in series to transmitter 305 (e.g., its cascode gate 324-1) may form resistor divider 322. As used herein, "enabling" one or more resistors and / or resistor dividers means allowing current to flow through the "enabled" resistors and / or resistor dividers.

[0035] When enabled, resistor divider 322 can reduce and maintain the level of capacitance associated with transmitter 305 at a particular level (e.g., a reduced level). For example, resistor divider 322 can reduce the voltage level of cascode gate 324-1 of transmitter 305 when enabled, which further reduces the capacitance level of transmitter 305, which is maintained at a higher level. At least when resistor divider 322 is enabled, the reduced capacitance level is maintained.

[0036] like Figure 3 , additional resistor 321-3 is connected in parallel with resistor 321-1 (e.g., connected to transmitter 305, such as cascode device 325). Additional resistor 312-3 can be enabled with resistor 321-1 to reduce the RC time constant associated with increasing the voltage level across cascode device 325 (e.g., to VDDA) (e.g., increasing to VDDA). Thus, additional resistor 321-3 enabled with first resistor 321-1 can increase the voltage level across cascode device 325 at a faster rate than the rate at which resistor 321-1 would otherwise be used alone to increase the voltage level, which can improve turnaround time. Resistors 321-2 and 321-3 can be enabled in an alternate manner such that resistors 321-2 and 321-3 are enabled one at a time. Thus, resistor 321-2 may be enabled to lower the voltage level of transmitter 305, while resistor 321-3 may be enabled to increase the voltage level of transmitter 305. When either resistor 321-2 or resistor 321-3 is enabled, resistor 321-1 may remain enabled.

[0037] As in Figure 3, resistor divider 322 is coupled to cascode device 325 within transmitter 305. As used herein, the term "cascode device" refers to an amplifier used to enhance the performance of transmitter 305. The cascode device may be a metal oxide semiconductor (MOS) device. In this illustration, cascode device 325 includes a cascode gate 324-1 and a common source transistor 324-2 arranged in a manner to enhance the performance of transmitter 305. Resistor 321 may interact with cascode device 325 through cascode gate 324-1 to increase or decrease the gate voltage of transmitter 305 (e.g., the voltage across cascode gate 324-1).

[0038] In one example, reducing the gate voltage of cascode device 325 may further “turn off” cascode device 325 (e.g., to place cascode device 325 in a high impedance state). In another example, increasing the gate voltage of cascode device 325 may further “turn on” cascode device 325 to enhance the performance of transmitter 305. The gate voltage in transmitter 305 may be set (e.g., determined) by the respective values ​​of resistors 321-1 and 321-2 of resistor divider 322.

[0039] Resistor 321 may be selectively enabled depending on whether transmitter 305 or receiver 307 is actively driving a signal (e.g., a signal indicating data, address, command, etc.) and / or whether transmitter 305 or receiver 307 is desired to actively drive the signal. For example, when receiver 307 is actively driving a signal, resistor divider 322 (e.g., including first resistor 321-1 and second resistor 321-2) may be enabled (e.g., to reduce the capacitance of cascode device 325). Alternatively, when transmitter 305 is actively driving a signal, third resistor 321-3 may be enabled (e.g., to increase the voltage level of cascode device 325). In both cases, first resistor 321-1 is continuously turned on to enable both the first signal driver and the second signal driver.

[0040] Switch 326 is operable to enable / disable resistor 321-2 within resistor divider 322, while switch 327 is operable to enable / disable resistor 321-3. For example, a specific timing signal (e.g., having a first voltage level and / or a first polarity) from control logic 102 may selectively activate CMOS switch 326 (while disabling switch 327) to enable resistor divider 322. For example, a specific timing signal (e.g., having a second voltage level and / or a second polarity) from control logic 102 may selectively activate switch 327 (while disabling switch 326) to enable resistor 321-3. Although embodiments are not so limited, switches 326 and / or 327 may be complementary metal oxide semiconductor (CMOS) based transmission gate switches. One of switches 326, 327 may be a P-type metal oxide semiconductor logic (PMOS) switch, while the other switch 326, 327 may be an N-channel metal oxide semiconductor (NMOS) switch. For example, switch 327 may be a PMOS switch and switch 326 may be an NMOS switch.

[0041] Figure 4 430 is a flow chart of a method for reducing transceiver capacitance according to several embodiments of the present disclosure. The method as illustrated by flow chart 430 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. Although shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At 432, a device coupled to an input / output (I / O) component (eg, at each Figures 1 to 3 307) to reduce and maintain the voltage level of the first signal driver of the transceiver of the I / O component at the first level when the second signal driver of the transceiver of the I / O component (e.g., the receiver 207, 307 or the transmitter 205, 305) is actively driving a signal (e.g., a signal indicating data, which is alternatively referred to as a "data signal"). Figure 3As illustrated, lowering the voltage level of the first signal driver 205, 305 may be similar to lowering the voltage level of (e.g., the voltage across) the cascode gate 324-1 of the transmitter 305. In some embodiments, the resistor divider 322 coupled to the first signal driver 205, 305 may be enabled by activating a first complementary metal oxide semiconductor (CMOS) switch 326 coupled to the resistor divider 322. Additionally, one or more resistors 321-1, 321-3 coupled to the first signal driver 305 may be disabled when the second signal driver 307 is actively driving a signal.

[0043] At 434, one or more resistors (e.g., resistors 321-1 and 321-3) coupled to the first signal driver 205, 305 may be enabled to increase the voltage level of the first signal driver 205, 305 to a second level at a first rate and maintain at the second level when the first signal driver 205, 305 is actively driving a signal. Figure 3 As illustrated, raising the voltage level of the first signal driver 205, 305 may be similar to increasing the voltage level of the cascode gate 324-1 of the transmitter 305 (e.g., the voltage across the cascode gate 324-1). The second level may be higher than the first level. In some embodiments, one or more resistors 321-1, 321-3 coupled to the first signal driver 205, 305 may be enabled by activating a second CMOS switch 327 coupled to the resistor divider 322. Furthermore, the resistor divider 322 coupled to the first signal driver 205, 305 may be disabled when the first signal driver 205, 305 is actively driving a signal.

[0044] In some embodiments, the resistor divider 322 may include a first resistor (e.g., resistor 321-1) and a second resistor (e.g., resistor 321-2). In addition, the one or more resistors may include a first resistor 321-1 and a third resistor (e.g., resistor 321-3). In this example, when the third resistor 321-3 is maintained disabled, the first resistor 321-1 may be enabled to increase the voltage level of the first signal driver 205, 305 to a second level and maintain it at the second level at a second rate when the first signal driver 205, 305 is actively driving a signal, wherein the second rate is faster than the first rate.

[0045] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It should be appreciated that the above description has been made in an illustrative and non-restrictive manner. After reviewing the above description, those skilled in the art will understand the combination of the above embodiments and other embodiments not explicitly described herein. The scope of one or more embodiments of the present disclosure includes other applications using the above structures and processes. Therefore, the scope of one or more embodiments of the present disclosure should be determined with reference to the attached claims and the full range of equivalents enjoyed by such claims.

[0046] In the foregoing detailed description, some features are grouped in a single embodiment for the purpose of simplifying the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the disclosed embodiments of the disclosure must use more features than those explicitly recited in each claim. Rather, as the appended claims reflect, the subject matter of the invention lies in less than all the features of a single disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device for reducing capacitance of a transceiver, comprising: A first signal driver (205; 305) of the transceiver; A second signal driver (207; 307) of the transceiver; an input / output I / O pad (206; 306) coupled to the first signal driver and the second signal driver; and A resistor divider (322) coupled to the first signal driver, the resistor divider when enabled is operable to reduce a capacitance of the first signal driver and maintain the reduced capacitance when the second signal driver is actively driving a signal.

2. The apparatus according to claim 1, wherein: The resistor voltage divider includes a first resistor (321-1) and a second resistor (321-2); and The apparatus further includes a third resistor (321-3) coupled in parallel with the first resistor.

3. The apparatus of claim 2, wherein the first resistor and the second resistor are enabled in parallel to reduce capacitance of the first signal driver. 4 . The apparatus of claim 2 , wherein the first resistor is enabled together with the third resistor to reduce an RC time constant associated with increasing a voltage level of the first signal driver.

5. The apparatus of claim 2, wherein the second resistor and the third resistor are coupled to different complementary metal oxide semiconductor (CMOS) switches (326, 327) to be enabled one at a time.

6. The apparatus according to claim 5, wherein: The second resistor is coupled to an N-channel metal oxide semiconductor (NMOS) switch (326); and The third resistor is coupled to the second CMOS switch (327) corresponding to a P-type metal oxide semiconductor logic (PMOS) switch.

7. The apparatus of claim 2, wherein: The device further includes an electrostatic discharge (ESD) circuit (315-1), the first resistor being located in the electrostatic discharge (ESD) circuit; and The second resistor and the third resistor are coupled to the ESD circuit.

8. The apparatus of any one of claims 1 to 7, wherein the resistor divider is operable to reduce a gate voltage of a cascode device (325) of the first signal driver at least when the second signal driver is actively driving the signal.

9. A system for transceiver capacitance reduction, comprising: Input / output I / O components (104-1, ..., 104-T), which include: A first signal driver (205; 305) of the transceiver; a second signal driver (207; 307) of the transceiver; and one or more resistors (321-1, 321-2, 321-3) coupled to the first signal driver; and A control logic (102) coupled to the I / O component, the control logic being configured to: sending a first timing signal to the I / O component to enable a first portion (321-1, 321-2) of the one or more resistors to maintain a voltage level associated with the first transceiver at a first level when the second transceiver is actively driving a signal; and A second timing signal is sent to the I / O component to enable a second portion (321-3) of the one or more resistors to maintain a voltage level associated with the first transceiver at a second level when the second transceiver is actively driving the signal, wherein the second level is higher than the first level.

10. The system of claim 9, wherein: The first portion of the one or more resistors further includes first and second resistors (321-1, 321-2) corresponding to a resistor divider (322) operable to reduce a voltage level of the first signal driver to the first level; and The second portion of the one or more resistors further includes a first resistor and a third resistor (321-3) that operates with the first resistor to increase the voltage level of the first signal driver to the second level at a first rate.

11. The system of claim 10, wherein the control logic is configured to send a disable signal to: maintaining the second resistor disabled when a voltage level associated with the first signal driver is reduced to and maintained at a third level, wherein the third level is higher than the first level; and Maintaining the third resistor disabled to increase the voltage level of the first signal driver to the second level at a second rate while the voltage level associated with the first signal driver is increased to and maintained at the second level, wherein the first rate is faster than the second rate.

12. The system of claim 10, wherein the first resistor and the second resistor are connected in series to the first signal driver.

13. The system of claim 10, wherein the control logic is configured to: sending the first timing signal to activate a first complementary metal oxide semiconductor (CMOS) switch (326) coupled to the resistor divider to further enable the resistor divider; and The second timing signal is sent to activate a second CMOS switch (327) coupled to the third resistor to further enable the first resistor and the third resistor.

14. A method for reducing transceiver capacitance, comprising: enabling a resistor divider (332) coupled to a first signal driver (205; 305) of a transceiver of an input / output (I / O) component to reduce and maintain a voltage level of the first signal driver of the I / O component to a first level when a second signal driver (207; 307) of the transceiver of the I / O component is actively driving a signal; as well as One or more resistors (321-1, 321-2, 321-3) coupled to the first signal driver are enabled to cause the voltage level of the first signal driver to increase to and remain at a second level at a first rate when the first signal driver is actively driving the signal, wherein the second level is higher than the first level.

15. The method according to claim 14, wherein: The resistor voltage divider includes a first resistor (321-1) and a second resistor (321-2); and The one or more resistors include the first resistor and a third resistor (321-3); The method further includes enabling the first resistor while maintaining the third resistor disabled to cause a voltage level of the first signal driver to increase to and remain at the second level at a second rate when the first signal driver is actively driving the signal, wherein the second rate is faster than the first rate.

16. A method according to claim 14 or claim 15, wherein: Enabling the resistor divider coupled to the first signal driver further comprises activating a first complementary metal oxide semiconductor (CMOS) switch (326) coupled to the resistor divider; and Enabling the one or more resistors coupled to the first signal driver further includes activating a second CMOS switch (327) coupled to the resistor divider.

17. The method according to claim 14 or claim 15, further comprising: disabling the resistor divider coupled to the first signal driver when the first signal driver is actively driving a signal; as well as When the second signal driver is actively driving a signal, the one or more resistors coupled to the first signal driver are disabled.

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