Novel FPGA (Field Programmable Gate Array) demodulation and decoding method and system for AC (Alternating Current) B code

Abstract

The invention provides a novel FPGA demodulation and decoding method and system for an AC B code, and relates to the technical field of signal processing. The system is realized through an FPGA, and comprises an AD sampling module, a digital low-pass filtering module, an AC B code demodulation module, and a DC B code decoding and phase compensation module. Wherein the AD sampling module converts an analog signal into a digital signal, the digital low-pass filtering module completes high-frequency noise filtering, the alternating-current B code demodulation module completes code pattern demodulation to obtain a direct-current B code signal, and the direct-current B code decoding and phase compensation module completes B code time interpretation, PPS pulse per second extraction and phase compensation; the method is realized through an FPGA (Field Programmable Gate Array), has the characteristics of strong anti-interference capability, low logic resource consumption and high decoding precision, and is suitable for alternating current B code signals with different amplitudes and modulation ratios; compared with the prior art, hardware cost is reduced, hardware design is simplified, logic implementation is simple, and system precision, reliability and universality are improved.

Description

Technical Field

[0001] The invention relates to the technical field of signal processing, in particular to a novel FPGA demodulation and decoding method and system for alternating current B code. Background Art

[0002] Time synchronization is an important basic guarantee in the fields of power, telecommunications, national defense and military. With the continuous development of science and technology, the accuracy of time synchronization is increasingly required, and various timing methods are constantly emerging. Timing equipment uses satellite system receivers such as Beidou, GPS or GLONASS, and outputs synchronization signals such as IRIG-B, 1PPS+TOD as reference time sources to provide time synchronization for automation equipment.

[0003] IRIG originated from the time synchronization technology of the US military shooting range. The shooting range time system provides a time reference for spacecraft or satellite launches, conventional weapons testing and measurement and control systems. IRIG-B is one of the IRIG series codes. It carries rich information, has good anti-interference and strong versatility.

[0004] There are two types of standard time formats used by IRIG-B codes in the shooting range: one is the parallel time code format, which is rarely used now; the other is the serial time code format. IRIG-B serial time code uses two code types in actual transmission: IRIG-B (AC) code and IRIG-B (DC) code. When the transmission distance is relatively long, IRIG-B (AC) code is used, and when the transmission distance is short, IRIG-B (DC) code is used.

[0005] For the IRIG-B (AC) code, the IRIG standard requires the analog signal output amplitude to reach 10Vp-p. After being transmitted through a long-distance channel, the AC B code signal amplitude has been greatly weakened, and may introduce greater environmental noise, and may even cause signal distortion and generate bit errors.

[0006] Traditional IRIG-B (AC) code demodulation and decoding method: complex hardware design, poor adaptability, high requirements for signal amplitude and signal-to-noise ratio, demodulation and decoding are easily affected by noise, and it is difficult to provide highly reliable and high-precision reference time information.

[0007] Therefore, there is an urgent need for a new FPGA demodulation and decoding method and system for AC B code to solve the above technical problems. Summary of the invention

[0008] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a new FPGA demodulation and decoding method and system for AC B code, aiming to reduce the complexity of hardware design, achieve adaptability and anti-interference, and improve the versatility and reliability of AC B code signals with different amplitudes and modulation ratios.

[0009] The purpose of the present invention is achieved through the following technical solutions:

[0010] On the one hand, the present invention provides a novel FPGA demodulation and decoding system for AC B code, which performs AC B code demodulation and decoding by setting system modules on FPGA and cooperating with each other through the system modules; wherein,

[0011] The system modules include an AD sampling module, a digital low-pass filtering module, an AC B code demodulation module, a DC B code decoding and phase compensation module;

[0012] The AD sampling module is used to perform AD sampling on the input analog AC B code, convert the analog signal into a digital signal, and obtain a digital AC B code;

[0013] The digital low-pass filter module is used to perform FIR digital low-pass filtering on the digital AC B code to filter out high-frequency sampling noise and environmental noise;

[0014] The AC B code demodulation module is used to perform code type demodulation on the filtered digital AC B code to complete the conversion from digital AC B code to digital DC B code;

[0015] The DC B code decoding and phase compensation module completes B code time interpretation, PPS second pulse extraction and phase compensation according to digital DC B code conversion.

[0016] As a further solution, the FIR digital low-pass filtering is performed by a multi-order Chebyshev window filter.

[0017] As a further solution, the multi-order Chebyshev window filter is a 110-order Chebyshev window filter, and the passband is set to 2 kHz and the stopband is set to 20 kHz.

[0018] On the other hand, the present invention provides a novel FPGA demodulation and decoding method for AC B code, which is applied to a novel FPGA demodulation and decoding system for AC B code as described in any one of the above items, and the AC B code is demodulated and decoded by the following steps:

[0019] Step 1: Perform AD sampling on the input analog AC B code through the AD sampling module, convert the analog signal into a digital signal, and obtain a digital AC B code;

[0020] Step 2: Perform FIR digital low-pass filtering on the digital AC B code through a digital low-pass filtering module to filter out high-frequency sampling noise and environmental noise; wherein, the FIR digital low-pass filtering is performed using a multi-order Chebyshev window filter;

[0021] Step 3: demodulate the filtered digital AC B code through the AC B code demodulation module to complete the conversion from digital AC B code to digital DC B code;

[0022] Step 4: The DC B code decoding and phase compensation module completes B code time interpretation, PPS pulse per second extraction and phase compensation according to the digital DC B code conversion.

[0023] As a further solution, step 3 is performed as follows:

[0024] Step 21: Obtain the latest N cycles of digital AC B code; wherein the digital AC B code is a sine wave signal;

[0025] Step 22: Find the peak value V of the digital AC B code in each cycle peak , and obtain the peak sequence

[0026] Step 23: Through the peak sequence Calculate the judgment reference value to obtain the judgment reference value V of the current cycle ref ;

[0027] Step 24: Perform binary classification judgment on the current cycle digital AC B code; wherein the peak value V peak If it is greater than the judgment reference value V ref , then output the high value; otherwise, output the low value;

[0028] Step 25: completing the conversion of the current cycle digital AC B code to digital DC B code by performing binary classification judgment of the current cycle digital AC B code;

[0029] Step 26: When the next cycle arrives, repeat steps 21 to 25 to complete the judgment reference value V ref The update and different cycle digital AC B code to digital DC B code conversion.

[0030] As a further solution, in step 21, the number of cycles N is greater than or equal to 9; wherein the value of N is proportional to the computing power support of the FPGA or is set to a fixed value.

[0031] As a further solution, the decision base value calculation: find the peak sequence The maximum value V peak-max and minimum value V peak-min , calculate the maximum value V peak-max and minimum value V peak-min The average value of V ref .

[0032] As a further solution, in step 4, the DC B code decoding module sets the pulse width of the reference bit to 8ms, the pulse width of the position identifier to 8ms, the pulse width of the high bit value to 5ms, and the pulse width of the low bit value to 2ms, and time-decodes the digital DC B code through IRIG-B encoding to obtain a B code time signal.

[0033] As a further solution, phase compensation is used to offset the comprehensive delay; the comprehensive delay includes peak signal delay, transmission link and hardware delay, FIR low-pass filter delay and other logic implementation delays; wherein, the peak signal delay is one quarter of the period of the sine wave signal.

[0034] Compared with the related art, the novel FPGA demodulation and decoding method and system of AC B code provided by the present invention has the following advantages:

[0035] 1. The hardware design of the solution architecture of the present invention is simple, all functions are completed by FPGA, there is no need to specially design analog low-pass filtering and AD sampling circuits, and the hardware cost is low.

[0036] 2. The present invention uses FIR digital low-pass filtering to filter out environmental noise and sampling noise interference in IRIG-B (AC) code digital signals, and has strong anti-interference ability; the digital low-pass filter is designed and implemented by FPGA, and has the advantages of low filter order and low logic resource consumption.

[0037] 3. The present invention can perform code demodulation, phase compensation and time decoding, and all functions are realized by FPGA. It has the characteristics of low logic resource consumption, easy algorithm implementation, short delay, high decoding accuracy and reliability, and has adaptive ability to decode IRIG-B (AC) code signals of different amplitudes (0.1V~10V) and modulation ratios (2:1~6:1), and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of the structure of a novel FPGA demodulation and decoding system for AC B code provided by the present invention;

[0039] Figure 2 A schematic diagram of the steps of a novel FPGA demodulation and decoding method for AC B code provided by the present invention;

[0040] Figure 3 A schematic diagram of the IRIG-B waveform provided by the present invention;

[0041] Figure 4 A schematic diagram of the IRIG-B encoding method provided by the present invention;

[0042] Figure 5A schematic diagram for comparing the waveforms of the IRIG-B (AC) alternating current code and the IRIG-B (DC) direct current code provided by the present invention;

[0043] Figure 6 This is a schematic diagram of a conversion decision example provided by the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] See also Figures 1 to 6 The present invention provides a novel FPGA demodulation and decoding system for AC B code, which performs AC B code demodulation and decoding by setting system modules on FPGA and cooperating with each other through the system modules; its purpose is to solve the problems of traditional IRIG-B (AC) code demodulation and decoding method, such as complex hardware design, poor adaptive ability, high requirements on signal amplitude and signal-to-noise ratio, susceptibility of demodulation and decoding to noise interference, and difficulty in providing highly reliable and high-precision reference time information.

[0046] For example, the invention application with publication number: CN102420609A discloses an AC B code decoding method, which first filters the IRIG-B AC analog signal through an analog low-pass filter, then uses an AD sampling circuit to sample the AC B code signal after analog filtering, and then uses a high-order digital filter to perform digital low-pass filtering on the sampled digital signal, and finally performs code type demodulation, time decoding and phase compensation on the filtered digital signal to achieve IRIG-B (AC) code demodulation and decoding.

[0047] However, the AC B code decoding method proposed in this invention has a relatively complex hardware design, requiring the design of analog low-pass filtering and AD sampling circuits, resulting in relatively high hardware costs; the FPGA demodulation and decoding algorithm implemented by this method is relatively complex in design, consumes a large amount of logic resources, and has a relatively large implementation delay.

[0048] For another example, the invention application with publication number: CN 101493674 A discloses an AC B code decoding method, which first measures the amplitude of the IRIG-B AC analog signal and compares it with a reference level to generate a square wave signal, thereby determining the positive zero crossing point of the analog signal; using the positive zero crossing point of the analog signal, sample the AC analog signal 250 microseconds after the positive zero crossing point, and compare and determine it with a preset reference amplitude to generate a DC signal; finally, complete the interpretation of the DC B code and output a second pulse signal and time information.

[0049] However, the AC B code demodulation and decoding method proposed in the invention has a complex hardware design and requires the design of a comparator and an AD sampling circuit, resulting in a high hardware cost. The method must preset a reference level and a reference amplitude, and has poor usability and versatility. For AC B codes with different amplitudes and adjustment ratios, both the reference level and the reference amplitude need to be re-debugged and set. The demodulation result of this method is easily affected and has poor accuracy.

[0050] The IRIG-B (AC) code uses a 1kHz sine wave as the carrier frequency for amplitude modulation and time codes the most recent 1s. It is a time serial code with one frame per second. Each code element has a width of 10ms and each frame includes 100 code elements. The code elements are pulse width coded. The waveform is shown below: Figure 3 As shown; where the reference bit and position identifier are 8ms wide, the pulse widths of binary "1" and "0" are 5ms and 2ms, and the IRIG-B encoding method is as follows Figure 4 shown.

[0051] like Figure 4 As shown, the B code time format contains days, hours, minutes, and seconds; the information bits are 7 seconds, 7 minutes, 6 hours, and 10 days, and their positions are between P0 and P5. P6 to P0 contain other control information. Among them, the "seconds" information: the 1st, 2nd, 3rd, 4th, 6th, 7th, and 8th code elements; the "minutes" information: the 10th, 11th, 12th, 13th, 15th, 16th, and 17th code elements; the "hours" information: the 20th, 21st, 22nd, 23rd, 25th, 26th, and 27th code elements; the 5th, 14th, and 24th code elements are index marks with a width of 2ms. Hours, minutes, and seconds are all represented by BCD codes, with the low bit in front, the high bit in the back, and the ones bit in front and the tens bit in the back.

[0052] IRIG-B (DC) code is the signal of IRIG-B (AC) code before modulation, and its data frame definition is exactly the same. The waveform comparison of IRIG-B (AC) code and IRIG-B (DC) code is as follows: Figure 5 shown.

[0053] In view of the shortcomings of the existing AC B code demodulation and decoding technology, the present invention provides a new FPGA demodulation and decoding method for AC B code. The method has the characteristics of simple hardware design, strong anti-noise ability, low FPGA logic resource consumption, high decoding accuracy and reliability, and has adaptive ability to decode AC B code signals with different amplitudes and modulation ratios, and has strong versatility. The architecture is as follows Figure 1 shown.

[0054] like Figure 2 As shown, the novel FPGA demodulation and decoding method of AC B code proposed by the present invention includes the following 4 steps:

[0055] Step 1: Perform AD sampling on the input analog AC B code through the AD sampling module, convert the analog signal into a digital signal, and obtain a digital AC B code;

[0056] Step 2: Perform FIR digital low-pass filtering on the digital AC B code through a digital low-pass filtering module to filter out high-frequency sampling noise and environmental noise; wherein, the FIR digital low-pass filtering is performed using a multi-order Chebyshev window filter;

[0057] Step 3: demodulate the filtered digital AC B code through the AC B code demodulation module to complete the conversion from digital AC B code to digital DC B code;

[0058] Step 4: The DC B code decoding and phase compensation module completes B code time interpretation, PPS pulse per second extraction and phase compensation according to the digital DC B code conversion.

[0059] The sampling function in step 1 is implemented by the ADC function of the FPGA, which performs AD sampling on the IRIG-B (AC) code and converts the analog signal into a digital signal. For example, the AD sampling frequency is 1MHz and the resolution is 14bit. The higher the AD sampling frequency, the higher the resolution, and the higher the hardware and computing requirements. We can select the appropriate value.

[0060] The digital low-pass filter module in step 2 adopts a 110-order Chebyshev window filter, and sets the passband of the FIR digital filter to 2kHz and the stopband to 20KHz to meet the B-code filtering requirements;

[0061] The AC B code demodulation module in step 3 has the advantages of simple implementation, low consumption of logic resources, small delay and strong versatility;

[0062] The specific demodulation steps are as follows:

[0063] Find the peak value V of the current cycle of the IRIG-B (AC) code digital signal (1kHz sine wave signal) after digital low-pass filtering peak The peak point judgment of the sine wave signal is completed by using the opposite polarity on both sides of the peak. The left side of the peak increases monotonically, and the right side of the peak decreases monotonically.

[0064] We need to obtain the most recent N cycles of digital AC B code, where the range of N value is limited and N needs to be greater than or equal to 9. The reason is to find the correct judgment benchmark. The peak sequence needs to have a peak corresponding to the number 1 and a peak corresponding to 0. The DC B code has a code element of 10ms, and the pulse width may be 8ms, 5ms, and 2ms. Therefore, at least 9 consecutive sine wave cycles must be sampled to ensure that there is a peak corresponding to 1 and a peak corresponding to 0 in the peak sequence.

[0065] The larger the value of N, the higher the resolution, the greater the amount of calculation, and the greater the demand for FPGA computing power; therefore, we need to choose an appropriate value for N, such as dynamically setting it in direct proportion to the computing power support of the FPGA, or setting it to a fixed value to balance the computing power and resolution requirements.

[0066] Therefore, in a specific embodiment, we set N to 10 and save the peak values ​​of the most recent 10 cycles of the sinusoidal digital signal. Take the maximum and minimum values ​​of the peak values ​​of the last 10 cycles and determine the reference value V ref is the mean of the maximum and minimum values ​​of the peak.

[0067] Each time the peak value V of the current cycle is found peak ,Will Update to Then Update to Update to V peak Update to Complete the update of the digital signal peak value storage of the latest 10 cycles; then complete the update of the maximum and minimum values ​​of the peak values ​​of the latest 10 cycles; finally complete the update of the judgment reference value.

[0068] Among them, the judgment reference value (V ref )The calculation process is as follows:

[0069] Each time the AC sinusoidal signal is found to have a peak value V in the most recent cycle peak After that, update

[0070] Find again The maximum value V peak-max and minimum value V peak-min .

[0071] Finally, calculate the judgment reference value V ref , which is equal to V peak-max and V peak-min The mean of .

[0072] If the peak value of the AD sampled sinusoidal digital signal in the current cycle is greater than the decision reference value, "1" is output; if the peak value is less than the decision reference value, "0" is output, completing the conversion from IRIG-B (AC) code to IRIG-B (DC) code. The specific implementation is as follows: Figure 6 As shown;

[0073] The conversion time from IRIG-B (AC) code to IRIG-B (DC) code is when the peak of the current sinusoidal signal is found. Therefore, the converted IRIG-B (DC) code has a quarter cycle (250us) delay, plus the transmission link and hardware delay, FIR filter delay and other parts of the logic implementation delay, to complete the delay compensation of the PPS second pulse.

[0074] Note: The AD sampling function of the present invention is implemented by using an FPGA with ADC function. It can be replaced by designing a hardware AD sampling circuit to implement the sampling function, and transmitting the sampled digital signal to the FPGA for processing. The use of an AD sampling chip can further increase the sampling rate and improve the AC B code demodulation and decoding accuracy.

[0075] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A new FPGA demodulation and decoding system for AC B code, characterized in that: By setting up system modules on FPGA, and cooperating with each other to perform AC B code demodulation and decoding; The system modules include an AD sampling module, a digital low-pass filtering module, an AC B code demodulation module, a DC B code decoding and phase compensation module; The AD sampling module is used to perform AD sampling on the input analog AC B code, convert the analog signal into a digital signal, and obtain a digital AC B code; The digital low-pass filter module is used to perform FIR digital low-pass filtering on the digital AC B code to filter out high-frequency sampling noise and environmental noise; The AC B code demodulation module is used to perform code type demodulation on the filtered digital AC B code to complete the conversion of the digital AC B code to the digital DC B code; The DC B code decoding and phase compensation module completes B code time interpretation, PPS second pulse extraction and phase compensation according to digital DC B code conversion.

2. The novel FPGA demodulation and decoding system of AC B code according to claim 1 is characterized in that: The FIR digital low-pass filtering is performed by a multi-order Chebyshev window filter.

3. The novel FPGA demodulation and decoding system of AC B code according to claim 2 is characterized in that: The multi-order Chebyshev window filter is a 110-order Chebyshev window filter, and the passband is set to 2 kHz and the stopband is set to 20 kHz.

4. A novel FPGA demodulation and decoding method for AC B code, applied to a novel FPGA demodulation and decoding system for AC B code as claimed in any one of claims 1 to 3, characterized in that: The AC B code is demodulated and decoded through the following steps: Step 1: Perform AD sampling on the input analog AC B code through the AD sampling module, convert the analog signal into a digital signal, and obtain a digital AC B code; Step 2: Perform FIR digital low-pass filtering on the digital AC B code through a digital low-pass filtering module to filter out high-frequency sampling noise and environmental noise; wherein, the FIR digital low-pass filtering is performed using a multi-order Chebyshev window filter; Step 3: demodulate the filtered digital AC B code through the AC B code demodulation module to complete the conversion from digital AC B code to digital DC B code; Step 4: The DC B code decoding and phase compensation module completes B code time interpretation, PPS pulse per second extraction and phase compensation according to the digital DC B code conversion.

5. The novel FPGA demodulation and decoding method of AC B code according to claim 4 is characterized in that: Step 3 is performed as follows: Step 21: Obtain the latest N cycles of digital AC B code; wherein the digital AC B code is a sine wave signal; Step 22: Find the peak value V of the digital AC B code in each cycle peak , and obtain the peak sequence Step 23: Through the peak sequence Calculate the judgment reference value to obtain the judgment reference value V of the current cycle ref ; Step 24: Perform binary classification judgment on the current cycle digital AC B code; wherein the peak value V peak If it is greater than the judgment reference value V ref , then output the high value; otherwise, output the low value; Step 25: completing the conversion of the current cycle digital AC B code to digital DC B code by performing binary classification judgment of the current cycle digital AC B code; Step 26: When the next cycle arrives, repeat steps 21 to 25 to complete the judgment reference value V ref The update and different cycle digital AC B code to digital DC B code conversion.

6. The novel FPGA demodulation and decoding method of AC B code according to claim 5 is characterized in that: In step 21, the number of cycles N is greater than or equal to 9; wherein the value of N is proportional to the computing power support of the FPGA or is set to a fixed value.

7. The novel FPGA demodulation and decoding method of AC B code according to claim 5 is characterized in that: Calculation of decision reference value: Find the peak sequence The maximum value V peak-max and minimum value V peak-min , calculate the maximum value V peak-max and minimum value V peak-min The average value of V ref .

8. The novel FPGA demodulation and decoding method of AC B code according to claim 5 is characterized in that: In step 4, the DC B code decoding module sets the pulse width of the reference bit to 8ms, the pulse width of the position identifier to 8ms, the pulse width of the high bit value to 5ms, and the pulse width of the low bit value to 2ms, and performs time decoding on the digital DC B code through the IRIG-B coding method to obtain the B code time signal.

9. The novel FPGA demodulation and decoding method of AC B code according to claim 5 is characterized in that: Phase compensation is used to offset the comprehensive delay; the comprehensive delay includes peak signal delay, transmission link and hardware delay, FIR low-pass filter delay and other logic implementation delays; wherein the peak signal delay is one quarter of the period of the sine wave signal.

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