Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a mold laminated structure on the substrate, wherein the mold laminated structure comprises a plurality of mold layers and a plurality of supporting layers which are alternately laminated along the direction far away from the substrate, and a first sacrificial layer and a second sacrificial layer which are laminated above the top supporting layer along the direction far away from the substrate; wherein the etching selection ratios of the first sacrificial layer, the second sacrificial layer and the supporting layer are different; patterning the mold laminated structure to form a grid pattern; removing the second sacrificial layer; forming a conductive structure in the grid pattern; removing the first sacrificial layer to expose the head of the conductive structure; forming a supplementary support layer covering the head of the conductive structure and the top support layer; and patterning the supplementary support layer and each support layer, and removing each mold layer to form a support structure. Structural distortion can be avoided, and device performance is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] With the development of semiconductor technology, the size of semiconductor devices is getting smaller and smaller, and the requirements for semiconductor manufacturing technology are also increasing. Memory is a commonly used semiconductor storage device in computers, which consists of many repeated storage cells. Each storage cell can include a capacitor and a transistor.

[0003] However, as the size of semiconductors decreases, the aspect ratio of capacitor holes in the capacitor manufacturing process increases, and due to the poor etching selectivity between materials, the capacitor holes formed by etching are prone to distortion, causing defects such as short circuits in the subsequently formed capacitors, reducing the reliability of the capacitors. Therefore, how to optimize the performance of capacitors has become an urgent problem to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the semiconductor problems in the prior art, which can at least avoid structural distortion and improve device performance.

[0005] In order to achieve the above objectives, according to some embodiments, one aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] A mold stacking structure is formed on the substrate, wherein the mold stacking structure includes multiple mold layers and multiple support layers alternately stacked in a direction away from the substrate, and a first sacrificial layer and a second sacrificial layer stacked in a direction away from the substrate and located above the top support layer; wherein the etching selectivity ratios of the first sacrificial layer, the second sacrificial layer and the support layer are all different;

[0008] Graphically stack the mold structure to form a grid pattern;

[0009] removing the second sacrificial layer;

[0010] forming a conductive structure within the grid pattern;

[0011] removing the first sacrificial layer to expose the head of the conductive structure;

[0012] forming a supplementary support layer covering the head of the conductive structure and the top support layer;

[0013] Graphically supplement the support layer and each support layer, and remove each mold layer to form a support structure.

[0014] In some embodiments, after exposing the head of the conductive structure and before forming a supplementary supporting layer covering the head of the conductive structure and the top supporting layer, the method for preparing the semiconductor structure further includes: etching the head of the conductive structure so that the cross-sectional area of ​​the head gradually decreases in a direction away from the substrate.

[0015] In some embodiments, the head of the conductive structure is processed using a radical etching process.

[0016] In some embodiments, the thickness of the top support layer is less than the thickness of the second top support layer; and the sum of the thickness of the top support layer and the first sacrificial layer is greater than or equal to the thickness of the second top support layer.

[0017] In some embodiments, patterning the mold stack structure to form a grid pattern includes:

[0018] forming a pattern transfer layer on the second sacrificial layer, wherein the pattern transfer layer has a first mask pattern;

[0019] The mold stack structure is dry-etched based on the first mask pattern to form a grid pattern.

[0020] In some embodiments, forming a conductive structure in a grid pattern includes:

[0021] forming a conductive material layer filling the grid pattern and covering the first sacrificial layer;

[0022] Dry-etching the conductive material layer to remove the conductive material layer above the first sacrificial layer to form a conductive structure; the conductive structure includes conductive parts respectively located in each grid in the grid pattern;

[0023] The first sacrificial layer is removed by a wet etching process.

[0024] In some embodiments, the supplemental support layer is made of the same material as the top support layer.

[0025] In some embodiments, the material of the first sacrificial layer includes silicon oxide; the material of the second sacrificial layer includes polysilicon; and the material of the supporting layer includes silicon nitride.

[0026] In some embodiments, the supplementary support layer and each support layer are patterned, and each mold layer is removed to form a support structure, including:

[0027] forming a photoresist pattern layer on the supplementary support layer; the photoresist pattern layer has a second mask pattern;

[0028] Based on the second mask pattern, the support layer in the mold stacking structure is patterned from top to bottom in sequence, and based on the patterned support layer, the mold layer corresponding to the lower surface thereof is removed; wherein the supplementary support layer and the top support layer are patterned synchronously.

[0029] In some embodiments, the supplementary support layer and the top support layer are patterned using a dry etching process, and the openings after the patterning of the supplementary support layer and the top support layer expose a side wall of the conductive structure corresponding to the head and a portion of the top surface connected to the side wall.

[0030] In some embodiments, the conductive structure includes conductive portions respectively located in each grid of the grid pattern; the conductive portions are first electrodes; and the method for preparing the semiconductor structure further includes:

[0031] A dielectric layer conformally covering the sidewall of the first electrode and a second electrode covering the dielectric layer are formed in the removed areas of the support layer and the mold layer.

[0032] According to some embodiments, another aspect of the present application provides a semiconductor structure, which includes a substrate, a conductive structure and a supporting structure, wherein the conductive structure includes a plurality of conductive parts distributed in a grid on the substrate; the supporting structure is prepared by a preparation method of a semiconductor structure as in any of the above embodiments; the supporting structure includes: a plurality of supporting layers spaced apart in a direction away from the substrate, and a supplementary supporting layer located on the top supporting layer; wherein each supporting layer and the supplementary supporting layer are located between corresponding adjacent conductive parts, and the supplementary supporting layer also covers at least a portion of the top surface of the corresponding conductive part.

[0033] In some embodiments, a cross-sectional area of ​​a head portion of each conductive portion gradually decreases in a direction away from the substrate.

[0034] In some embodiments, the sum of the thicknesses of the top support layer and the supplemental support layer is greater than the thickness of the next top support layer.

[0035] In some embodiments, the conductive portion is a first electrode; the semiconductor structure further includes a dielectric layer and a second electrode, the dielectric layer conformally covers the sidewall corresponding to the first electrode; and the second electrode covers the dielectric layer.

[0036] The embodiments of the present disclosure may or at least have the following advantages:

[0037] In the embodiment of the present disclosure, since the etching selectivity ratios of the first sacrificial layer, the second sacrificial layer, and the supporting layer are all different, when the mold stacking structure is patterned, the grid pattern can maintain a good morphology during the transfer from the second sacrificial layer to the first sacrificial layer and from the first sacrificial layer to each supporting layer, so that the mold stacking structure after patterning will not be distorted, avoiding defects such as short circuits in the subsequently formed devices, and improving the reliability of the capacitor. In addition, after removing the first sacrificial layer and exposing the head of the conductive structure, a supplementary supporting layer covering the head of the conductive structure and the top supporting layer is formed, which can reduce the thickness of the mold stacking structure while ensuring the height of the conductive structure, so as to reduce the depth-to-width ratio of the grid pattern, thereby reducing the etching difficulty of the patterned mold stacking structure, which is beneficial to the optimization of the subsequent device process technology. In addition, by etching the head of the conductive structure, the cross-sectional area of ​​the head gradually decreases in the direction away from the substrate, so as to increase the process window and further reduce the process difficulty of preparing the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 Figures (a) to (f) are schematic diagrams of structures obtained in different steps of a method for preparing a capacitor;

[0040] Figure 2 A flowchart of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0041] Figure 3 It is a schematic cross-sectional view of a structure obtained in step 311 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0042] Figure 4 It is a schematic cross-sectional view of a structure obtained in step 312 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0043] Figure 5 It is a schematic cross-sectional view of a structure obtained in step 313 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0044] Figure 6 It is a schematic cross-sectional view of a structure obtained in step 314 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0045] Figure 7It is a schematic cross-sectional view of a structure obtained in step 315 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 8 It is a schematic cross-sectional view of a structure obtained in step 316 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0047] Fig. 9 It is a schematic cross-sectional view of a structure obtained in step 317 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0048] Fig.10 It is a schematic cross-sectional view of a structure obtained in step 32 of the method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0049] Fig.11 It is a schematic cross-sectional view of a structure obtained in step 40 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0050] Fig.12 It is a schematic cross-sectional view of a structure obtained in step 51 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Fig.13 It is a schematic cross-sectional view of a structure obtained in step 52 of the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Fig.14 It is a schematic cross-sectional view of a structure obtained in step 60 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Fig.15 It is a schematic cross-sectional view of a structure obtained in step 61 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Fig.16 It is a schematic cross-sectional view of a structure obtained in step 70 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0055] Fig.17 It is a schematic cross-sectional view of a structure obtained in step 81 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0056] Fig.18 It is a cross-sectional schematic diagram of a structure obtained in step 82 of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Fig.19 In a method for preparing a semiconductor structure provided in an embodiment of the present disclosure, Fig.18 The structure shown is an enlarged schematic cross-sectional view of the Z region of the structure obtained by executing step 90.

[0058] Description of reference numerals:

[0059] 1. substrate; 2. mold stack structure; 2a. grid pattern; 3. mold layer; 301. first mold layer; 302. second mold layer; 4. support layer; 4a. support structure; 401. bottom support layer; 402. middle support layer; 403. top support layer; 41. supplementary support layer; 411. photoresist pattern layer; 411a. first mask pattern; 51. first sacrificial layer; 52. second sacrificial layer; 6. conductive structure; 61. conductive material layer; 62. conductive part; 7. first mask stack; 71. Pattern transfer layer; 71a. First mask pattern; 72. First hard mask layer; 73. Second hard mask layer; 74. First spin-coated hard mask layer; 75. First silicon oxynitride layer; 76. First photoresist layer; 8. Second mask stack; 81. First silicon oxide layer; 82. Second spin-coated hard mask layer; 83. Second silicon oxynitride layer; 84. Third spin-coated hard mask layer; 85. Third silicon oxynitride layer; 86. Second silicon oxide mask layer; 87. Second photoresist layer; 91. Dielectric layer; 92. Second electrode. DETAILED DESCRIPTION

[0060] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0061] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0062] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0063] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0064] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0065] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0066] Please refer to Figure 1 In the current capacitor manufacturing process, the aspect ratio of the capacitor hole increases with the increase of the semiconductor size, and due to the poor etching selectivity between the support layer and the first sacrificial layer, when the pattern of the first sacrificial layer is transferred to the capacitor hole formed in the support layer, distortion is easily generated in the support layer, causing the conductive parts subsequently formed in the capacitor hole to be disconnected from each other, thereby reducing the reliability of the device.

[0067] In view of the deficiencies in the above-mentioned related technologies, the present application provides a semiconductor structure and a method for preparing the same, the details of which will be described in subsequent embodiments.

[0068] According to some embodiments, the present disclosure provides a method for preparing a semiconductor device structure. As an example, the semiconductor device structure can be used to form a capacitor, for example, it can be used as a capacitor in a memory, and the capacitor in the memory is used to store data, but it is not limited to this. The semiconductor device structure provided in the embodiment of the present application can also be used as other structures.

[0069] Please refer to Figure 2 In some embodiments, the method for preparing a semiconductor structure may include the following steps:

[0070] S10: providing a substrate;

[0071] S20: forming a mold stacking structure on the substrate, the mold stacking structure comprising a plurality of mold layers and a plurality of support layers alternately stacked in a direction away from the substrate, and a first sacrificial layer and a second sacrificial layer stacked in a direction away from the substrate and located above the top support layer; wherein the first sacrificial layer, the second sacrificial layer, and the support layer have different etching selectivity ratios;

[0072] S30: patterning the mold stack structure to form a grid pattern;

[0073] S40: removing the second sacrificial layer;

[0074] S50: forming a conductive structure in the grid pattern;

[0075] S60: removing the first sacrificial layer to expose the head of the conductive structure;

[0076] S70: forming a supplementary support layer covering the head of the conductive structure and the top support layer;

[0077] S80: Graphically supplement the support layer and each support layer, and remove each mold layer to form a support structure.

[0078] In the preparation method of the semiconductor structure of the above-mentioned embodiment, since the etching selectivity ratios of the first sacrificial layer, the second sacrificial layer and the supporting layer are different, when the mold stack structure is patterned, the grid pattern can maintain a good morphology during the process of transferring from the second sacrificial layer to the first sacrificial layer and from the first sacrificial layer to each supporting layer, so that the mold stack structure after patterning will not be distorted, thereby avoiding defects such as short circuits in subsequently formed devices and improving the reliability of the capacitor.

[0079] Furthermore, after removing the first sacrificial layer and exposing the head of the conductive structure, a supplementary support layer is formed to cover the head of the conductive structure and the top support layer. This can reduce the thickness of the mold stack structure while ensuring the height of the conductive structure, thereby reducing the aspect ratio of the grid pattern and alleviating the difficulty of etching the graphic mold stack structure, which is beneficial to the optimization of subsequent device process technology.

[0080] In some embodiments, the thickness of the top support layer is less than that of the second top support layer; the sum of the thickness of the top support layer and the first sacrificial layer is greater than or equal to the thickness of the second top support layer, which can further reduce the thickness of the mold stacking structure to reduce the aspect ratio of the grid pattern.

[0081] In some embodiments, step S30, patterning the mold stack structure to form a grid pattern, includes:

[0082] S31: forming a pattern transfer layer on the second sacrificial layer, wherein the pattern transfer layer has a first mask pattern;

[0083] S32: dry-etching the mold stack structure based on the first mask pattern to form a grid pattern.

[0084] In some embodiments, step S50, forming a conductive structure in the grid pattern, includes:

[0085] S51: forming a conductive material layer filling the grid pattern and covering the first sacrificial layer;

[0086] S52: performing dry etching on the conductive material layer to remove the conductive material layer above the first sacrificial layer to form a conductive structure; the conductive structure includes conductive parts respectively located in each grid in the grid pattern;

[0087] The first sacrificial layer is removed by a wet etching process.

[0088] In some embodiments, after exposing the head of the conductive structure in step S60, and before forming a supplementary support layer covering the head of the conductive structure and the top support layer in step S70, the method for preparing the semiconductor structure further includes:

[0089] S61: etching the head of the conductive structure so that the cross-sectional area of ​​the head gradually decreases in a direction away from the substrate, so as to increase the process window and further reduce the process difficulty of preparing the semiconductor structure.

[0090] In some embodiments, the head of the conductive structure is processed using a radical etching process.

[0091] In some embodiments, step S80, patterning the supplementary support layer and each support layer, and removing each mold layer to form a support structure, includes:

[0092] S81: forming a photoresist pattern layer on the supplementary supporting layer; the photoresist pattern layer has a second mask pattern;

[0093] S82: Based on the second mask pattern, the support layers in the mold stacking structure are patterned sequentially from top to bottom, and based on the patterned support layers, the mold layers corresponding to the lower surfaces thereof are removed; wherein the supplementary support layers and the top support layers are patterned synchronously.

[0094] In some embodiments, the supplementary support layer and the top support layer are patterned using a dry etching process, and the openings after the patterning of the supplementary support layer and the top support layer expose a side wall of the conductive structure corresponding to the head and a portion of the top surface connected to the side wall.

[0095] In some embodiments, the conductive structure includes conductive portions respectively located in each grid of the grid pattern; the conductive portions are first electrodes; and the method for preparing the semiconductor structure further includes:

[0096] S90: forming a dielectric layer conformally covering the sidewall of the first electrode and a second electrode covering the dielectric layer in the removed area of ​​the support layer and the mold layer.

[0097] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0098] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiments, Figure 3 To understand some embodiments of the present application.

[0099] The present disclosure does not specifically limit the material of the substrate 1. For example, the material of the substrate 1 may be metal, such as metal tungsten.

[0100] Please refer to Figure 3 In step S20, a mold stacking structure 2 is formed on the substrate 1. The mold stacking structure 2 includes multiple mold layers 3 and multiple support layers 4 alternately stacked in a direction away from the substrate 1. The mold layer 3 will be removed in the subsequent process. The function of the support layer 4 is to serve as a support frame after the mold layer 3 is removed to improve the mechanical strength of the structure when the capacitor is subsequently manufactured. The number of mold layers 3 and support layers 4 can be set according to the height required for the subsequent capacitor. The number of stacked layers can be 1 to 10 layers or more. For example, the number of mold layers 3 and support layers 4 can be 2 to 5 layers respectively. In the embodiment of the present disclosure, the mold layer 3 is 2 layers and the support layer 4 is 3 layers for exemplary description.

[0101] It should be noted that the support layer 4 and the mold layer 3 are made of different materials, and in the same etching process, for example, in the same etchant, the corrosion rates of the two are different. Specifically, in the same etching process, the etching rate of the mold layer 3 is greater than the etching rate of the support layer 4, so that when the mold layer 3 is completely removed, the support layer 4 is completely retained.

[0102] For example, a multi-layer mold layer 3 and a multi-layer support layer 4 that are alternately stacked in a direction away from the substrate 1 can be formed by chemical vapor deposition or physical vapor deposition, and the chemical vapor deposition process can include one or more of normal pressure chemical vapor deposition, low pressure chemical or plasma enhanced chemical vapor deposition. For example, a low pressure chemical vapor deposition method can be used to form a multi-layer mold layer 3 and a multi-layer support layer 4 that are alternately stacked in a direction away from the substrate 1. The low pressure chemical vapor deposition method has good step coverage, composition and structure controllability. The use of the low pressure chemical vapor deposition method can increase the deposition rate and output, and reduce the process cost. The low pressure chemical vapor deposition method does not require a carrier gas, thereby reducing particle contamination.

[0103] For example, after each mold layer 3 or support layer 4 is formed, a preset cleaning process can be performed. The preset cleaning process can include a wet cleaning process and a dry cleaning process. The wet cleaning process uses specific chemical liquids and deionized water to clean the wafer surface without causing damage. Wet cleaning mainly includes RCA cleaning method, dilute chemical method, IMEC cleaning method or single wafer cleaning method, etc. For example, the single wafer cleaning method not only has a better cleaning effect, but also can reduce the consumption of chemicals and improve the cost-effectiveness of the wafer through the recycling of chemical liquids and deionized water during the cleaning process.

[0104] For example, the support layer 4 may be a silicon nitride layer or a silicon oxynitride layer, and the mold layer 3 may be a silicon oxide layer. Since the etching selectivity between silicon oxide and silicon nitride is relatively high, the mold layer 3 can be better removed in subsequent processes to avoid residual mold layer 3.

[0105] In some embodiments, the thickness of the top support layer 403 is less than the thickness of the second top support layer 402; the sum of the thickness of the top support layer 403 and the first sacrificial layer 51 is greater than or equal to the thickness of the second top support layer 402, which can further reduce the thickness of the mold stacking structure 2 to reduce the aspect ratio of the grid pattern 2a.

[0106] Please continue to refer to Figure 3 In step S20, the mold stack structure 2 also includes a first sacrificial layer 51 and a second sacrificial layer 52 stacked above the top support layer 403 in a direction away from the substrate 1; wherein the etching selectivity ratios of the first sacrificial layer 51, the second sacrificial layer 52 and the support layer 4 are different.

[0107] For example, the first sacrificial layer 51 may be a silicon oxide layer, and the second sacrificial layer 52 may be a polysilicon layer. Since the etching selectivity between silicon oxide and polysilicon is relatively high, a better morphology can be retained when the mold stack structure 2 is subsequently patterned.

[0108] Please refer to Figures 3 to 10 In some embodiments, step S30, patterning the mold stack structure 2 to form a grid pattern 2a, includes:

[0109] S31: Figures 3 to 9 As shown, a pattern transfer layer 71 is formed on the second sacrificial layer 52, and the pattern transfer layer 71 has a first mask pattern 71a;

[0110] S32: Fig.10 As shown, the mold stack structure 2 is dry-etched based on the first mask pattern 71a to form a grid pattern 2a.

[0111] Wherein, step S31 may include:

[0112] S311: Figure 3 As shown, a first mask stack 7 is formed on the surface of the substrate 1, and the first mask stack 7 may include a pattern transfer layer 71, a first hard mask layer 72, a second hard mask layer 73, a first spin-on hard mask layer 74, and a first silicon oxynitride layer 75 sequentially deposited on the surface of the substrate 1, and a photoresist layer is formed on the first mask stack 7, and the photoresist layer is exposed and developed to form a first pattern in the photoresist layer, thereby forming a first photoresist layer 76;

[0113] For example, the first spin-on hard mask layer 74 can be formed by a spin coating process; for example, the first spin-on hard mask layer 74 can be an insulating layer of a carbon-hydrogen (CxHy) system, which can include silicon hard mask materials, carbon hard mask materials, and organic hard mask materials, etc.

[0114] For example, the photoresist used in the first photoresist layer 76 may be a positive photoresist or a negative photoresist, and the development method used in the first photoresist layer 76 may be a positive development method or a negative development method.

[0115] S312: Figure 4 As shown, the first spin-on hard mask layer 74 and the first silicon oxynitride layer 75 are etched based on the first photoresist layer 76 to transfer the first pattern to the spin-on hard mask layer and the first silicon oxynitride layer 75, and remove the first photoresist layer 76;

[0116] S313: Figure 5 As shown, a first silicon oxide layer 81 is deposited on the sidewalls and top surfaces of the first spin-on hard mask layer 74 and the first silicon oxynitride layer 75;

[0117] S314: Figure 6 As shown, the structure obtained by the back-etching step 313 is removed to remove the second hard mask layer 73 and the part of the first silicon oxide layer 81 on the top surface of the first silicon nitride oxide layer 75, and the remaining first silicon oxide layer 81 has the second pattern. For example, this step can be back-etched by anisotropic etching, which can selectively etch materials in a preset crystal direction or crystal plane direction, and leave only a few or almost no etching marks in other directions. In this step, the back-etching by anisotropic etching can make the morphology of the obtained structure more accurate and controllable;

[0118] S315: Figure 7As shown, a second spin-coated hard mask layer 82 filled with a second pattern is formed and the obtained structure is etched back until the top surface of the first silicon oxide layer 81 is exposed, and then a second silicon nitride oxide layer 83, a third spin-coated hard mask layer 84, a third silicon nitride oxide layer 85 and a second silicon oxide mask layer 86 are sequentially formed on the top surfaces of the first silicon oxide layer 81 and the second spin-coated hard mask layer 82, wherein the first silicon oxide layer 81, the second spin-coated hard mask layer 82, the second silicon nitride oxide layer 83, the third spin-coated hard mask layer 84, the third silicon nitride oxide layer 85 and the second silicon oxide mask layer 86 together constitute a second mask stack 8, the third spin-coated hard mask layer 84 and the third silicon nitride oxide layer 85 have a third pattern, and the second silicon oxide mask layer 86 is located on the sidewalls and the top of the third spin-coated hard mask layer 84 and the third silicon nitride oxide layer 85; and a photoresist layer is formed on the second silicon oxide mask layer 86, and the photoresist layer is exposed and developed to form a second photoresist layer 87;

[0119] For example, in step S315, the step of forming a second silicon oxide mask layer 86 located on the sidewalls and top of the third spin-coated hard mask layer 84 and the third silicon oxynitride layer 85 may include: sequentially forming a third spin-coated hard mask layer 84 and a third silicon oxynitride layer 85 on the surface of the second silicon oxynitride layer 83, etching the third spin-coated hard mask layer 84 and the third silicon oxynitride layer 85 so that the third spin-coated hard mask layer 84 and the third silicon oxynitride layer 85 have a third pattern, and forming a second silicon oxide mask layer 86, wherein the second silicon oxide mask layer 86 is located on the sidewalls and top of the third spin-coated hard mask layer 84 and the third silicon oxynitride layer 85.

[0120] S316: Figure 8 As shown, based on the second photoresist layer 87, a portion of the third spin-on hard mask layer 84 and the third silicon oxynitride layer 85 are removed to form a fourth pattern;

[0121] S317: Fig. 9 As shown, the second hard mask layer 73, the first hard mask layer 72 and the pattern transfer layer 71 are etched based on the fourth pattern to form a first mask pattern 71a in the pattern transfer layer 71, and the remaining second hard mask layer 73, the first hard mask layer 72 and the second mask stack 8 are removed.

[0122] like Fig.10As shown, in step S32, the mold stack structure 2 is dry-etched based on the first mask pattern 71a to form a grid pattern 2a. Since the etching selectivities of the first sacrificial layer 51, the second sacrificial layer 52 and the support layer 4 are different, when the mold stack structure 2 is patterned, the grid pattern 2a can maintain a good morphology during the process of transferring from the second sacrificial layer 52 to the first sacrificial layer 51, and from the first sacrificial layer 51 to each support layer 4. Therefore, the mold stack structure 2 after patterning will not be distorted, thereby avoiding defects such as short circuits in subsequently formed devices and improving the reliability of the capacitor.

[0123] For example, the support layer 4 includes a bottom support layer 401, an intermediate support layer 402 and a top support layer 403 arranged in sequence from bottom to top on the substrate 1; the mold layer 3 includes a first mold layer 301 and a second mold layer 302, the first mold layer 301 is located between the bottom support layer 401 and the intermediate support layer 402, and the second mold layer 302 is located between the intermediate support layer 402 and the top support layer 403.

[0124] For example, the materials of the first mold layer 301 and the second mold layer 302 may be the same or different. For example, the materials of the first mold layer 301 and the second mold layer 302 include silicon oxide, silicon oxynitride, or boron-phosphorus-doped silicon oxide (BPSG, borophosphosilicate glass), etc. For example, the materials of the first mold layer 301 and the second mold layer 302 are boron-phosphorus-doped silicon oxide (BPSG, borophosphosilicate glass), and the phosphorus ion doping concentrations at different thicknesses of the first mold layer 301 and the second mold layer 302 are different, which is manifested as including a lower layer and an upper layer, wherein the phosphorus ion doping concentration of the lower layer is greater than the phosphorus ion doping concentration of the upper layer. Since the corrosion rate of BPSG is affected by the concentrations of boron ions and phosphorus ions, the corrosion rate decreases with increasing the content of boron ions, and increases significantly with increasing the content of phosphorus ions. The first mold layer 301 and the second mold layer 302 need to be removed through the same etching process in the subsequent process. Therefore, increasing the phosphorus ion concentration of the lower layer of the first mold layer 301 and the second mold layer 302 can effectively ensure the complete etching of the first mold layer 301 and the second mold layer 302, thereby avoiding the reduction of capacitor performance due to insufficient etching.

[0125] For example, in step S32, the mold stack structure 2 may be dry-etched using a one-time etching process to form a grid pattern 2a, that is, etching based on the pattern of the same mask layer to form the same pattern. The mold stack structure 2 may also be dry-etched using multiple etching processes to form the grid pattern 2a. For example, the step of dry-etching the mold stack structure 2 using multiple etching processes may include:

[0126] S321: dry-etching the second sacrificial layer 52 based on the first mask pattern 71 a to form a second sacrificial layer 52 having an initial pattern;

[0127] S322: based on the initial pattern, the top support layer 403, the second mold layer 302, the middle support layer 402, the first mold layer 301 and the bottom support layer 401 are dry-etched in sequence to form a grid pattern 2a.

[0128] like Fig.11 As shown, in step S40 , the second sacrificial layer 52 is removed.

[0129] Please refer to Fig.12 and Fig.13 , step S50, forming a conductive structure 6 in the mesh pattern 2a, comprising:

[0130] S51: Fig.12 As shown, a conductive material layer 61 is formed to fill the mesh pattern 2a and cover the first sacrificial layer 51;

[0131] For example, in step 51, the conductive material layer 61 may be formed by chemical vapor deposition or physical vapor deposition, and the chemical vapor deposition process may include one or more of atmospheric pressure chemical vapor deposition, low pressure chemical or plasma enhanced chemical vapor deposition. For example, the conductive material layer 61 may be formed by atomic layer deposition, because the atomic layer deposition process has excellent conformality and uniformity when depositing on a three-dimensional complex surface, so that a void-free conductive material layer 61 can be formed in the grid pattern 2a, thereby improving the coverage of the conductive material layer 61 and ensuring the electrical reliability of the capacitor formed subsequently.

[0132] S52: Fig.13 As shown, the conductive material layer 61 is dry-etched to remove the conductive material layer 61 above the first sacrificial layer 51 to form a conductive structure 6; the conductive structure 6 includes conductive portions 62 respectively located in each grid of the grid pattern 2a;

[0133] For example, in step S52 , the first sacrificial layer 51 is removed by a wet etching process.

[0134] For example, in step S52, the conductive material layer 61 may be dry-etched using a plasma etching process. Plasma etching refers to the use of a high-frequency glow discharge reaction to activate the reaction gas into active particles, such as atoms or free radicals. These active particles diffuse to the etched area and react with the etched material to form volatile products that are removed, thereby increasing the process rate.

[0135] Illustratively, the material of the conductive structure 6 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon, titanium carbide, polysilicon or a combination thereof.

[0136] Please refer to Fig.14 , in step S60, the first sacrificial layer 51 is removed to expose the head of the conductive structure 6;

[0137] Please refer to Fig.15 In some embodiments, after exposing the head of the conductive structure 6 in step S60, and before forming the supplementary support layer 41 covering the head of the conductive structure 6 and the top support layer 403 in step S70, the method for preparing the semiconductor structure further includes:

[0138] S61: etching the head of the conductive structure 6 so that the cross-sectional area of ​​the head gradually decreases in a direction away from the substrate 1, so as to increase the process window and further reduce the process difficulty of manufacturing the semiconductor structure.

[0139] In some embodiments, the head of the conductive structure 6 is processed by a free radical etching process. It is understood that in the related art, vacuum plasma processing technology usually uses corrosive gases such as SF6 and CH4. The plasma source ionizes the gas under the stimulation of external conditions such as radio frequency or microwaves, and generates plasma with active molecules to react with the components, thereby achieving the purpose of optimizing the surface quality of the components. However, silicon-based optical components are difficult to react with etching gases such as CF4 or SF6 under normal circumstances. The free radical etching process ionizes the etching gas through a free radical plasma source to generate a free radical plasma, so that the etching gas contains a large number of free radicals, which enhances the reaction activity and is sufficient to destroy the chemical bonds of the silicon-based material, thereby reacting and combining with it to produce the volatile substance SiF4, thereby achieving the etching purpose. In this way, the head of the conductive structure 6 is processed by a free radical etching process, which can have a higher etching rate and good stability.

[0140] Please refer to Fig.16 , in step S70 , a supplementary support layer 41 is formed to cover the head of the conductive structure 6 and the top support layer 403 ;

[0141] For example, the sum of the thicknesses of the top support layer 403 and the supplementary support layer 41 is greater than or equal to the thickness of the second top support layer 402 , so as to enhance the support effect of the support layer 4 and avoid structural collapse.

[0142] In some embodiments, the material of the supplementary support layer 41 is the same as the material of the top support layer 403 .

[0143] Please refer to Figure 17 to Figure 18In some embodiments, step S80, patterning the supplementary support layer 41 and each support layer 4, and removing each mold layer 3 to form a support structure 4a, includes:

[0144] S81: Fig.17 As shown, a photoresist pattern layer 411 is formed on the supplementary support layer 41; the photoresist pattern layer 411 has a second mask pattern 411a;

[0145] S82: Fig.18 As shown, based on the second mask pattern 411a, the support layer 4 in the mold stack structure 2 is patterned from top to bottom, and based on the patterned support layer 4, the mold layer 3 corresponding to its lower surface is removed; wherein, the supplementary support layer 41 and the top support layer 403 are patterned simultaneously.

[0146] For example, in step S82 , the corresponding mold layer 3 may be removed by using a wet etching process.

[0147] In some embodiments, the supplementary support layer 41 and the top support layer 403 are patterned using a dry etching process, and the openings after patterning the supplementary support layer 41 and the top support layer 403 expose a side wall of the conductive structure 6 corresponding to the head and a portion of the top surface connected to the side wall.

[0148] Please refer to Fig.18 and Fig.19 In some embodiments, the conductive structure 6 includes conductive portions 62 respectively located in each grid of the grid pattern 2a; the conductive portions 62 are first electrodes; and the method for preparing the semiconductor structure further includes:

[0149] S90 : forming a dielectric layer 91 conformally covering the sidewall of the first electrode, and a second electrode 92 covering the dielectric layer 91 in the removed areas of the support layer 4 and the mold layer 3 .

[0150] For example, the material of the dielectric layer 91 can be selected as a high-K dielectric material to increase the capacitance value of the capacitor per unit area, which includes at least one of zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium zirconium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx).

[0151] Illustratively, the material of the second electrode 92 is the same as or similar to that of the first electrode and is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide, titanium carbide, polysilicon or a combination thereof.

[0152] According to some embodiments, a semiconductor structure is also provided.

[0153] Please refer to Fig.19The semiconductor structure includes a substrate 1, a conductive structure 6 and a support structure 4a, wherein the conductive structure 6 includes a plurality of conductive parts 62 distributed in a mesh shape on the substrate 1; the support structure 4a is prepared by a preparation method of a semiconductor structure as in any of the above embodiments; the support structure 4a includes: a plurality of support layers 4 spaced apart in a direction away from the substrate 1, and a supplementary support layer 41 located on a top support layer 403; wherein each support layer 4 and the supplementary support layer 41 are located between corresponding adjacent conductive parts 62, and the supplementary support layer 41 also covers at least a portion of the top surface of the corresponding conductive part 62.

[0154] For example, the number of support layers 4 can be set according to the height required by the subsequent capacitor, and the number of stacked layers can be 1 to 10 or more, for example, the number of support layers 4 can be 2 to 5. In the embodiment of the present disclosure, the support layer 4 is exemplified as 3 layers.

[0155] For example, the support layer 4 includes a bottom support layer 401 , a middle support layer 402 and a top support layer 403 which are arranged in sequence from bottom to top on the substrate 1 .

[0156] For example, the thickness of the top support layer 403 ranges from 5 nm to 10 nm. For example, the thickness of the top support layer 403 may be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm, thereby reducing the difficulty of etching and simplifying the process flow.

[0157] In some embodiments, the cross-sectional area of ​​the head of each conductive portion 62 gradually decreases in a direction away from the substrate 1 .

[0158] In some embodiments, the sum of the thicknesses of the top support layer 403 and the supplemental support layer 41 is greater than the thickness of the second top support layer 402 .

[0159] In some embodiments, the conductive portion 62 is a first electrode; the semiconductor structure further includes a dielectric layer 91 and a second electrode 92 , the dielectric layer 91 conformally covers the sidewall of the corresponding first electrode; and the second electrode 92 covers the dielectric layer 91 .

[0160] For example, the material of the dielectric layer 91 can be selected as a high-K dielectric material to increase the capacitance value of the capacitor per unit area, which includes at least one of zirconium oxide (ZrOx), hafnium oxide (HfOx), titanium zirconium oxide (ZrTiOx), ruthenium oxide (RuOx), antimony oxide (SbOx), and aluminum oxide (AlOx).

[0161] For example, the material of the second electrode 92 is the same as or similar to the material of the first electrode. The material of the first electrode is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide, titanium carbide, polysilicon or a combination thereof. The material of the second electrode 92 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium silicide, titanium carbide, polysilicon or a combination thereof.

[0162] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0163] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; A mold stacking structure is formed on the substrate, wherein the mold stacking structure includes multiple mold layers and multiple support layers alternately stacked in a direction away from the substrate, and a first sacrificial layer and a second sacrificial layer stacked in a direction away from the substrate and located above the top support layer; wherein the first sacrificial layer, the second sacrificial layer, and the support layer have different etching selectivities; Graphically forming the mold stack structure to form a grid pattern; removing the second sacrificial layer; forming a conductive structure within the grid pattern; removing the first sacrificial layer to expose the head of the conductive structure; forming a supplementary supporting layer covering the head of the conductive structure and the top supporting layer; The supplementary support layer and each of the support layers are patterned, and each of the mold layers is removed to form a support structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: After exposing the head of the conductive structure and before forming a supplementary supporting layer covering the head of the conductive structure and the top supporting layer, the method for preparing the semiconductor structure further includes: The head of the conductive structure is etched so that the cross-sectional area of ​​the head gradually decreases in a direction away from the substrate.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The head of the conductive structure is processed by a free radical etching process.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the support layer of the top layer is less than the thickness of the support layer of the second top layer; The sum of the thicknesses of the top support layer and the first sacrificial layer is greater than or equal to the thickness of the second top support layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of patterning the mold stack structure to form a grid pattern includes: forming a pattern transfer layer on the second sacrificial layer, wherein the pattern transfer layer has a first mask pattern; The mold stack structure is dry-etched based on the first mask pattern to form the grid pattern.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of a conductive structure in the grid pattern comprises: forming a conductive material layer filling the grid pattern and covering the first sacrificial layer; Performing dry etching on the conductive material layer to remove the conductive material layer above the first sacrificial layer to form the conductive structure; the conductive structure comprises conductive parts respectively located in each grid of the grid pattern; Wherein, the first sacrificial layer is removed by a wet etching process.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the supplementary supporting layer is the same as that of the top supporting layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the first sacrificial layer includes silicon oxide; The material of the second sacrificial layer includes polysilicon; The material of the support layer includes silicon nitride.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of patterning the supplementary support layer and each of the support layers and removing each of the mold layers to form a support structure includes: forming a photoresist pattern layer on the supplementary support layer; the photoresist pattern layer has a second mask pattern; Based on the second mask pattern, the support layer in the mold stacking structure is patterned sequentially from top to bottom, and based on the patterned support layer, the mold layer corresponding to the lower surface thereof is removed; wherein the supplementary support layer and the top support layer are patterned synchronously.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The supplementary support layer and the top support layer are patterned by dry etching process, and the openings after patterning of the supplementary support layer and the top support layer expose a side wall of the conductive structure corresponding to the head and a portion of the top surface connected to the side wall.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 10, characterized in that: The conductive structure includes conductive parts respectively located in each grid of the grid pattern; The conductive portion is a first electrode; The method for preparing the semiconductor structure further comprises: A dielectric layer conformally covering the sidewall of the first electrode and a second electrode covering the dielectric layer are formed in the removed areas of the support layer and the mold layer.

12. A semiconductor structure, characterized in that: include: substrate; A conductive structure, comprising a plurality of conductive parts distributed in a mesh shape on the substrate; A support structure, prepared by the method according to any one of claims 1 to 11; the support structure comprises: a plurality of support layers spaced apart in a direction away from the substrate, and a supplementary support layer located on the top support layer; Wherein, each of the supporting layers and the supplementary supporting layer is located between the corresponding adjacent conductive parts, and the supplementary supporting layer also covers at least a portion of the top surface of the corresponding conductive part.

13. The semiconductor structure according to claim 12, characterized in that: The cross-sectional area of ​​the head of each conductive portion gradually decreases in a direction away from the base.

14. The semiconductor structure according to claim 12, characterized in that: The sum of the thickness of the top support layer and the supplementary support layer is greater than the thickness of the second top support layer.

15. The semiconductor structure according to any one of claims 12 to 14, characterized in that: The conductive portion is a first electrode; the semiconductor structure further includes: a dielectric layer conformally covering a side wall corresponding to the first electrode; The second electrode covers the dielectric layer.

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