Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and a storage system, and the semiconductor device comprises a plurality of channel structures which extend along a first direction, and each channel structure comprises a first channel end and a second channel end which are opposite to each other in the first direction; the first grid electrode extends along the first direction and is positioned between the adjacent channel structures, the first grid electrode comprises a first grid electrode top surface and a first grid electrode bottom surface which are opposite in the first direction, and the first grid electrode top surface is close to the first channel end; the second grid electrode extends in the first direction and is located on the side, away from the first grid electrode, of the channel structure in the second direction, the second grid electrode comprises a second grid electrode top face and a second grid electrode bottom face which are opposite in the first direction, and the second grid electrode bottom face is close to the second channel end; the second gate top surface is located on the side, close to the first channel end, of the first gate top surface, the first gate bottom surface is located on the side, close to the second channel end, of the second gate bottom surface, and the first direction intersects with the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Dynamic random access memory is an important memory. The storage unit of dynamic random access memory mainly includes a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor is used to store data, and the transistor is used to control the storage of data in the storage capacitor.

[0003] At present, the storage density of dynamic random access memory needs to be further improved. How to improve the storage density of dynamic random access memory is a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system, which are conducive to improving the storage density of the semiconductor device.

[0005] In a first aspect, the present application provides a semiconductor device, comprising:

[0006] A plurality of channel structures extending along a first direction, the channel structures comprising a first channel end and a second channel end opposite to each other in the first direction;

[0007] a first gate extending along the first direction, located between adjacent channel structures, and comprising a first gate top surface and a first gate bottom surface opposite to each other in the first direction, wherein the first gate top surface is close to the first channel end; and

[0008] A second gate extending along the first direction is located on a side of the channel structure facing away from the first gate in the second direction, and the second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface is close to the second channel end, in the first direction, the second gate top surface is located on a side of the first gate top surface close to the first channel end, the first gate bottom surface is located on a side of the second gate bottom surface close to the second channel end, and the first direction intersects with the second direction.

[0009] In some embodiments, in the first direction, the second gate bottom surface is located on a side of the first gate top surface close to the first gate bottom surface.

[0010] In some embodiments, in the second direction, the top surface of the first gate is aligned with the bottom surface of the second gate.

[0011] In some embodiments, in the first direction, the second gate bottom surface is located on a side of the first gate top surface away from the first gate bottom surface.

[0012] In some embodiments, it also includes:

[0013] a first bottom insulating portion, wherein in the first direction, the first bottom insulating portion is located on a side of the first gate bottom surface away from the first gate top surface and is in contact with the first gate bottom surface; and

[0014] A second bottom insulating portion, in the first direction, the second bottom insulating portion is located on a side of the second gate bottom surface away from the second gate top surface and contacts the second gate bottom surface, and the size of the second bottom insulating portion in the first direction is greater than the size of the first bottom insulating portion in the first direction.

[0015] In some embodiments, the second bottom insulating portion includes an insulating core and a protection layer, the protection layer covers sidewalls of the insulating core and a bottom wall of the insulating core away from the second gate, and a material of the insulating core is different from a material of the protection layer.

[0016] In some embodiments, it also includes:

[0017] a first top insulating portion, wherein in the first direction, the first top insulating portion is located on a side of the first gate top surface away from the first gate bottom surface and is in contact with the first gate top surface; and

[0018] A second top insulating portion, in the first direction, the second top insulating portion is located on a side of the second gate top surface away from the second gate bottom surface and contacts the second gate top surface, and the size of the second top insulating portion in the first direction is smaller than the size of the first top insulating portion in the first direction.

[0019] In some embodiments, a plurality of the first gates and a plurality of the second gates are arranged alternately and at intervals along the second direction, and the first gates and the second gates further extend along a third direction, and the third direction intersects the first direction and the second direction;

[0020] The opposite ends of the first grid in the third direction are staggered with the opposite ends of the second grid in the third direction.

[0021] In some embodiments, a size of the first gate in the third direction is different from a size of the second gate in the third direction.

[0022] In some embodiments, the first gate includes a first gate end and a second gate end opposite to each other in the third direction;

[0023] The second gate includes a third gate end and a fourth gate end opposite to each other in the third direction, and the third gate end is close to the first gate end;

[0024] The semiconductor device further comprises:

[0025] at least one first gate contact connected to the first gate terminal of at least one first gate; and

[0026] At least one second gate contact is connected to the third gate terminal of at least one of the second gates.

[0027] In some embodiments, in two adjacent first gates, the first gate end of one of the first gates is connected to one of the first gate contacts, and the second gate end of the other first gate is connected to the other of the first gate contacts;

[0028] In two adjacent second gates, the third gate terminal of one of the second gates is connected to one of the second gate contacts, and the fourth gate terminal of the other of the second gates is connected to the other of the second gate contacts.

[0029] In some embodiments, the first gate includes a first gate end and a second gate end opposite to each other in the third direction;

[0030] The second gate includes a third gate end and a fourth gate end opposite to each other in the third direction, and the third gate end is close to the first gate end;

[0031] The semiconductor device further comprises:

[0032] at least one first gate contact connected to the first gate terminal of at least one first gate; and

[0033] At least one second gate contact is connected to the fourth gate terminal of at least one of the second gates.

[0034] In some embodiments, the first gate terminals of two adjacent first gates are respectively connected to two first gate contacts, and the fourth gate terminals of two adjacent second gates are respectively connected to two second gate contacts.

[0035] In a second aspect, the present application further provides a method for manufacturing a semiconductor device, the method comprising:

[0036] forming a plurality of active pillars extending along a first direction, the active pillars comprising first and second ends opposite to each other in the first direction;

[0037] forming a first gate extending along the first direction between adjacent active pillars, the first gate comprising a first gate top surface and a first gate bottom surface opposite to each other in the first direction, the first gate top surface being close to the first end; and

[0038] A second gate extending along the first direction is formed, the second gate is located on a side of the active column in the second direction away from the first gate, and the second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface is close to the second end, in the first direction, the second gate top surface is located on a side of the first gate top surface close to the first end, the first gate bottom surface is located on a side of the second gate bottom surface close to the second end, and the first direction intersects with the second direction.

[0039] In the method for manufacturing a semiconductor device in some embodiments, forming a plurality of active pillars extending along a first direction includes:

[0040] forming a first groove and a second groove arranged along the second direction and extending along a third direction, wherein the first groove and the second groove intersect with the plurality of active lines, and opposite ends of the first groove in the third direction are staggered with opposite ends of the second groove in the third direction, and the third direction intersects with the first direction and the second direction;

[0041] The forming of the first gate extending along the first direction between the adjacent active pillars comprises: filling the first groove with a first conductive layer;

[0042] removing a portion of the first conductive layer close to the first end, and the remaining first conductive layer forms a first initial gate;

[0043] A portion of the first initial gate close to the second end is removed, and the remaining first initial gate forms the first gate.

[0044] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: filling a dielectric layer in the plurality of recessed portions;

[0045] The removing a portion of the first initial gate close to the second end comprises:

[0046] Thinning the second surface of the semiconductor layer until the dielectric layer is exposed, and forming a thinned third surface;

[0047] forming an opening in the dielectric layer to expose the first initial gate, wherein the opening is sunken from the third surface to the first surface;

[0048] A portion of the first initial gate close to the second end is removed through the opening.

[0049] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: forming a first bottom insulating portion close to the second end on the first gate through the opening.

[0050] In the method for manufacturing a semiconductor device in some embodiments, before filling the first conductive layer in the first groove, the method further includes:

[0051] forming a sacrificial layer in the first groove and the second groove;

[0052] forming a protection layer covering the sacrificial layer in the second groove; and

[0053] The sacrificial layer in the first groove is removed.

[0054] In the method for manufacturing a semiconductor device in some embodiments, forming a second gate extending along the first direction includes:

[0055] removing the protective layer and the sacrificial layer in the second groove;

[0056] forming a second bottom insulating portion in the second groove, wherein a dimension of the second bottom insulating portion in the first direction is smaller than a depth of the second groove; and

[0057] The second gate is formed on the second bottom insulating portion.

[0058] In a third aspect, the present application further provides a storage system, including:

[0059] A memory, comprising the semiconductor device described in any of the above embodiments; and

[0060] The controller is connected to the memory and is used to control the memory.

[0061] The beneficial effects of some embodiments of the present application include: in the second direction, the first gate and the second gate are respectively located on opposite sides of the channel structure. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate close to the first channel end, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate close to the second channel end. With this design, at least part of the first gate is staggered with the second gate in the first direction, and each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, that is, each of the first gate and the second gate can control the part of the two adjacent channel structures in the second direction to be in the on state or the off state. Moreover, on the basis that each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, the size of the first gate and the second gate in the second direction can be smaller, that is, it is conducive to miniaturization of the size of the first gate and the second gate in the second direction, and it is conducive to increasing the number of the first gate, the second gate and the channel structure, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0063] Figure 2A It is a schematic plan view of forming a plurality of active lines and a dielectric layer in a semiconductor layer in some embodiments of the present application;

[0064] Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure taken by the AA tangent line in FIG.

[0065] Figure 2C A schematic plan view of forming a first groove and a second groove intersecting with a plurality of active lines in some embodiments of the present application;

[0066] Figure 2D A schematic plan view of forming a first groove and a second groove intersecting with a plurality of active lines in some other embodiments of the present application;

[0067] Figure 2E For along Figure 2C Schematic diagram of the cross-sectional structure taken by the BB tangent line;

[0068] Figure 3A It is a schematic cross-sectional structure diagram of forming a sacrificial layer in the first groove and the second groove in some embodiments of the present application;

[0069] Figure 3B A schematic cross-sectional structure diagram of forming a protective layer covering the sacrificial layer in the second groove and removing the sacrificial layer in the first groove in some embodiments of the present application;

[0070] Figure 3C It is a schematic cross-sectional structure diagram of forming a first conductive layer in a first groove in some embodiments of the present application;

[0071] Figure 3D Schematic diagram of a cross-sectional structure of forming a first initial gate in a first groove in some embodiments of the present application;

[0072] Figure 3E It is a schematic cross-sectional structure diagram of a first top insulating portion formed in a first groove and located on a first initial gate in some embodiments of the present application;

[0073] Figure 3F A schematic cross-sectional structure diagram of removing the protective layer and the sacrificial layer in the second groove in some embodiments of the present application;

[0074] Figure 3G It is a schematic cross-sectional structure diagram of forming a second bottom insulating portion in the second groove in some embodiments of the present application;

[0075] Figure 3H It is a schematic cross-sectional structure diagram of forming a second bottom insulating portion in the second groove in some other embodiments of the present application;

[0076] Fig. 3I It is a schematic cross-sectional structure diagram of forming a second gate insulating layer and a second conductive layer in the second groove in some embodiments of the present application;

[0077] Figure 3J It is a schematic diagram of a planar structure of forming a second gate and a second top insulating portion in some embodiments of the present application;

[0078] Figure 3K For along Figure 3J Schematic diagram of the cross-sectional structure taken by the CC tangent line in FIG.

[0079] Figure 3L For along Figure 3J Schematic diagram of the cross-sectional structure taken by the DD tangent line;

[0080] Figure 3M A schematic diagram of a planar structure in which the second surface of the semiconductor layer is thinned to form a third surface in some embodiments of the present application;

[0081] Figure 3N For along Figure 3M Schematic diagram of the cross-sectional structure taken by the EE tangent line in FIG.

[0082] Fig.3O For along Figure 3M Schematic diagram of the cross-sectional structure taken by the FF tangent line;

[0083] Figure 3PIt is a schematic plan view of a structure in which an opening is formed to expose a first initial gate and a second bottom insulating portion in some embodiments of the present application;

[0084] Figure 3Q For along Figure 3P Schematic diagram of the cross-sectional structure taken by the GG tangent line;

[0085] Figure 3R For along Figure 3P Schematic diagram of the cross-sectional structure taken along the HH tangent line;

[0086] Figure 3S A schematic cross-sectional structure diagram of etching back the first initial gate through an opening to form a first gate and forming a first bottom insulating portion in some embodiments of the present application;

[0087] Figure 3T A schematic cross-sectional structure diagram of an insulating filling layer forming a filling opening in some embodiments of the present application;

[0088] Figure 3U Schematic diagrams of cross-sectional structures of semiconductor devices in other embodiments of the present application;

[0089] Figure 3V Schematic diagram of the cross-sectional structure of semiconductor devices in other embodiments of the present application;

[0090] Figure 4A Schematic diagram of the cross-sectional structure of a first gate, a second gate, a channel structure, a first gate contact, and a second gate contact in some embodiments of the present application;

[0091] Figure 4B Schematic diagram of the cross-sectional structure of the first gate, the second gate, the channel structure, the first gate contact and the second gate contact in some other embodiments of the present application;

[0092] Figure 5 A block diagram of a storage system according to some embodiments of the present application;

[0093] Figure 6 A block diagram of a storage system according to some other embodiments of the present application;

[0094] Figure 7 A block diagram of an electronic device according to some embodiments of the present application.

[0095] The reference numerals are as follows:

[0096] z, first direction; y, second direction; x, third direction;

[0097] 10, semiconductor layer; 10a, first surface; 10b, second surface; 10c, first groove; 10d, second groove; 101, recessed portion; 102, active line; 103, active pillar; 1031, first end; 1032, second end; 1033, first electrode; 1034, second electrode; 1035, channel structure; 10351, first channel end; 10352, second channel end; 10e, third surface; 10f, opening;

[0098] 111, dielectric layer; 112, first gate insulating layer; 113, second gate insulating layer;

[0099] 121, mask pattern; 122, sacrificial layer; 123, protective layer; 124, insulating filling layer;

[0100] 131, first conductive layer; 132, first initial gate; 133, first gate; 133a, first gate top surface; 133b, first gate bottom surface; 1331, first gate terminal; 1332, second gate terminal; 134, second conductive layer; 135, second gate; 135a, second gate top surface; 135b, second gate bottom surface; 1351, third gate terminal; 1352, fourth gate terminal;

[0101] 141, first top insulating portion; 1411, first air gap; 142, second bottom insulating portion; 1421, insulating core; 1422, protective layer; 1423, second air gap; 143, second top insulating portion; 144, first bottom insulating portion;

[0102] 151, a first gate contact; 152, a second gate contact;

[0103] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; 600, host. DETAILED DESCRIPTION

[0104] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0105] Please refer to Figure 1 As shown, it is a schematic flow chart of a method for manufacturing a semiconductor device in some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:

[0106] Step S101: forming a plurality of active pillars extending along a first direction, wherein the active pillars include a first end and a second end opposite to each other in the first direction;

[0107] Step S102: forming a first gate extending along a first direction between adjacent active pillars, the first gate comprising a first gate top surface and a first gate bottom surface opposite to each other in the first direction, the first gate top surface being close to the first end; and

[0108] Step S103: forming a second gate extending along the first direction, the second gate being located on a side of the active column away from the first gate in the second direction, and the second gate comprising a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface being close to the second end, and in the first direction, the second gate top surface being located on a side of the first gate top surface close to the first end, the first gate bottom surface being located on a side of the second gate bottom surface close to the second end, and the first direction intersects the second direction.

[0109] In some embodiments of the present application, the above method is adopted to form a first gate and a second gate on both sides of the active column in the second direction. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate close to the first end, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate close to the second end. Therefore, at least part of the first gate is staggered with the second gate in the first direction, and each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, that is, each of the first gate and the second gate can control the part of the two adjacent channel structures in the second direction to be in the on state or the off state. Moreover, on the basis that each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, the size of the first gate and the second gate in the second direction can be smaller, that is, it is conducive to the miniaturization of the size of the first gate and the second gate in the second direction, and it is conducive to increasing the number of the first gate and the second gate in the second direction, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device.

[0110] The manufacturing method of the semiconductor device is described in detail below in conjunction with specific implementations.

[0111] First, please refer to FIG. 2A to FIG. 2E As shown, step S101 is performed: a plurality of active pillars 103 extending along a first direction z are formed, and the active pillars 103 include a first end 1031 and a second end 1032 opposite to each other in the first direction z.

[0112] In some embodiments, please refer to FIG. 2A to FIG. 2EAs shown, forming a plurality of active pillars 103 extending along a first direction z includes: forming a plurality of recessed portions 101 in a semiconductor layer 10, and the remaining semiconductor layer 10 includes a plurality of active lines 102 extending along the first direction z, the recessed portions 101 are sunken from a first surface 10a of the semiconductor layer 10 to a second surface 10b, and the first surface 10a and the second surface 10b are arranged opposite to each other in the first direction z; and

[0113] A first groove 10c and a second groove 10d are formed which are arranged at intervals along the second direction y and extend along the third direction x. The first groove 10c and the second groove 10d intersect with a plurality of active lines 102. The remaining active lines 102 form a plurality of active pillars 103. The opposite ends of the first groove 10c in the third direction x are staggered with the opposite ends of the second groove 10d in the third direction x. The third direction x intersects with the first direction z and the second direction y.

[0114] In some embodiments, reference Figure 2A and Figure 2B As shown, forming a plurality of recessed portions 101 in a semiconductor layer 10 includes: providing a semiconductor layer 10, wherein the semiconductor layer 10 includes a first surface 10a and a second surface 10b oppositely disposed in a first direction z; and

[0115] Part of the semiconductor layer 10 is removed to form a plurality of recessed portions 101 extending along the first direction z and the second direction y and arranged along the third direction x. The remaining semiconductor layer 10 includes a plurality of active lines 102 extending along the first direction z and the second direction y and arranged at intervals along the third direction x. An active line 102 is located between two adjacent recessed portions 101, and the recessed portion 101 is sunken from the first surface 10a to the second surface 10b.

[0116] In some embodiments, the material of the semiconductor layer 10 includes a single semiconductor material, which includes but is not limited to single crystal silicon. Specifically, the semiconductor layer 10 includes a silicon wafer.

[0117] In some embodiments, any two of the first direction z, the second direction y, and the third direction x are perpendicular to each other, but the present invention is not limited thereto.

[0118] In some embodiments, the shape of the cross section of the recessed portion 101 parallel to the first direction z and the third direction x is a rectangle, an inverted trapezoid or other shapes. The shape of the cross section of the active line 102 parallel to the first direction z and the third direction x is a rectangle, a trapezoid or other shapes. For example, the shape of the cross section of the recessed portion 101 parallel to the first direction z and the third direction x is a rectangle; correspondingly, the shape of the cross section of the active line 102 parallel to the first direction z and the third direction x is also a rectangle.

[0119] In some embodiments, removing a portion of the semiconductor layer 10 includes: forming a mask pattern 121 on the first surface 10 a of the semiconductor layer 10 ; and etching the semiconductor layer 10 using the mask pattern 121 as a mask to obtain a plurality of recessed portions 101 .

[0120] In some embodiments, please refer to Figure 2A and Figure 2B As shown, after forming the plurality of recessed portions 101 , the method for manufacturing a semiconductor device further includes: filling a dielectric layer 111 in the plurality of recessed portions 101 .

[0121] In some embodiments of the present application, the dielectric layer 111 isolates the plurality of active lines 102 from each other. The material of the dielectric layer 111 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0122] In some embodiments, please refer to Figure 2C , Figure 2D and Figure 2E As shown, forming the first groove 10c and the second groove 10d arranged along the second direction y and extending along the third direction x includes: removing part of the active line 102 and part of the dielectric layer 111 to form the first groove 10c and the second groove 10d arranged along the second direction y, and the remaining active line 102 includes a plurality of active pillars 103 arranged in an array along the second direction y and the third direction x and extending along the first direction z.

[0123] In some embodiments of the present application, the two opposite ends of the first groove 10c in the third direction x are staggered with the two opposite ends of the second groove 10d in the third direction x, so as to better distinguish the first groove 10c from the second groove 10d, and form different gates in the first groove 10c and the second groove 10d, respectively. Moreover, when different gates are led out separately, the process window for the lead-out structures of different gates is larger.

[0124] In some embodiments, reference Figure 2C As shown, the first groove 10c and the second groove 10d are both linear. The dimension of the first groove 10c along the third direction x is greater than the dimension of the second groove 10d along the third direction x. The opposite ends of the first groove 10c in the third direction x are respectively located on both sides of the second groove 10d in the third direction x.

[0125] In some embodiments, reference Figure 2DAs shown, the dimension of the first groove 10c along the third direction x is the same as the dimension of the second groove 10d along the third direction x. One end of the first groove 10c in the third direction x is adjacent to one end of the second groove 10d in the third direction x, and the other end of the first groove 10c in the third direction x is adjacent to the other end of the second groove 10d in the third direction x. One end of the first groove 10c in the third direction x protrudes from one end of the second groove 10d in the third direction x, and the other end of the second groove 10d in the third direction x protrudes from the other end of the first groove 10c in the third direction x.

[0126] In some embodiments, reference Figure 2C and Figure 2D As shown, the plurality of first grooves 10c and the plurality of second grooves 10d are arranged alternately and at intervals in a one-to-one manner along the second direction y, but the present invention is not limited thereto.

[0127] In some embodiments, reference Figure 2C and Figure 2E As shown, the size of the first groove 10c along the first direction z can be the same as the size of the second groove 10d along the first direction z, and the size of the first groove 10c along the second direction y can be the same as the size of the second groove 10d along the second direction y, so as to form the first groove 10c and the second groove 10d at the same time, simplifying the manufacturing process of the semiconductor device. In other embodiments, the size of the first groove 10c along the second direction y can also be different from the size of the second groove 10d along the second direction y, and the size of the first groove 10c along the first direction z can also be different from the size of the second groove 10d along the first direction z.

[0128] In some embodiments, reference Figure 2E As shown, since a plurality of first grooves 10c and a plurality of second grooves 10d intersect with a plurality of active lines 102, the remaining active lines 102 include a plurality of active pillars 103. A plurality of active pillars 103 are arranged in an array along the second direction y and the third direction x and extend along the first direction z. A first groove 10c is disposed between two adjacent rows of active pillars 103 arranged along the second direction y, and a second groove 10d is disposed between two adjacent rows of active pillars 103 arranged along the second direction y. A row of active pillars 103 includes a plurality of active pillars 103 arranged side by side along the third direction x. The active pillars 103 include a first end 1031 and a second end 1032 opposite to each other in the first direction z. The first end 1031 is away from the second surface 10b, and the second end 1032 is close to the second surface 10b.

[0129] In some embodiments, reference Figure 3A and Figure 3BAs shown, after forming the first groove 10c and the second groove 10d arranged along the second direction y and extending along the third direction x, the manufacturing method of the semiconductor device also includes: forming a sacrificial layer 122 in the first groove 10c and the second groove 10d; forming a protective layer 123 covering the sacrificial layer 122 in the second groove 10d; and removing the sacrificial layer 122 in the first groove 10c.

[0130] In some embodiments of the present application, before forming the first gate 133 in the first groove 10c, a sacrificial layer 122 is formed in the second groove 10d, and a protective layer 123 is formed to cover the sacrificial layer 122 in the second groove 10d. In this way, when the sacrificial layer 122 in the first groove 10c is removed, the protective layer 123 protects the sacrificial layer 122 in the second groove 10d, ensuring that when the sacrificial layer 122 in the first groove 10c is removed, the sacrificial layer 122 in the second groove 10d is still retained.

[0131] In some embodiments, the material of the sacrificial layer 122 includes but is not limited to spin on carbon (SOC). The material of the protective layer 123 includes an insulating material, and the insulating material includes but is not limited to at least one of silicon oxide, silicon nitride and silicon oxynitride.

[0132] Next, execute the above step S102, referring to Figure 3C to Figure 3V As shown, a first gate 133 extending along the first direction z is formed between adjacent active pillars 103 . The first gate 133 includes a first gate top surface 133 a and a first gate bottom surface 133 b opposite to each other in the first direction z. The first gate top surface 133 a is close to the first end 1031 .

[0133] In some embodiments, reference Figure 3C As shown, before forming the first gate 133 extending along the first direction z between adjacent active pillars 103, the method for manufacturing a semiconductor device further includes: forming a first gate insulating layer 112 on the groove wall of the first groove 10c. Specifically, the first gate insulating layer 112 is located on the groove wall of the first groove 10c and covers the protection layer 123 and the mask pattern 121.

[0134] In some embodiments, the material of the first gate insulating layer 112 is the same as that of the protective layer, but is not limited thereto. In some embodiments, the semiconductor layer 10 is subjected to a high temperature oxidation treatment to form the first gate insulating layer 112 on the groove wall of the first groove 10c. In other embodiments, the first gate insulating layer 112 is formed by a thin film deposition process. The material of the first gate insulating layer 112 includes an oxide, and the oxide includes but is not limited to silicon oxide.

[0135] In some embodiments, reference Figure 3C and Figure 3D As shown, forming a first gate 133 extending along a first direction z between adjacent active pillars 103 includes: filling a first conductive layer 131 in a first groove 10c; removing a portion of the first conductive layer 131 close to the first end 1031, and the remaining first conductive layer 131 forms a first initial gate 132.

[0136] Specifically, a first conductive layer 131 covering the first gate insulating layer 112 is formed by a thin film deposition process, and the portion of the first conductive layer 131 located in the first groove 10c fills the first groove 10c; then, a portion of the first conductive layer 131 is etched away, and the remaining first conductive layer 131 is the first initial gate 132.

[0137] In some embodiments of the present application, the first conductive layer 131 is filled in the first groove 10c, and a portion of the first conductive layer 131 close to the first end 1031 is etched away, and the remaining first conductive layer 131 forms the first initial gate 132. This method is conducive to aligning the ends of the multiple first initial gates 132 close to the first end 1031 of the active pillar 103, that is, the ends of the multiple first initial gates 132 close to the first end 1031 are located in a plane, and the plane is parallel to the second direction y. Moreover, the first initial gate 132 is formed by an etching process, which is conducive to simplifying the manufacturing process of the first gate 133. In addition, the first conductive layer 131 fills the first groove 10c, which can make fuller use of the space in the second direction y to set the first gate 133, and facilitates the miniaturization of the size of the first gate 133 in the second direction y.

[0138] In some embodiments, the material of the first conductive layer 131 includes metal and non-metal conductive materials. The metal includes but is not limited to at least one of tungsten, aluminum, and copper. The non-metal conductive material includes but is not limited to titanium nitride.

[0139] In some embodiments, reference Figure 3E and Figure 3H As shown, after forming the first initial gate 132, the method for manufacturing a semiconductor device includes: forming a first top insulating portion 141 filling the first groove 10c on the first initial gate 132. The material of the first top insulating portion 141 includes an insulating material, and the insulating material includes but is not limited to at least one of silicon oxide, silicon nitride, and silicon oxynitride. Specifically, the material of the first top insulating portion 141 includes silicon oxide to simplify the preparation process of the first top insulating portion 141.

[0140] In some embodiments, reference Figure 3EAs shown, there is a first air gap 1411 inside the first top insulating portion 141. The first air gap 1411 can improve the coupling effect between the two channel structures 1035 adjacent to the first top insulating portion 141 in the second direction y described below, that is, it can improve the row hammer problem of the semiconductor device. In other embodiments, a first isolation portion (not shown) can also be formed on the first initial gate 132, and a first conductive shielding structure (not shown) located in the first groove 10c can be formed on the first isolation portion. The first conductive shielding structure is connected to a ground voltage or a constant voltage, which can also improve the coupling effect between adjacent channel structures 1035.

[0141] In other embodiments, referring to Figure 3H As shown, there may be no first air gap 1411 or a small amount of air gap inside the first top insulating portion 141 .

[0142] Finally, refer to Figure 3F to Figure 3L As shown, the above step S103 is performed to form a second gate 135 extending along the first direction z, the second gate 135 is located on the side of the active pillar 103 away from the first gate 133 in the second direction y, and the second gate 135 includes a second gate top surface 135a and a second gate bottom surface 135b opposite to each other in the first direction z, the second gate bottom surface 135b is close to the second end 1032, in the first direction z, the second gate top surface 135a is located on the side of the first gate top surface 133a close to the first end 1031, the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b close to the second end 1032, and the first direction z intersects with the second direction y.

[0143] In some embodiments, reference Figure 3F to Figure 3L As shown, forming a second gate 135 extending along the first direction z includes: removing the protection layer 123 and the sacrificial layer 122 in the second groove 10d; forming a second bottom insulating portion 142 in the second groove 10d, the size of the second bottom insulating portion 142 in the first direction z is smaller than the depth of the second groove 10d; and forming a second gate 135 on the second bottom insulating portion 142.

[0144] Reference Figure 3G and Figure 3H As shown, the second bottom insulating portion 142 includes an insulating core 1421 and a protective layer 1422. The protective layer 1422 covers the side walls of the insulating core 1421 and the bottom wall of the insulating core 1421. The bottom wall of the insulating core 1421 is close to the bottom of the second groove 10d. The material of the insulating core 1421 is different from that of the protective layer. The material of the insulating core 1421 includes but is not limited to silicon oxide, and the material of the protective layer 1422 includes but is not limited to silicon nitride.

[0145] It should be noted that, during the process of forming the second bottom insulating portion 142 , the protection layer 1422 plays a role in protecting the active pillar 103 .

[0146] In some embodiments, reference Figure 3G As shown, there is a second air gap 1423 inside the second bottom insulating portion 142. The second air gap 1423 improves the coupling effect between the two channel structures 1035 adjacent to the second bottom insulating portion 142, that is, it can further improve the hammer problem of the semiconductor device. Wherein, in the case where there is a second air gap 1423 inside the second bottom insulating portion 142, the second air gap 1423 is located inside the insulating core 1421. In other embodiments, a second conductive shielding structure (not shown) can also be formed in the second groove 10d, and a second isolation portion (not shown) is provided between the second conductive shielding structure and the active column 103. The second conductive shielding structure is connected to the ground potential or a constant voltage, which can also improve the coupling effect between adjacent channel structures 1035.

[0147] In other embodiments, referring to Figure 3H As shown, there may be no second air gap 1423 or a small amount of air gap inside the second bottom insulating portion 142 .

[0148] In some embodiments, reference Figure 3G and Figure 3H As shown, after forming the second bottom insulating portion 142 , the mask pattern 121 is removed.

[0149] In some embodiments, reference Fig. 3I As shown, before forming the second gate 135 on the second bottom insulating portion 142, the method for manufacturing a semiconductor device further includes: forming a second gate insulating layer 113 on the sidewall of the second groove 10d and the second bottom insulating portion 142. The second gate insulating layer 113 serves to isolate the second gate 135 from the active pillar 103. The material of the second gate insulating layer 113 includes, but is not limited to, oxide materials such as silicon oxide.

[0150] In some embodiments, reference FIG. 3I to FIG. 3K As shown, forming the second gate 135 on the second bottom insulating portion 142 includes: forming a second conductive layer 134, the second conductive layer 134 covers the second gate insulating layer 113 in the second groove 10d and fills the second groove 10d, the second conductive layer 134 also covers the top surface of the first top insulating portion 141 away from the first initial gate 132 and the end surface of the active column 103 away from the second surface 10b; removing part of the second conductive layer 134, and the remaining second conductive layer 134 in the second groove 10d constitutes the second gate 135.

[0151] In some embodiments, removing part of the second conductive layer 134 includes: removing the second conductive layer 134 outside the second groove 10d by using a chemical machine polishing process, and removing part of the second conductive layer 134 in the second groove 10d by using an etching process to form a second gate 135. Removing part of the second conductive layer 134 by using a chemical machine polishing process and an etching process to form the second gate 135 is conducive to simplifying the manufacturing process of the second gate 135, thereby simplifying the manufacturing process of the semiconductor device.

[0152] In some embodiments, when the second conductive layer 134 outside the second groove 10d is removed by chemical machine polishing, the second gate insulating layer 113 outside the second groove 10d and the portion of the first top insulating portion 141 protruding from the active pillar 103 can also be removed simultaneously.

[0153] It should be noted that in some related technologies, the preparation of the gate requires a punching process, which is difficult. In the present application, the second gate 135 is formed by a thin film deposition process, chemical mechanical polishing and etching process, and the preparation of the second gate 135 is simpler.

[0154] The second gate 135 includes a second gate top surface 135 a and a second gate bottom surface 135 b which are opposite to each other in the first direction z. The second gate bottom surface 135 b is in contact with the second bottom insulating portion 142 .

[0155] In some embodiments, the material of the second conductive layer 134 includes metal and non-metal conductive materials. The metal includes but is not limited to at least one of tungsten, aluminum, and copper. The non-metal conductive material includes but is not limited to titanium nitride.

[0156] In some embodiments, a sum of a size of the second gate 135 in the first direction z and a size of the second bottom insulating portion 142 in the first direction z is smaller than a depth of the second groove 10 d .

[0157] In some embodiments, reference Figure 3J to Figure 3L As shown, after forming the second gate 135, the method for manufacturing a semiconductor device further includes: forming a second top insulating portion 143 filling the second groove 10d on the second gate 135. The second top insulating portion 143 is used to isolate the second gate 135 from other structures and protect the second gate 135.

[0158] In some embodiments, the material of the second top insulating portion 143 is the same as that of the first top insulating portion 141. The size of the first top insulating portion 141 in the first direction z is larger than the size of the second top insulating portion 143 in the first direction z, which is beneficial for at least a portion of the first gate 133 to be staggered with the second gate 135 in the first direction.

[0159] In some embodiments, please refer to Figure 3J and Figure 3K As shown, after forming the second top insulating portion 143 , the method for manufacturing the semiconductor device further includes: performing ion doping treatment on the first end 1031 of the active pillar 103 to form a first electrode 1033 ; and forming a capacitor (not shown) connected to the first electrode 1033 .

[0160] In some embodiments, reference Figure 3M to Figure 3O As shown, after forming the capacitor, removing a portion of the first initial gate 132 near the second end 1032 includes: thinning the second surface 10b of the semiconductor layer 10 to expose the dielectric layer 111, and forming a thinned third surface 10e. The surface of the dielectric layer 111 and the surface of the semiconductor layer 10 together constitute the third surface 10e.

[0161] In some embodiments of the present application, the second surface 10b of the semiconductor layer 10 is thinned to expose the dielectric layer 111 and form a thinned third surface 10e, so as to form an opening 10f on the third surface 10e to expose the first initial gate 132, and the first initial gate 132 is etched back to form a first gate 133.

[0162] In some embodiments, reference Figure 3P to Figure 3R As shown, after the third surface 10e is formed, removing a portion of the first initial gate 132 close to the second end 1032 also includes: forming an opening 10f in the dielectric layer 111 to expose the first initial gate 132, the opening 10f being recessed from the third surface 10e to the first surface 10a; and removing a portion of the first initial gate 132 close to the second end 1032 through the opening 10f, and the remaining first initial gate 132 constitutes the first gate 133.

[0163] The first gate 133 includes a first gate top surface 133a and a first gate bottom surface 133b opposite to each other in the first direction z, and the first gate top surface 133a is in contact with the first top insulating portion 141. The second gate top surface 135a is located on a side of the first gate top surface 133a close to the first electrode 1033, and the first gate bottom surface 133b is located on a side of the second gate bottom surface 135b away from the first electrode 1033.

[0164] In some embodiments of the present application, after the second surface 10b of the semiconductor layer 10 is thinned, a third surface 10e is formed. Next, an opening 10f is formed in the dielectric layer 111 and exposes the first initial gate 132 from the third surface 10e to the first surface 10a. Finally, the first initial gate 132 is etched back. This method is used to ensure that the first gate bottom surfaces 133b of the multiple first gates 133 are aligned, so as to better ensure that the sizes of the multiple first gates 133 in the first direction z are controllable and uniform.

[0165] In some embodiments, each opening 10f extends along the second direction y, and the opening 10f exposes the first initial gate 132 and the second bottom insulating portion 142. A plurality of second openings 10f are arranged at intervals along the third direction x. In the third direction x, a row of active pillars 103 is arranged between two adjacent second openings 10f, and a row of active pillars 103 includes a plurality of active pillars 103 arranged side by side along the second direction y.

[0166] In some embodiments, reference Figure 3S As shown, the method for manufacturing a semiconductor device further includes: forming a first bottom insulating portion 144 near the second end 1032 on the first gate 133 through the opening 10f. The first bottom insulating portion 144 contacts the bottom surface 133b of the first gate and fills the space between the first gate 133 and the semiconductor layer 10 to isolate the first gate 133 from the semiconductor layer 10.

[0167] It should be noted that, refer to Figure 3T As shown, the insulating filling layer 124 is formed by a thin film deposition process. The insulating filling layer 124 includes the first bottom insulating portion 144 . Part of the insulating filling layer 124 also fills the opening 10 f . The insulating filling layer 124 covers the second bottom insulating portion 142 .

[0168] In some embodiments, the material of the insulating filling layer 124 is the same as that of the dielectric layer. Specifically, the material of the insulating filling layer 124 includes but is not limited to silicon oxide.

[0169] In some embodiments, please refer to Figure 3S As shown, after forming the first bottom insulating portion 144, the method for manufacturing the semiconductor device also includes: performing ion doping treatment on the second end 1032 of the active pillar 103 to form a second electrode 1034, and the remaining active pillar 103 constitutes a channel structure 1035; and forming a bit line (not shown) connected to the second electrode 1034.

[0170] It should be noted that one of the first electrode 1033 and the second electrode 1034 is a source electrode, and the other of the first electrode 1033 and the second electrode 1034 is a drain electrode. The channel structure 1035 includes a first channel end 10351 and a second channel end 10352 opposite to each other in the first direction z, the first channel end 10351 is adjacent to and in contact with the first electrode 1033, and the plurality of second channel ends 10352 are adjacent to and in contact with the second electrode 1034.

[0171] In some embodiments, reference Figure 4A and Figure 4B As shown, the method for manufacturing a semiconductor device further includes: forming a first gate contact 151 connected to the first gate 133 ; and forming a second gate contact 152 connected to the second gate 135 .

[0172] In some embodiments, the first gate contact 151 and the second gate contact 152 are located on the same side of the plurality of channel structures 1035, so as to form the first gate contact 151 and the second gate contact 152 at the same time, thereby simplifying the manufacturing process of the semiconductor device. For example, the first gate contact 151 and the second gate contact 152 are located on a side of the second electrode 1034 away from the first electrode 1033.

[0173] Reference Figure 4A and Figure 4B As shown, the first gate 133 includes a first gate terminal 1331 and a second gate terminal 1332 that are opposite to each other in the third direction x. The second gate 135 includes a third gate terminal 1351 and a fourth gate terminal 1352 that are opposite to each other in the third direction x. The third gate terminal 1351 is close to the first gate terminal 1331. The first gate terminal 1331 is staggered with the third gate terminal 1351, and the fourth gate terminal 1352 is staggered with the second gate terminal 1332.

[0174] In some embodiments, reference Figure 4A As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133. At least one second gate contact 152 is connected to the third gate terminal 1351 of at least one second gate 135. In two adjacent first gates 133, the first gate terminal 1331 of one first gate 133 is connected to one first gate contact 151, and the second gate terminal 1332 of the other first gate 133 is connected to the other first gate contact 151. In two adjacent second gates 135, the third gate terminal 1351 of one second gate 135 is connected to one second gate contact 152, and the fourth gate terminal 1352 of the other second gate 135 is connected to the other second gate contact 152. With this design, the process windows of the first gate contact 151 and the second gate contact 152 are both large, further reducing the difficulty of manufacturing semiconductor devices.

[0175] In other embodiments, referring to Figure 4B As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133, and at least one second gate contact 152 is connected to the fourth gate terminal 1352 of at least one second gate 135. The first gate terminals 1331 of two adjacent first gates 133 are respectively connected to the two first gate contacts 151, and the fourth gate terminals 1352 of two adjacent second gates 135 are respectively connected to the two second gate contacts 152. With this design, the process windows of the first gate contacts 151 and the second gate contacts 152 are both large, further reducing the difficulty of manufacturing semiconductor devices.

[0176] In some embodiments of the present application, a first groove 10c and a second groove 10d are formed to intersect with a plurality of active lines 102. A first conductive layer 131 is formed in the first groove 10c, and the first conductive layer 131 is etched to form a first gate 133. A second conductive layer 134 is formed in the second groove 10d, and the second conductive layer 134 is etched to form a second gate 135. Therefore, the first gate 133 and the second gate 135 are both formed by etching the conductive layer, and the manufacturing process of the first gate 133 and the second gate 135 is simpler, which reduces the manufacturing process of the semiconductor device. Moreover, by using the manufacturing method of the semiconductor device of the present application, the size of the first gate 133 in the second direction y and the size of the second gate 135 in the second direction y can be smaller, which is conducive to increasing the number of the first gate 133, the second gate 135 and the channel structure 1035, thereby improving the storage density of the semiconductor device. Furthermore, the first air gap 1411 can improve the coupling effect between two adjacent channel structures 1035 in the second direction y, and the second air gap 1423 can also improve the coupling effect between two adjacent channel structures 1035 in the second direction y.

[0177] In some related technologies, a gate conductive layer is formed on the side wall and bottom wall of the groove, and the gate conductive layer is disconnected by a punching process to form two gate lines. Due to the difficulty of the punching process, the manufacturing difficulty of the semiconductor device is relatively greater.

[0178] In some embodiments, reference Figure 3S , Figure 3U and Figure 3VAs shown, the second gate top surface 135a is located on the side of the first gate top surface 133a close to the first channel end 10351, and the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b close to the second channel end 10352. With this design, at least part of the first gate 133 is staggered with the second gate 135 in the first direction z, and each of the first gate 133 and the second gate 135 can be shared by two adjacent channel structures 1035 in the second direction y, that is, each of the first gate 133 and the second gate 135 can control whether the part of the two adjacent channel structures 1035 in the second direction y is in the on state or in the off state.

[0179] The present application also provides a semiconductor device prepared by the manufacturing method of the semiconductor device as described above, Figure 3S , Figure 3U , Figure 3V , Figure 4A as well as Figure 4B A semiconductor device of the present application is described.

[0180] The semiconductor device includes multiple channel structures 1035, multiple first gates 133, multiple second gates 135, a first bottom insulating portion 144, a second bottom insulating portion 142, a first top insulating portion 141, a second top insulating portion 143, a first gate contact 151, a second gate contact 152, a first gate insulating layer 112 and a second gate insulating layer 113.

[0181] A plurality of channel structures 1035 extend along a first direction z and are arranged in an array in a second direction y and a third direction x. Each channel structure 1035 includes a first channel end 10351 and a second channel end 10352 that are opposite to each other in the first direction z. The first channel end 10351 of the channel structure 1035 is connected to and in contact with the first electrode 1033. The second channel end 10352 of the channel structure 1035 is connected to and in contact with the second electrode 1034. One of the first electrode 1033 and the second electrode 1034 is a source, and the other of the first electrode 1033 and the second electrode 1034 is a drain.

[0182] Any two of the first direction z, the second direction y and the third direction x intersect each other. Specifically, any two of the first direction z, the second direction y and the third direction x are perpendicular to each other, but the present invention is not limited thereto.

[0183] The plurality of first gates 133 extend along the first direction z and the third direction x. The plurality of first gates 133 are arranged at intervals along the second direction y. One first gate 133 is located between two adjacent rows of channel structures 1035 in the second direction y. Each first gate 133 includes a first gate top surface 133a and a first gate bottom surface 133b opposite to each other in the first direction z, and the first gate top surface 133a is close to the first channel end 10351. A first gate insulating layer 112 is arranged between the first gate 133 and the sidewall of the channel structure 1035.

[0184] A plurality of second gates 135 extend along the first direction z and the third direction x. A plurality of second gates 135 are arranged at intervals along the second direction y. One second gate 135 is located on the side of the channel structure 1035 away from the first gate 133 in the second direction y, and one second gate 135 is located between two adjacent rows of channel structures 1035 in the second direction y. A second gate insulating layer 113 is arranged between the second gate 135 and the sidewall of the channel structure 1035. The second gate 135 includes a second gate top surface 135a and a second gate bottom surface 135b that are opposite to each other in the first direction z, and the second gate bottom surface 135b is close to the second channel end 10352.

[0185] In some embodiments, the plurality of first gate electrodes 133 and the plurality of second gate electrodes 135 are alternately and spaced apart in a one-to-one manner along the second direction y.

[0186] In some embodiments, for the adjacent first gate 133 and the second gate 135, in the first direction z, the second gate top surface 135a is located on the side of the first gate top surface 133a close to the first channel end 10351, and the first gate bottom surface 133b is located on the side of the second gate bottom surface 135b close to the second channel end 10352. With this design, at least a portion of the first gate 133 is staggered with the second gate 135 in the first direction z, and each of the first gate 133 and the second gate 135 can be shared by two adjacent channel structures 1035 in the second direction y, that is, each of the first gate 133 and the second gate 135 can control a portion of the two adjacent channel structures 1035 in the second direction y to be in an on state or an off state.

[0187] In some embodiments, reference Figure 3S As shown, in the first direction z, the second gate bottom surface 135b is located on the side of the first gate top surface 133a close to the first gate bottom surface 133b. With this design, in the first direction z, part of the first gate 133 is staggered with the second gate 135. Moreover, when the adjacent first gate 133 and the second gate 135 apply a voltage to the channel structure 1035 therebetween, the current of the channel structure 1035 when it is turned on will be larger.

[0188] In other embodiments, referring to Figure 3U As shown, in the second direction y, the first gate top surface 133a and the second gate bottom surface 135b are aligned.

[0189] It should be noted that, refer to Figure 3U As shown, the alignment in this application is an alignment within a certain process error range.

[0190] In other embodiments, referring to Figure 3V As shown, in the first direction z, the second gate bottom surface 135b is located on the side of the first gate top surface 133a away from the first gate bottom surface 133b. With this design, the first gate 133 and the second gate 135 are completely staggered.

[0191] It should be noted that for Figure 3V In the semiconductor device shown, in the first direction z, when the first gate 133 and the second gate 135 are completely staggered, for an area where the voltages of the first gate 133 and the second gate 135 cannot act on the channel structure 1035, the area of ​​the channel structure 1035 can be doped to reduce the resistance of the area, thereby ensuring that the channel structure 1035 is turned on under the action of the adjacent first gate 133 and the second gate 135.

[0192] For the semiconductor device of the present application, a gate group is used as a basic control unit to control the conduction of a channel structure 1035. A gate group includes a group of gate pairs and another group of gate pairs adjacent to each other in the second direction y, one group of gate pairs includes an adjacent first gate 133 and a second gate 135, and the other group of gate pairs includes another adjacent first gate 133 and another second gate 135, and one second gate 135 is arranged adjacent to another first gate 133. Therefore, a gate group includes two first gates 133 and two second gates 135.

[0193] In some embodiments of the present application, a control method of a gate group includes: a second gate 135 and another first gate 133 are respectively connected to a second gate on voltage and a first gate on voltage, and the first gate 133 and another second gate 135 are respectively connected to a first gate off voltage and a second gate off voltage. With this control method, the channel structure 1035 between a second gate 135 and another first gate 133 is turned on.

[0194] In some embodiments, reference Figure 4A and Figure 4BAs shown, the two opposite ends of the first gate 133 in the third direction x are staggered with the two opposite ends of the second gate 135 in the third direction x, so that the process windows of the first gate contact 151 connected to the first gate 133 and the second gate contact 152 connected to the second gate 135 are large enough, thereby simplifying the manufacturing process of the semiconductor device.

[0195] Specifically, the first gate 133 includes a first gate terminal 1331 and a second gate terminal 1332 that are opposite to each other in the third direction x. The second gate 135 includes a third gate terminal 1351 and a fourth gate terminal 1352 that are opposite to each other in the third direction x, and the third gate terminal 1351 is close to the first gate terminal 1331. The first gate terminal 1331 is staggered with the third gate terminal 1351, and the fourth gate terminal 1352 is staggered with the second gate terminal 1332.

[0196] In some embodiments, reference Figure 4A As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133. At least one second gate contact 152 is connected to the third gate terminal 1351 of at least one second gate 135. In two adjacent first gates 133, the first gate terminal 1331 of one first gate 133 is connected to one first gate contact 151, and the second gate terminal 1332 of the other first gate 133 is connected to the other first gate contact 151. In two adjacent second gates 135, the third gate terminal 1351 of one second gate 135 is connected to one second gate contact 152, and the fourth gate terminal 1352 of the other second gate 135 is connected to the other second gate contact 152. With this design, the process windows of the first gate contact 151 and the second gate contact 152 are both large, further reducing the difficulty of manufacturing semiconductor devices.

[0197] In other embodiments, referring to Figure 4B As shown, at least one first gate contact 151 is connected to the first gate terminal 1331 of at least one first gate 133, and at least one second gate contact 152 is connected to the fourth gate terminal 1352 of at least one second gate 135. The first gate terminals 1331 of two adjacent first gates 133 are respectively connected to the two first gate contacts 151, and the fourth gate terminals 1352 of two adjacent second gates 135 are respectively connected to the two second gate contacts 152. With this design, the process windows of the first gate contacts 151 and the second gate contacts 152 are both large, further reducing the difficulty of manufacturing semiconductor devices.

[0198] In some embodiments, the size of the first gate 133 in the third direction x is different from the size of the second gate 135 in the third direction x, so as to distinguish the first gate 133 and the second gate 135, reduce the difficulty of manufacturing the first gate 133 and the second gate 135, and further reduce the difficulty of manufacturing the semiconductor device. Figure 4A As shown, the size of the first gate 133 in the third direction x is larger than the size of the second gate 135 in the third direction x; or, the size of the first gate 133 in the third direction x is smaller than the size of the second gate 135 in the third direction x. Figure 4B As shown, the size of the first gate 133 in the third direction x may also be equal to the size of the second gate 135 in the third direction x.

[0199] In some embodiments, the size of the first gate 133 in the second direction y is the same as the size of the second gate 135 in the second direction y, which is conducive to the first groove 10c and the second groove 10d having the same size along the second direction y, simplifying the manufacturing process of the semiconductor device. In other embodiments, the size of the first gate 133 in the second direction y may be different from the size of the second gate 135 in the second direction y.

[0200] In the first direction z, the first bottom insulating portion 144 and the first top insulating portion 141 are located on both sides of the first gate. In the first direction z, the first bottom insulating portion 144 is located on the side of the first gate bottom surface 133b away from the first gate top surface 133a and contacts the first gate bottom surface 133b. In the first direction z, the first top insulating portion 141 is located on the side of the first gate top surface 133a away from the first gate bottom surface 133b and contacts the first gate top surface 133a. In some embodiments, the size of the first bottom insulating portion 144 along the first direction z is smaller than the size of the first top insulating portion 141 along the first direction z.

[0201] In some embodiments, the first top insulating portion 141 includes a first air gap 1411 therein to improve the coupling effect between two channel structures 1035 adjacent to the first top insulating portion 141 in the second direction y.

[0202] In the first direction z, the second bottom insulating portion 142 and the second top insulating portion 143 are located on opposite sides of the second gate. In the first direction z, the second bottom insulating portion 142 is located on a side of the second gate bottom surface 135b away from the second gate top surface 135a and contacts the second gate bottom surface 135b. In the first direction z, the second top insulating portion 143 is located on a side of the second gate top surface 135a away from the second gate bottom surface 135b and contacts the second gate top surface 135a. In some embodiments, the size of the second bottom insulating portion 142 along the first direction z is greater than the size of the second top insulating portion 143 along the first direction z.

[0203] In some embodiments, the second bottom insulating portion 142 includes a second air gap 1423 inside the second bottom insulating portion 142 to improve the coupling effect between two channel structures 1035 adjacent to the second bottom insulating portion 142 in the second direction.

[0204] In some embodiments, the size of the second bottom insulating portion 142 in the first direction z is larger than the size of the first bottom insulating portion 144 in the first direction z, and the size of the second top insulating portion 143 in the first direction z is smaller than the size of the first top insulating portion 141 in the first direction z, so as to accommodate the staggered arrangement of at least a portion of the first gate and the second gate in the first direction.

[0205] The second bottom insulating portion 142 includes an insulating core 1421 and a protection layer 1422 . The protection layer 1422 covers the sidewalls of the insulating core 1421 and the bottom wall of the insulating core 1421 away from the second gate 135 . The material of the insulating core 1421 is different from that of the protection layer 1422 .

[0206] In some embodiments of the present application, in the second direction, the first gate and the second gate are respectively located on opposite sides of the channel structure. In the first direction, the top surface of the second gate is located on the side of the top surface of the first gate close to the first channel end, and the bottom surface of the first gate is located on the side of the bottom surface of the second gate close to the second channel end. With this design, at least part of the first gate and the second gate are staggered in the first direction, and each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, that is, each of the first gate and the second gate can control the part of the two adjacent channel structures in the second direction to be in the on state or the off state. Moreover, on the basis that each of the first gate and the second gate can be shared by two adjacent channel structures in the second direction, the size of the first gate and the second gate in the second direction can be smaller, that is, it is conducive to miniaturization of the size of the first gate and the second gate in the second direction, and it is conducive to increasing the number of the first gate, the second gate and the channel structure, thereby increasing the storage density of the semiconductor device and improving the performance of the semiconductor device.

[0207] In addition, see Figure 5 and Figure 6 As shown, based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the above embodiments.

[0208] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0209] In some embodiments, reference Figure 5 As shown, the storage system 400 includes a memory 200 and a controller 300. The storage system 400 may be integrated into a three-dimensional memory card.

[0210] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0211] In other embodiments, referring to Figure 6 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0212] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0213] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0214] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0215] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0216] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0217] Please refer to Figure 7 Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0218] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0219] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A plurality of channel structures extending along a first direction, the channel structures comprising a first channel end and a second channel end opposite to each other in the first direction; a first gate extending along the first direction, located between adjacent channel structures, and comprising a first gate top surface and a first gate bottom surface opposite to each other in the first direction, wherein the first gate top surface is close to the first channel end; as well as A second gate extending along the first direction is located on a side of the channel structure facing away from the first gate in the second direction, and the second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface is close to the second channel end, in the first direction, the second gate top surface is located on a side of the first gate top surface close to the first channel end, the first gate bottom surface is located on a side of the second gate bottom surface close to the second channel end, and the first direction intersects with the second direction.

2. The semiconductor device according to claim 1, wherein: In the first direction, the second gate bottom surface is located on a side of the first gate top surface close to the first gate bottom surface.

3. The semiconductor device according to claim 1, wherein: In the second direction, the top surface of the first gate is aligned with the bottom surface of the second gate.

4. The semiconductor device according to claim 1, wherein: In the first direction, the second gate bottom surface is located on a side of the first gate top surface away from the first gate bottom surface.

5. The semiconductor device according to claim 1, wherein: Also includes: a first bottom insulating portion, wherein in the first direction, the first bottom insulating portion is located on a side of the first gate bottom surface away from the first gate top surface and is in contact with the first gate bottom surface; and A second bottom insulating portion, in the first direction, the second bottom insulating portion is located on a side of the second gate bottom surface away from the second gate top surface and contacts the second gate bottom surface, and the size of the second bottom insulating portion in the first direction is greater than the size of the first bottom insulating portion in the first direction.

6. The semiconductor device according to claim 5, characterized in that The second bottom insulating portion includes an insulating core and a protection layer, wherein the protection layer covers the sidewalls of the insulating core and a bottom wall of the insulating core away from the second gate, and the material of the insulating core is different from that of the protection layer.

7. The semiconductor device according to claim 1, wherein: Also includes: a first top insulating portion, wherein in the first direction, the first top insulating portion is located on a side of the first gate top surface away from the first gate bottom surface and is in contact with the first gate top surface; and A second top insulating portion, in the first direction, the second top insulating portion is located on a side of the second gate top surface away from the second gate bottom surface and contacts the second gate top surface, and the size of the second top insulating portion in the first direction is smaller than the size of the first top insulating portion in the first direction.

8. The semiconductor device according to claim 1, wherein: A plurality of the first grid electrodes and a plurality of the second grid electrodes are arranged alternately and at intervals along the second direction, and the first grid electrodes and the second grid electrodes further extend along a third direction, and the third direction intersects with the first direction and the second direction; The opposite ends of the first grid in the third direction are staggered with the opposite ends of the second grid in the third direction.

9. The semiconductor device according to claim 8, characterized in that A size of the first gate in the third direction is different from a size of the second gate in the third direction.

10. The semiconductor device according to claim 8, characterized in that The first gate includes a first gate end and a second gate end opposite to each other in the third direction; The second gate includes a third gate end and a fourth gate end opposite to each other in the third direction, and the third gate end is close to the first gate end; The semiconductor device further comprises: at least one first gate contact connected to the first gate terminal of at least one first gate; as well as At least one second gate contact is connected to the third gate terminal of at least one of the second gates.

11. The semiconductor device according to claim 10, characterized in that In two adjacent first gates, the first gate end of one of the first gates is connected to one of the first gate contacts, and the second gate end of the other of the first gates is connected to the other of the first gate contacts; In two adjacent second gates, the third gate terminal of one of the second gates is connected to one of the second gate contacts, and the fourth gate terminal of the other of the second gates is connected to the other of the second gate contacts.

12. The semiconductor device according to claim 8, characterized in that The first gate includes a first gate end and a second gate end opposite to each other in the third direction; The second gate includes a third gate end and a fourth gate end opposite to each other in the third direction, and the third gate end is close to the first gate end; The semiconductor device further comprises: at least one first gate contact connected to the first gate terminal of at least one first gate; as well as At least one second gate contact is connected to the fourth gate terminal of at least one of the second gates.

13. The semiconductor device according to claim 12, characterized in that The first gate ends of two adjacent first gates are connected to two first gate contacts respectively, and the fourth gate ends of two adjacent second gates are connected to two second gate contacts respectively.

14. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a plurality of active pillars extending along a first direction, the active pillars comprising first and second ends opposite to each other in the first direction; forming a first gate extending along the first direction between adjacent active pillars, the first gate comprising a first gate top surface and a first gate bottom surface opposite to each other in the first direction, the first gate top surface being close to the first end; and A second gate extending along the first direction is formed, the second gate is located on a side of the active column in the second direction away from the first gate, and the second gate includes a second gate top surface and a second gate bottom surface opposite to each other in the first direction, the second gate bottom surface is close to the second end, in the first direction, the second gate top surface is located on a side of the first gate top surface close to the first end, the first gate bottom surface is located on a side of the second gate bottom surface close to the second end, and the first direction intersects with the second direction.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that: The forming of a plurality of active pillars extending along the first direction comprises: forming a first groove and a second groove arranged along the second direction and extending along a third direction, wherein the first groove and the second groove intersect with the plurality of active lines, and opposite ends of the first groove in the third direction are staggered with opposite ends of the second groove in the third direction, and the third direction intersects with the first direction and the second direction; The first gate extending along the first direction and formed between adjacent active pillars comprises: Filling a first conductive layer in the first groove; removing a portion of the first conductive layer close to the first end, and the remaining first conductive layer forms a first initial gate; A portion of the first initial gate close to the second end is removed, and the remaining first initial gate forms the first gate.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The method further comprises: filling a dielectric layer in the plurality of recessed portions; The removing a portion of the first initial gate close to the second end comprises: Thinning the second surface of the semiconductor layer until the dielectric layer is exposed, and forming a thinned third surface; forming an opening in the dielectric layer to expose the first initial gate, wherein the opening is sunken from the third surface to the first surface; A portion of the first initial gate close to the second end is removed through the opening.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: The method further includes forming a first bottom insulating portion on the first gate through the opening and close to the second end.

18. The method for manufacturing a semiconductor device according to claim 15, characterized in that Before the first conductive layer is filled in the first groove, the method further includes: forming a sacrificial layer in the first groove and the second groove; forming a protection layer covering the sacrificial layer in the second groove; and The sacrificial layer in the first groove is removed.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that: The forming of the second gate extending along the first direction comprises: removing the protective layer and the sacrificial layer in the second groove; forming a second bottom insulating portion in the second groove, wherein a dimension of the second bottom insulating portion in the first direction is smaller than a depth of the second groove; and The second gate is formed on the second bottom insulating portion.

20. A storage system, characterized in that: include: A memory, comprising a semiconductor device as claimed in any one of claims 1 to 13; as well as The controller is connected to the memory and is used to control the memory.

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