Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment. The semiconductor device comprises a plurality of transistors stacked in the direction perpendicular to a substrate, and word lines penetrating through different layers and extending in the direction perpendicular to the substrate. The semiconductor layer comprises a first part in contact with the first electrode or the second electrode and a second part not in contact with the first electrode and the second electrode, and the first part only extends in the direction perpendicular to the substrate; the second part comprises a first extension part which extends along a direction perpendicular to the substrate and a second extension part which extends from the first extension part to a direction which is far away from the side wall of the word line and is parallel to the substrate; the plurality of semiconductor layers are disconnected. According to the scheme provided by the embodiment of the invention, the semiconductor device is simple in structure and simple in manufacturing process.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory (RAM, including DRAM and SRAM, etc.) and non-volatile memory (ROM and non-ROM) based on application.

[0003] In order to reduce the cost of memory products as much as possible, people hope to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and an electronic device, which can eliminate parasitic MOS tubes and simplify the process.

[0006] The present disclosure provides a semiconductor device, including:

[0007] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0008] A word line, extending through the different layers in a direction perpendicular to the substrate;

[0009] The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer comprises a first portion in contact with the first electrode or the second electrode, and a second portion not in contact with the first electrode or the second electrode, the first portion extending only in a direction perpendicular to the substrate; the second portion comprises a first extension portion extending in a direction perpendicular to the substrate and a second extension portion extending from the first extension portion to a direction away from the sidewall of the word line and parallel to the substrate;

[0010] The plurality of semiconductor layers of the plurality of transistors are physically disconnected and distributed in different regions of the sidewall of the word line.

[0011] In some embodiments, along a direction perpendicular to the substrate and perpendicular to an arrangement direction of the first electrode and the second electrode, a cross section of the semiconductor layer is U-shaped, and an opening of the U-shape faces a direction away from a side wall of the word line.

[0012] In some embodiments, the word line includes a vertical portion extending in a direction perpendicular to the substrate and a plurality of protruding portions extending from sidewalls of the vertical portion, wherein the protruding portions are located between semiconductor layers adjacent to each other in a direction perpendicular to the substrate.

[0013] In some embodiments, the transistor further comprises a gate insulating layer;

[0014] The semiconductor device further comprises:

[0015] Second insulating layers and conductive layers are alternately distributed in a direction perpendicular to the substrate; through holes penetrate each of the second insulating layers and each of the conductive layers;

[0016] The word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer are sequentially distributed in the through hole from inside to outside;

[0017] The first electrode and the second electrode are disposed on the conductive layer and are electrically connected to the semiconductor layer.

[0018] In some embodiments, the U-shaped opening of the semiconductor layer is filled with a film layer made of the same material as the insulating layer.

[0019] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor includes a first electrode and a second electrode, and the method for manufacturing the semiconductor device includes:

[0020] A substrate is provided, and sacrificial layer films and conductive films are alternately deposited on the substrate in sequence to form a plurality of stacked structures, each of which comprises a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a preset pattern, and a first insulating layer forming a complementary pattern to the preset patterns of the sacrificial layers and the conductive layers; the preset pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed;

[0021] A through hole is formed in a direction perpendicular to the substrate and simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure, wherein the through hole comprises a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and the sacrificial layer only exposes a side wall in the first sub-hole, the conductive layer only exposes a side wall in the second sub-hole, the first insulating layer exposes a side wall and a surface extending in a direction parallel to the substrate in the first sub-hole, and the first insulating layer only exposes a side wall in the second sub-hole; and the second sub-hole disconnects the first electrode and the second electrode in the conductive layer;

[0022] Depositing a semiconductor film, a gate insulating film and a gate electrode film filling the through hole in sequence in the through hole to form a semiconductor layer and a gate insulating layer of the transistor in multiple layers, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors;

[0023] Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes;

[0024] The semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.

[0025] In some embodiments, the forming of a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate comprises:

[0026] Forming an initial through hole penetrating the stack structure in a direction perpendicular to the substrate by dry etching the stack structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer;

[0027] Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed;

[0028] Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of a corresponding area of ​​the first insulating layer, thereby obtaining a through hole located in the sacrificial layer;

[0029] The aperture of the initial through hole in the conductive layer is increased by wet etching the conductive layer, and the conductive layer is divided into two parts to obtain a through hole located in the conductive layer.

[0030] In some embodiments, etching the first insulating layer and the sacrificial layer to expose the semiconductor layer in the first sub-hole comprises:

[0031] dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer;

[0032] The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

[0033] In some embodiments, after the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors in different layers, the method further includes:

[0034] An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

[0035] In some embodiments, the sacrificial layer film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0036] An embodiment of the present disclosure provides an electronic device, including the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments.

[0037] The disclosed embodiments include a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a word line running through the different layers and extending in a direction perpendicular to the substrate; the semiconductor layer includes a first portion in contact with the first electrode or the second electrode, and a second portion not in contact with the first electrode or the second electrode, the first portion extending only in a direction perpendicular to the substrate; the second portion includes a first extension extending in a direction perpendicular to the substrate and a second extension extending from the first extension away from the word line sidewall and parallel to the substrate; the plurality of semiconductor layers of the plurality of transistors are physically disconnected, and the plurality of semiconductor layers are distributed in different regions of the word line sidewall. In the semiconductor device provided by the disclosed embodiments, the plurality of semiconductor layers of the plurality of transistors are arranged at intervals, which can eliminate parasitic MOS tubes between layers, and the structure is simple and easy to manufacture.

[0038] Other features and advantages of the present disclosure will be described in the following description, and partly become apparent from the description, or be understood by implementing the present disclosure. The objects and advantages of the present disclosure can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0039] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution and do not constitute a limitation on the technical solution.

[0041] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment;

[0042] Figure 1B For along Figure 1A Schematic diagram of the aa' direction;

[0043] Figure 1C For along Figure 1ASchematic diagram of the bb' direction;

[0044] Figure 1D For along Figure 1A Schematic diagram of the cc' direction;

[0045] Figure 1E For along Figure 1A Schematic diagram of the dd' direction;

[0046] Figure 2 A schematic cross-sectional view along the aa' direction after a stacked structure is formed according to an exemplary embodiment;

[0047] Figure 3A A cross-sectional view of a conductive layer along a direction parallel to a substrate provided for an exemplary embodiment;

[0048] Figure 3B A cross-sectional view along the aa' direction after a preset pattern is formed provided by an exemplary embodiment;

[0049] Figure 3C A cross-sectional view along the bb' direction after a preset pattern is formed provided by an exemplary embodiment;

[0050] Figure 3D A cross-sectional view along the cc' direction after a preset pattern is formed provided by an exemplary embodiment;

[0051] Figure 3E A cross-sectional view along the dd' direction after a preset pattern is formed provided by an exemplary embodiment;

[0052] Figure 4A A cross-sectional view along the aa' direction after a capacitor is formed provided by an exemplary embodiment;

[0053] Figure 4B A cross-sectional view along the bb' direction after a capacitor is formed provided by an exemplary embodiment;

[0054] Figure 4C A cross-sectional view along the cc' direction after a capacitor is formed provided by an exemplary embodiment;

[0055] Figure 4D A cross-sectional view along the dd' direction after a capacitor is formed provided by an exemplary embodiment;

[0056] Figure 5A A cross-sectional view along the aa' direction after an initial through hole is formed provided for an exemplary embodiment;

[0057] Figure 5B A cross-sectional view along the bb' direction after an initial through hole is formed provided for an exemplary embodiment;

[0058] Figure 5CA cross-sectional view along the cc' direction after forming an initial through hole provided by an exemplary embodiment;

[0059] Fig. 6A A cross-sectional view along the aa' direction after the sacrificial layer is laterally etched provided for an exemplary embodiment;

[0060] Figure 6B A cross-sectional view along the bb' direction after the sacrificial layer is laterally etched provided for an exemplary embodiment;

[0061] Figure 6C A cross-sectional view along the cc' direction after the sacrificial layer is laterally etched provided for an exemplary embodiment;

[0062] Fig. 7A A cross-sectional view along the aa' direction after the first insulating layer and the fourth insulating layer are laterally etched provided for an exemplary embodiment;

[0063] Figure 7B A cross-sectional view along the bb' direction after the first insulating layer and the fourth insulating layer are laterally etched provided for an exemplary embodiment;

[0064] Figure 7C A cross-sectional view along the cc' direction after the first insulating layer and the fourth insulating layer are laterally etched provided for an exemplary embodiment;

[0065] Fig. 8A A cross-sectional view along the aa' direction after the conductive layer is laterally etched provided for an exemplary embodiment;

[0066] Figure 8B A cross-sectional view along the bb' direction after the conductive layer is laterally etched provided by an exemplary embodiment;

[0067] Figure 8C A cross-sectional view along the cc' direction after lateral etching of the conductive layer provided for an exemplary embodiment

[0068] Fig.9A A cross-sectional view along the aa' direction after forming a semiconductor layer, a gate insulating layer and a word line provided for an exemplary embodiment;

[0069] Fig. 9B A cross-sectional view along the bb' direction after forming a semiconductor layer, a gate insulating layer and a word line provided for an exemplary embodiment;

[0070] Fig. 9C A cross-sectional view along the cc' direction after forming a semiconductor layer, a gate insulating layer and a word line provided for an exemplary embodiment;

[0071] FIG10A is a schematic plan view of a mask pattern for forming the fifth trench provided by an exemplary embodiment;

[0072] Fig. 10BA cross-sectional view along the aa' direction after forming a fifth trench provided for an exemplary embodiment;

[0073] Fig. 10C A cross-sectional view along the bb' direction after forming a fifth trench provided for an exemplary embodiment;

[0074] Fig. 10D A cross-sectional view along the cc' direction after forming a fifth groove provided for an exemplary embodiment;

[0075] Fig.11A A cross-sectional view along the aa' direction after etching the sacrificial layer provided by an exemplary embodiment;

[0076] Fig. 11B A cross-sectional view along the bb' direction after etching the sacrificial layer provided by an exemplary embodiment;

[0077] Fig. 11C A cross-sectional view along the cc' direction after etching the sacrificial layer 9 provided in an exemplary embodiment;

[0078] Fig. 12A A cross-sectional view along the aa' direction after etching the semiconductor layer located in the first sub-hole provided by an exemplary embodiment;

[0079] Fig. 12B A cross-sectional view along the bb' direction after etching the semiconductor layer located in the first sub-hole provided by an exemplary embodiment;

[0080] Fig. 12C A cross-sectional view along the cc' direction after etching the semiconductor layer located in the first sub-hole is provided for an exemplary embodiment.

[0081] Fig.13A A cross-sectional view along the aa' direction after forming the second insulating layer provided for an exemplary embodiment;

[0082] Fig. 13B A cross-sectional view along the bb' direction after forming the second insulating layer provided by an exemplary embodiment;

[0083] Fig. 13C A cross-sectional view along the cc' direction after forming the second insulating layer is provided for an exemplary embodiment. DETAILED DESCRIPTION

[0084] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0085] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0086] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0087] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0088] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0089] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0090] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0091] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0092] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0093] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0094] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0095] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A.

[0096] With the development of 3D memory array stacking structure, various problems will be encountered; as the number of stacking layers increases, the array becomes larger, and the unit devices become closer, the presence of parasitic MOS tubes between different layers will have a greater impact on the retention of capacitor storage charge and the overall stability of the device. The present application proposes a semiconductor device and a method for removing parasitic MOS in a semiconductor device. The semiconductor device has a simple structure, a simple corresponding process, and reduces costs.

[0097] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment, Figure 1B For along Figure 1A Schematic diagram of the aa' direction, Figure 1C For along Figure 1A Schematic diagram of the bb' direction, Figure 1D For along Figure 1A Schematic diagram of the cc' direction, Figure 1E For along Figure 1A Schematic diagram of the dd' direction. Figure 1AOnly the structure of the active region 300 where the transistor is located is shown, and the structure of the capacitor region 200 is not shown. The semiconductor device may be a transistor, or a memory cell including a transistor, or a memory cell array including a memory cell, or a 3D stacked structure including a memory cell array, or a memory including a transistor or a memory cell array, etc.

[0098] like Figures 1A to 1E As shown, the present disclosure provides a semiconductor device, including:

[0099] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

[0100] A word line 40, penetrating through the different layers and extending in a direction perpendicular to the substrate 1;

[0101] The transistor may include a first electrode 51, a second electrode 52, and a semiconductor layer 23 surrounding the sidewall of the word line 40; the semiconductor layer 23 includes a first portion in contact with the first electrode 51 or the second electrode 51, and a second portion not in contact with the first electrode 51 or the second electrode 52, the first portion only extending in a direction perpendicular to the substrate 1; the second portion includes a first extension portion extending in a direction perpendicular to the substrate 1 and a second extension portion extending from the first extension portion to a direction away from the sidewall of the word line 40 and parallel to the substrate 1;

[0102] The semiconductor layers 23 of the transistors are physically separated and arranged, and the semiconductor layers 23 are distributed in different regions of the sidewall of the word line 40 .

[0103] The solution provided in this embodiment is that the multiple semiconductor layers of the multiple transistors are physically disconnected, which can eliminate the parasitic MOS tubes between the layers, reduce the leakage current, and improve the stability of the device. In addition, the structure can be realized through the following process characteristics and is easy to manufacture.

[0104] The manufacturing process corresponding to the structure does not need to make a dummy word line, and does not need to make a dummy isolation layer (spacer) on the conductor layer. Instead, a first insulating layer is filled outside the hole, and the first insulating layer is etched inside the hole to expand the hole diameter, so as to form two grooves on the first insulating layer. The semiconductor layer of the parasitic MOS tube is formed in the groove and at the end of the sacrificial layer, and a hole is opened outside the hole to remove the sacrificial layer and the first insulating layer to expose the semiconductor layer of the parasitic MOS tube.

[0105] The arrangement direction of the first electrode 51 and the second electrode 52 is a direction from the first electrode 51 to the second electrode 52, or a direction from the contact surface of the first electrode 51 and the semiconductor layer 23 to the contact surface of the second electrode 52 and the semiconductor layer 23. The arrangement direction perpendicular to the substrate 1 and perpendicular to the first electrode 51 and the second electrode 52 may be, for example, the cc' direction, and the arrangement direction perpendicular to the substrate 1 and parallel to the first electrode 51 and the second electrode 52 may be, for example, the aa' direction.

[0106] In some embodiments, along a direction perpendicular to the substrate 1 and perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52, the cross section of the semiconductor layer 23 may be U-shaped, and the opening of the U-shape faces a direction away from the side wall of the word line 40. The side wall of the word line 40 is a surface formed along the extension direction of the word line 40.

[0107] In some embodiments, the semiconductor device may further include a gate electrode 26, and the gate electrode 26 of transistors of different layers may be a part of the word line 40. It is understandable that before and after the word line 40 is formed, there is no need to separately manufacture the gate electrode 26, and after the word line 40 is manufactured, a part of the word line 40 serves as the gate electrode 26.

[0108] In some embodiments, the word line 40 is filled in the through hole, and its shape is adapted to the through hole. For example, the word line 40 may include a vertical portion extending in a direction perpendicular to the substrate 1 and a plurality of protrusions extending from the sidewalls of the vertical portion, and the protrusions extend in a direction parallel to the substrate 1 and perpendicular to the arrangement direction of the first electrode 51 and the second electrode 52, and the protrusions may be located between the semiconductor layers 23 adjacent to each other in a direction perpendicular to the substrate. The semiconductor layer 23 may be distributed on the opposite surfaces of two adjacent protrusions and on the sidewalls of the vertical portion defined between the two protrusions. That is, distributed on the lower surface of one protrusion (the surface facing the substrate 1 side) and the upper surface of another protrusion (the surface away from the substrate 1 side), as well as on the sidewalls of the vertical portion between the two protrusions.

[0109] In some embodiments, on a plane perpendicular to the substrate 1, the orthographic projections of the protrusion and the first electrode 51 and the second electrode 52 do not overlap. That is, in the vertical direction, the protrusion and the first electrode 51 and the second electrode 52 are at different distances from the substrate and are film layers at different heights.

[0110] In some embodiments, along a direction perpendicular to the substrate 1, the first electrode 51 and the second electrode 52 may be located in the same conductive film layer. It can be understood that the first electrode 51 and the second electrode 52 are formed by patterning the same conductive film layer. In some embodiments, the conductive film layer is approximately parallel to the upper surface of the substrate 1. However, the embodiments of the present disclosure are not limited thereto, and the first electrode 51 and the second electrode 52 may be located in different conductive film layers.

[0111] In an exemplary embodiment, the first electrode 51 or the second electrode 52 of transistors in different layers may be located in different conductive film layers distributed in a vertical direction and isolated by an insulating film layer or the like.

[0112] In some embodiments, the transistor may further include: a gate insulating layer 24 disposed between the word line 40 and the semiconductor layer 23 , and the gate insulating layer 24 may surround a sidewall of the word line 40 .

[0113] In some embodiments, the gate insulating layers 24 of multiple transistors at different layers are an integrated structure. In this embodiment, the gate insulating layers 24 of each transistor can be deposited on the inner sidewall of the through hole in one process, and subsequent processes do not need to be cut, thereby simplifying the process. However, the embodiments of the present disclosure are not limited thereto, and the gate insulating layers 24 of multiple transistors at different layers can be disconnected.

[0114] In some embodiments, the semiconductor device may further include:

[0115] The second insulating layers 11 and the conductive layers are alternately distributed in a direction perpendicular to the substrate 1; and a through hole penetrates each of the second insulating layers 11 and each of the conductive layers;

[0116] The word line 40, the gate insulating layer 24 surrounding the sidewall of the word line 40, and the plurality of semiconductor layers 23 surrounding different regions of the sidewall of the gate insulating layer 24 are sequentially distributed in the through hole from the inside to the outside with the hole center as a reference;

[0117] The first electrode 51 and the second electrode 52 of the same transistor are disposed in one of the conductive layers and are electrically connected to the semiconductor layer 23 .

[0118] In this embodiment, transistors stacked in different layers share the hole where the word line 40 is located, and the gate electrode 26 , the gate insulating layer 24 , and the semiconductor layer 23 of the stacked transistors are formed in the hole in one process, which can simplify the process.

[0119] In some embodiments, a plurality of the second insulating layers 11 distributed between different conductive layers are connected to form an integrated structure, the integrated structure comprising a lateral extension portion disposed between adjacent conductive layers and a longitudinal extension portion extending in a direction perpendicular to the substrate 1, the longitudinal extension portion being provided with a protrusion disposed between adjacent conductive layers and facing the side wall of the word line 40, such as Figure 1D As shown, the longitudinal extension portion of the second insulating layer 11 includes a plurality of protrusions, which face the sidewalls of the word line 40 and correspond one to one with the protrusions of the word line 40. When manufacturing the semiconductor layer, after etching away the semiconductor layer of the parasitic MOS outside the hole, the insulating film layer is filled to form the protrusions of the longitudinal extension portion.

[0120] The second insulating layer is not only filled between the stacked adjacent conductive layers but also filled in the U-shaped opening. The second insulating layer may be a silicon oxide film layer.

[0121] In some embodiments, the semiconductor device further comprises a first insulating layer 10, which is disposed between the longitudinal extension of the second insulating layer 11 and the semiconductor layer 23 and fills the U-shaped opening of the semiconductor layer 23. In some embodiments, the semiconductor device may be a memory cell array, wherein the memory cell array comprises a plurality of memory cells, and the memory cells comprise transistors. Figure 1A As shown, the transistors in the same layer form a memory cell array distributed along the first direction X and the second direction Y respectively. Each layer may also include: a bit line 30 connected to the second electrode 52 of the transistors in the same column in one layer. Figure 1A It is shown that each layer includes four rows and two columns of storage units, but the embodiments of the present disclosure are not limited thereto. Each layer may include storage units with other numbers of rows and columns, for example, may include only one storage unit.

[0122] In some embodiments, the second electrodes 52 of the transistors of the memory cells in two adjacent columns are connected to the same bit line 30 .

[0123] In some embodiments, the second electrode 52 of the transistor may be a part of the bit line 30 connected to the second electrode 52. For example, the bit line 30 is a straight line, and the sidewall of the straight line in the extension direction is connected to the semiconductor layer 23, or the bit line 30 has an integrally designed branch, and the branch is connected to the semiconductor layer 23, wherein the extension direction of the branch intersects with the extension direction of the bit line 30, such as being approximately perpendicular.

[0124] The branches may be a plurality of branches on one side wall of the bit line, or a plurality of branches on both side walls at the same time, and each branch may form a transistor or a memory cell accordingly.

[0125] In some embodiments, the bit line 30 may extend along the second direction Y, the first electrode 51 and the second electrode 52 may extend along the first direction X, respectively, and the first electrode 51 and the second electrode 52 are sequentially arranged along the first direction X.

[0126] The stacked transistor can be applied to multiple memory cell scenarios of memory, such as traditional 1T and 2T memory cells in DRAM scenarios, memory cells with or without capacitors, or 4T or 6T memory cell scenarios in SRAM.

[0127] In some embodiments, the semiconductor device may further include a data storage element of a memory.

[0128] In some embodiments, the data storage element is, for example, a capacitor, that is, a 1T1C storage structure is formed. However, the embodiments of the present disclosure are not limited thereto, and other transistors may be combined to form a 2T0C storage structure, and so on.

[0129] In some embodiments, the capacitor may include a first pole 41 and a second pole 42 , wherein the first pole 41 is connected to the first electrode 51 .

[0130] In some embodiments, the first pole 41 and the first electrode 51 may be connected to form an integrated structure, or they may share one electrode, which may be a wire extending laterally in a direction parallel to the substrate 1 .

[0131] In some embodiments, the first electrode 41 may include a first end surface facing the word line 40 and a second end surface away from the word line 40, as well as a side surface connecting the first end surface and the second end surface, the first electrode 51 serves as the first electrode 41 of the capacitor, and the second electrode 42 surrounds the side surface of the first electrode 51.

[0132] In some embodiments, the semiconductor device may further include: a support layer 45 extending in a direction perpendicular to the substrate 1, the support layer 45 connecting the second end surface of each first electrode 51. The support layer 45 forms a plate-like film layer extending in a direction perpendicular to the substrate 1, and may be formed before manufacturing the capacitor to provide support for the subsequent manufacturing process of forming the capacitor.

[0133] In some embodiments, the support layer 45 may wrap the second end surface of each first electrode 51, and contact the area of ​​the side surface of the first electrode 51 close to the second end surface, so as to support the first electrode 51. In this solution, the support layer 45 may be partially laid on the upper surface of the first electrode 51, so as to enhance the support performance of the support layer 45.

[0134] In some embodiments, transistors stacked along a direction perpendicular to the substrate 1 are periodically distributed in the direction perpendicular to the substrate 1 .

[0135] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made by a deposition or coating process of a certain material. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0136] In an exemplary embodiment, the method for manufacturing the semiconductor device includes:

[0137] 1) A sacrificial layer film and a first conductive film are sequentially deposited on a substrate 1 to form a stacked structure including a sacrificial layer 9 and a conductive layer 12 arranged alternately, such as Figure 2 As shown, Figure 2 The cross-sectional schematic diagram along the aa' direction after forming the stacked structure is provided for an exemplary implementation, and the cross-sectional schematic diagrams along the bb' direction, the cc' direction and the dd' direction are similar and thus omitted. In some embodiments, a sacrificial layer 9 is disposed on the topmost conductive layer 12, and the bottommost sacrificial layer 9 can be used as a stop layer in subsequent etching operations.

[0138] In some embodiments, the sacrificial layer film may be an insulating material having a greater etching selectivity ratio with the conductive layer and the isolation layer, including but not limited to aluminum oxide (Al 2 O 3 ) and the like.

[0139] In some embodiments, the first conductive film may be a conductive material as follows:

[0140] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0141] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0142] Alternatively, it may be polysilicon material, doped semiconductor material, etc., for example, doped silicon, doped germanium, doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0143] Figure 2 The stacked structure shown in FIG. 1 includes four sacrificial layers 9 and three conductive layers 12 , which is only an example. In other embodiments, the stacked structure may include more or fewer film layers.

[0144] 2) patterning the stacked structure so that the stacked structure forms a preset pattern;

[0145] The patterning of the stacked structure may include:

[0146] Using a mask containing a preset pattern, the stacked structure is etched from the top layer to the bottom layer (excluding the substrate 1) by dry etching, so that the conductive layer 12 and the sacrificial layer 9 both form a preset pattern, and the preset pattern defines the transistor electrode pattern and the bit line pattern. Figure 3A As shown, in the stacked structure, the mask shielding part is retained, and the unshielded part is removed, and the removed area forms a first groove. The first groove extends along the X direction, and the area between the first grooves is a strip area extending along the X direction.

[0147] The preset pattern of the conductive layer 12 may include a plurality of first conductive portions 121 and second conductive portions 122, wherein the first conductive portions 121 may extend along a first direction X, and the second conductive portions 122 may extend along a second direction Y;

[0148] Depositing a first insulating film to form a first insulating layer 10 filling the first trench and covering the stacked structure; Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E As shown, Figure 3A is a cross-sectional view of the conductive layer 12 along a direction parallel to the substrate 1, Figure 3B To form a cross-sectional view along the aa' direction after forming a preset pattern, Figure 3C To form a cross-sectional view along the bb' direction after forming a preset pattern, Figure 3D This is a cross-sectional view along the cc' direction after forming a preset pattern. Figure 3EIt is a cross-sectional view along the dd' direction after the preset pattern is formed. The preset pattern and the pattern of the plurality of first grooves are complementary, that is, the pattern of the preset pattern and the pattern of the first grooves are combined to form the shape of the conductive layer 12 in step 1). The first direction X and the second direction Y may intersect. In some embodiments, the first direction X and the second direction Y may be perpendicular.

[0149] The first conductive portion 121 may subsequently form a first electrode 51 of a transistor, and the second conductive portion 122 may form a second electrode 52 of a transistor, and further, form a bit line 30 .

[0150] Alternatively, the first conductive portion 121 may subsequently form the first electrode 51 and the second electrode 52 of the transistor, and the second conductive portion 122 may form the bit line 30 .

[0151] In some embodiments, the first insulating film may include but is not limited to silicon oxide, such as silicon dioxide (SiO 2 ).

[0152] Figure 3A The preset shapes shown are only examples, and the preset shapes may be other shapes.

[0153] 3) Forming capacitance;

[0154] The forming of capacitance may include:

[0155] The stacked structure is etched from the top layer to the bottom layer in the support area 100 by dry etching to form a second groove, exposing the end surface of the first conductive part 121 away from the second conductive part 122; the support area 100 is located on the side of the first conductive part 121 away from the second conductive part 122.

[0156] A support layer thin film is deposited in the second groove to form a support layer 45, and the support layer 45 fills the second groove; the support layer 45 may be a plate-shaped film layer extending in a direction perpendicular to the substrate and parallel to the cc' direction.

[0157] Exposing the first conductive portion 121 located in the capacitor region 200;

[0158] Depositing a dielectric film and a conductor material in sequence to form a dielectric layer 43 and a second electrode 42 respectively, wherein the dielectric layer 43 covers the exposed area of ​​the first conductive layer 121;

[0159] Depositing a second conductive film to form a second conductive layer 7 covering the second electrode 42 and filling the third groove; the second conductive layer 7 is connected to the second electrode 42, and the second conductive layer 7 can be grounded, thereby realizing capacitor grounding;

[0160] Grinding the second conductive layer 7, depositing a third insulating film to form a third insulating layer 13, wherein the third insulating layer 13 covers the second conductive layer 7;

[0161] Etching is performed in the active area 300 by dry etching, and the etching stops at the topmost sacrificial layer to form a fourth trench; a fourth insulating film is deposited in the fourth trench and polished to form a fourth insulating layer 14 filling the fourth trench;

[0162] A fifth insulating film is deposited on the substrate having the above structure to form a fifth insulating layer 15, and the fifth insulating layer 15 covers the third insulating layer 13 and the fourth insulating layer 14; the fifth insulating layer 15 is used as a stop layer when the word line 40 is subsequently polished. Figure 4A , Figure 4B , Figure 4C , Figure 4D As shown, Figure 4A This is the cross-sectional view along the aa' direction after the capacitor is formed. Figure 4B This is the cross-sectional view along the bb' direction after the capacitor is formed. Figure 4C This is the cross-sectional view along the cc' direction after the capacitor is formed. Figure 4D This is a cross-sectional view along the dd' direction after the capacitor is formed. In subsequent steps, the cross-sectional view along the dd' direction remains unchanged, and the cross-sectional view along the dd' direction is no longer provided.

[0163] In some embodiments, the support layer film may be an insulating film layer different from the second insulating film eventually filled between transistors, including but not limited to silicon nitride (SiN).

[0164] In some embodiments, the dielectric film may be a High-K dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0165] In some embodiments, the conductor material includes but is not limited to at least one of the following: metal, metal alloy, polysilicon, silicon-doped conductive layer, and metal oxide conductive layer.

[0166] In some embodiments, the second conductive film includes but is not limited to metal, metal alloy, polysilicon, silicon-doped conductive layer, metal oxide conductive layer, such as Poly-GiSe, etc.

[0167] The second pole 42 may surround the side wall of the first conductive portion 121 , and the second pole 42 is insulated from the first conductive portion 121 by the dielectric layer 43 .

[0168] In some embodiments, the third insulating film includes but is not limited to silicon nitride (SiN).

[0169] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0170] In some embodiments, the fifth insulating film includes but is not limited to SiN.

[0171] 4) forming an initial through hole K0;

[0172] The forming of the initial through hole K0 may include: etching the stacked structure by dry etching to form a plurality of initial through holes K0 penetrating the stacked structure, wherein the sidewalls of the initial through holes K0 expose each of the conductive layer 12 and the sacrificial layer 9, and the aperture sizes of the initial through holes K0 at different layers are substantially consistent, and along the cc' direction, the size of the initial through hole K0 is smaller than the size of the first conductive portion 121, and the initial through hole K0 does not disconnect the conductive layer 12, and the entire area of ​​the conductive layer 12 remains connected, such as Figure 5A , Figure 5B and Figure 5C As shown, Figure 5A It is a cross-sectional view along the aa' direction after the initial through hole K0 is formed. Figure 5B It is a cross-sectional view along the bb' direction after the initial through hole K0 is formed. Figure 5C It is a cross-sectional view along the cc' direction after the initial through hole K0 is formed.

[0173] 5) Laterally etching the sacrificial layer 9;

[0174] The lateral etching of the sacrificial layer 9 may include: lateral etching of the sacrificial layer 9 in the initial through hole K0, and stopping when the etching reaches the first insulating layer 10, that is, in the cc' direction, the sacrificial layer 9 is etched through, and the side wall of the initial through hole K0 exposes the first insulating layer 10, at this time, in the aa' direction, the aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is larger than the aperture d1 of the second sub-hole of the initial through hole K0 located in the conductive layer 12, in the cc' direction, the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is larger than the aperture d3 of the second sub-hole located in the conductive layer 12, and in the cc' direction, the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 is consistent with the size of the sacrificial layer 9 along the cc' direction, such as Fig. 6A , Figure 6B and Figure 6C As shown, Fig. 6A is the cross-sectional view along the aa' direction, Figure 6B is the cross-sectional view along the bb' direction, Figure 6C It is a cross-sectional view along the cc' direction.

[0175] 6) Laterally etching the first insulating layer 10 and the fourth insulating layer 14;

[0176] The lateral etching of the first insulating layer 10 and the fourth insulating layer 14 may include: lateral etching of the first insulating layer 10 and the fourth insulating layer 14 in the initial through hole K0, etching the first insulating layer 10 to a preset thickness h, for example, 5nm to 15nm, and the etching thickness is less than the thickness of the first insulating layer along the cc' direction, so as to avoid the same initial through hole K0 being connected, resulting in the connection of the film layers of adjacent transistors, such as Fig. 7A , Figure 7B and Figure 7C As shown, Fig. 7A is the cross-sectional view along the aa' direction, Figure 7B is the cross-sectional view along the bb' direction, Figure 7C It is a cross-sectional view along the cc' direction.

[0177] At this time, the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction is further enlarged, that is, it is enlarged by 2 times the thickness of the first insulating layer 10 etched, that is, h*2. The aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the aa' direction remains unchanged. The apertures d1 and d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 remain unchanged.

[0178] 7) Laterally etching the conductive layer 12;

[0179] The laterally etching the conductive layer 12 may include: laterally etching the conductive layer 12 so that the first conductive portion 121 is disconnected from the second conductive portion 122. Fig. 8A , Figure 8B and Figure 8C As shown, Fig. 8A is a cross-sectional view along the aa' direction after the conductive layer 12 is laterally etched. Figure 8B is a cross-sectional view along the bb' direction after the conductive layer 12 is laterally etched. Figure 8C It is a cross-sectional view along the cc' direction after the conductive layer 12 is laterally etched.

[0180] like Figure 8C As shown, at this time, there is no conductive layer 12 on the cross section in the cc' direction, that is, in the cc' direction, the aperture d3 of the second sub-hole of the initial through hole K0 located in the conductive layer 12 is consistent with the size of the first conductive portion 121 along the cc' direction, but is still smaller than the aperture d4 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 in the cc' direction; in the aa' direction, the aperture d2 of the first sub-hole of the initial through hole K0 located in the sacrificial layer 9 can be equal to the aperture d1 of the second sub-hole of the initial through hole K0 located in the conductive layer 12.

[0181] At this point, the etching of the initial through hole K0 is completed, which is called through hole K1; in the aa' direction, the orthographic projection of the second sub-hole of the through hole K1 located in the conductive layer 12 on the substrate 1 can overlap with the orthographic projection of the first sub-hole of the through hole K1 located in the conductive sacrificial layer 9 on the substrate 1; in the cc' direction, the orthographic projection of the second sub-hole on the substrate 1 falls within the orthographic projection of the first sub-hole on the substrate 1, that is, in the cc' direction, there is an aperture difference between the sub-holes of the through hole K1 in the conductive layer 12 and the sacrificial layer 9, which is convenient for subsequent exposure of the semiconductor layer located in the first sub-hole.

[0182] 8) forming a semiconductor layer 23, a gate insulating layer 24 and a word line 40;

[0183] The forming of the semiconductor layer 23, the gate insulating layer 24 and the word line 40 may include:

[0184] A semiconductor film, a gate insulating film and a gate electrode film are sequentially deposited and polished in the through hole K1 to form a semiconductor layer 23, a gate insulating layer 24 and a word line 40. The gate electrode film fills the through hole K1. Fig.9A , Fig. 9B and Fig. 9C As shown, Fig.9A is a cross-sectional view along the aa' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed. Fig. 9B is a cross-sectional view along the bb' direction after the semiconductor layer 23, the gate insulating layer 24 and the word line 40 are formed. Fig. 9C It is a cross-sectional view along the cc′ direction after the semiconductor layer 23 , the gate insulating layer 24 and the word line 40 are formed.

[0185] In some embodiments, the semiconductor film, the gate insulating film, and the gate electrode film may be deposited by ALD.

[0186] In an exemplary embodiment of the present disclosure, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 2 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 2 eV.

[0187] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0188] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0189] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0190] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0191] In an exemplary embodiment of the present disclosure, the material of the gate insulating layer 24 may include one or more layers of High-K dielectric material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), titanium oxide (TiO2) and other high-K materials.

[0192] In some embodiments, the gate electrode film may be one or more of the following different types of materials:

[0193] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0194] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), aluminum doped zinc oxide (AZO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0195] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0196] 9) forming a fifth trench T5;

[0197] Exposing the sacrificial layer 9 and exposing a portion of the semiconductor layer 23 located in the first sub-hole may include: etching the stacked structure from the top layer to the bottom layer (excluding the substrate 1) by dry etching to form a plurality of fifth trenches T5, exposing the sidewalls of the sacrificial layer 9 and exposing a portion of the semiconductor layer 23 located in the first sub-hole, as shown in FIG. 10A, Fig. 10B , Fig. 10C and Fig. 10D 10A is a schematic plan view of a mask pattern for forming the fifth trench T5, Fig. 10B is a cross-sectional view along the aa' direction after the fifth trench T5 is formed. Fig. 10C is a cross-sectional view along the bb' direction after the fifth trench T5 is formed, Fig. 10D The cross-sectional view along the cc' direction after the fifth trench T5 is formed. The mask pattern includes a first region 101, a second region 102, a third region 103 and a fourth region 104. The first region 101 corresponds to the capacitor region, and the second region 102 corresponds to the region where the bit line 30 is located. The capacitor region and the region where the bit line 30 is located are both covered to avoid being etched. The third region 103 corresponds to the region where the word line 40 and the gate insulating layer 40 and the semiconductor layer 23 located in the second sub-hole are located. The fourth region 104 corresponds to the region where the first electrode 51 is located. The width s1 of the fourth region 104 can be the size of the first electrode 51 along the direction parallel to the cc' direction. The width s2 of the third region 103 can be the aperture d4 of the through hole K1 in the first sub-hole of the sacrificial layer 9 along the cc' direction. The length s3 can be the size of the semiconductor layer 23 located in the first sub-hole along the direction parallel to the aa' direction, so that the semiconductor layer 23 located in the first sub-hole and parallel to the aa' direction can be completely exposed.

[0198] 10) etching the sacrificial layer 9;

[0199] The etching of the sacrificial layer 9 may include: removing the remaining sacrificial layer 9 by wet etching to expose the semiconductor layer 23 located in the first sub-hole and parallel to the cc' direction, so that the semiconductor layer 23 located in the first sub-hole is exposed, which facilitates the subsequent removal of the semiconductor layer 23 located in the first sub-hole, such as Fig.11A , Fig. 11B and Fig. 11C As shown, Fig.11A is a cross-sectional view along the aa' direction after etching the sacrificial layer 9, Fig. 11B is a cross-sectional view along the bb' direction after etching the sacrificial layer 9, Fig. 11C It is a cross-sectional view along the cc' direction after etching the sacrificial layer 9.

[0200] 11) etching the semiconductor layer 23 located in the first sub-hole;

[0201] The etching of the semiconductor layer 23 located in the first sub-hole may include: removing the exposed semiconductor layer 23 located in the first sub-hole by wet etching, such as Fig. 12A , Fig. 12B and Fig. 12C As shown, Fig. 12A is a cross-sectional view along the aa' direction after etching the semiconductor layer 23 located in the first sub-hole, Fig. 12B is a cross-sectional view along the bb' direction after etching the semiconductor layer 23 located in the first sub-hole, Fig. 12C This is a cross-sectional view along the cc' direction after etching the semiconductor layer 23 located in the first sub-hole. It can be seen that the semiconductor layers 23 of different transistors have been disconnected, so that the parasitic MOS transistors between the layers can be eliminated.

[0202] 12) forming a second insulating layer 11;

[0203] The forming of the second insulating layer 11 may include: depositing a second insulating film on the substrate forming the aforementioned structure to form a fifth insulating layer 16 filling the area where the sacrificial layer 9 is located and the area where the semiconductor layer 23 is etched away, such as Fig.13A , Fig. 13B and Fig. 13C As shown, Fig.13A is a cross-sectional view along the aa' direction after the second insulating layer 11 is formed. Fig. 13B is a cross-sectional view along the bb' direction after the second insulating layer 11 is formed. Fig. 13C It is a cross-sectional view along the cc' direction after the second insulating layer 11 is formed.

[0204] In some embodiments, the second insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO 2 ) and the like.

[0205] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor includes a first electrode and a second electrode, and the method for manufacturing the semiconductor device includes:

[0206] A substrate is provided, and sacrificial layer films and conductive films are alternately deposited on the substrate in sequence to form a plurality of stacked structures, each of which comprises a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a preset pattern, and a first insulating layer forming a complementary pattern to the preset patterns of the sacrificial layers and the conductive layers; the preset pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed;

[0207] A through hole is formed in a direction perpendicular to the substrate and simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure, wherein the through hole comprises a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and the sacrificial layer only exposes a side wall in the first sub-hole, the conductive layer only exposes a side wall in the second sub-hole, the first insulating layer exposes a side wall and a surface extending in a direction parallel to the substrate in the first sub-hole, and the first insulating layer only exposes a side wall in the second sub-hole; and the second sub-hole disconnects the first electrode and the second electrode in the conductive layer;

[0208] Depositing a semiconductor film, a gate insulating film and a gate electrode film filling the through hole in sequence in the through hole to form a semiconductor layer and a gate insulating layer of the transistor in multiple layers, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors;

[0209] Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes;

[0210] The semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.

[0211] In some embodiments, the forming of a through hole that simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure in a direction perpendicular to the substrate comprises:

[0212] Forming an initial through hole penetrating the stack structure in a direction perpendicular to the substrate by dry etching the stack structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer;

[0213] Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed;

[0214] Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of a corresponding area of ​​the first insulating layer, thereby obtaining a through hole located in the sacrificial layer;

[0215] The aperture of the initial through hole in the conductive layer is increased by wet etching the conductive layer, and the conductive layer is divided into two parts to obtain a through hole located in the conductive layer.

[0216] In some embodiments, etching the first insulating layer and the sacrificial layer to expose the semiconductor layer in the first sub-hole comprises:

[0217] dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer;

[0218] The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

[0219] In some embodiments, after the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors in different layers, the method further includes:

[0220] An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

[0221] In some embodiments, the sacrificial layer film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

[0222] The present disclosure also provides an electronic device, including the semiconductor device of the aforementioned embodiment, or including a semiconductor device formed using any of the aforementioned semiconductor device manufacturing methods. The electronic device may be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0223] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A word line, extending through the different layers in a direction perpendicular to the substrate; The transistor comprises a first electrode, a second electrode and a semiconductor layer surrounding the sidewall of the word line; the semiconductor layer comprises a first portion in contact with the first electrode and the second electrode, and a second portion not in contact with the first electrode and the second electrode, the first portion extending only in a direction perpendicular to the substrate; the second portion comprises a first extension portion extending in a direction perpendicular to the substrate and a second extension portion extending from the first extension portion to a direction away from the sidewall of the word line and parallel to the substrate; The plurality of semiconductor layers of the plurality of transistors are physically disconnected and distributed in different regions of the sidewall of the word line.

2. The semiconductor device according to claim 1, wherein: Along a direction perpendicular to the substrate and perpendicular to an arrangement direction of the first electrode and the second electrode, a cross section of the semiconductor layer is U-shaped, and an opening of the U-shape faces a direction away from a side wall of the word line.

3. The semiconductor device according to claim 1, wherein: The word line includes a vertical portion extending in a direction perpendicular to the substrate and a plurality of protruding portions extending from side walls of the vertical portion, wherein the protruding portions are located between the semiconductor layers adjacent to each other in a direction perpendicular to the substrate.

4. The semiconductor device according to claim 2, characterized in that The transistor further comprises a gate insulating layer; The semiconductor device further comprises: Insulating layers and conductive layers are alternately distributed in a direction perpendicular to the substrate; through holes penetrate each of the insulating layers and each of the conductive layers; The word line, the gate insulating layer surrounding the sidewall of the word line, and the plurality of semiconductor layers surrounding different regions of the sidewall of the gate insulating layer are sequentially distributed in the through hole from inside to outside; The first electrode and the second electrode are disposed on the conductive layer and are electrically connected to the semiconductor layer.

5. The semiconductor device according to claim 4, characterized in that The U-shaped opening of the semiconductor layer is filled with a film layer made of the same material as the insulating layer.

6. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises a plurality of transistors stacked in a direction perpendicular to a substrate, and a word line extending in a direction perpendicular to the substrate through different layers, wherein the transistor comprises a first electrode and a second electrode, and a method for manufacturing the semiconductor device comprises: A substrate is provided, and sacrificial layer films and conductive films are alternately deposited on the substrate in sequence to form a plurality of stacked structures, each of which comprises a stack of a plurality of sacrificial layers and a plurality of conductive layers alternately arranged to form a preset pattern, and a first insulating layer forming a complementary pattern to the preset patterns of the sacrificial layers and the conductive layers; the preset pattern of the conductive layer comprises a first electrode and a second electrode of the transistor to be formed; A through hole is formed in a direction perpendicular to the substrate and simultaneously penetrates each sacrificial layer and each conductive layer of the stacked structure, wherein the through hole comprises a plurality of first sub-holes respectively located in the sacrificial layer and a plurality of second sub-holes respectively located in the conductive layer, and the sacrificial layer only exposes a side wall in the first sub-hole, the conductive layer only exposes a side wall in the second sub-hole, the first insulating layer exposes a side wall and a surface extending in a direction parallel to the substrate in the first sub-hole, and the first insulating layer only exposes a side wall in the second sub-hole; and the second sub-hole disconnects the first electrode and the second electrode in the conductive layer; Depositing a semiconductor film, a gate insulating film and a gate electrode film filling the through hole in sequence in the through hole to form a semiconductor layer and a gate insulating layer of the transistor in multiple layers, as well as a word line; wherein the semiconductor layer is connected to the first electrode and the second electrode corresponding to each layer of transistors; Etching the first insulating layer and each of the sacrificial layers outside the through hole to expose the semiconductor layer located in each of the first sub-holes; The semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors at different layers.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The through hole formed in a direction perpendicular to the substrate and penetrating through each sacrificial layer and each conductive layer of the stacked structure comprises: Forming an initial through hole penetrating the stack structure in a direction perpendicular to the substrate by dry etching the stack structure in one process, wherein the initial through hole located in the conductive layer is completely surrounded by the conductive layer; Using the conductive layer as a barrier layer, wet-etching the sacrificial layer in the initial through hole to increase the aperture of the initial through hole in the sacrificial layer until the first insulating layer is exposed; Using the conductive layer and the sacrificial layer as barrier layers, wet-etching the exposed first insulating layer to increase the aperture of a corresponding area of ​​the first insulating layer, thereby obtaining a through hole located in the sacrificial layer; The aperture of the initial through hole in the conductive layer is increased by wet etching the conductive layer, and the conductive layer is divided into two parts to obtain a through hole located in the conductive layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The etching of the first insulating layer and the sacrificial layer to expose the semiconductor layer in the first sub-hole comprises: dry-etching the first insulating layer outside the through hole to expose the sidewall of each sacrificial layer connected to the first insulating layer and the semiconductor layer located in the first sub-hole and connected to the first insulating layer; The entire sacrificial layer is removed by wet etching to expose the semiconductor layer located in the first sub-hole and connected to the sacrificial layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After the semiconductor layer in the first sub-hole is removed by etching so as to disconnect the semiconductor layers of transistors in different layers, the method further includes: An insulating film is deposited to form a second insulating layer filling the etched sacrificial layer and the area where the first insulating layer is located.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The sacrificial layer film includes silicon nitride or aluminum oxide, and the first insulating layer and the second insulating layer are silicon oxide.

11. An electronic device, characterized in that: A semiconductor device comprising any one of claims 1 to 5, or a semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 6 to 10.

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