Memory cell, memory device, and method of manufacturing a memory device

Abstract

The present application provides a memory cell, comprising: a write transistor including a first semiconductor channel, a first source-drain and a second source-drain; a read transistor including a second semiconductor channel, a third source-drain and a fourth source-drain; a part of the first semiconductor channel between the first source-drain and the second source-drain is a first effective semiconductor channel; a part of the second semiconductor channel between the third source-drain and the fourth source-drain is a second effective semiconductor channel; a channel outer ring size of a part of the first effective semiconductor channel close to the first source-drain is different from a channel outer ring size of a part of the first effective semiconductor channel close to the second source-drain; a channel outer ring size of a part of the second effective semiconductor channel close to the third source-drain is different from a channel outer ring size of a part of the second effective semiconductor channel close to the fourth source-drain. The present application also provides a memory device and a manufacturing method thereof. The present application can improve channel length and improve storage density.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a storage unit, a storage device and a manufacturing method of the storage device. BACKGROUND

[0002] With the further improvement of the requirements of mobile consumer electronic products for miniaturization, function integration and large-capacity storage space, the demand for miniaturization and high density of components is increasing, and how to realize higher storage density of devices is the focus of research of many researchers and chip development engineers. 2T0CDRAM is easier to realize higher storage density than 1T1CDRAM because it does not have a capacitor tube structure, and is therefore of great concern to manufacturers.

[0003] In the traditional process, the transistor of 2T0C is a vertical structure. In order to solve the short channel effect, the height of the channel needs to be designed higher, but the increase of the height will cause problems such as wafer bending, which will cause device failure and other situations, and also cause greater challenges to the lithography alignment process.

[0004] In addition, with the development of the semiconductor industry, the requirement for the storage density of DRAM is getting higher and higher. In addition to directly increasing the number of stacked layers of devices to improve the storage density, it is also necessary to continuously reduce the height of each layer. However, if the height of each layer is directly reduced without corresponding structural changes, it will inevitably cause short channel effect, resulting in increased leakage. SUMMARY

[0005] The embodiment of the present application provides a storage unit, which aims to solve the technical problem of how to control the channel height while solving the short channel effect in the structure of 2T0C DRAM.

[0006] The embodiment of the present application is implemented in the following manner. A storage unit comprises:

[0007] a write transistor, the write transistor comprising a first gate, a first gate dielectric surrounding the first gate, a first semiconductor channel surrounding the first gate dielectric, a first source / drain and a second source / drain; the first source / drain is arranged at a first end of the first gate and located outside the first semiconductor channel; the second source / drain is arranged at a second end of the first gate and located outside the first semiconductor channel;

[0008] a read transistor, the read transistor comprising a second gate, a second gate dielectric surrounding the second gate, a second semiconductor channel surrounding the second gate dielectric, a third source-drain and a fourth source-drain; the second source-drain and the second gate being conductively connected; the third source-drain being disposed at a first end of the second gate and outside the second semiconductor channel; the fourth source-drain being disposed at a second end of the second gate and outside the second semiconductor channel;

[0009] wherein a portion of the first semiconductor channel between the first source-drain and the second source-drain is a first effective semiconductor channel; a portion of the second semiconductor channel between the third source-drain and the fourth source-drain is a second effective semiconductor channel;

[0010] a channel outer ring size of a portion of the first effective semiconductor channel close to the first source-drain is different from a channel outer ring size of a portion of the first effective semiconductor channel close to the second source-drain; a channel outer ring size of a portion of the second effective semiconductor channel close to the third source-drain is different from a channel outer ring size of a portion of the second effective semiconductor channel close to the fourth source-drain.

[0011] Embodiments of the present application also provide a memory device, comprising:

[0012] a semiconductor substrate; and

[0013] at least one memory cell according to any one of the above on the semiconductor substrate.

[0014] Embodiments of the present application also provide a method for manufacturing a memory device, the method comprising the following steps:

[0015] providing a semiconductor substrate, depositing a first insulating layer and a first conductive material layer on the semiconductor substrate in sequence, etching the first conductive material layer to form a first signal line;

[0016] depositing a first dielectric layer and a second conductive material layer on the layer where the first signal line is located in sequence, etching the second conductive material layer to form a second signal line;

[0017] depositing a second insulating layer and a first hard mask layer on the layer where the second signal line is located in sequence, etching the first hard mask layer, the second insulating layer, the second signal line and the first dielectric layer to form a second via extending to the upper surface of the first signal line in a vertical direction, a pore diameter of a portion of the second via located on the upper surface of the first dielectric layer being different from a pore diameter of a portion of the second via located on the lower surface of the first dielectric layer;

[0018] removing the first hard mask layer, a read transistor is formed in the second via;

[0019] a third conductive material layer is deposited on the second insulating layer, and the third conductive material layer is etched to form a contact bump, a lower surface of the contact bump is in conductive connection with the second gate, and the contact bump is insulated from the second semiconductor channel;

[0020] a second dielectric layer and a fourth conductive material layer are sequentially deposited on a layer where the contact bump is located, and the fourth conductive material layer is etched to form a third signal line, the third signal line being a bit line of a write transistor;

[0021] a second hard mask layer and a third insulating layer are sequentially deposited on a layer where the third signal line is located, and the second hard mask layer, the third insulating layer, the third signal line and the second dielectric layer are etched to form a first via extending to an upper surface of the contact bump in a vertical direction, a hole diameter of a portion of the first via located on an upper surface of the second dielectric layer is different from a hole diameter of a portion of the first via located on a lower surface of the second dielectric layer;

[0022] the second hard mask layer is removed, and a write transistor is formed in the first via;

[0023] a fifth conductive material layer is deposited on the third insulating layer, and the fifth conductive material layer is etched to form a fourth signal line in contact connection with the first gate, the fourth signal line being a word line of the write transistor.

[0024] In the storage unit of the embodiment of the present application, the outer ring sizes of the two ends of the first effective semiconductor channel and the second effective semiconductor channel are different, so that the outer ring walls of the first effective semiconductor channel and the second effective semiconductor channel are not in a completely vertical state with the horizontal plane as the outer ring walls of the current vertical channel, but present an arc shape in the vertical direction in the forming process. The height of the first effective semiconductor channel and the second effective semiconductor channel can be controlled while the overall length of the first effective semiconductor channel and the second effective semiconductor channel is ensured, so as to control the overall height of the write transistor and the read transistor, thereby improving the storage density of the storage unit and avoiding the short channel effect caused by directly shortening the channel length, effectively controlling the leakage, and ensuring the performance of the storage unit. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 FIG. 1 is a structural schematic diagram of a storage unit according to an embodiment of the present application;

[0026] Figure 2 FIG. 2 is a structural schematic diagram of a storage unit according to another embodiment of the present application;

[0027] Figure 3A structural schematic diagram of a storage unit provided by another embodiment of the present application;

[0028] Figures 4 to 19 A process flow chart of a manufacturing method of a memory device provided by an embodiment of the present application;

[0029] Figure 20 A flow schematic diagram of a manufacturing method of a memory device of an embodiment of the present application.

[0030] Main figure mark explanation:

[0031] Storage unit-100; Write transistor-110; First gate-111; First gate dielectric-112; First semiconductor channel-113; First active semiconductor channel-1131; First source-drain-114; Second source-drain-115; Read transistor-120; Second gate-121; Second gate dielectric-122; Ring-shaped insulating layer-1221; Second semiconductor channel-123; Second active semiconductor channel-1231; Third source-drain-124; Fourth source-drain-125; Contact plug-130; First signal line-140; Second signal line-150; Third signal line-160; Fourth signal line-170; First insulating layer-101; First conductive material layer-102; First dielectric layer-103; Second conductive material layer-104; Second insulating layer-105; First hard mask layer-106; Second via-107; Third conductive material layer-108; Second dielectric layer-109; Fourth conductive material layer-10a; Third insulating layer-10b; Second hard mask layer-10c; First via-10d; Fifth conductive material layer-10e; Semiconductor substrate-200; Memory device-1000. DETAILED DESCRIPTION

[0032] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. The examples of the embodiments are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application. In addition, it should be understood that the specific embodiments described herein are only used to explain the present application and cannot be used to limit the present application.

[0033] In the description of the present application, it should be understood that the orientation or position relationship indicated in the description of the direction and position relationship is based on the orientation or position relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0034] Furthermore, the terms "first", "second", etc. are used herein only to describe different instances, and do not imply or suggest relative importance or a number of the technical features indicated. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically limited.

[0035] The following disclosure provides many different embodiments, or examples, for implementing different structures of the present application. For the purpose of simplification, the components and arrangements of specific examples are described in the following. Of course, they are merely examples, and the purpose is not to limit the present application. In addition, the present application can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art can realize the application of other processes and / or the use of other materials.

[0036] In the prior art 2T0C DRAM, the channel regions of the read transistor and the write transistor in the memory cell are generally vertically arranged, and in order to avoid the leakage problem caused by the short channel effect, the channel region needs to be arranged higher (i.e. longer), but the increase in height will cause problems such as wafer bending.

[0037] As the requirement for the storage density of DRAM is getting higher and higher, in addition to directly increasing the number of device stacks to improve the storage density, it is also necessary to continuously reduce the height of each layer, so it is necessary to control the height of the channel region, but due to the influence of the short channel effect, the channel region cannot be directly shortened to meet the requirements, resulting in that the storage density of the current 2T0C DRAM is difficult to effectively improve.

[0038] To solve the above problems, please refer to Figures 1 to 3 The embodiment of the present application provides a memory cell 100, which comprises a write transistor 110 and a read transistor 120.

[0039] The write transistor 110 comprises a first gate 111, a first gate dielectric 112 surrounding the first gate 111, a first semiconductor channel 113 surrounding the first gate dielectric 112, a first source-drain electrode 114 and a second source-drain electrode 115; the first source-drain electrode 114 is arranged at a first end of the first gate 111 and located outside the first semiconductor channel 113; the second source-drain electrode 115 is arranged at a second end of the first gate 111 and located outside the first semiconductor channel 113.

[0040] The read transistor 120 comprises a second gate 121, a second gate dielectric 122 surrounding the second gate 121, a second semiconductor channel 123 surrounding the second gate dielectric 122, a third source-drain electrode 124 and a fourth source-drain electrode 125; the second source-drain electrode 115 and the second gate 121 are conductively connected; the third source-drain electrode 124 is arranged at a first end of the second gate 121 and located outside the second semiconductor channel 123; and the fourth source-drain electrode 125 is arranged at a second end of the second gate 121 and located outside the second semiconductor channel 123.

[0041] The part of the first semiconductor channel 113 between the first source-drain electrode 114 and the second source-drain electrode 115 is a first effective semiconductor channel 1131, and the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the first source-drain electrode 114 is different from the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the second source-drain electrode 115.

[0042] The part of the second semiconductor channel 123 between the third source-drain electrode 124 and the fourth source-drain electrode 125 is a second effective semiconductor channel 1231, and the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the third source-drain electrode 124 is different from the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the fourth source-drain electrode 125.

[0043] In the storage unit 100, the outer ring sizes of the two ends of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are different, so that the outer ring walls of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are not in a vertical state as the outer ring walls of the current vertical channel, but are in an arc shape in the forming process. The height of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 can be controlled while the overall length of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 is ensured, so as to control the overall height of the write transistor 110 and the read transistor 120, thereby improving the storage density of the storage unit 100 and avoiding the short channel effect caused by directly shortening the channel length, effectively controlling the leakage current and ensuring the performance of the storage unit 100.

[0044] The embodiment of the storage unit 100 mainly describes the structural features of the write transistor 110 and the read transistor 120, and the specific forming process and materials of the structures such as the write transistor 110, the read transistor 120, the signal lines below and the contact block 130 below are only briefly described in the embodiment of the storage unit 100, and will be described in detail in the following embodiment of the manufacturing method of the memory device 1000.

[0045] Specifically, the storage unit 100 is formed on a semiconductor substrate, and specifically, the read transistor 120 and the write transistor 110 are sequentially formed on the semiconductor substrate 200, that is, the write transistor 110 is located above the read transistor 120, the first semiconductor channel 113 is located above the second semiconductor channel 123, and the central axis of the first semiconductor channel 113 coincides with the central axis of the second semiconductor channel 123.

[0046] Since the first semiconductor channel 113 and the second semiconductor channel 123 are the basic structures of the write transistor 110 and the read transistor 120, the first gate 111, the first gate dielectric 112, the first source / drain 114, and the second source / drain 115 are formed based on the formation of the first semiconductor channel 113, and the second gate 121, the second gate dielectric 122, the third source / drain 124, and the fourth source / drain 125 are formed based on the formation of the second semiconductor channel 123. The coincidence of the central axes of the two channels can accurately correspond the write transistor 110 and the read transistor 120, thereby making the structure of the storage unit 100 more regular, controlling the height and volume of the storage unit 100, facilitating miniaturization, and improving the storage density.

[0047] Taking the formation of the write transistor 110 as an example, the first semiconductor channel 113, the first gate dielectric 112, and the first gate 111 can all be formed by a deposition process. For example, a channel through hole can be etched on a semiconductor stack structure (including a semiconductor substrate, a conductive material layer, a dielectric layer, and an insulating layer, etc.) first, and the channel through hole is continuously etched to meet the above-mentioned condition of "different outer ring size of the channel" when forming the first semiconductor channel 113. A certain thickness of semiconductor material is deposited on the bottom surface and the peripheral wall of the above-mentioned channel through hole to form the first semiconductor channel 113. Then, a certain thickness of gate dielectric material is deposited on the surface of the first semiconductor channel 113 to form the first gate dielectric 112. Then, the gate material is deposited in the space surrounded by the first gate dielectric 112 to form the first gate 111 to form the write transistor 110.

[0048] The deposition process can be chemical vapor deposition (CVD), atomic layer deposition (ALD), molecular layer deposition (MLD), or physical layer deposition (PVD), etc.

[0049] The formation process of the read transistor 120 can refer to the formation process of the write transistor 110 described above, which will not be repeated here.

[0050] Please continue to refer to Figures 1 to 3Further, a projection of the first semiconductor channel 113 on a plane perpendicular to the axis thereof is conformal with a projection of the second semiconductor channel 123 on a plane perpendicular to the axis thereof.

[0051] Conformal can be understood as coinciding.

[0052] Exemplarily, the central axis of the first semiconductor channel 113 and the central axis of the second semiconductor channel 123 are both perpendicular to the plane where the semiconductor substrate is located in the vertical direction, that is, perpendicular to the horizontal plane, so that the projection of the first semiconductor channel 113 and the projection of the second semiconductor channel 123 on the plane where the semiconductor substrate is located are conformal, that is, the projection of the first semiconductor channel 113 and the projection of the second semiconductor channel 123 on the plane where the semiconductor substrate is located coincide, so that the write transistor 110 and the read transistor 120 can further accurately correspond, and further, the structure of the storage unit 100 is more regular, the height and volume of the storage unit 100 can be further controlled, and the storage density of the memory device 1000 is further improved.

[0053] In the embodiment of the application, the shape (external contour) of the first semiconductor channel 113 and the shape of the second semiconductor channel 123 can be approximately a cuboid, a cylinder, a pyramid or other regular or irregular columnar shape, etc.

[0054] Since the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 are not completely parallel to the respective central axes, but are inclined or arc-shaped relative to the central axes, or in other words, the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 are not completely perpendicular to the plane where the semiconductor substrate 200 is located, there is a certain inclination or arc in the vertical direction, so that while controlling the overall height of the write transistor 110 and the read transistor 120 to improve the storage density, the channel length of the write transistor 110 and the read transistor 120 is extended, avoiding the short channel effect.

[0055] The shape of the first semiconductor channel 113 and the shape of the second semiconductor channel 123 can be the same or different. Preferably, in the embodiment of the application, the shape of the first semiconductor channel 113 and the shape of the second semiconductor channel 123 are the same, so that the shape of the storage unit 100 is more regular, and the manufacturing process of the storage unit 100 is also simplified.

[0056] In Figures 1 to 3 In the embodiment shown, the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 can be considered as a slanted wall slanted outward (i.e. outward of the storage unit 100) in the vertical direction or an arc-shaped wall extending outward in an arc shape.

[0057] For example, the first semiconductor channel 113 and the second semiconductor channel 123 can be approximately prismatic structures, in which case the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 can include multiple side walls that are inclined in different directions, and the write transistor 110 and the read transistor 120 are approximately prismatic.

[0058] In one possible embodiment, based on the structural feature that the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 are outwardly inclined or arc-shaped walls, the first semiconductor channel 113 and the second semiconductor channel 123 can also be approximately conical or inverted-tai-shaped structures, in which case the channel walls of the first semiconductor channel 113 and the channel walls of the second semiconductor channel 123 are curved and outwardly inclined, and the write transistor 110 and the read transistor 120 are also approximately conical or inverted-tai-shaped structures.

[0059] For example, the channel walls of the first semiconductor channel 113 are outwardly inclined, in which case, in the embodiment of the present application, the channel walls of the first semiconductor channel 113 can be formed by inclined etching. For example, a regular channel through hole can be first formed on the semiconductor stack structure, which can be a rectangular hole, a cylindrical hole, or other columnar hole, and then the inner wall of the channel through hole is etched from the bottom of the channel through hole (i.e., the end close to the read transistor 120).

[0060] After etching part of the inner wall of the channel through hole, the inner wall of the channel through hole is etched upwards along the axial direction of the channel through hole and to the outside of the channel through hole, so that the inner wall of the channel through hole is offset outward by a certain distance layer by layer. In this way, the channel through hole with an outwardly inclined inner wall is formed by gradually etching the inner wall of the channel through hole upwards and outward, and the area of the lower port of the channel through hole is smaller than the area of the upper port. Then, a certain thickness of semiconductor material is deposited on the inner wall of the channel through hole, so as to form the first semiconductor channel 113 with the channel walls that are outwardly inclined. The outwardly inclined channel walls of the first semiconductor channel 113 can also be understood as the semiconductor layer of the first semiconductor channel 113 being outwardly inclined.

[0061] The formation process of the second semiconductor channel 123 can refer to the formation process of the first semiconductor channel 113 described above, which will not be repeated here.

[0062] It should be noted that the "skew" mentioned in the embodiments of the present application is not that the entire wall is regularly skewed to be a skew wall, but the outer profile of the wall is approximately skewed, that is, it presents a shape of outward skew or outward protrusion relative to the central axis of the first semiconductor channel 113 / second semiconductor channel 123. It can also be understood that the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 are not walls perpendicular to the horizontal plane, but are outwardly inclined or outwardly protruding walls.

[0063] For ease of description, as shown in Figure 2 Since the channel wall of the first semiconductor channel 113 and the channel wall of the second semiconductor channel 123 are approximately arc-shaped from a macroscopic perspective, in the following, the channel wall of the first semiconductor channel 113 is arc-shaped in the central axis direction (i.e. vertical direction) of the first semiconductor channel 113, and the channel wall of the second semiconductor channel 123 is arc-shaped in the central axis direction of the second semiconductor channel 123, that is, the "arc-shaped" mentioned in the following should be understood as arc-shaped in the central axis direction of the first semiconductor channel 113 and the second semiconductor channel 123.

[0064] Since the first semiconductor channel 113 is the basic structure of the write transistor 110, the first gate dielectric 112 is formed on the channel wall of the first semiconductor channel 113, which is a layered structure, and the first gate 111 is formed in the first gate dielectric 112, which can be columnar. The first semiconductor channel 113 surrounds the first gate dielectric 112, and the first gate dielectric 112 surrounds the first gate 111 to achieve insulation between the first gate 111 and the first semiconductor channel 113, so the shape of the first gate dielectric 112 and the first gate 111 is adapted to the shape of the first semiconductor, that is, the outer profile of the first gate dielectric 112 and the first gate 111 is also arc-shaped.

[0065] Since the shape of the second semiconductor channel 123, the second gate dielectric 122 and the second gate 121 can be referred to the related description of the first semiconductor channel 113 above, detailed description is not given here.

[0066] It can be understood that in order to connect a plurality of storage units 100 to further form a storage device 1000 and achieve signal connection between the storage device 1000 and an external control unit, signal lines for connecting a plurality of storage units 100 and an external control unit also need to be designed, such as commonly known write word lines, write bit lines, read word lines and read bit lines.

[0067] In the embodiments of the present application, the part of the first semiconductor channel 113 and the second semiconductor channel 123 that contacts the corresponding signal line or the connection structure between the write transistor 110 and the read transistor 120 (i.e. the contact guide block 130 in the following) is the source-drain of the write transistor 110 and the source-drain of the read transistor 120.

[0068] As the part of the write bit line and the contact guide block 130 contacting the first semiconductor channel 113 is the first source-drain 114 and the second source-drain 115 respectively, the first source-drain 114 can be the drain or source of the write transistor 110, and the second source-drain 115 can be the source or drain of the write transistor 110.

[0069] As the part of the read bit line and the contact guide block 130 contacting the second semiconductor channel 123 is the third source-drain 124 and the fourth source-drain 125 respectively, the third source-drain 124 can be the source or drain of the read transistor 120, and the fourth source-drain 125 can be the drain or source of the read transistor 120.

[0070] Since the corresponding signal line and the contact guide block 130 are both in contact with the outside of the write transistor 110 and the outside of the read transistor 120, the first source-drain 114 and the second source-drain 115 are located on the outside of the first semiconductor channel 113, i.e., on the outermost part of the first semiconductor channel 113, and the third source-drain 124 and the fourth source-drain 125 are located on the outside of the second semiconductor channel 123, i.e., on the outermost part of the first semiconductor channel 113.

[0071] Please refer to Figures 1 to 3 Furthermore, the first source-drain 114 is arranged around the first end of the first gate 111, and the third source-drain 124 is arranged around the first end of the second gate 121.

[0072] The first end and the second end of the first gate 111 can be understood as the top end and the bottom end of the first gate 111, and the first source-drain 114 is arranged around the first end of the first gate 111, i.e., it can be understood as a structure arranged around the top end part of the first gate 111. Since the top end of the first gate 111 will design a signal line connected to the write transistor 110, the first semiconductor channel 113 and the first gate 111 will pass through the signal line, and thus the first source-drain 114 formed by the signal line contacting the first semiconductor channel 113 is arranged around the first gate 111.

[0073] The first end and the second end of the second gate 121 can be understood as the top end and the bottom end of the second gate 121, and the third source-drain 124 is arranged around the first end of the second gate 121, i.e., it can be understood as a structure arranged around the top end part of the second gate 121. Since the top end of the second gate 121 will design a signal line connected to the read transistor 120, the second semiconductor channel 123 and the second gate 121 will pass through the signal line, and thus the third source-drain 124 formed by the signal line contacting the second semiconductor channel 123 is arranged around the second gate 121.

[0074] Of course, the first end and the second end of the first gate 111 can also be the bottom end and the top end, and the first end and the second end of the second gate 121 can also be the bottom end and the top end, and are not limited to the above description.

[0075] In the embodiment of the present application, the first effective semiconductor channel 1131 is the part of the first semiconductor channel 113 of the write transistor 110 between the first source-drain electrode 114 and the second source-drain electrode 115, which can also be understood as the part of the first semiconductor channel 113 between the write word line and the above-mentioned connection structure, and this part is the part of the first source-drain electrode 114 and the second source-drain electrode 115 transmitting electrical signals to the first gate 111, and the other part of the first semiconductor channel 113 is the part between the two signal lines connected with the write transistor 110.

[0076] The second effective semiconductor channel 1231 is the part of the second semiconductor channel 123 of the read transistor 120 between the third source-drain electrode 124 and the fourth source-drain electrode 125, which can also be understood as the part of the second semiconductor channel 123 between the two signal lines connected with the read transistor 120, and this part is the part of the third source-drain electrode 124 and the fourth source-drain electrode 125 transmitting electrical signals to the second gate 121, and the other part of the second semiconductor channel 123 is the part between the signal lines and the above-mentioned connection structure.

[0077] Since the first semiconductor channel 113 and the second semiconductor channel 123 are formed by depositing a certain thickness of semiconductor material on the inner wall of the channel via hole, both have a certain thickness. Therefore, in the embodiment of the present application, the channel outer ring size of the first effective semiconductor channel 1131 and the channel outer ring size of the second effective semiconductor channel 1231 can be understood as the outermost ring size of the first effective semiconductor channel 1131 and the outermost ring size of the second effective semiconductor channel 1231, that is, the size of a circle of surface (ring) of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 in contact with the corresponding channel via hole, and the size of a circle of surface of the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 setting the first gate dielectric 112 and the second gate dielectric 122 can be understood as the channel inner ring size.

[0078] Similarly, the technical features such as outer ring / outer ring size in the following can also be understood as above.

[0079] In the embodiment of the present application, the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the first source-drain electrode 114 is different from the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the second source-drain electrode 115, which can be understood as:

[0080] The channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the first source-drain electrode 114 is greater than the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the second source-drain electrode 115; or, the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the first source-drain electrode 114 is smaller than the channel outer ring size of the portion of the first effective semiconductor channel 1131 close to the second source-drain electrode 115.

[0081] In this way, in the process of forming the first effective semiconductor channel 1131, the channel wall of the first effective semiconductor channel 1131 is not perpendicular to the semiconductor substrate 200, that is, not parallel to the central axis of the first semiconductor channel 113, compared with the existing channel wall perpendicular to the semiconductor substrate 200, the purpose of extending the channel length of the first effective semiconductor channel 1131 while controlling the overall height of the write transistor 110 can be achieved.

[0082] In the embodiment of the present application, the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source-drain electrode 124 is different from the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source-drain electrode 125, which can be understood as:

[0083] The channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source-drain electrode 124 is greater than the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source-drain electrode 125; or, the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the third source-drain electrode 124 is smaller than the channel outer ring size of the portion of the second effective semiconductor channel 1231 close to the fourth source-drain electrode 125.

[0084] In this way, in the process of forming the second effective semiconductor channel 1231, the channel wall of the second effective semiconductor channel 1231 is not perpendicular to the semiconductor substrate 200, that is, not parallel to the central axis of the second semiconductor channel 123, compared with the existing channel wall perpendicular to the semiconductor substrate 200, the purpose of extending the channel length of the second effective semiconductor channel 1231 while controlling the overall height of the write transistor 110 can be achieved.

[0085] Please refer to Figures 1 to 3 Furthermore, the outer ring size of the first effective semiconductor channel 1131 is tapered or gradually expanded, and the outer ring size of the second effective semiconductor channel 1231 is tapered or gradually expanded.

[0086] Taking the central axis of the first effective semiconductor channel 1131 and the central axis of the second effective semiconductor channel 1231 as reference and direction, the central axes of the two coincide and are in the vertical direction, for example:

[0087] The outer ring size of the first effective semiconductor channel 1131 gradually decreases from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually decreases from top to bottom in the vertical direction.

[0088] The outer ring size of the first effective semiconductor channel 1131 gradually increases from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually decreases from top to bottom in the vertical direction.

[0089] The outer ring size of the first effective semiconductor channel 1131 gradually decreases from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually increases from top to bottom in the vertical direction.

[0090] The outer ring size of the first effective semiconductor channel 1131 gradually increases from top to bottom in the vertical direction, and the outer ring size of the second effective semiconductor channel 1231 gradually increases from top to bottom in the vertical direction.

[0091] In the embodiment of the present application, the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 have the same change trend, that is, both gradually decrease or gradually increase in the same direction, so that the structure of the memory cell 100 is more regular.

[0092] In a preferred embodiment of the present application, the outer ring size of the first effective semiconductor channel 1131 and the outer ring size of the second effective semiconductor channel 1231 gradually decrease from top to bottom in the vertical direction, or are understood to gradually increase from bottom to top in the vertical direction.

[0093] From the perspective of etching, etching the channel through hole corresponding to the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 to gradually increase from bottom to top in the vertical direction is easier to achieve, that is, making the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 gradually increase from bottom to top is easier to achieve, which can control the manufacturing difficulty of the memory cell 100.

[0094] Please refer to Figure 1 and Figure 3 Furthermore, in the embodiment of the present application, the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 are both stepped and gradually expanded from bottom to top, such as inverted tower shape.

[0095] The first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 can be approximately in a quadrangular prism shape, that is, the channel walls of both are composed of four side walls, the four side walls are connected to form the above-mentioned channel walls, each side wall can be smoothly connected by multiple planes (which can be vertical planes or inclined planes) distributed in the Z-axis direction, each plane can extend in the Y-axis and Z-axis directions or in the X-axis and Z-axis directions, and adjacent two planes on the same side wall are staggered in the Y-axis or X-axis direction, that is, the normal projection of the adjacent two planes in the Z-axis direction is staggered to form a stepped surface, that is, the four side walls are all stepped side walls, thereby making the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 approximately in an inverted tower shape.

[0096] When etching the channel through hole for forming the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231, the bottommost layer of planes can be etched on the inner circumferential wall of the channel through hole at first, at this time, the four planes are connected together, approximately in a rectangular body space, and then the second layer of planes is continuously etched to form a rectangular body space with a larger area, until the top of the channel through hole is etched to realize complete etching, and then the semiconductor material is deposited in the channel through hole to form the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 in an inverted tower shape.

[0097] The forming process of the channel wall of the first effective semiconductor channel 1131 and the channel wall of the second effective semiconductor channel 1231 in an arc shape can refer to the above-mentioned forming process, which will not be described here.

[0098] However, compared with this, etching the two channel through holes into a structure gradually expanded in a stepped shape from bottom to top to form the first effective semiconductor channel 1131 and the second effective semiconductor channel 1231 into a structure gradually expanded in a stepped shape from bottom to top is easier to control the etching amplitude and has lower process difficulty.

[0099] Please refer to Figures 1 to 3 Furthermore, a contact guide block 130 is arranged between the write transistor 110 and the read transistor 120, the second source-drain electrode 115 and the second gate 121 are conductively connected through the contact guide block 130, the central axis of the contact guide block 130 coincides with the central axes of the first semiconductor channel 113 and the second semiconductor channel 123. The upper surface of the contact guide block 130 is in contact with the first semiconductor channel 113, the lower surface of the contact guide block 130 is in contact with the second gate 121, and the contact guide block 130 is insulated from the second semiconductor channel 123.

[0100] Specifically, the contact block 130 can be a square block, a rectangular block, or a circular block, etc. In the embodiment, the contact block 130 is a square block structure, which can be made of a conductive material, such as a conductive metal (conductor) material or a semiconductor material, etc. for conductive connection between the second source-drain 115 and the second gate 121 to realize the conductive connection between the write transistor 110 and the read transistor 120.

[0101] The central axis of the contact block 130 coincides with the central axes of the first semiconductor channel 113 and the second semiconductor channel 123, that is, the second semiconductor channel 123, the contact block 130, and the first semiconductor channel 113 accurately correspond to the central axes, so that the structure of the memory cell 100 is more regular, which is conducive to promoting the miniaturization of the memory cell 100 and improving the storage density.

[0102] In the embodiment, the part of the contact block 130 in contact with the first semiconductor channel 113 forms the second source-drain 115 of the write transistor 110, that is, it can be understood that the part structure of the upper surface of the contact block 130 in contact with the first semiconductor channel 113 constitutes the second source-drain 115. The second source-drain 115 is a part of the contact block 130, and the contact block 130 and the second source-drain 115 are integrally formed, and their materials are the same. The second source-drain 115 can be directly conductively connected with the second gate 121 located in the contact block 130 through the contact block 130.

[0103] For example, the second source-drain 115 can be the drain of the write transistor 110, which is conductively connected with the contact block 130 at the bottom of the first semiconductor channel 113, and then conductively connected with the read transistor 120 through the contact block 130. The first source-drain 114 can be the source of the write transistor 110, which is conductively connected with the signal line at the outside of the first semiconductor channel 113 to realize the signal access of the write transistor 110.

[0104] The contact block 130 is insulated from the second semiconductor channel 123, for example, the contact block 130 can be insulated from the second semiconductor channel 123 through the second gate medium 122 layer, or an insulation layer is arranged between the contact block 130 and the second semiconductor channel 123 to insulate them. In this way, the short circuit problem caused by the conductive connection of the contact block 130 with the second gate 121 and the second semiconductor channel 123 at the same time can be avoided.

[0105] Please refer to Figures 1 to 3 Furthermore, in the embodiment, the size of the lower surface of the contact block 130 is greater than the size of the outer ring of the second gate medium 122, and the size of the upper surface of the contact block 130 is greater than or equal to the size of the contact surface of the first semiconductor channel 113.

[0106] Specifically, the size of the lower surface of the contact block 130 is greater than the size of the outer ring of the second gate dielectric 122, which can avoid the situation that the size of the lower surface of the contact block 130 is less than the size of the outer ring of the second gate dielectric 122, and the contact block 130 does not completely contact the second gate 121 surrounded by the second gate dielectric 122, thereby affecting the conduction. Moreover, the contact block 130 in the embodiment can be designed as a block-shaped cuboid or a square, i.e., the lower surface of the contact block 130 is a rectangle or a square, such as a square, and the cross section of the second gate dielectric 122 is annular. In order to enable the contact block 130 to completely cover the second gate dielectric 122, the size of the lower surface of the contact block 130 can also be designed to be greater than the size of the outer ring of the second gate dielectric 122.

[0107] In addition, in order to ensure that the contact block 130 is in full contact with the first semiconductor channel 113, and to ensure the formation of the second source-drain 115, such as to ensure that the size of the formed second source-drain 115 is large enough to ensure the conduction connection effect, the size of the upper surface of the contact block 130 in the embodiment is greater than or equal to the size of the contact surface of the first semiconductor channel 113. Since the second end of the first semiconductor channel 113 is in contact with the contact block 130, it can also be understood that the size of the upper surface of the contact block 130 is greater than or equal to the size of the second end of the first semiconductor channel 113.

[0108] In the embodiment of the application, the contact surface of the first semiconductor channel 113 and the contact block 130 is the surface of the second end of the first semiconductor channel 113, i.e., the bottom end surface of the first semiconductor channel 113. The surface is a circular surface. Preferably, the size of the upper surface of the contact block 130 can be slightly greater than the size of the first semiconductor channel 113. For example, the upper surface of the contact block 130 can be designed as a square, and the shape of the bottom end surface of the first semiconductor channel 113 can be an inscribed circle of the square surface, so as to avoid the situation that the manufacturing process error causes the contact block 130 to fail to completely cover the bottom end surface of the first semiconductor channel 113.

[0109] Please refer to Figures 1 to 3 Furthermore, the upper surface of the second gate 121 and the upper surface of the second gate dielectric 122 are flush, and the upper surface of the second semiconductor channel 123 is lower than the upper surface of the second gate 121 and the upper surface of the second gate dielectric 122.

[0110] An annular insulating layer 1221 is arranged between the lower surface of the contact block 130 and the upper surface of the second semiconductor channel 123. The inner ring size of the annular insulating layer 1221 is equal to the outer ring size of the second gate dielectric 122, and the outer ring size of the annular insulating layer 1221 is equal to the outer ring size of the second semiconductor channel 123.

[0111] In the embodiment of the present application, the upper surface of the second gate 121 and the upper surface of the second gate dielectric 122 are both in contact with, or covered by, the lower surface of the contact plug 130, and the upper surface of the second gate 121 is flush with the upper surface of the second gate dielectric 122 to ensure that the surface of the first end of the read transistor 120 (i.e. the first end of the second gate 121) is flat and regular, and also to ensure that the contact surface between the contact plug 130 and the second gate 121 and the second gate dielectric 122 is flat and regular, facilitating the contact connection of the contact plug 130.

[0112] The upper surface of the second semiconductor channel 123 is lower than the upper surface of the second gate dielectric 122, so that the space between the upper surface of the second semiconductor channel 123 and the upper surface of the second gate dielectric 122 can be used to form a structure for insulating and spacing the contact plug 130 from the second semiconductor channel 123, such as the annular insulating layer 1221 described above.

[0113] The annular insulating layer 1221 is made of insulating material and has an annular structure, and can be formed by extending horizontally outward from the top of the second gate dielectric 122. The inner ring size of the annular insulating layer 1221 is equal to the outer ring size of the second gate dielectric 122, and the outer ring size is equal to the outer ring size of the second semiconductor channel 123, so as to space and block part of the structure of the second semiconductor channel 123 towards the contact plug 130, so as to effectively insulate the second semiconductor channel 123 from the contact plug 130, and the structure is regular and flat, which is conducive to the integration and miniaturization of the memory cell 100 and improves the storage density.

[0114] Further, in the embodiment of the present application, the annular insulating layer 1221 is integrally formed with the second gate dielectric 122 and has the same material as the second gate dielectric 122.

[0115] It can be understood that the annular insulating layer 1221 is part of the second gate dielectric 122, specifically part of the structure of the second gate dielectric 122 between the contact plug 130 and the second semiconductor channel 123, and has an annular structure and can be formed by extending horizontally outward from the top of the second gate dielectric 122. For example, during the deposition of the second gate dielectric 122 on the inner wall of the second semiconductor channel 123, after the second gate dielectric 122 is deposited to a certain height, the second gate dielectric 122 is extended outward from the top, and a certain thickness of insulating material is deposited on the top of the second semiconductor channel 123 to form the annular insulating layer 1221, which is located between the second semiconductor channel 123 and the contact plug 130.

[0116] In addition, an annular insulating layer is also provided between the lower surface of the fourth signal line 170 and the upper surface of the first semiconductor channel 113. The structure and formation method of this annular insulating layer are the same as those of the annular insulating layer 1221 on the lower surface of the contact block 130. That is, the inner ring size of this annular insulating layer is equal to the outer ring size of the first gate dielectric 112, and its outer ring size is equal to the outer ring size of the first semiconductor channel 113. Moreover, this annular insulating layer and the first gate dielectric 112 are integrally formed and are made of the same material.

[0117] For details regarding the annular insulating layer formed between the fourth signal line 170 and the first semiconductor channel 113, please refer to the above-mentioned content regarding the annular insulating layer 1221 on the second gate dielectric 122, which will not be described in detail here.

[0118] Please see Figures 1 to 3 as well as Figure 18 The storage device 1000 of the present invention includes a semiconductor substrate 200 and at least one storage cell 100 formed on the semiconductor substrate 200 according to any one of the above claims. When there are multiple storage cells 100, each storage cell 100 is electrically connected to the others through a signal line.

[0119] When manufacturing the memory device 1000, multiple memory cells 100 are simultaneously formed on the semiconductor substrate 200. They can be insulated from each other by insulating structures, such as forming a dielectric layer / insulating layer between adjacent memory cells 100, to avoid electrical conduction between adjacent memory cells 100 and causing problems that prevent normal operation.

[0120] The storage cells 100 can be adjacent in the X-axis direction and / or the Y-axis direction. In order to realize the transmission of signals between multiple storage cells 100, multiple storage cells 100 can be electrically connected in different directions by different signal lines distributed in the X-axis direction or the Y-axis direction.

[0121] Please continue reading. Figures 1 to 3 as well as Figures 18 to 19 Furthermore, in this embodiment of the invention, there are multiple storage units 100, which form a storage array structure on a horizontal plane. The overall structure of the storage array is regular and compact, and the volume of the storage units 100 can be controlled, thereby increasing the storage density of the storage device 1000.

[0122] Furthermore, the multiple storage cells 100 in the storage array structure are arranged in an array in a first direction and a second direction, with the first direction intersecting the second direction.

[0123] It can be understood that by arranging the plurality of storage units 100 in an array to form a storage array structure, the number of storage units 100 is increased in an array in the first direction (such as the Y / X axis direction) and the second direction (the X / Y axis direction), so that a storage device 1000 of any size in an array structure can be formed, such as a regular shape of a cube, a cuboid or a quadrangular prism, to meet different storage capacity requirements, and the structure of the storage device 1000 is regular and compact, and the volume of the storage device 1000 can be controlled to improve the storage density.

[0124] Further, in the embodiment of the present application, the first direction and the second direction intersect at 90°.

[0125] For example, if the first direction is the Y axis direction and the second direction is the X axis direction, the two directions intersect at 90°, and the plurality of storage units 100 are arranged in an array in the Y axis direction and the X axis direction, so that a cuboid or a cube storage array structure can be formed, and the structure of the obtained storage device 1000 is regular and compact, which further improves the storage density from the overall structure layout of the storage device 1000 on the basis of improving a single storage unit 100.

[0126] Please refer to Figure 19 Further, the storage device 1000 of the embodiment of the present application further comprises a first signal line 140, a second signal line 150, a third signal line 160 and a fourth signal line 170, the first signal line 140 and the second signal line 150 are signal lines electrically connected with the read transistor 120, the third signal line 160 and the fourth signal line 170 are signal lines electrically connected with the write transistor 110, the first signal line 140 and the third signal line 160 extend in the first direction, i.e. along the Y axis direction, and the second signal line 150 and the fourth signal line 170 extend in the second direction, i.e. along the X axis direction.

[0127] Since the storage unit 100 is a plurality, the number of the first signal line 140, the second signal line 150, the third signal line 160 and the fourth signal line 170 is a plurality, which matches the number of rows and columns in the storage array structure, specifically, the number of the first signal line 140 and the third signal line 160 matches the number of columns of the storage unit 100 in the storage array structure, and the number of the second signal line 150 and the fourth signal line 170 matches the number of rows. Among them, the number of the first signal line 140 and the number of the third signal line 160 are the same, and the number of the second signal line 150 and the number of the fourth signal line 170 are the same.

[0128] Exemplarily, if the number of columns of the memory cells 100 in the memory array structure is 10 columns, i.e. the memory cells 100 arranged along the first direction (Y-axis direction) in the memory array structure are 10 columns, the number of the first signal lines 140 and the third signal lines 160 is 10. If the number of rows of the memory cells 100 in the memory array structure is 10 rows, i.e. the memory cells 100 arranged along the second direction (X-axis direction) in the memory array structure are 10 rows, the number of the second signal lines 150 and the fourth signal lines 170 is 10.

[0129] The first signal lines 140 are arranged in the second direction (X-axis) and connected with the fourth source-drain electrodes 125, and the fourth source-drain electrodes 125 of the plurality of read transistors 120 arranged in the first direction (X-axis) are connected to the same first signal line 140, wherein the first signal line 140 can be a bit line or a word line of the read transistor 120.

[0130] The second signal lines 150 are arranged in the first direction (Y-axis) and connected with the third source-drain electrodes 124, and the third source-drain electrodes 124 of the plurality of read transistors 120 arranged in the second direction (Y-axis) are connected to the same second signal line 150, and the second signal line 150 is a word line or a bit line of the read transistor 120.

[0131] The third signal lines 160 are arranged in the second direction and connected with the first source-drain electrodes 114, and the first source-drain electrodes 114 of the plurality of write transistors 110 arranged in the first direction are connected to the same third signal line 160, wherein the third signal line 160 is a bit line of the write transistor 110. The fourth signal lines 170 are arranged in the first direction (Y-axis) and connected with the first gate electrodes 111, and the first gate electrodes 111 of the plurality of write transistors 110 arranged in the second direction are connected to the same fourth signal line 170, wherein the fourth signal line 170 is a word line of the write transistor 110.

[0132] The working principle of the memory device 1000 in the embodiment is as follows. In the operation of "writing", the write transistor 110 is controlled to be turned on by the fourth signal line 170, and the potential of the third signal line 160 is transmitted to the second gate electrode 121 of the read transistor 120, so that the potential of the second gate electrode 121 is synchronized with the third signal line 160 to realize the writing of "0" and "1". Then, the write transistor 110 is controlled to be turned off. In the operation of "reading", only the storage state needs to be judged according to the high and low of the current of the read transistor 120.

[0133] And the plurality of memory cells 100 array arrangement, the same fourth signal line 170 can control in the first direction arranged a plurality of write transistor 110 open, can be in the second direction interval arranged a plurality of third signal line 160 potential transmission to the respective corresponding read transistor 120 second gate 121, in order to achieve the batch writing of "0" and "1", improve the read-write efficiency of the memory device 1000.

[0134] Please refer to Figure 18 , combined with the position of each signal line and contact guide block 130, in the embodiment of the present application, the first effective semiconductor channel 1131 is the shape of the third signal line 160 from the contact guide block 130 direction ladder gradually shrink, the second effective semiconductor channel 1231 is the shape of the second signal line 150 from the first signal line 140 direction ladder gradually shrink.

[0135] More, the material of the fourth signal line 170 can be the same as the material of the first gate 111, the material of the third signal line 160 can be the same as the material of the first source drain 114, the material of the second signal line 150 can be the same as the material of the third source drain 124, the material of the first signal line 140 can be the same as the material of the fourth source drain 125, in order to realize the good coupling between the corresponding parts.

[0136] Further, in the embodiment of the present application, the first signal line 140 and the fourth source drain 125 are integrally formed and the material of the two is the same, which can be understood as the fourth source drain 125 is a part of the first signal line 140, which is the part structure of the first signal line 140 and the second semiconductor channel 123. The second signal line 150 and the third source drain 124 are integrally formed and the material of the two is the same, which can be understood as the third source drain 124 is a part of the second signal line 150, which is the part structure of the second signal line 150 and the second semiconductor channel 123. The third signal line 160 and the first source drain 114 are integrally formed and the material of the two is the same, which can be understood as the first source drain 114 is a part of the third signal line 160, which is the part structure of the third signal line 160 and the first semiconductor channel 113.

[0137] The material of the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide block 130 can be the same or different, for example, can be metal material or conductive material, such as TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt and other materials or any combination of the above materials.

[0138] In the embodiment of the present application, the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide block 130 are all made of TiN. The above description of the first signal line 140, the second signal line 150, the third signal line 160, the fourth signal line 170 and the contact guide block 130 is only exemplary and should not be construed as a limitation of the present application.

[0139] Referring to Figure 20 The preparation method of the memory device 1000 of the embodiment of the present application is used to manufacture the memory device 1000 in any of the above embodiments, and the preparation method comprises the following steps:

[0140] S10: providing a semiconductor substrate 200, depositing a first insulating layer 101 and a first conductive material layer 102 on the semiconductor substrate 200 in sequence, and etching the first conductive material layer 102 to form the first signal line 140. Wherein, the adjacent first signal lines 140 are filled with insulating material for insulating isolation.

[0141] Referring to Figures 4 to 5 Specifically, the material of the semiconductor substrate 200 can include various semiconductor materials, such as silicon (for example, monocrystalline silicon Si), silicon germanium (SiGe), silicon-on-insulator (SOI), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), germanium-on-insulator (GOI), silicon carbide (SIC), etc.

[0142] Alternatively, the semiconductor substrate 200 can be made of a non-conductive material such as glass, plastic, or sapphire wafer. Or, the semiconductor substrate 200 can also be an insulating dielectric material such as silicon dioxide (SiO2) and silicon nitride (SiN). Or, the semiconductor substrate 200 can also be other materials, such as III-V compound semiconductors such as gallium arsenide.

[0143] In yet another embodiment, the semiconductor substrate 200 can be made of semiconductor materials, insulating materials, conductor materials, or any combination of material types thereof.

[0144] In one embodiment, the semiconductor substrate 200 can be a single-layer structure, for example, a single-layer structure made of silicon, germanium, gallium arsenide, etc.

[0145] In another embodiment, the semiconductor substrate 200 can also be a multi-layer structure, for example, a layered substrate including a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, a silicon-on-insulator or a silicon germanium-on-insulator, etc.

[0146] In the embodiment of the present application, the semiconductor substrate 200 is a monocrystalline silicon substrate, and a thin film of silicon oxide is generated on the surface of the semiconductor substrate 200 to protect the semiconductor substrate 200.

[0147] In some embodiments, the first insulating layer 101 and the first conductive material layer 102 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular layer deposition (MLD), or the like.

[0148] It can be understood that any suitable material and deposition process can be used to form the first insulating layer 101 and the first conductive material layer 102.

[0149] Exemplarily, the material of the first insulating layer 101 can be SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3, or a combination, a stack, or a combination stack of the above materials, and can also be TEOS.

[0150] In an embodiment of the present application, the material of the first insulating layer 101 is SiN.

[0151] Exemplarily, the material of the first conductive material layer 102 can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, or any combination of the above materials.

[0152] In an embodiment of the present application, the material of the first conductive material layer 102 is TiN.

[0153] In an embodiment, the forming process of the first signal line 140 can be a dry etching, a wet etching, or a combination of dry etching and wet etching. The wet etching can use a chlorine or fluorine based etchant to etch the first conductive material layer 102.

[0154] In an embodiment of the present application, when forming the first signal line 140, a photoetching process can be used for patterning, and then etching to transfer the pattern to the first conductive material layer 102.

[0155] Exemplarily, a photoresist layer can be formed on the first conductive material layer 102, and then the photoresist layer is etched to form a photoresist pattern corresponding to the shape of the first signal line 140. The first conductive material layer 102 under the photoresist layer is etched based on the photoresist pattern to transfer the photoresist pattern to the first conductive material layer 102, i.e., to form a pattern corresponding to the photoresist pattern on the first conductive material layer 102. Finally, the photoresist pattern is removed, and the first conductive material layer 102 is etched to form the first signal line 140.

[0156] In one embodiment, to increase the storage density of the memory device 1000, the first signal line 140 can be formed using a SADP (Self-Aligned Double Patterning) process to obtain a first signal line 140 with a smaller line width.

[0157] In step S10, the first signal line 140 formed by etching extends in a first direction (Y-axis direction).

[0158] In addition, after the first insulating layer 101 and the first conductive material layer 102 are deposited respectively, an optional annealing process (e.g., rapid thermal annealing, oxidation densification, etc.) and / or an optional planarization process (e.g., chemical mechanical planarization) can be performed to harden and / or planarize the first layer of isolation, so that the subsequent deposition stack remains flat. This step can also be applied to the processing of each layer in the following steps.

[0159] In addition, after the first insulating layer 101 and the first conductive material layer 102 are formed, a mask layer, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the first conductive material layer 102, thereby facilitating subsequent etching of the first conductive material layer 102 based on the mask pattern in the patterned mask layer. This step can also be applied to the processing of each layer in the following steps.

[0160] In one embodiment, the mask layer can be a conductive or non-conductive material, and can be selected from materials including silicon nitride, silicon oxynitride, amorphous silicon, polysilicon, polysilicon germanium, metal nitride, metal silicide, metal oxide, and metal. The mask layer can be deposited by PVD, CVD, ALD, MLD sputtering deposition, or other techniques for depositing selected materials.

[0161] Once the mask layer is deposited, it can be patterned using, for example, a photomask and etching process. Once the mask layer is patterned, one or more suitable removal processes (e.g., ashing, selective etching, combination) can be used to remove the areas that need to be removed, while ensuring that the mask areas are not removed or damaged.

[0162] S20: A first dielectric layer 103 and a second conductive material layer 104 are sequentially deposited on the layer where the first signal line 140 is located, and the second conductive material layer 104 is etched to form a second signal line 150.

[0163] Please refer to Figure 6 With Figure 7 It can be understood that the layer where the first signal line 140 is located is the original first conductive material layer 102, and to achieve insulation and isolation from the second conductive material layer 104, a first dielectric layer 103 is first deposited on the original first conductive material layer 102.

[0164] The first dielectric layer 103 and the second conductive material layer 104 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular layer deposition (MLD), or the like.

[0165] It can be understood that any suitable material and deposition process can be used to form the first dielectric layer 103 and the second conductive material layer 104, which is not specifically limited herein.

[0166] For example, the material of the first dielectric layer 103 can be an insulating oxide such as SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3, or a combination, a stack, or a combination stack of the above materials, and can also be TEOS.

[0167] In an embodiment of the present application, the material of the first dielectric layer 103 is SiO2.

[0168] For example, the material of the second conductive material layer 104 can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, or any combination of the above materials. The material of the second conductive material layer 104 can be the same as or different from the material of the first conductive material layer 102.

[0169] In an embodiment of the present application, the material of the second conductive material layer 104 is the same as the material of the first conductive material layer 102, and both are TiN.

[0170] In an embodiment, the forming process of the second signal line 150 can be dry etching, wet etching, or a combination of dry etching and wet etching. The wet etching can use a chlorine or fluorine-based etchant to etch the second conductive material layer 104.

[0171] In an embodiment of the present application, when forming the second signal line 150, a photolithography process can be used for patterning, and then etching to transfer the pattern to the second conductive material layer 104.

[0172] For example, a photoresist layer can be formed on the second conductive material layer 104, and then the photoresist layer is etched to form a photoresist pattern corresponding to the shape of the second signal line 150. Based on the photoresist pattern, the second conductive material layer 104 under the photoresist layer is etched to transfer the photoresist pattern to the second conductive material layer 104, i.e., to form a pattern corresponding to the photoresist pattern on the second conductive material layer 104. Finally, the photoresist pattern is removed, and the second conductive material layer 104 is etched to form the second signal line 150.

[0173] In one embodiment, to increase the storage density of the memory device 1000, the second signal line 150 can be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a second signal line 150 with a smaller line width.

[0174] In step S20, the etched second signal line 150 extends in a second direction (X-axis direction).

[0175] S30: A second insulating layer 105 and a first hard mask layer 106 are sequentially deposited on the layer where the second signal line 150 is located, the first hard mask layer 106, the second insulating layer 105, the second signal line 150 and the first dielectric layer 103 are etched, a second via hole 107 extending in a vertical direction to the upper surface of the first signal line 140 is formed, and the aperture of the part of the second via hole 107 located on the upper surface of the first dielectric layer 103 is different from the aperture of the part of the second via hole 107 located on the lower surface of the first dielectric layer 103.

[0176] Please refer to Figure 8 and Figure 9 The layer where the second signal line 150 is located is the original second conductive material layer 104, and the second insulating layer 105 and the first hard mask layer 106 can be sequentially formed on the original second conductive material layer 104 by using deposition methods such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), PVD (Physical Vapor Deposition) and MLD (Molecular Layer Deposition).

[0177] For example, the material of the second insulating layer 105 can be SiON, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3 or a combination of the above materials, a stacked material, a combined stacked material, or TEOS.

[0178] The material of the second insulating layer 105 can be the same as or different from the material of the first insulating layer 101. In the embodiment of the present application, the material of the second insulating layer 105 is different from the material of the first insulating layer 101, and is SiN.

[0179] It is worth mentioning that the first hard mask layer 106 can be a single-layer structure or a superposition structure of multiple hard mask layers, and the multiple-layer structure can improve the etching selectivity of the hard mask layer.

[0180] In the embodiment of the present application, the first hard mask layer 106 is a superposition structure of multiple hard mask layers, specifically a superposition structure of two layers of SOC (Spin-on Carbon) and SiON, and the SOC layer is deposited on the second insulating layer 105.

[0181] It can be understood that any suitable material and deposition process can be used to form the second insulating layer 105 and the first hard mask layer 106, which are not specifically limited herein.

[0182] In one embodiment, the forming process of the second via hole 107 can be dry etching, wet etching, or a combination of dry etching and wet etching. The wet etching can use a chlorine or fluorine-based etchant.

[0183] Exemplarily, the second via hole 107 can be a rectangular hole, a cylindrical hole, or other columnar hole. The hole diameter of the portion of the second via hole 107 on the upper surface of the first dielectric layer 103 (referred to as the upper hole diameter of the second via hole 107) and the hole diameter of the portion of the second via hole 107 on the lower surface of the first dielectric layer 103 (referred to as the lower hole diameter of the second via hole 107) can be different. For example, the upper hole diameter of the second via hole 107 can be greater than or less than the lower hole diameter of the second via hole 107.

[0184] For example, when the upper hole diameter of the second via hole 107 is greater than the lower hole diameter, the etching of the second via hole 107 starts from the bottom end of the second via hole 107 (i.e., one end of the upper surface of the first signal line 140). After etching part of the inner wall of the second via hole 107, the inner wall of the second via hole 107 is continuously etched upwards and to the outside of the second via hole 107 along the central axis of the second via hole 107, so that the inner wall of the second via hole 107 is offset outward by a certain distance layer by layer, until the upper hole diameter of the second via hole 107 is greater than the lower hole diameter.

[0185] Further, in the embodiment of the present application, the plasma gas for etching the second insulating layer 105 is a mixed gas of CH3F, CH2F2, O2, and Ar, the plasma source power is 500-1000 W, and the bias voltage is 200-500 V. The plasma gas for etching the first dielectric layer 103 is a mixed gas of C4F8 and O2, the plasma source power is 800-1500 W, and the bias voltage is 250-500 V.

[0186] S40: removing the first hard mask layer 106 to form the read transistor 120 in the second via hole 107.

[0187] The first hard mask layer 106 can be removed by wet etching, dry etching, or a combination of wet etching and dry etching, which is not specifically described herein.

[0188] Please refer to Figure 10 After removing the first mask layer, the specific way of forming the read transistor 120 in the second via hole 107 can be sequentially depositing the second semiconductor channel 123, the second gate dielectric 122, and the second gate 121 in the second via hole 107 to form the read transistor 120.

[0189] Exemplarily, a certain thickness of semiconductor material can be deposited on the inner surface of the second via hole 107 first, and then a part of the semiconductor material above the second insulating layer 105 and in the second via hole 107 is removed by etching back to form the second semiconductor channel 123, and then a certain thickness of gate dielectric material and gate material is deposited on the inner surface and the upper surface of the second semiconductor channel 123, and the gate dielectric material and the gate material above the second insulating layer 105 are removed by using a planarization process (for example, chemical mechanical grinding CMP) to form the second gate dielectric 122 and the second gate 121.

[0190] In some embodiments, the second semiconductor channel 123, the second gate dielectric 122 and the second gate 121 can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD).

[0191] The material of the second gate 121 can be a metal material or a conductive material, for example, TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt or any combination of the above materials.

[0192] In an embodiment of the present application, the material of the second gate 121 is IZO.

[0193] The material of the second semiconductor channel 123 can be an oxide semiconductor (OS), specifically, ZnO, In2O3, IGZO, ITO, IWO and IAZO (In-Al-Zn-O) or the like.

[0194] In an embodiment of the present application, the material of the second semiconductor channel 123 is In-Ga-Zn-O (IGZO).

[0195] The material of the second gate dielectric 122 can be an insulating material, for example, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3 and HFO or a combination material, a laminated material or a combined laminated material of the above materials.

[0196] In an embodiment of the present application, the material of the second gate dielectric 122 is HFO.

[0197] It can be understood that any suitable material and deposition process can be used to form the second semiconductor channel 123, the second gate dielectric 122 and the second gate 121, which is not specifically limited herein.

[0198] S50: depositing a third conductive material layer 108 on the second insulating layer 105, etching the third conductive material layer 108 to form a contact block 130, a lower surface of the contact block 130 being in conductive connection with the second gate 121, and the contact block 130 being insulated from the second semiconductor channel 123. Insulating material is filled between adjacent contact blocks 130 to insulate and separate them.

[0199] Please refer to Figure 11 and Figure 12 In some embodiments, the third conductive material layer 108 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular layer deposition (MLD), or the like.

[0200] Exemplarily, the material of the third conductive material layer 108 can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, or the like, or any combination thereof. The material of the third conductive material layer 108 can be the same as or different from the material of the second conductive material layer 104 and the material of the first conductive material layer 102.

[0201] In the embodiments of the present application, the material of the third conductive material layer 108 is the same as the material of the first conductive material layer 102 and the material of the second conductive material layer 104, and is TiN.

[0202] After the third conductive material layer 108 is deposited, the third conductive material layer 108 is etched at a position corresponding to the read transistor 120 to form the contact block 130. The contact block 130 can be in the shape of a block or a particle, and its lower surface is in conductive connection with the second gate 121 and covers the second gate dielectric 122 and the annular insulating layer 1221, thereby achieving close connection with the read transistor 120 and effective insulation from the second semiconductor channel 123.

[0203] In the embodiments of the present application, the shape of the lower surface of the contact block 130 is adapted to the shape of the top surface of the read transistor 120, so as to ensure close adaptation of the contact block 130 to the read transistor 120. Exemplarily, if the shape of the top surface of the read transistor 120 is square, the shape of the lower surface of the contact block 130 can also be square, and if the shape of the top surface of the read transistor 120 is circular, the shape of the lower surface of the contact block 130 can also be circular.

[0204] In the embodiments of the present application, the contact block 130 is etched into a rectangular body with square upper and lower surfaces.

[0205] In one embodiment, the forming process of the contact bump 130 can be a dry etching, a wet etching or a combination of dry etching and wet etching. The wet etching can use a chlorine or fluorine based etchant.

[0206] In the embodiment of the present application, the end of the read transistor 120 in contact with the contact bump 130 is the first end of the read transistor 120 and also the first end of the second gate 121, the end of the read transistor 120 in contact with the first signal line 140 is the second end of the read transistor 120 and also the second end of the second gate 121, the part of the second semiconductor channel 123 between the first signal line 140 and the second signal line 150 is the second effective semiconductor channel 1231, the second effective semiconductor channel 1231 has a shape gradually expanding from the first signal line 140 to the second signal line 150, the part of the first signal line 140 in contact with the second semiconductor channel 123 is the fourth source-drain 125, and the part of the second signal line 150 in contact with the second semiconductor channel 123 is the third source-drain 124.

[0207] The channel outer ring size of the part of the second effective semiconductor channel 1231 close to the third source-drain 124 is different from the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the fourth source-drain 125, i.e. the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the second signal line 150 is different from the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the first signal line 140, specifically, the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the second signal line 150 is greater than the channel outer ring size of the part of the second effective semiconductor channel 1231 close to the first signal line 140.

[0208] In addition, the second effective semiconductor channel 1231 is the part of the second semiconductor channel 123 located on the first dielectric layer 103, i.e. the channel outer ring size of the second effective semiconductor channel 1231 on the upper surface of the first dielectric layer 103 is different from the channel outer ring size of the second effective semiconductor channel 1231 on the lower surface of the first dielectric layer 103, specifically, the second effective semiconductor channel 1231 gradually expands from bottom to top on the first dielectric layer 103.

[0209] S60: sequentially depositing the second dielectric layer 109 and the fourth conductive material layer 10a on the layer where the contact bump 130 is located, etching the fourth conductive material layer 10a to form the third signal line 160, and the third signal line 160 is the bit line of the write transistor 110. The adjacent third signal lines 160 are filled with insulating material for insulation and isolation.

[0210] Please refer to Figure 13 and Figure 14It can be understood that the layer where the contact guide block 130 is located is the original third conductive material layer 108. In order to realize insulation and isolation from the fourth conductive material layer 10a, a second dielectric layer 109 is deposited on the original third conductive material layer 108.

[0211] Similarly, the second dielectric layer 109 and the fourth conductive material layer 10a can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD).

[0212] It can be understood that any suitable material and deposition process can be used to form the second dielectric layer 109 and the fourth conductive material layer 10a, which is not specifically limited here.

[0213] Exemplarily, the material of the second dielectric layer 109 is an insulating oxide, such as SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3, or a combination of the above materials, a stacked material, a combined stacked material, and TEOS.

[0214] In an embodiment of the present application, the material of the second dielectric layer 109 is SiO2.

[0215] Exemplarily, the material of the fourth conductive material layer 10a can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt, or any combination of the above materials. The material of the fourth conductive material layer 10a can be the same as or different from the material of other conductive material layers.

[0216] In an embodiment of the present application, the material of the fourth conductive material layer 10a is the same as the material of other conductive material layers, and both are TiN.

[0217] In one embodiment, the forming process of the third signal line 160 can be dry etching, wet etching, or a combination of dry etching and wet etching. The wet etching can use a chlorine or fluorine-based etchant to etch the fourth conductive material layer 10a.

[0218] In an embodiment of the present application, when forming the third signal line 160, a photolithography process can be used for patterning, and then etching to transfer the pattern to the fourth conductive material layer 10a.

[0219] Exemplarily, a photoresist layer can be formed on the fourth conductive material layer 10a first, and then the photoresist layer is etched to form a photoresist pattern, which is a pattern corresponding to the shape of the third signal line 160. The fourth conductive material layer 10a under the photoresist pattern is etched based on the photoresist pattern to transfer the photoresist pattern to the fourth conductive material layer 10a, i.e., to form a pattern corresponding to the photoresist pattern on the fourth conductive material layer 10a. Finally, the photoresist pattern is removed, and the fourth conductive material layer 10a is etched to form the third signal line 160.

[0220] In one embodiment, to increase the storage density of the memory device 1000, the SADP (Self-Aligned Double Patterning) process can be used to form the third signal line 160 to obtain a third signal line 160 with a smaller line width.

[0221] In step S60, the third signal line 160 formed by etching extends in the first direction (Y-axis direction).

[0222] S70: The third insulating layer 10b and the second hard mask layer 10c are sequentially deposited on the layer where the third signal line 160 is located, and the second hard mask layer 10c, the third insulating layer 10b, the third signal line 160, and the second dielectric layer 109 are etched to form the first via hole 10d extending in the vertical direction to the upper surface of the contact bump 130. The aperture of the part of the first via hole 10d located on the upper surface of the second dielectric layer 109 is different from the aperture of the part of the first via hole 10d located on the lower surface of the second dielectric layer 109.

[0223] Please refer to Figure 15 and Figure 16 The layer where the third signal line 160 is located is the original fourth conductive material layer 10a. The third insulating layer 10b and the second hard mask layer 10c can be sequentially formed on the original fourth conductive material layer 10a by deposition methods such as CVD (Chemical Vapor Deposition), ALD (Atomic Layer Deposition), PVD (Physical Vapor Deposition), and MLD (Molecular Layer Deposition).

[0224] Exemplarily, the material of the third insulating layer 10b can be SiON, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3, or a combination of the above materials, a stacked material, a combined stacked material, or TEOS.

[0225] The material of the third insulating layer 10b can be the same as or different from the material of other insulating layers. In the embodiment of the present application, the material of the third insulating layer 10b is the same as the material of the second insulating layer 105, which is SiN.

[0226] It is worth mentioning that the second hard mask layer 10c can be a single-layer structure or a superposition structure of multiple hard mask layers. The multiple-layer structure can improve the etching selectivity of the hard mask layer.

[0227] In the embodiment of the present application, the second hard mask layer 10c is a superposition structure of multiple hard mask layers, specifically a two-layer superposition structure of a spin-on carbon (SOC) layer and a SiON layer, and the SOC layer is deposited on the third insulating layer 10b.

[0228] It can be understood that any suitable material and deposition process can be used to form the third insulating layer 10b and the second hard mask layer 10c, which is not limited here.

[0229] In one embodiment, the forming process of the first via hole 10d can be a dry etching, wet etching or a combination of dry etching and wet etching. Among them, the wet etching can use chlorine or fluorine-based etchant to etch the second hard mask layer 10c, the third insulating layer 10b, the third signal line 160 and the second dielectric layer 109.

[0230] Exemplarily, the first via hole 10d can be a rectangular hole, a cylindrical hole or other columnar hole, and the hole diameter of the part of the first via hole 10d on the upper surface of the second dielectric layer 109 (referred to as the upper hole diameter of the first via hole 10d) and the hole diameter of the part of the first via hole 10d on the lower surface of the second dielectric layer 109 (referred to as the lower hole diameter of the first via hole 10d) can be different, that is, the upper hole diameter of the first via hole 10d is greater than or less than the lower hole diameter of the first via hole 10d.

[0231] Taking the example that the upper hole diameter of the first via hole 10d is greater than the lower hole diameter, when etching the first via hole 10d, the etching starts from the bottom end of the first via hole 10d (i.e. one end of the upper surface of the contact block 130), and after etching part of the inner wall of the first via hole 10d, the etching of the inner wall of the first via hole 10d continues upwards and to the outside of the first via hole 10d along the central axis of the first via hole 10d, so that the inner wall of the first via hole 10d is offset outward by a certain distance layer by layer, until the upper hole diameter of the first via hole 10d is greater than the lower hole diameter.

[0232] Further, in the embodiment of the present application, the plasma gas for etching the third insulating layer 10b is a mixed gas of CH3F, CH2F2, O2 and Ar, the plasma source power is 500-1000W, and the bias voltage is 200-500V. The plasma gas for etching the second dielectric layer 109 is a mixed gas of C4F8 and O2, the plasma source power is 800-1500W, and the bias voltage is 250-500V.

[0233] S80: Remove the second hard mask layer 10c to form the write transistor 110 in the first via hole 10d.

[0234] The second hard mask layer 10c can be removed by a wet method, a dry method or a combination of the wet method and the dry method, and thus no detailed description is given herein.

[0235] Referring to Figure 17 After the second mask layer is removed, the write transistor 110 can be formed by sequentially depositing the first semiconductor channel 113, the first gate dielectric 112 and the first gate 111 in the first via 10d.

[0236] For example, a semiconductor material with a certain thickness can be first deposited on the inner surface of the first via 10d, and then a part of the semiconductor material above the third insulating layer 10b and in the first via 10d is removed by etching back to form the first semiconductor channel 113. Then, a gate dielectric material and a gate material with a certain thickness are deposited on the inner surface and the upper surface of the first semiconductor channel 113, and the gate dielectric material and the gate material above the third insulating layer 10b are removed by a planarization process (for example, chemical mechanical polishing CMP) to form the first gate dielectric 112 and the first gate 111.

[0237] In some embodiments, the first semiconductor channel 113, the first gate dielectric 112 and the first gate 111 can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD).

[0238] The material of the first gate 111 can be a metal material or a conductive material, for example, TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Cu, Ru, Ag, Pt or any combination of the above materials.

[0239] In the embodiment of the present application, the material of the first gate 111 is IZO.

[0240] The material of the first semiconductor channel 113 can be an oxide semiconductor (OS), for example, ZnO, In2O3, IGZO, ITO, IWO and IAZO (In-Al-Zn-O).

[0241] In the embodiment of the present application, the material of the first semiconductor channel 113 is In-Ga-Zn-O (IGZO).

[0242] The material of the first gate dielectric 112 can be an insulating material, for example, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3 and HFO or a combination material, a laminated material or a combined laminated material of the above materials.

[0243] In the embodiment of the present application, the material of the first gate dielectric 112 is HFO.

[0244] It can be understood that any suitable material and deposition process can be used to form the first semiconductor channel 113, the first gate dielectric 112 and the first gate 111, which are not specifically limited herein.

[0245] S90: depositing a fifth conductive material layer 10e on the third insulating layer 10b, and etching the fifth conductive material layer 10e to form a fourth signal line 170 in contact with the first gate 111, the fourth signal line 170 being a word line of the write transistor 110.

[0246] Please refer to Figure 18 and Figure 19 In some embodiments, the fifth conductive material layer 10e can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular layer deposition (MLD) and the like.

[0247] Exemplarily, the material of the fifth conductive material layer 10e can be TiN, Ti, Au, W, Mo, In-Ti-O (ITO), In-Zn-O (IZO), Al, Cu, Ru, Ag, Pt and the like, or any combination of the above materials.

[0248] The material of the fifth conductive material layer 10e can be the same as or different from that of other metal layers. In the embodiment of the present application, the material of the fifth conductive material layer 10e is the same as that of other metal layers, both being TiN.

[0249] It can be understood that any suitable material and deposition process can be used to form the fifth conductive material layer 10e, which is not specifically limited herein.

[0250] In one embodiment, the forming process of the fourth signal line 170 can be a dry etching, wet etching or a combination of dry etching and wet etching. The wet etching can use chlorine or fluorine-based etchant to etch the fifth conductive material layer 10e.

[0251] In the embodiment of the present application, when forming the fourth signal line 170, a photolithography process can be used for patterning first, and then etching to transfer the pattern to the fifth conductive material layer 10e.

[0252] Exemplarily, a photoresist layer can be formed on the fifth conductive material layer 10e first, and then the photoresist layer is etched to form a photoresist pattern, the photoresist pattern is a pattern corresponding to the shape of the fourth signal line 170, the fifth conductive material layer 10e under the photoresist pattern is etched based on the photoresist pattern to transfer the photoresist pattern to the fifth conductive material layer 10e, i.e., a pattern corresponding to the photoresist pattern is formed on the fifth conductive material layer 10e, and finally the photoresist pattern is removed, and the fifth conductive material layer 10e is etched to form the fourth signal line 170.

[0253] In one embodiment, to increase the storage density of the memory device 1000, the fourth signal line 170 can be formed by using a SADP (Self-Aligned Double Patterning) process to obtain a fourth signal line 170 with a smaller line width.

[0254] In step S90, the fourth signal line 170 formed by etching extends in the second direction (X-axis direction).

[0255] In the embodiment of the present application, the end of the write transistor 110 in contact with the fourth signal line 170 is the first end of the write transistor 110 and also the first end of the first gate 111, the end of the write transistor 110 in contact with the contact plug 130 is the second end of the write transistor 110 and also the second end of the first gate 111, the part of the first semiconductor channel 113 between the third signal line 160 and the contact plug 130 is the first effective semiconductor channel 1131, the first effective semiconductor channel 1131 has a shape gradually expanding from the contact plug 130 to the third signal line 160, the part of the contact plug 130 in contact with the first semiconductor channel 113 is the second source / drain 115, and the part of the third signal line 160 in contact with the first semiconductor channel 113 is the first source / drain 114.

[0256] The channel outer ring size of the part of the first effective semiconductor channel 1131 close to the first source / drain 114 is different from the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the second source / drain 115, i.e., the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the third signal line 160 is different from the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the contact plug 130, specifically, the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the third signal line 160 is greater than the channel outer ring size of the part of the first effective semiconductor channel 1131 close to the contact plug 130.

[0257] In addition, the first effective semiconductor channel 1131 is a part of the first semiconductor channel 113 located on the second dielectric layer 109, that is, the outer ring size of the first effective semiconductor channel 1131 on the upper surface of the second dielectric layer 109 is different from the outer ring size of the first effective semiconductor channel 1131 on the lower surface of the second dielectric layer 109, specifically, the first effective semiconductor channel 1131 gradually expands from bottom to top on the second dielectric layer 109.

[0258] Further, in the embodiment of the present application, the step S10 can include the steps of:

[0259] S101: depositing a third hard mask layer on the first conductive material layer 102, etching the third hard mask layer and the first conductive material layer 102 to form a laminated structure of the third hard mask layer and the first signal line 140;

[0260] Wherein, the structure and forming process of the third hard mask layer can refer to the structure and forming process of the first hard mask layer 106 described above, except that the amorphous carbon (Amorphous Carbon) layer and the SiON layer are sequentially deposited on the first conductive material layer 102, the SOC layer is deposited on the SiON layer, and the SiON layer is deposited on the SOC layer to form the third hard mask layer.

[0261] In one embodiment, the process of etching the third hard mask layer and the first conductive material layer 102 can be a dry etching, wet etching or a combination of dry etching and wet etching process. Wherein, the third hard mask layer and the first conductive material layer 102 can be etched by using a chlorine or fluorine-based etchant.

[0262] S102: removing the third hard mask layer to expose the first signal line 140 and the first insulating layer 101;

[0263] Wherein, the third hard mask layer can be removed by wet etching, dry etching or a combination of wet etching and dry etching, which will not be described in detail here.

[0264] S103: depositing a fourth insulating layer on the first signal line 140 and the surface of the first insulating layer 101 not shielded by the first signal line 140;

[0265] Wherein, the fourth insulating layer can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) and molecular layer deposition (MLD) and the like. The material of the fourth insulating layer can be SiON, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3 and the like, or a combination of the above materials, laminated materials, combined laminated materials, and can also be TEOS.

[0266] In the embodiment of the present application, the material of the fourth insulating layer is SiN.

[0267] S104: Polishing the fourth insulating layer to expose the first signal line 140, and leaving the fourth insulating layer on the first insulating layer 101.

[0268] Wherein, the polishing of the fourth insulating layer can be achieved by chemical-mechanical polishing (CMP).

[0269] It can be understood that the first conductive material layer 102 can be etched to form a plurality of first signal lines 140 spaced apart in the second direction, and in this step, the fourth insulating layer is used to separate adjacent first signal lines 140, and the fourth insulating layer on the first insulating layer 101 is integrated with the first insulating layer 101 to ensure surface flatness and facilitate subsequent deposition of other structures.

[0270] Further, in the embodiment of the present application, step S20 can include the following steps:

[0271] S201: Depositing a fourth hard mask layer on the second conductive material layer 104, etching the fourth hard mask layer and the second conductive material layer 104 to form a laminated structure of the fourth hard mask layer and the second signal line 150;

[0272] Wherein, the structure and forming process of the fourth hard mask layer can refer to the structure and forming process of the first hard mask layer 106 described above, except that an amorphous carbon (Amorphous Carbon) layer and a SiON layer are further deposited on the second conductive material layer 104, an SOC layer is deposited on the SiON layer, and a SiON layer is further deposited on the SOC layer to form the fourth hard mask layer.

[0273] In one embodiment, the etching process of the fourth hard mask layer and the second conductive material layer 104 can be dry etching, wet etching, or a combination of dry etching and wet etching. Wherein, the wet etching can use chlorine or fluorine-based etchant to etch the fourth hard mask layer and the second conductive material layer 104.

[0274] S202: Removing the fourth hard mask layer to expose the second signal line 150 and the first dielectric layer 103;

[0275] Wherein, the fourth hard mask layer can be removed by wet etching, dry etching, or a combination of wet etching and dry etching, which will not be described in detail here.

[0276] S203: Depositing a fifth insulating layer on the second signal line 150 and the surface of the first dielectric layer 103 not shielded by the second signal line 150;

[0277] The fifth insulating layer can be formed by deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and molecular layer deposition (MLD). The material of the fifth insulating layer can be SiON, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3, or a combination, a stack, or a combination stack of the above materials, and can also be TEOS.

[0278] In the embodiment of the present application, the material of the fifth insulating layer is SiN.

[0279] S204: Polishing the fifth insulating layer to expose the second signal line 150 and retaining the fifth insulating layer on the first dielectric layer 103.

[0280] The polishing of the fifth insulating layer can be achieved by chemical-mechanical polishing (CMP).

[0281] It can be understood that the second conductive material layer 104 can be etched to form a plurality of second signal lines 150 spaced apart in the first direction. In this step, the fifth insulating layer is used to separate adjacent second signal lines 150, and the fifth insulating layer on the first dielectric layer 103 is used to isolate the first dielectric layer 103 from other layers deposited thereon later.

[0282] Further, in the embodiment of the present application, the process of forming the second via hole 107 in step S30 includes the following steps:

[0283] S301: Forming a first photoresist layer on the first hard mask layer 106 and etching the first photoresist layer to form a first photoresist pattern;

[0284] The part of the first photoresist layer where the first photoresist pattern is to be formed can be etched by photolithography to form a designed shape, i.e., the first photoresist pattern, and the shape corresponding to the first photoresist pattern is the hole shape of the second via hole 107, such as a circular shape, a square shape, or other shapes.

[0285] S302: Etching the first hard mask layer 106 to transfer the first photoresist pattern to the first hard mask layer 106 and the second insulating layer 105;

[0286] After etching the first photoresist layer to form the first photoresist pattern, the first hard mask layer 106 and the second insulating layer 105 under the first photoresist layer are further etched based on the first photoresist pattern, and the first photoresist pattern is transferred to the first hard mask layer 106 and the second insulating layer 105, i.e., a pattern corresponding to the first photoresist pattern is formed on the first hard mask layer 106 and the second insulating layer 105.

[0287] In one embodiment, the process of etching the first hard mask layer 106 and the second insulating layer 105 can be a dry etching process, a wet etching process, or a combination of dry etching and wet etching. The wet etching can use chlorine or fluorine based etching agent to etch the first hard mask layer 106 and the second insulating layer 105.

[0288] S303: removing the first photoresist pattern, etching the second signal line 150 and the first dielectric layer 103 to form the second via hole 107 extending from the upper surface of the second insulating layer 105 to the upper surface of the first signal line 140 in the vertical direction;

[0289] In one embodiment, the process of removing the first photoresist pattern can be a wet cleaning process or an ashing process.

[0290] In one embodiment, the process of etching the second signal line 150 and the first dielectric layer 103 can be a dry etching process, a wet etching process, or a combination of dry etching and wet etching. The wet etching can use chlorine or fluorine based etching agent to etch the second signal line 150 and the first dielectric layer 103.

[0291] In one embodiment, the process of etching the first dielectric layer 103 is to etch the first dielectric layer 103 in the vertical direction in a stepwise manner, so that the aperture of the part of the second via hole 107 located on the upper surface of the first dielectric layer 103 is different from the aperture of the part of the second via hole 107 located on the lower surface of the first dielectric layer 103.

[0292] If the first dielectric layer 103 is etched in a stepwise manner in a gradually expanding manner from the lower part to the upper part along the central axis of the second via hole 107, the aperture of the part of the second via hole 107 located on the upper surface of the first dielectric layer 103 will be larger than the aperture of the part of the second via hole 107 located on the lower surface of the first dielectric layer 103. If the first dielectric layer 103 is etched in a stepwise manner in a gradually shrinking manner from the lower part to the upper part along the central axis of the second via hole 107, the aperture of the part of the second via hole 107 located on the upper surface of the first dielectric layer 103 will be smaller than the aperture of the part of the second via hole 107 located on the lower surface of the first dielectric layer 103.

[0293] For example, the second via hole 107 after etching is approximately in the shape of a quadrangular prism, and the aperture of the part of the second via hole 107 located on the upper surface of the first dielectric layer 103 is larger than the aperture of the part of the second via hole 107 located on the lower surface of the first dielectric layer 103.

[0294] The circumferential wall of the second through hole 107 after etching includes four side walls connected to form the circumferential wall, each side wall can be smoothly connected by multiple vertical planes distributed in the Z-axis direction, each vertical plane can extend in the Y-axis and Z-axis direction or extend in the X-axis and Z-axis direction, and adjacent two vertical planes on the same side wall are staggered in the Y-axis direction or the X-axis direction, that is, the normal projection of the adjacent two vertical planes in the Z-axis direction is staggered to form a stepped surface, that is, the four side walls are all stepped side walls, so that the second through hole 107 after etching is approximately inverted tower-shaped.

[0295] Before etching, the second through hole 107 is in a cuboid shape, and the opening shape can be square. During etching, the first layer of vertical planes can be etched on the circumferential wall of the second through hole 107, that is, etching starts near the lower surface of the first dielectric layer 103. At this time, the four vertical planes are connected together, which is approximately a rectangular space. The second layer of vertical planes is continuously etched to form a rectangular space with a larger area. The third layer, the fourth layer, and so on are continuously etched until the upper surface of the first dielectric layer 103 is etched to achieve complete etching.

[0296] Further, in the embodiment of the present application, step S50 includes the following steps:

[0297] S501: depositing a fifth hard mask layer on the third conductive material layer 108, forming a third photoresist layer on the fifth hard mask layer, etching the third photoresist layer to form a third photoresist pattern, etching the fifth hard mask layer, transferring the third photoresist pattern to the fifth hard mask layer, and then removing the third photoresist pattern;

[0298] The content of depositing and forming the fifth hard mask layer can refer to the forming process of the first hard mask layer 106 to the fourth hard mask layer described above, which will not be described in detail here.

[0299] The part of the third photoresist layer that needs to form a third photoresist pattern can be etched by photolithography to form a designed shape, that is, a third photoresist pattern, and the shape corresponding to the third photoresist pattern is a hole shape of a through hole, such as a circular shape, a square shape or other shapes. In the embodiment of the present application, the third photoresist pattern is a square shape.

[0300] After etching the third photoresist layer to form a third photoresist pattern, the fifth hard mask layer under the third photoresist layer is etched based on the third photoresist pattern, and the third photoresist pattern is transferred to the fifth hard mask layer, that is, a pattern corresponding to the third photoresist pattern is formed on the fifth hard mask layer.

[0301] In one embodiment, the process of removing the third photoresist pattern can be a wet cleaning or ashing process.

[0302] S502: depositing a sixth insulating layer on the fifth hard mask layer and the third photoresist pattern, removing the sixth insulating layer on the surface of the fifth hard mask layer, and retaining the sixth insulating layer in the third photoresist pattern;

[0303] The formation and removal of the sixth insulating layer can refer to the formation and removal of the fifth insulating layer, which will not be described in detail herein.

[0304] S503: removing the fifth hard mask layer, etching the third conductive material layer 108 through the remaining sixth insulating layer as a mask to form a contact guide block 130, the lower surface of the contact guide block 130 being conductively connected to the second gate 121, and the contact guide block 130 being insulated from the second semiconductor channel 123;

[0305] In this step, the shape of the contact guide block 130 formed is adapted to the shape of the upper opening of the second via hole 107, such as a rectangular block-shaped contact guide block 130, the upper and lower surfaces of which are substantially square.

[0306] S504: removing the remaining sixth insulating layer, depositing a seventh insulating layer on the contact guide block 130 and the second insulating layer 105, polishing the seventh insulating layer to expose the contact guide block 130, and retaining the seventh insulating layer on the second insulating layer 105.

[0307] Etching the third conductive material layer 108 can form a plurality of contact guide blocks 130, and in this step, the seventh insulating layer remaining on the second insulating layer 105 is used to insulate adjacent contact guide blocks 130 to avoid electrical connection between adjacent contact guide blocks 130.

[0308] Further, in the embodiment of the present application, step S60 can include the following steps:

[0309] S601: depositing a sixth hard mask layer on the fourth conductive material layer 10a, etching the sixth hard mask layer and the fourth conductive material layer 10a to form a laminated structure of the sixth hard mask layer and the third signal line 160;

[0310] The structure and formation process of the sixth hard mask layer can refer to the structure and formation process of the first hard mask layer, except that the fourth conductive material layer 10a is further sequentially deposited with an amorphous carbon (Amorphous Carbon) layer and a SiON layer, the SOC layer is deposited on the SiON layer, and the SiON layer is further deposited on the SOC layer to form the sixth hard mask layer.

[0311] S602: removing the sixth hard mask layer to expose the third signal line 160 and the second dielectric layer 109;

[0312] The sixth hard mask layer can be removed by wet etching, dry etching or a combination of wet etching and dry etching, and thus no detailed description is given herein.

[0313] S603: depositing an eighth insulating layer on the third signal line 160 and the surface of the second dielectric layer 109 not covered by the third signal line 160;

[0314] The eighth insulating layer can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) or molecular layer deposition (MLD). The material of the eighth insulating layer can be SiON, SiOx, SiNx, Al2O3, HfO2, ZrO2, TiO2, Y2O3 or a combination, a stack or a combination stack of the above materials, or TEOS.

[0315] In the embodiment of the present application, the material of the eighth insulating layer is SiN.

[0316] S604: polishing the eighth insulating layer to expose the third signal line 160 and keep the eighth insulating layer on the second dielectric layer 109.

[0317] The eighth insulating layer can be polished by chemical-mechanical polishing (CMP).

[0318] It can be understood that the fourth conductive material layer 10a can be etched to form a plurality of third signal lines 160 spaced apart along the first direction. In this step, the eighth insulating layer is used to separate adjacent third signal lines 160, and the eighth insulating layer on the second dielectric layer 109 is used to isolate the second dielectric layer 109 from other layers deposited thereon later.

[0319] Further, in the embodiment of the present application, the process of forming the first via 10d in step S70 includes the following steps:

[0320] S701: forming a second photoresist layer on the second hard mask layer 10c and etching the second photoresist layer to form a second photoresist pattern;

[0321] The part of the second photoresist layer where the second photoresist pattern is to be formed can be etched by photolithography to form a designed shape, i.e., the second photoresist pattern, and the shape corresponding to the second photoresist pattern is the shape of the first via 10d, such as a circular shape, a square shape or other shapes.

[0322] S702: etching the second hard mask layer 10c to transfer the second photoresist pattern to the second hard mask layer 10c and the third insulating layer 10b;

[0323] After the second photoresist layer is etched to form the second photoresist pattern, the second hard mask layer 10c and the third insulating layer 10b under the second photoresist layer are continuously etched based on the second photoresist pattern, so that the second photoresist pattern is transferred to the second hard mask layer 10c and the third insulating layer 10b, that is, a pattern corresponding to the second photoresist pattern is formed on the second hard mask layer 10c and the third insulating layer 10b.

[0324] In one embodiment, the process of etching the second hard mask layer 10c and the third insulating layer 10b can be a dry etching process, a wet etching process, or a combination of dry etching and wet etching. In the wet etching process, a chlorine or fluorine-based etchant can be used to etch the second hard mask layer 10c and the third insulating layer 10b.

[0325] S703: Remove the second photoresist pattern, etch the third signal line 160 and the second dielectric layer 109 to form a first via 10d extending from the upper surface of the third insulating layer 10b to the upper surface of the contact block 130 in the vertical direction;

[0326] In one embodiment, the process of removing the second photoresist pattern can be a wet cleaning process or an ashing process.

[0327] In one embodiment, the process of etching the third signal line 160 and the second dielectric layer 109 can be a dry etching process, a wet etching process, or a combination of dry etching and wet etching. In the wet etching process, a chlorine or fluorine-based etchant can be used to etch the third signal line 160 and the second dielectric layer 109.

[0328] In one embodiment, the process of etching the second dielectric layer 109 is performed in a step-by-step manner in the vertical direction, that is, the first via 10d has different diameters at different positions in the vertical direction.

[0329] The specific formation process of the first via 10d can refer to the formation process of the second via 107 described above, and will not be described in detail here.

[0330] Further, in the present embodiment, step S90 can include the following steps:

[0331] S901: Deposit a seventh hard mask layer on the fifth conductive material layer 10e, etch the seventh hard mask layer and the fifth conductive material layer 10e to form a stacked structure of the seventh hard mask layer and the fourth signal line 170;

[0332] S902: Remove the seventh hard mask layer to expose the fourth signal line 170 and the third insulating layer 10b;

[0333] S903: depositing a ninth insulating layer on the fourth signal line 170 and the surface of the third insulating layer 10b not covered by the fourth signal line 170;

[0334] S904: grinding the ninth insulating layer to expose the fourth signal line 170 and keep the ninth insulating layer on the third insulating layer 10b.

[0335] The detailed forming process of the fourth signal line 170 can refer to the forming process of the second signal line 150 or other signal lines described above, and will not be described in detail here.

[0336] In the description of the present specification, the description referring to the terms "embodiment one", "embodiment two", and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0337] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory cell, comprising: The application relates to a semiconductor device, comprising: a write transistor, the write transistor comprising a first gate, a first gate dielectric surrounding the first gate, a first semiconductor channel surrounding the first gate dielectric, a first source-drain electrode and a second source-drain electrode; the first source-drain electrode is arranged at a first end of the first gate and outside the first semiconductor channel; the second source-drain electrode is arranged at a second end of the first gate and outside the first semiconductor channel; a read transistor, the read transistor comprising a second gate, a second gate dielectric surrounding the second gate, a second semiconductor channel surrounding the second gate dielectric, a third source-drain electrode and a fourth source-drain electrode; the second source-drain electrode and the second gate are electrically connected; the third source-drain electrode is arranged at a first end of the second gate and outside the second semiconductor channel; the fourth source-drain electrode is arranged at a second end of the second gate and outside the second semiconductor channel; wherein a part of the first semiconductor channel between the first source-drain electrode and the second source-drain electrode is a first effective semiconductor channel; a part of the second semiconductor channel between the third source-drain electrode and the fourth source-drain electrode is a second effective semiconductor channel; a part of the first effective semiconductor channel close to the first source-drain electrode has a different channel outer ring size than a part of the first effective semiconductor channel close to the second source-drain electrode; a part of the second effective semiconductor channel close to the third source-drain electrode has a different channel outer ring size than a part of the second effective semiconductor channel close to the fourth source-drain electrode.

2. The memory cell of claim 1, wherein, The outer ring size of the first effective semiconductor channel is gradually reduced or gradually increased.

3. The memory cell of claim 1, wherein, The outer ring size of the second effective semiconductor channel is gradually reduced or gradually increased.

4. The memory cell of claim 1, wherein, The write transistor is above the read transistor, and the central axis of the first semiconductor channel and the central axis of the second semiconductor channel coincide.

5. The memory cell of claim 4, wherein, The projection of the first semiconductor channel on a plane perpendicular to the central axis is conformal to the projection of the second semiconductor channel on a plane perpendicular to the central axis.

6. The memory cell of claim 4, wherein, A contact block is arranged between the write transistor and the read transistor, the second source-drain electrode and the second gate are electrically connected through the contact block, and the central axis of the contact block coincides with the central axis of the first semiconductor channel and the central axis of the second semiconductor channel; The upper surface of the contact block is in contact with the first semiconductor channel, the lower surface of the contact block is in contact with the second gate, and the contact block is insulated from the second semiconductor channel.

7. The memory cell of claim 6, wherein, The contact block is integrally formed with the second source-drain electrode, and the material of the contact block is the same as that of the second source-drain electrode.

8. The memory cell of claim 6, wherein, The size of the lower surface of the contact block is greater than the outer ring size of the second gate dielectric.

9. The memory cell of claim 8, wherein, The upper surface of the second gate and the upper surface of the second gate dielectric are flush, and the upper surface of the second semiconductor channel is lower than the upper surface of the second gate and the upper surface of the second gate dielectric. An annular insulating layer is arranged between the lower surface of the contact bump and the upper surface of the second semiconductor channel, the inner ring size of the annular insulating layer is equal to the outer ring size of the second gate dielectric, and the outer ring size of the annular insulating layer is equal to the outer ring size of the second semiconductor channel.

10. The memory cell of claim 9, wherein, The annular insulating layer is integrally formed with the second gate dielectric and has the same material as the second gate dielectric.

11. The memory cell of claim 6, wherein, The size of the upper surface of the contact bump is greater than or equal to the size of the contact surface of the first semiconductor channel.

12. The memory cell of claim 1, wherein, The first source / drain is arranged around the first end of the first gate, and the third source / drain is arranged around the first end of the second gate.

13. A memory device, comprising: Comprise: a semiconductor substrate; and at least one memory cell according to any one of claims 1 to 12 formed on the semiconductor substrate.

14. The memory device of claim 13, wherein, The number of memory cells is multiple, and multiple memory cells form a memory array structure in a horizontal plane.

15. The memory device of claim 14, wherein, The multiple memory cells in the memory array structure are arranged in an array in a first direction and a second direction, and the first direction intersects the second direction.

16. The memory device of claim 15, wherein, The first direction intersects the second direction at 90°.

17. The memory device of claim 15, wherein, The memory device further comprises: a first signal line, a second signal line, a third signal line and a fourth signal line, the first signal line and the third signal line extend in the first direction, and the second signal line and the fourth signal line extend in the second direction; the number of the first signal line, the second signal line, the third signal line and the fourth signal line is multiple, and matches the number of rows and columns in the memory array structure; wherein the number of the first signal line is the same as the number of the third signal line, and the number of the second signal line is the same as the number of the fourth signal line; the first signal line is arranged in the second direction and is in contact with the fourth source / drain; the second signal line is arranged in the first direction and is in contact with the third source / drain; the third signal line is arranged in the second direction and is in contact with the first source / drain, and the third signal line is the bit line of the write transistor; the fourth signal line is arranged in the first direction and is in contact with the first gate, and the fourth signal line is the word line of the write transistor.

18. The memory device of claim 17, wherein, The first signal line is integrally formed with the fourth source / drain and has the same material as the fourth source / drain; The second signal line is integrally formed with the third source / drain and has the same material as the third source / drain; The third signal line is integrally formed with the first source / drain and has the same material as the first source / drain.

19. A method of manufacturing a memory device, for manufacturing a memory device according to any one of claims 13 to 18, characterized in that, Comprise the following steps: providing a semiconductor substrate, depositing a first insulating layer and a first conductive material layer on the semiconductor substrate in sequence, etching the first conductive material layer to form a first signal line; depositing a first dielectric layer and a second conductive material layer on the layer where the first signal line is located in sequence, etching the second conductive material layer to form a second signal line; Depositing a second insulating layer and a first hard mask layer on the layer where the second signal line is located in sequence, etching the first hard mask layer, the second insulating layer, the second signal line and the first dielectric layer to form a second via hole extending to the upper surface of the first signal line in the vertical direction, the aperture of the part of the second via hole located on the upper surface of the first dielectric layer being different from the aperture of the part of the second via hole located on the lower surface of the first dielectric layer; Removing the first hard mask layer to form a read transistor in the second via hole; Depositing a third conductive material layer on the second insulating layer, and etching the third conductive material layer to form a contact bump, the lower surface of the contact bump being in conductive connection with the second gate, and the contact bump being insulated from the second semiconductor channel; Depositing a second dielectric layer and a fourth conductive material layer on the layer where the contact bump is located in sequence, and etching the fourth conductive material layer to form a third signal line, the third signal line being a bit line of a write transistor; Depositing a third insulating layer and a second hard mask layer on the layer where the third signal line is located in sequence, etching the second hard mask layer, the third insulating layer, the third signal line and the second dielectric layer to form a first via hole extending to the upper surface of the contact bump in the vertical direction, the aperture of the part of the first via hole located on the upper surface of the second dielectric layer being different from the aperture of the part of the first via hole located on the lower surface of the second dielectric layer; Removing the second hard mask layer to form a write transistor in the first via hole; Depositing a fifth conductive material layer on the third insulating layer, and etching the fifth conductive material layer to form a fourth signal line in contact connection with the first gate, the fourth signal line being a word line of the write transistor.

20. The method of manufacturing a memory device according to claim 19, wherein, The plasma gas for etching the second insulating layer and the third insulating layer is a mixed gas of CH3F, CH2F2, O2 and Ar, the plasma source power is 500-1000 W, and the bias voltage is 200-500 V; The plasma gas for etching the first dielectric layer and the second dielectric layer is a mixed gas of C4F8 and O2, the plasma source power is 800-1500 W, and the bias voltage is 250-500 V.

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