Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A method for manufacturing a semiconductor device includes: forming a preliminary horizontal layer vertically stacked over a lower structure in a first direction and horizontally extending in a second direction crossing the first direction; forming a finishing target layer around each preliminary horizontal layer; forming a horizontal layer by trimming the preliminary horizontal layer in a third direction crossing the second direction; forming a trimmed target layer by trimming the trimming target layer in a third direction; and replacing the trimmed target layer with a conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0104844, filed on August 10, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a three-dimensional memory cell and a method of manufacturing the semiconductor device. Background Art

[0004] Recently, in order to cope with demands for large capacity and miniaturization of memory devices, a technology for providing a 3D memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0005] Embodiments of the present invention relate to a three-dimensional semiconductor device including highly integrated memory cells arranged in a three-dimensional array and a method for manufacturing the semiconductor device. Hereinafter, the three-dimensional semiconductor device is also referred to as a semiconductor device for short.

[0006] According to an embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming preliminary horizontal layers vertically stacked on a lower structure in a first direction, each preliminary horizontal layer extending in a second direction intersecting the first direction; forming a trimming target layer around each preliminary horizontal layer; forming a horizontal layer by trimming the preliminary horizontal layer in a third direction intersecting the second direction; forming a trimmed target layer by trimming the trimming target layer in the third direction; and replacing the trimmed target layer with a conductive layer.

[0007] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming preliminary horizontal layers vertically stacked on a lower structure in a first direction and extending horizontally in a second direction intersecting the first direction; forming a conductive target layer arranged in the upper and lower parts of each preliminary horizontal layer; forming a horizontal layer by trimming the preliminary horizontal layer in a third direction intersecting the second direction; forming a trimmed conductive target layer by trimming the conductive target layer in the third direction; and forming a pair of horizontal conductive wires respectively arranged on the upper and lower surfaces of the horizontal layer by horizontally recessing edge portions on both sides of the trimmed conductive target layer in the second direction.

[0008] According to another embodiment of the present invention, a semiconductor device includes: a unit separation layer vertically oriented in a first direction; a horizontal layer horizontally oriented in a second direction intersecting the first direction and vertically stacked between the unit separation layers in the first direction; a vertical conductive wire vertically oriented in the first direction and coupled to a first edge of the horizontal layer; a horizontal conductive wire intersecting each horizontal layer in a third direction intersecting the first direction and the second direction; and data storage elements respectively coupled to the second edges of the horizontal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention.

[0010] Figure 1B It is shown Figure 1A A schematic cross-sectional view of a memory cell is shown.

[0011] Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0012] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention.

[0013] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention.

[0014] Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown.

[0015] Figure 3B is along Figure 2 A cross-sectional view taken along line AA' is shown.

[0016] Figure 3C is along Figure 2 A cross-sectional view taken along line BB' is shown.

[0017] Figure 3D is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0018] FIG. 4A to FIG. 26B An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0019] FIG. 27A to FIG. 38B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0020] FIG. 39A to FIG. 39Cis a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0021] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in multiple drawings and embodiments of the present invention.

[0022] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0023] The following embodiments of the present invention relate to three-dimensional memory cells. Memory cell density can be increased and parasitic capacitance can be reduced by vertically stacking memory cells.

[0024] Figure 1A is a schematic perspective view showing a storage unit according to an embodiment of the present invention. Figure 1B It is shown Figure 1A A schematic cross-sectional view of a memory cell is shown. Figure 1C It is shown Figure 1A A plan view of the switching element shown.

[0025] Reference Figures 1A to 1C , the memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0026] The first wire BL may be oriented in a first direction D1. The first direction D1 may also be referred to as a stacking direction or a vertical direction. In some embodiments, the first direction may be a vertical direction. In some embodiments, the first direction may be a vertical direction or a vertical direction. It should be noted that although some elements of the present invention are described as being vertically or vertically oriented, the present invention is not limited thereto. The first wire BL may include a bit line. The first wire BL may also be referred to as a vertical wire, a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first wire BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0027] The switching element TR may have a function of controlling a voltage (or current) source to the data storage element CAP in a data write operation and a data read operation of the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. In some embodiments, the horizontal layer HL may be a horizontal layer. The second wire DWL may include a horizontal wire or a horizontal word line, and the horizontal layer HL may include an active layer. The switching element TR may include a transistor, and in this case, the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as an access element or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line. In some embodiments, the second wire DWL may extend in a horizontal direction and may be referred to as a horizontal gate electrode or a horizontal word line.

[0028] The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second direction D2 may also be referred to as a horizontal direction D2. In some embodiments, the second direction may be a horizontal direction. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The third direction D3 may be a second horizontal direction. The second direction D2 and the third direction D3 may be orthogonal to each other. The first direction, the second direction, and the third direction may be orthogonal to each other. In some embodiments, the first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. For example, the horizontal layer HL may extend along a first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend along a second horizontal direction (i.e., the third direction D3).

[0029] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon-germanium. According to another embodiment of the present invention, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present invention, the horizontal layer HL may include a conductive metal oxide.

[0030] The upper surface and the lower surface of the horizontal layer HL may have flat surfaces. The upper surface and the lower surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0031] The horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doping region SR and the second doping region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body.

[0032] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type impurities or P-type impurities. The first doping region SR and the second doping region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR may be coupled to the first conductive line BL, and the second doping region DR may be coupled to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as a first source / drain region and a second source / drain region.

[0033] The horizontal layer HL may be horizontally oriented in the second direction D2 from the first conductive line BL.

[0034] The second wire DWL may have a double structure. For example, the second wire DWL may include an upper horizontal wire G1 and a lower horizontal wire G2 facing each other and with the horizontal layer HL therebetween. In some embodiments, the upper horizontal wire G1 and the lower horizontal wire G2 may be an upper horizontal wire G1 and a lower horizontal wire G2. The interlayer dielectric layer GD may be formed on or above the upper surface and the lower surface of the horizontal layer HL. The upper horizontal wire G1 may be disposed above the horizontal layer HL, and the lower horizontal wire G2 may be disposed below the horizontal layer HL. The second wire DWL may include a pair of upper horizontal wires G1 and lower horizontal wires G2. In the second wire DWL, the same driving voltage may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. For example, the upper horizontal wire G1 and the lower horizontal wire G2 may form a pair and may be coupled to one memory cell MC. According to another embodiment of the present invention, different driving voltages may be applied to the upper horizontal wire G1 and the lower horizontal wire G2. In this case, one between the upper horizontal wire G1 and the lower horizontal wire G2 may be used as a back gate or a shielding gate.

[0035] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more. The second wire DWL may include a stack of a low work function material and a high work function material.

[0036] Each of the upper horizontal line G1 and the lower horizontal line G2 may have a width in the second direction D2, for example, a width of an overlapping portion overlapping the horizontal layer HL, which is greater than a width of a portion not overlapping the horizontal layer HL. Due to this width difference, a sidewall of the second conductive line DWL extending along the third direction D3 may have a notch-shaped sidewall.

[0037] Return to reference Figure 1C , the second conductive line DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may refer to a portion overlapping with the channel CH of the horizontal layer HL, and the channel non-overlap portion NOL may refer to a portion not overlapping with the horizontal layer HL. The channel overlap portion WLP may have a cross shape or a diamond shape. According to another embodiment of the present invention, a side surface of the channel overlap portion WLP may have a curved shape or a circular shape.

[0038] The channel CH and the channel overlap portion WLP of the second conductive line DWL may overlap each other. The channel CH may have a cross shape or a diamond shape. The size of the channel overlap portion WLP of the second conductive line DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second conductive line DWL may completely overlap with the channel CH.

[0039] From a top view perspective, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, a side surface of the horizontal layer HL may have a curved shape or a rounded shape.

[0040] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a lateral or horizontal layer side dielectric layer. The interlayer dielectric layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0041] The data storage element CAP may include a storage element, such as a capacitor. The data storage element CAP may be arranged laterally (e.g., horizontally) from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN extending laterally (e.g., horizontally) from the horizontal layer HL in the second direction D2. The data storage element CAP may also include a second electrode PN on the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be arranged laterally (e.g., horizontally) along the second direction D2. The first electrode SN may include an internal space and a plurality of external surfaces, and the internal space of the first electrode SN may include a plurality of internal surfaces. The outer surface of the first electrode SN may include a vertical (e.g., vertical) external surface and a plurality of lateral (e.g., horizontal) external surfaces. For example, the vertical external surface of the first electrode SN may extend vertically in the first direction D1, and the horizontal external surface of the first electrode SN may extend laterally (e.g., horizontally) in the second direction D2 or the third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover or conformally be located on the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed in an inner space of the first electrode SN over the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0042] The data storage element CAP may have a three-dimensional structure. The first electrode SN may have a 3D structure, and the first electrode SN of the 3D structure may have a lateral (e.g., horizontal) 3D structure oriented along the second direction D2. As an example of a 3D structure, the first electrode SN may have a barrel shape. The barrel shape of the first electrode SN may include a barrel inner surface and a barrel outer surface. Some barrel outer surfaces of the first electrode SN may be electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN may be disposed on the barrel inner surface of the first electrode SN.

[0043] According to another embodiment of the present invention, the first electrode SN may have a pillar shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which a pillar shape and a barrel shape are combined.

[0044] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as a second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0045] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer DE may be formed by a composite layer including two or more layers of the aforementioned high-k materials.

[0046] The dielectric layer DE may be formed of a zirconium (Zr)-based oxide. The dielectric layer DE may have a stacking structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide (ZrO2)-based layer. According to another embodiment of the present invention, the dielectric layer DE may be formed of a hafnium (Hf)-based oxide. The dielectric layer DE may have a stacking structure including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may be referred to as a hafnium oxide (HfO2) base layer. In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a dielectric constant lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high-k material and a high-band gap material having a band gap energy greater than that of the high-k material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may include silicon oxide (SiO2) as a high-band gap material. Since the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the dielectric layer DE may include a stacking structure in which the high-k material and the high bandgap material are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacking structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0047] According to another embodiment of the present invention, the dielectric layer DE may include a high-k material and a high bandgap material, and may include a stacked structure in which multiple high-k materials and multiple high bandgap materials are stacked, or a mixed structure in which the high-k material and the high bandgap material are mixed with each other.

[0048] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0049] According to another embodiment of the present invention, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of an antiferroelectric material and a ferroelectric material.

[0050] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0051] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor. The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0052] For example, the memory cell MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced by an anode wire. The horizontal layer HL may include four semiconductor layers stacked laterally along the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows or a low conductance state in which a small amount of current or no current flows. Each memory cell MC may have a "1" state or a "0" state based on the high conductance state and the low conductance state of the thyristor.

[0053] Return to reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and each of the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0054] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present invention. Figure 1D The memory cell MC1 shown may be similar to Figures 1A to 1C The memory cell MC shown in FIG. 1 may be omitted in the following text. Figures 1A to 1C A detailed description of the constituent elements that appear in.

[0055] The memory cell MC1 may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second conductive line DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0056] The memory cell MC1 may further include a first contact node BLC between the first conductive line BL and the horizontal layer HL, and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. Each of the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0057] The second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second work function electrode G12, the first work function electrode G11, and the third work function electrode G13 may be arranged transversely along the second direction D2, for example, arranged horizontally. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first wire BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The first work function electrode G11 may be arranged between the second work function electrode G12 and the third work function electrode G13. The thickness of the horizontal layer HL may be thinner than the thickness of each of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0058] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of materials having different work functions. The first work function electrode G11 may have a higher work function than the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include a low work function material. The second work function electrode G12 and the third work function electrode G13 may have a work function lower than the mid-gap work function of silicon. The high work function material may have a work function higher than about 4.5 eV, and the low work function material may have a work function lower than about 4.5 eV. The first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may include a semiconductor material.

[0059] The second work function electrode G12 and the third work function electrode G13 may include doped polysilicon doped with an N-type dopant (doped polysilicon of an N-type dopant). The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0060] According to an embodiment of the present invention, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a second work function electrode G12-a first work function electrode G11-a third work function electrode G13, which are arranged laterally (e.g., horizontally) in the second direction D2. The first work function electrode G11 may include metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0061] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a PMP (polysilicon-metal-polysilicon) structure, in which polysilicon, metal, and polysilicon are arranged laterally (e.g., horizontally) in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may be doped polysilicon of an N-type dopant, which is polysilicon doped with an N-type dopant. The N-type dopant may include phosphorus or arsenic.

[0062] The first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface, and one side surface of the first work function electrode G11 or be located on the upper surface, the lower surface, and one side surface of the first work function electrode G11.

[0063] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13, so the second wire DWL may have a low resistance. The first work function electrode G11 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The second work function electrode G12 and the third work function electrode G13 of the upper horizontal line G1 and the lower horizontal line G2 may overlap vertically in the first direction D1, with the horizontal layer HL interposed therebetween. The overlapping area between the first work function electrode G11 and the horizontal layer HL may be greater than the overlapping area between the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrode G13 may have an independent structure overlapping the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlap portion WLP and a channel non-overlap portion NOL, and the second work function electrode G12 and the third work function electrode G13 may be part of the channel overlap portion WLP. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may directly contact each other.

[0064] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a three-electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13 extending in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0065] like Figure 1C As shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a rhombus shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending along the third direction D3 through the channel overlap portion WLP and the channel non-overlap portion NOL may have a notched sidewall. From the perspective of the top view, the notched sidewall may be provided by a protruding portion of the channel overlap portion WLP and a recessed portion of the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, and the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may overlap vertically with the channel CH.

[0066] In the second direction D2, the first work function electrode G11 having a high work function can be disposed at the center of the second wire DWL, and the second work function electrode G2 and the third work function electrode G3 having a low work function can be disposed at both ends of the second wire DWL. In this way, leakage current problems such as gate induced drain leakage (GIDL) can be improved.

[0067] Since the first work function electrode G11 having a high work function is disposed at the center of the second wire DWL, the threshold voltage of the switching element TR can be increased. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field can be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second wire DWL.

[0068] As described above, the memory cell MC1 may include a second wire DWL having a three-work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap the channel CH, and the second work function electrode G12 may be disposed adjacent to the first wire BL and the first doping region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doping region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, thereby reducing leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, thereby improving leakage current. Due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR may be increased. In addition, the high electric field of the first work function electrode G11 may reduce the height of the memory cell MC1, which is advantageous in terms of integration.

[0069] Figure 2 is a schematic plan view showing a semiconductor device according to an embodiment of the present invention. Figure 3A It is shown Figure 2 A schematic three-dimensional diagram of a first memory cell array MCA1 is shown in FIG. Figure 3B is along Figure 2 A cross-sectional view taken along the line AA′ shown in FIG. Figure 3C is along Figure 2 A cross-sectional view taken along line BB' shown in FIG. Figure 3D is along Figure 2 A cross-sectional view taken along line CC' is shown.

[0070] Reference Figure 2 , Figure 3A , Figure 3B , Figure 3C and Figure 3D , the semiconductor device 100 may include a memory cell array MCA. The memory cell array MCA may include a plurality of memory cells MC. For the memory cells MC, reference may be made to Figures 1A to 1C Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP.

[0071] The memory cell array MCA may include a three-dimensional array of memory cells MC. The 3D array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may have a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may have a plurality of memory cells MC arranged laterally (e.g., horizontally) in a second direction D2 and a third direction D3. The memory cell array MCA may include a sub-memory cell array MCA1 arranged adjacent to each other in the second direction D2. The sub-memory cell array MCA1 may have a mirror-type structure in which two memory cells MC share a first conductive line BL. According to another embodiment of the present invention, the semiconductor device 100 may further include a sub-memory cell array of a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 in which memory cells MC are vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of sub-memory cell arrays MCA1 arranged horizontally in the third direction D3.

[0072] According to another embodiment of the present invention, in the memory cell array MCA, a plurality of sub-memory cell arrays MCA1 may be arranged along the second direction D2. For example, in the second direction D2, the data storage element CAP, the switch element TR, the first conductive line BL and the switch element TR may be alternately arranged in the order mentioned.

[0073] The inter-cell dielectric layer IL may be disposed between the memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include silicon oxide. The inter-cell dielectric layer IL may be referred to as a lateral (eg, horizontal) inter-cell dielectric layer. The hard mask layer HM may be disposed on the uppermost inter-cell dielectric layer IL.

[0074] The cell isolation layers ISOA and ISOB may be disposed between adjacent memory cells MC in the third direction D3. The cell isolation layers ISOA and ISOB may be referred to as vertical inter-cell dielectric layers. The cell isolation layers ISOA and ISOB may include silicon oxide, silicon oxycarbide (SiCO), silicon nitride, or a combination thereof. The cell isolation layers ISOA and ISOB may include a first cell isolation layer ISOA and a second cell isolation layer ISOB. The first cell isolation layer ISOA and the second cell isolation layer ISOB may extend vertically along the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may have a column structure extending vertically in the first direction D1. The first cell isolation layer ISOA and the second cell isolation layer ISOB may be alternately and repeatedly disposed along the second direction D2. The first cell isolation layer ISOA may be disposed between the data storage elements CAP along the third direction D3. The second cell isolation layer ISOB may be disposed between the first conductive lines BL along the third direction D3. The second conductive line DWL may be disposed between the first cell isolation layer ISOA and the second cell isolation layer ISOB along the second direction D2. Each of the first cell isolation layer ISOA and the second cell isolation layer ISOB may include a stack of a cell isolation liner layer ISOL and a cell isolation interstitial layer ISOG. The cell isolation liner layer ISOL may include silicon oxycarbide, and the cell isolation interstitial layer ISOG may include silicon oxycarbide.

[0075] The memory cell array MCA may be disposed on the lower structure LS.

[0076] The memory cell array MCA may include a plurality of second conductive lines DWL vertically stacked along a first direction D1. The memory cell array MCA may include a plurality of horizontal layers HL vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP vertically stacked along the first direction D1. The memory cell array MCA may include a plurality of first conductive lines BL spaced apart from each other in a third direction D3.

[0077] like Figure 1C As shown, each second conductor DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second conductor DWL extending along the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portion WLP and the channel non-overlap portion NOL are alternately repeated in the third direction D3, the second conductor DWL may have a notched sidewall.

[0078] A plurality of first passivation layers BF1 may be disposed between the bottommost second wire DWL among the second wires DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include silicon oxide. The first to third passivation layers BF1, BF2, and BF3 may electrically disconnect the first wire BL, the second wire DWL, and the data storage element CAP from the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The bottommost inter-cell dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0079] The first wire BL may extend vertically from the upper portion of the lower structure LS in the first direction D1. The horizontal layer HL may extend in a second direction D2 crossing the first direction D1. The second wire DWL may extend in a third direction D3 crossing the first direction D1 and the second direction D2.

[0080] From the perspective of the top view, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present invention, the side surface of the horizontal layer HL may have a curved shape or a circular shape. Figure 1B As shown, the horizontal layer HL may include a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP. Figure 3C , a horizontal-level spacer HLS may be formed over a side surface of the horizontal layer HL. The horizontal-level spacer HLS may include a dielectric material such as silicon oxide.

[0081] The first cover layer BC may be disposed between the second wire DWL and the first wire BL. The second cover layer CC may be disposed between the second wire DWL and the first electrode SN of the data storage element. The first cover layer BC may be disposed between the upper horizontal line G1 and the first wire BL, and the first cover layer BC may be disposed between the lower horizontal line G2 and the first wire BL. The second cover layer CC may be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC may be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC may include a pair of first cover layers BC and a pair of second cover layers CC.

[0082] The first cover layer BC and the second cover layer CC may include a dielectric material. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, an air gap or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride. According to another embodiment of the present invention, the first cover layer BC may include a stack of silicon oxide and silicon nitride.

[0083] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround an outer wall of the first conductive line BL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC may include doped polysilicon, and each of the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0084] The horizontal layers HL of the switching elements TR disposed transversely (e.g., horizontally) in the third direction D3 may share one second wire DWL. The horizontal layers HL of the switching elements TR disposed transversely (e.g., horizontally) in the third direction D3 may be coupled to different first wires BL. The switching elements TR stacked along the first direction D1 may share one first wire BL. The switching elements TR disposed transversely (e.g., horizontally) in the third direction D3 may share one second wire DWL.

[0085] The first cell isolation layer ISOA may be disposed between the first electrodes SN of the data storage element CAP along the third direction D3. The first electrodes SN may be isolated from each other by the first cell isolation layer ISOA. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0086] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, and other memory or peripheral circuit units.

[0087] For example, the lower structure LS may include a structure in which a peripheral circuit unit, a metal interconnection structure, and a bonding pad structure are sequentially stacked. The memory cell array MCA and the peripheral circuit unit of the lower structure LS may be coupled by wafer bonding.

[0088] The peripheral circuit unit of the lower structure LS may be arranged at a level lower than the memory cell array MCA. This may be referred to as a peripheral upper unit (COP) structure. The peripheral circuit unit may include at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit unit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit unit may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit unit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0089] For example, the peripheral circuit unit may include a sub word line driver and a sense amplifier. The second conductive line DWL may be coupled to the sub word line driver. The first conductive line BL may be coupled to the sense amplifier.

[0090] According to another embodiment of the present invention, the peripheral circuit unit may be arranged at a level higher than the memory cell array MCA. This may be referred to as a peripheral on cell (POC) structure. In this case, the lower structure LS may include a first semiconductor substrate, and the peripheral circuit unit may include a second semiconductor substrate.

[0091] According to another embodiment of the present invention, the memory cell array MCA may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND memory, a ferroelectric RAM (FeRAM), a spin transfer torque RAM (STTRAM), a phase change RAM (PCRAM or a resistive RAM (ReRAM).

[0092] According to another embodiment of the present invention, a single memory cell MC may be used Figure 1D substituted by the memory cell MC1 shown in FIG.

[0093] FIG. 4A to FIG. 26B An example of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0094] Figure 4A is a plan view of the fourth layer 14 level for describing a method of forming the stacked body SB and the sacrificial isolation openings 15A and 15B, and Figure 4B is along Figure 4A A cross-sectional view taken along line AA' is shown. Figure 4C is along Figure 4A A cross-sectional view taken along line BB' is shown.

[0095] Reference FIG. 4A to FIG. 4C, the stack SB may be formed on the lower structure 11. The lower structure 11 may be a material suitable for semiconductor processing. The lower structure 11 may include a conductive material, a dielectric material, a semiconductor material, or any combination thereof. Different materials may be formed on the lower structure 11. The lower structure 11 may include a semiconductor substrate. The lower structure 11 may be formed of a material containing silicon. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials, such as germanium. The lower structure 11 may include a III / V semiconductor substrate, such as a compound semiconductor substrate of, for example, GaAs. The lower structure 11 may include a silicon-on-insulator (SOI) substrate.

[0096] In the stack SB, a plurality of sub-stacks may be alternately stacked. Each sub-stack may include a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14 stacked in the order mentioned. The first layer 12A and the third layer 12B may be formed of the same material and may include silicon germanium or single crystal silicon germanium. The second layer 13 and the fourth layer 14 may be formed of the same material, and the second layer 13 and the fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 may be formed by an epitaxial growth process. The bottommost first layer 12A may be used as a seed layer during the epitaxial growth process. The first layer 12A may be thinner than the second layer 13, and the fourth layer 14 may be thicker than the second layer 13.

[0097] According to an embodiment of the present invention, the stack SB may include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, and a third stack SB3. The stack SB may include a first stack SB1, a fourth layer 14, a second stack SB2, a fourth layer 14, and a third stack SB3 stacked in the order mentioned. Each of the first stack SB1, the second stack SB2, and the third stack SB3 may include a three-layer stack of a first layer 12A / a second layer 13 / a third layer 12B. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first stack SB1, the second stack SB2, and the third stack SB3 may include a stack of a first silicon germanium / single crystal silicon / a second silicon germanium (SiGe / Si / SiGe). The third stack SB3 may also include a second layer 13 on top of the three-layer stack of the first layer 12A / a second layer 13 / a third layer 12B.

[0098] The second layer 13 may include a first single crystal silicon layer, and the fourth layer 14 may include a second single crystal silicon layer. The second single crystal silicon layer may be thicker than the first single crystal silicon layer. Therefore, in the stacked body SB, the first stack SB1 may be disposed below the second single crystal silicon layer, and the second stack SB2 may be disposed above the second single crystal silicon layer. Each of the first stack SB1 and the second stack SB2 may include a three-layer stack of a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer, and the second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0099] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as “sacrificial layers”, and the fourth layer 14 may be referred to as a recess target layer.

[0100] The stack SB may be referred to as a vertical stack. The stack SB may be formed by alternating a plurality of sacrificial layers and a recessed target layer. The sacrificial layer may include a first stack SB1, a second stack SB2, and a third stack SB3, and each of the first stack SB1, the second stack SB2, and the third stack SB3 may include a three-layer stack of a first layer 12A / a second layer 13 / a third layer 12B. The recessed target layer may include a fourth layer 14. Each sacrificial layer may include a first silicon germanium layer /

[0101] A first single crystal silicon layer / a second silicon germanium layer are stacked in three layers, and each recessed target layer may include a single layer of a second single crystal silicon layer.

[0102] The second single crystal silicon layer may be thicker than the first single crystal silicon layer.

[0103] As mentioned above Figures 2 to 3D As described, when the memory cells MC are vertically stacked, the first stack SB1 , the fourth layer 14 , the second stack SB2 , the fourth layer 14 , and the third stack SB3 may be alternately stacked several times.

[0104] Subsequently, a portion of the stack SB may be etched to form a plurality of sacrificial isolation openings 15A and 15B. The sacrificial isolation openings 15A and 15B may be initial openings for cell isolation, and the sacrificial isolation openings 15A and 15B may include a large opening 15A and a small opening 15B. The size of the large opening 15A may be greater than the size of the small opening 15B. From a top view, the large opening 15A and the small opening 15B may have a rectangular shape. According to another embodiment of the present invention, the large opening 15A and the small opening 15B may have a circular shape or an elliptical shape. According to another embodiment of the present invention, the sacrificial isolation openings 15A and 15B may be referred to as sacrificial isolation trenches. The large opening 15A and the small opening 15B may extend vertically along the first direction D1. The large opening 15A and the small opening 15B may be alternately arranged along the second direction D2. A plurality of large openings 15A may be arranged in the third direction D3. A plurality of small openings 15B may be arranged in the third direction D3. The large opening 15A and the small opening 15B may penetrate the stacked body SB in the first direction D1.

[0105] After forming the sacrificial isolation openings 15A and 15B, the portion of the lower structure 11 exposed under the sacrificial isolation openings 15A and 15B may be etched. As a result, the bottom surfaces of the sacrificial isolation openings 15A and 15B may extend into the lower structure 11. The bottom surfaces of the sacrificial isolation openings 15A and 15B may include a U-shaped profile. Due to the sacrificial isolation openings 15A and 15B, the fourth layer 14 may have a mesh pattern.

[0106] Figure 5A is a plan view of a fourth level 14 showing a method for forming sacrificial isolation layers 16A and 16B, Figure 5B is along Figure 5A A cross-sectional view taken along line BB' is shown.

[0107] Reference Figure 5A and Figure 5B , sacrificial isolation layers 16A and 16B filling the sacrificial isolation openings 15A and 15B may be formed. The sacrificial isolation layers 16A and 16B may include a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A may fill the large opening 15A, and the second sacrificial isolation layer 16B may fill the small opening 15B.

[0108] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. Forming the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include forming a sacrificial isolation material on the stack SB to fill the sacrificial isolation openings 15A and 15B, and flattening the sacrificial isolation material to expose the uppermost layer of the stack SB. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have different sizes or different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A may be greater than the size (or volume) of the second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may have the same length in the third direction D3 and different lengths in the second direction D2. The length of the first sacrificial isolation layer 16A in the second direction D2 may be greater than the length of the second sacrificial isolation layer 16B.

[0109] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in the second direction D2. A plurality of first sacrificial isolation layers 16A may be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may pass through the stack SB in the first direction D1.

[0110] The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include the same material. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be formed of a dielectric material. For example, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof.

[0111] Fig. 6A is a plan view of the fourth level 14 showing a method for forming sacrificial vertical openings V1' and V2', Figure 6B is along Fig. 6A A cross-sectional view taken along line AA' is shown.

[0112] Reference Fig. 6A and Figure 6B A hard mask layer pattern 17 may be formed over the stacked body SB, the first sacrificial isolation layer 16A, and the second sacrificial isolation layer 16B. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a mask layer. A plurality of hole-type openings may be defined in the hard mask layer pattern 17.

[0113] Subsequently, a portion of the stacked body SB may be etched by using the hard mask layer pattern 17 as an etching barrier. As a result, a plurality of sacrificial vertical openings V1' and V2' may be formed in the stacked body SB. The sacrificial vertical openings V1' and V2' may include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be hole-type openings. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may extend vertically along the first direction D1. The first sacrificial vertical opening V1' and the second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1' may be formed by etching the stacked body SB between the second sacrificial isolation layer 16B. The second sacrificial vertical opening V2' may be formed by etching the stacked body SB between the first sacrificial isolation layers 16A. The first sacrificial vertical opening V1' may be disposed between the second sacrificial isolation layers 16B along the third direction D3. The second sacrificial vertical opening V2' may be disposed between the first sacrificial isolation layers 16A along the third direction D3. From a top view, the cross-sections of the first sacrificial vertical opening V1 ′ and the second sacrificial vertical opening V2 ′ may be rectangular, circular, or elliptical.

[0114] Fig. 7A is a plan view showing a method for forming the preliminary horizontal layer 14A, Figure 7B is along Fig. 7A The cross-sectional view taken along the line AA' is shown. Figure 7C is along Fig. 7A A cross-sectional view taken along line BB' is shown.

[0115] Reference 7A to 7C , a portion of the hard mask layer pattern 17 may be trimmed (refer to reference numeral ' 17T').

[0116] Subsequently, the first layer 12A and the third layer 12B may be selectively removed through the first sacrificial vertical opening V1' and the second sacrificial vertical opening V2'. In order to selectively remove the first layer 12A and the third layer 12B, the difference between the etching selectivity of the second layer 13 and the fourth layer 14 and the etching selectivity of the first layer 12A and the third layer 12B may be utilized. The first layer 12A and the third layer 12B may be removed by a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 and the fourth layer 14 include a single crystal silicon layer, the silicon germanium layer may be etched using an etchant or etching gas that is selective to the single crystal silicon layer.

[0117] Subsequently, the second layer 13 and the fourth layer 14 may be recessed. In order to recess the second layer 13 and the fourth layer 14, a wet etching process or a dry etching process may be used. According to this embodiment of the present invention, the fourth layer 14 may be partially etched while removing the second layer 13. As a result, the second layer 13 may be removed, and the fourth layer 14 may be thinned (as shown in the reference numeral "14A"). The recess process for forming the thin fourth layer 14A (i.e., the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. In order to form the preliminary horizontal layer 14A, the upper surface, the lower surface, and the side surface of the fourth layer 14 may be recessed. The preliminary horizontal layer 14A may be referred to as a thin-body active layer. The preliminary horizontal layer 14A may extend in a lateral direction. In some embodiments, the lateral direction may be a horizontal direction, but the present invention is not limited thereto. The preliminary horizontal layer 14A may include a single crystal silicon layer. The recess process for forming the preliminary horizontal layer 14A may use, for example, hot SC-1 (Hot SC-1, HSC1). The HSC1 may include a solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) are mixed in a ratio of about 1:4:20. The second layer 13 and the fourth layer 14 may be selectively etched using the HSC1.

[0118] As described above, the preliminary horizontal layer 14A may be formed by a recessing process of the fourth layer 14, and a horizontal recess 18 (e.g., a horizontal recess) may be formed between the preliminary horizontal layers 14A. The preliminary horizontal recess 18 may extend laterally, for example, horizontally. Each of the upper and lower surfaces of the preliminary horizontal layer 14A may include a flat surface.

[0119] The preliminary horizontal layer 14A may have a cross shape from a top view perspective. A side surface of the preliminary horizontal layer 14A may have a curved shape or a rounded shape.

[0120] After forming the preliminary horizontal layer 14A, the first sacrificial vertical opening and the second sacrificial vertical opening may be expanded as shown in the reference numerals "V1" and "V2". The preliminary horizontal layer 14A may be spaced apart from each other by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 in the second direction D2. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged in the third direction D3.

[0121] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral '11A'). As a result, the depths of the first sacrificial vertical openings V1 ′ and the second sacrificial vertical openings V2 ′ may be increased.

[0122] The first sacrificial vertical openings V1 and the second sacrificial vertical openings V2 may be alternately disposed between the preliminary horizontal layers 14A along the second direction D2, the first sacrificial vertical openings V1 may be disposed between the second sacrificial isolation layers 16B along the third direction D3, and the second sacrificial vertical openings V2 may be disposed between the first sacrificial isolation layers 16A along the third direction D3.

[0123] Fig. 8A is a plan view showing a method for forming the first dielectric layer 19 and the second dielectric layer 20, Figure 8B is along Fig. 8A A cross-sectional view taken along line AA' is shown. Figure 8C is along Fig. 8A A cross-sectional view taken along line BB' is shown.

[0124] Reference FIG. 8A to FIG. 8C , a first dielectric layer 19 covering the preliminary horizontal layer 14A may be formed. The first dielectric layer 19 may include silicon nitride. The first dielectric layer 19 may completely cover the upper surface, the lower surface, and the side surface of the preliminary horizontal layer 14A.

[0125] While forming the first dielectric layer 19, a dummy dielectric layer 19D may be formed over the surface of the lower structure 11. Some of the first dielectric layer 19 may completely cover the upper, lower, and side surfaces of the hard mask layer pattern 17.

[0126] Subsequently, a second dielectric layer 20 may be formed on the first dielectric layer 19. The second dielectric layer 20 may fill between the first dielectric layers 19 disposed vertically adjacent to each other. The second dielectric layer 20 may include silicon oxide. Portions of the second dielectric layer 20 may be conformally formed on surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. Figure 7B and Figure 7C The horizontal recess 18 in the dielectric layer 14 may be filled with the first dielectric layer 19 and the second dielectric layer 20 .

[0127] Subsequently, a sacrificial column 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial column 21 may have a sacrificial material and may include amorphous carbon. According to another embodiment of the present invention, a column cover layer may also be formed on the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 21 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial column 21 may be performed until the uppermost first dielectric layer 19 is exposed. Subsequently, the uppermost second dielectric layer 20 may also be planarized until the uppermost first dielectric layer 19 is exposed. The sacrificial column 21 may not be formed between the vertically stacked first dielectric layers 19.

[0128] The second dielectric layer 20 and the sacrificial column 21 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening V1 and the second sacrificial column structure SV2. The first sacrificial column structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial column structure SV2 may fill the second sacrificial vertical opening V2. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From the perspective of the top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may have a rectangular cross-section. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be hole-type sacrificial columns. According to another embodiment of the present invention, a portion of the first dielectric layer 19 may be conformally formed on the surface of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2, so the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may also include a portion of the first dielectric layer 19.

[0129] Return to reference Figure 8C , the first dielectric layer 19 may be formed between the preliminary horizontal layers 14A, and the second dielectric layer 20 may be disposed inside the first dielectric layer 19. The first dielectric layer 19 may surround the second dielectric layer 20. The first dielectric layer 19 may include a first surrounding portion and a second surrounding portion. The first surrounding portion may surround the preliminary horizontal layer 14A in the AA' direction, and the second surrounding portion may surround the second dielectric layer 20 in the BB' direction.

[0130] As described above, a cell mold structure may be formed by forming a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. The cell mold structure may include a plurality of cell molds CM. Each cell mold CM may include a plurality of mold layers. The mold layer may refer to a preliminary horizontal layer 14A, a first dielectric layer 19, and a second dielectric layer 20. Each cell mold CM may include an oxide-nitride-silicon-nitride (ONSN) stack. Here, the ONSN stack may refer to a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are sequentially stacked. Silicon oxide may correspond to the second dielectric layer 20, and the first silicon nitride and the second silicon nitride may correspond to the first dielectric layer 19. The single crystal silicon layer may correspond to the preliminary horizontal layer 14A. A cell mold structure including a plurality of cell molds CM may be referred to as a vertical stack. On the other hand, the cell mold structure may include an oxide-nitride-silicon-nitride-oxide (ONSNO) stack. Here, the ONSNO stack may refer to a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are sequentially stacked.

[0131] As described above, the sub-stacks of the stack SB can be formed by FIG. 4A to FIG. 8C A series of processes are replaced by the unit mold CM. The first layer 12A, the second layer 13, and the third layer 12B can be replaced by the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 can be turned into a preliminary horizontal layer 14A through a recess process. The first dielectric layer 19 can be referred to as a trimming target layer.

[0132] Fig. 9A is a plan view showing a method for forming cell isolation openings 22A and 22B and a horizontal layer 14B, Fig. 9B is along Fig. 9A A cross-sectional view taken along line BB' is shown.

[0133] Reference Fig. 9A and Fig. 9B In order to form the cell isolation openings 22A and 22B, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be removed. When the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B are removed, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be covered by the mask layer. The side surfaces of the first dielectric layer 19 and the preliminary horizontal layer 14A may be exposed in the BB' direction through the cell isolation openings 22A and 22B.

[0134] Subsequently, the side surface of the preliminary horizontal layer 14A may be trimmed in the second direction D2 and the third direction D3 by the cell isolation openings 22A and 22B. As a result, a trimmed horizontal layer 14B may be formed. A horizontal level gap 14R may be formed on the side surface of the horizontal layer 14B. The horizontal level gap 14R and the horizontal layer 14B may be disposed between the first dielectric layer 19. The horizontal layer 14B may be referred to as a “trimmed horizontal layer pattern”. In some embodiments, the horizontal layer 14B may be a horizontal layer and may be referred to as a “trimmed horizontal layer pattern”.

[0135] When the horizontal layer 14B is formed, the surface of the lower structure 11 , for example, the bottom surface of the cell isolation openings 22A and 22B may be extended.

[0136] The horizontal layer 14B may be disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2 along the second direction D2. From a top view, the horizontal layer 14B may have a cross shape. The horizontal layer 14B may have a cross shape smaller in size than the preliminary horizontal layer 14A. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged, while the horizontal layer 14B may have a shape in which the cross shapes are separated separately in the third direction D3. A horizontal level gap 14R may be formed between the horizontal layers 14B disposed along the third direction D3. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be disposed between the horizontal layers 14B along the second direction D2.

[0137] Fig. 10A is a plan view showing a method for forming a horizontal-level spacer 23 and a first dielectric layer 19A, Fig. 10B is along Fig. 10A A cross-sectional view taken along line BB' is shown.

[0138] Reference Fig. 10A and Fig. 10B , the horizontal level spacer 23 may be formed on the side surface of the horizontal layer 14B. Forming the horizontal level spacer 23 may include forming a spacer material on the side surface of the horizontal layer 14B and etching the spacer material. The horizontal level spacer 23 may include a dielectric material, such as silicon oxide. The horizontal level spacer 23 may fill the horizontal level gap 14R. The horizontal layers 14B disposed in the third direction D3 may be separated from each other by the horizontal level spacer 23.

[0139] Subsequently, a portion of the first dielectric layer 19 may be laterally trimmed (e.g., horizontally trimmed) through the cell isolation openings 22A and 22B. After the trimming process, the first dielectric layer 19 may remain, as indicated by reference numeral 19A. Therefore, from the perspective of B-B', a pair of first dielectric layers 19A may be disposed between the horizontal layer 14B, and one second dielectric layer 20 may be disposed between the pair of first dielectric layers 19A.

[0140] Reference 9A to 10B The width of the first dielectric layer 19A in the third direction D3 between the cell isolation openings 22A and 22B may be greater than the width of the horizontal layer 14B. That is, the trimming depth of the first dielectric layer 19 in the third direction D3 may be less than the trimming depth of the preliminary horizontal layer 14A.

[0141] A pair of first dielectric layers 19A may vertically overlap one horizontal layer 14B. The trimmed first dielectric layer 19A may be referred to as a trimmed first dielectric layer.

[0142] As mentioned above, it is possible to 9A to 10B The first dielectric layer 19 and the preliminary horizontal layer 14A are horizontally trimmed by a series of processes. As a result, the unit mold may include the horizontal layer 14B, the first dielectric layer 19A, and the second dielectric layer 20.

[0143] Fig.11A is a plan view showing a method for forming cell isolation layers 24A and 24B, Fig. 11B is along Fig.11A A cross-sectional view taken along line BB' is shown. Fig.11A may be a plan view of a first dielectric layer 19A level illustrating a method for forming the cell isolation layers 24A and 24B.

[0144] Reference Fig.11A and Fig. 11B , cell isolation layers 24A and 24B filling the cell isolation openings 22A and 22B may be formed. The cell isolation layers 24A and 24B may include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B may include the same material. The first cell isolation layer 24A and the second cell isolation layer 24B may be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. From a top view, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide.

[0145] Forming the first cell isolation layer 24A and the second cell isolation layer 24B may include forming a cell isolation material filling the cell isolation openings 22A and 22B and planarizing the cell isolation material and the uppermost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first cell isolation layer 24A and the second cell isolation layer 24B may have different sizes or different volumes. The first cell isolation layer 24A and the second cell isolation layer 24B may include a dual structure of silicon oxide and silicon oxycarbide. For example, silicon oxycarbide may be deposited after silicon oxide is deposited. According to another embodiment of the present invention, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and the embedded air gap may be provided when silicon oxycarbide is deposited. The second sacrificial column structure SV2 may be disposed between the first cell isolation layer 24A in the third direction D3, and the first sacrificial column structure SV1 may be disposed between the second cell isolation layer 24B in the third direction D3. The first cell isolation layer 24A and the second cell isolation layer 24B may extend vertically in the first direction D1.

[0146] The first cell isolation layer 24A and the second cell isolation layer 24B may correspond to Figures 2 to 3D The cell isolation layers ISOA and ISOB are shown. Figure 3C and Figure 3D As shown, each of the first cell isolation layer 24A and the second cell isolation layer 24B may include a stack of a cell isolation liner layer ISOL and a cell isolation gap filling layer ISOG. The cell isolation liner layer ISOL may include silicon oxide, and the cell isolation gap filling layer ISOG may include silicon oxycarbide. According to another embodiment of the present invention, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and the embedded air gap may be provided when forming the cell isolation gap filling layer ISOG.

[0147] The first cell isolation layer 24A and the second cell isolation layer 24B may directly contact the first dielectric layer 19 A. A horizontal level spacer 23 may be disposed between the horizontal layer 14B and the first cell isolation layer 24A and the second cell isolation layer 24B.

[0148] Fig.12 is a plan view showing a method for forming a first dielectric layer pattern 19B, FIG. 13A to FIG. 13D is based on Fig.12 The illustrated line AA′ shows a cross-sectional view of a method for forming the first dielectric layer pattern 19B.

[0149] First, refer to Fig.13A , the hard mask layer pattern 17 and the uppermost first dielectric layer 19A may be removed to form a hard mask level recess 25 .

[0150] Reference Fig. 13B , a top dielectric layer 26 filling the hard mask level recess 25 may be formed. The top dielectric layer 26 may include silicon oxide.

[0151] Reference Fig. 13C The initial vertical opening 27 may be formed by removing the second sacrificial pillar structure SV2 . Subsequently, the second dielectric layer 20 may be laterally recessed, for example, horizontally recessed, so that the first dielectric layer 19A and the dummy dielectric layer 19D may be exposed through the initial vertical opening 27 .

[0152] Reference Fig.13D , the dummy dielectric layer 19D and the first dielectric layer 19A may be selectively recessed laterally (eg, horizontally recessed). As a result, the first dielectric layer pattern 19B and the dielectric level recess 28 may be formed. Portions of the horizontal layer 14B may be exposed through the dielectric level recess 28.

[0153] Fig.14A is a plan view showing a method for forming a vertical sacrificial structure 29, and Fig. 14B It is along Fig.14A A cross-sectional view taken along line AA' is shown.

[0154] Reference Fig.14A and Fig. 14B A vertical sacrificial structure 29 filling the dielectric level recess 28 and the initial vertical opening 27 may be formed. The vertical sacrificial structure 29 may include a sacrificial material. The vertical sacrificial structure 29 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0155] Fig.15A is a plan view showing a method for forming the vertical stage path 30, Fig. 15B is along Fig.15A A cross-sectional view taken along line AA' is shown.

[0156] Reference Fig.15A and Fig. 15B In order to form the vertical stage path 30 , the sacrificial pillar 21 of the first sacrificial pillar structure SV1 may be removed.

[0157] Subsequently, in order to form the lower level gap 19D′, the dummy dielectric layer 19D below the vertical level path 30 may be removed.

[0158] Fig.16A is a plan view showing a method for forming a first hole-type vertical opening 32, Fig. 16B is along Fig.16A A cross-sectional view taken along line AA' is shown.

[0159] Reference Fig.16A and Fig. 16B In order to form the first hole-type vertical opening 32 , the second dielectric layer 20 may be cut 31 through the vertical step path 30 .

[0160] Subsequently, a first passivation layer BF1 filling the lower gap 19D' may be formed. The first passivation layer BF1 may include silicon oxide. Forming the first passivation layer BF1 may include depositing silicon oxide filling the lower gap 19D' and etching the silicon oxide. Subsequently, a second passivation layer BF2 may be formed in the lower region of the first hole-type vertical opening 32. For example, the surface of the lower structure 11 may be oxidized to form the second passivation layer BF2.

[0161] Fig.17A is a plan view showing a method for forming a horizontal step recess 33, Fig. 17B is along Fig.17A A cross-sectional view taken along line AA' is shown. Fig. 17C is along Fig.17A The cross-sectional view is shown taken along line BB'. In some embodiments, the horizontal level recess 33 may be a lateral level recess.

[0162] Reference 17A to 17C , the first dielectric layer pattern 19B can be removed through the first hole-type vertical opening 32 to form a horizontal level recess 33. A portion of the horizontal layer 14B can be exposed by the horizontal level recess 33. Return Fig. 17C , the horizontal level recess 33 may be disposed between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal level recesses 33 may face each other with one horizontal layer 14B interposed therebetween.

[0163] Fig.18A is a plan view showing a method for forming a horizontal conductive line 35, Fig.18B is along Fig.18A A cross-sectional view taken along line AA' is shown. Fig.18C is along Fig.18A A cross-sectional view taken along line BB' is shown.

[0164] Reference 18A to 18C , an interlayer dielectric layer 34 may be formed on the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 may be referred to as a gate dielectric layer. The interlayer dielectric layer 34 may correspond to Figures 1A to 3B The interlayer dielectric layer GD is shown.

[0165] The interlayer dielectric layer 34 may be formed by oxidizing the surface of the horizontal layer 14B. According to another embodiment of the present invention, the interlayer dielectric layer 34 may be formed by a deposition process of silicon oxide. The interlayer dielectric layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON or a combination thereof.

[0166] Subsequently, a horizontal conductor 35 filling the horizontal level recess 33 may be formed on the interlayer dielectric layer 34. In some embodiments, the horizontal conductor 35 may extend laterally, for example, horizontally, and may be referred to as a horizontal conductor. Forming the horizontal conductor 35 may include depositing a conductive material filling the horizontal level recess 33 on the interlayer dielectric layer 34 and etching back the conductive material. The horizontal conductor 35 may include a pair of first horizontal conductors 35A and second horizontal conductors 35B facing each other, with the horizontal layer 14B interposed therebetween. The first horizontal conductor 35A and the second horizontal conductor 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductor 35A and the second horizontal conductor 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductor 35A and the second horizontal conductor 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductor 35A and the second horizontal conductor 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0167] The horizontal conductor 35 may correspond to Figures 1A to 1D The second wire DWL shown in FIG. 1A and the first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal wire G1 and the lower horizontal wire G2. Figures 1A to 1DAs shown, each of the first horizontal conductor 35A and the second horizontal conductor 35B may have a cross shape and may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The term "overlap" is used herein to indicate that two structures are positioned or stacked above or below each other and share a common space in the stacking direction. In addition, unless further specified, "overlap" as used herein may mean complete overlap or partial overlap. Complete overlap means that two structures completely cover each other or completely share the same space, and no part of any structure is separated from each other. Partial overlap means that only a portion of one structure or object overlaps with another structure or object.

[0168] Fig.19A is a plan view showing a method for forming a vertical conductive line 39, Fig.19B is along Fig.19A A cross-sectional view taken along line AA' is shown.

[0169] Reference Fig.19A and Fig.19B , a first capping layer 36 may be formed on one side of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, silicon oxycarbide, an embedded air gap, or a combination thereof. The capping material may be deposited and etched back to form the first capping layer 36. When or after forming the first capping layer 36, a portion of the interlayer dielectric layer 34 may be removed to expose a first edge portion of each horizontal layer 14B.

[0170] Subsequently, a vertical conductive line 39 coupled to a first edge portion of each horizontal layer 14B may be formed. The vertical conductive line 39 may fill the first hole-type vertical opening 32. The vertical conductive lines 39 may be commonly coupled to the horizontal layers 14B arranged along the first direction D1. The vertical conductive lines 39 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive lines 39 may be referred to as bit lines or vertical bit lines. The vertical conductive lines 39 adjacent to each other in the third direction D3 may be spaced apart from each other by the second cell isolation layer 24B.

[0171] Before forming the vertical conductive line 39, a first doped region 37 and a first contact node 38 may be formed. The first doped region 37 may be formed in a first edge portion of the horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment step, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doped region 37 may be formed by a doping process of impurities.

[0172] The first contact node 38 may include doped polysilicon. The first doping region 37 may include impurities diffused from the first contact node 38. An ohmic contact layer such as metal silicide may be formed between the vertical conductive line 39 and the first contact node 38.

[0173] The vertical conductors 39 may correspond to Figures 1A to 1D The first wire BL is shown.

[0174] Fig. 20A is a plan view showing a method for forming a preliminary second hole type vertical opening 29V, Fig. 20B is along Fig. 20A A cross-sectional view taken along line AA' is shown.

[0175] Reference Fig. 20A and Fig. 20B , a portion of the vertical sacrificial structure 29 may be removed to form a preliminary second hole type vertical opening 29V. The first side surface (i.e., the second edge portion) of the horizontal layer 14B may be exposed by the preliminary second hole type vertical opening 29V. After forming the preliminary second hole type vertical opening 29V, a preliminary second cover layer 29A may be formed on the upper and lower surfaces of the horizontal layer 14B.

[0176] When the preliminary second capping layer 29A is formed, a lowermost dielectric layer 29L may be formed over the side surface of the first passivation layer BF1 by removing a portion of the vertical sacrificial structure 29 .

[0177] Fig.21A is a plan view showing a method for forming a horizontal layer HL, Fig. 21B is along Fig.21A A cross-sectional view taken along line AA' is shown.

[0178] Reference Fig.21A and Fig. 21B , a third passivation layer BF3 may be formed on a surface of the lower structure 11. The third passivation layer BF3 may include silicon oxide.

[0179] Subsequently, the second edge portion of the horizontal layer 14B may be laterally (eg, horizontally) recessed in the second direction D2 (refer to reference numeral 14C). As a result, the horizontal layer may remain, as shown by reference numeral "HL".

[0180] After forming the horizontal layer HL, the preliminary second hole type vertical opening may be enlarged, as indicated by reference numeral 40. Hereinafter, the enlarged preliminary second hole type vertical opening may be simply referred to as the second hole type vertical opening 40.

[0181] Fig.22A is a plan view showing a method for forming the storage opening 41, Fig. 22B is along Fig.22AA cross-sectional view taken along line AA' is shown.

[0182] Reference Fig.22A and Fig. 22B In order to form the second capping layer 29C, the preliminary second capping layer 29A may be selectively recessed. The second capping layer 29C may include silicon oxide, silicon nitride, or a combination thereof.

[0183] After forming the second cover layer 29C, a storage opening 41 extending laterally (eg, horizontally) from the second hole-type vertical opening 40 may be formed. The storage opening 41 may be referred to as a capacitor opening.

[0184] The horizontal layer HL may include a first edge and a second edge. The first edge may refer to a portion coupled to the first contact node 38 and the vertical conductive line 39 , and the second edge may refer to a portion exposed by the storage opening 41 .

[0185] The storage opening 41 may be disposed between the second dielectric layers 20. The second cover layers 29C may be disposed on lower and upper portions of the horizontal layer HL, respectively.

[0186] As described above, forming the horizontal layer HL and the storage opening 41 may include forming the second hole-type vertical opening 40 , recessing the horizontal layer 14B, and forming the second cover layer 29C.

[0187] Fig.23A is a plan view showing a method for forming the second contact node 42, Fig. 23B is along Fig.23A A cross-sectional view taken along line AA' is shown.

[0188] Reference Fig.23A and Fig. 23B , the second doped regions 43 may be respectively formed in the second edges of the horizontal layer HL. Forming the second doped regions 43 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped regions 43 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the doped polysilicon may remain after the heat treatment.

[0189] Subsequently, a second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doping region 43 may include impurities diffused from the second contact node 42.

[0190] Each horizontal layer HL may include a first doping region 37, a second doping region 43, and a channel 44 that are laterally (eg, horizontally) disposed in the second direction D2. The channel 44 may be defined between the first doping region 37 and the second doping region 43. The channel 44 may vertically overlap the horizontal conductive line 35. Figures 1A to 1DAs shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0191] Fig.24A is a plan view showing a method for forming the first electrode 45, Fig. 24B is along Fig.24A A cross-sectional view taken along line AA' is shown.

[0192] Reference Fig.24A and 24B , the first electrode 45 of the data storage element may be formed on the second contact node 42. The first electrode 45 may have a horizontally oriented cylindrical shape. The first electrodes 45 may be respectively disposed in the storage openings 41. The first electrodes 45 disposed adjacent to each other in the second direction D2 may be spaced apart from each other by the second hole-type vertical opening 40. The first electrodes 45 disposed adjacent to each other in the third direction D3 may be spaced apart from each other by the first cell isolation layer 24A.

[0193] Fig.25A is a plan view showing a method of exposing the outer wall of the first electrode 45, Fig.25B It is along Fig.25A A cross-sectional view taken along line AA' is shown.

[0194] Reference Fig.25A and Fig.25B , the second dielectric layer 20 may be horizontally recessed (reference numeral '46'). As a result, the outer wall of the first electrode 45 may be exposed. The recessed second dielectric layer 20 may correspond to Figure 3B The inter-cell dielectric layer IL is shown.

[0195] Fig.26A is a plan view showing a method for forming the dielectric layer 47 and the second electrode 48, Fig.26B is along Fig.26A A cross-sectional view taken along line AA' is shown.

[0196] Reference Fig.26A and Fig.26B , a dielectric layer 47 and a second electrode 48 may be sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 may become a data storage element CAP.

[0197] Each first electrode 45 may include an inner space and a plurality of outer surfaces, and the inner space of the first electrode 45 may include a plurality of inner surfaces. The outer surface of the first electrode 45 may include a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode 45 may extend vertically in the first direction D1, and the horizontal outer surface of the first electrode 45 may extend horizontally in the second direction D2 or the third direction D3. The inner space of the first electrode 45 may be a three-dimensional space. The dielectric layer 47 may conformally cover the inner and outer surfaces of the first electrode 45 or may be located on the inner and outer surfaces of the first electrode 45. The second electrode 48 may be disposed in the inner space of the first electrode 45 on the dielectric layer 47. Some outer surfaces of the first electrode 45 may be electrically connected to the second doping region 43 of the horizontal layer HL.

[0198] The first electrode 45 may have a barrel shape. The barrel shape of the first electrode 45 may include a barrel inner surface and a barrel outer surface. Some outer surfaces of the barrel of the first electrode 45 may be electrically connected to the second doping region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 may be disposed on the inner surface of the barrel space of the first electrode 45. The second electrode 48 may extend vertically in the first direction D1.

[0199] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W) or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack or a combination thereof. The second electrode 48 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling an inner space of the first electrode 45, titanium nitride (TiN) may be used as a second electrode 48 of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0200] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 may include silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 47 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The dielectric layer 47 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0201] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first electrode 45 and the dielectric layer 47. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN) or a combination thereof. The interface control layer may also be formed between the second electrode 48 and the dielectric layer 47.

[0202] According to reference FIG. 4A to FIG. 26B , according to an embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a preliminary horizontal layer 14A on a lower structure 11, the preliminary horizontal layer 14A being vertically stacked in a first direction D1 and extending laterally (e.g., horizontally) in a second direction D2 intersecting the first direction D1; forming trimming target layers respectively surrounding the preliminary horizontal layer 14A; forming a horizontal layer 14B by trimming the preliminary horizontal layer 14A in a third direction D3 intersecting the second direction D2; forming a trimmed target layer by trimming the trimming target layer in the third direction D3; and replacing the trimmed target layer with a horizontal conductive line 35. The trimming target layer may correspond to FIG. 8A to FIG. 8C The first dielectric layer 19 is shown. The trimmed target layer may correspond to Fig. 10A and Fig. 10B The trimmed first dielectric layer 19A is shown.

[0203] According to the above-described embodiments of the present invention, since the cross-shaped horizontal layer HL is formed, the channel width and the bridge between the memory cells can be improved.

[0204] Furthermore, since an operation of forming a trimmed target layer 19A by trimming the trimming target layer 19 and an operation of replacing the trimmed target layer 19A with the horizontal conductive line 35 are included, bridging between the vertically stacked horizontal conductive lines 35 may be improved.

[0205] FIG. 27A to FIG. 38B is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 27A to FIG. 36B Another embodiment of a method for forming horizontal conductive lines 35 is shown.

[0206] As execution FIG. 4A to FIG. 7B As a result of the series of processes shown, a preliminary horizontal layer 14A and a horizontal recess 18 may be formed.

[0207] Fig.27A is a plan view showing a method for forming an interlayer dielectric layer 34 and a horizontal conductive layer 35C, Fig.27B It is along Fig.27A A cross-sectional view taken along line AA' is shown. Fig.27C is along Fig.27A A cross-sectional view taken along line BB' is shown.

[0208] Reference FIG. 27A to FIG. 27C , the interlayer dielectric layer 34 may be formed to completely cover the preliminary horizontal layer 14A or be located on the preliminary horizontal layer 14A. The interlayer dielectric layer 34 may be referred to as a gate dielectric layer. The interlayer dielectric layer 34 may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. The interlayer dielectric layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof.

[0209] The interlayer dielectric layer 34 may be formed by oxidizing the surface of the preliminary horizontal layer 14A. According to another embodiment of the present invention, the interlayer dielectric layer 34 may be formed by a silicon oxide deposition process.

[0210] While the interlayer dielectric layer 34 is formed, a dummy interlayer dielectric layer 34D may be formed over the surface of the lower structure 11. The interlayer dielectric layer 34 and the dummy interlayer dielectric layer 34D may be formed of the same material.

[0211] Subsequently, a horizontal conductive layer 35C may be formed on the interlayer dielectric layer 34. The horizontal conductive layer 35C may include a metal-based material, a semiconductor material, or a combination thereof. The horizontal conductive layer 35C may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the horizontal conductive layer 35C may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductive layer 35C may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more. While forming the horizontal conductive layer 35, a dummy horizontal conductive layer 35C' may be formed on the dummy interlayer dielectric layer 34D. The horizontal conductive layer 35C and the dummy horizontal conductive layer 35C' may be formed of the same material.

[0212] Subsequently, a second dielectric layer 20 may be formed on the horizontal conductive layer 35C. The second dielectric layer 20 may be filled between the horizontal conductive layers 35C disposed vertically adjacent to each other. The second dielectric layer 20 may include silicon oxide. A portion of the second dielectric layer 20 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontal recess ( Figure 7B and Figure 7C 18 ) in the embodiment may be filled with a horizontal conductive layer 35C and a second dielectric layer 20 .

[0213] Subsequently, a sacrificial column 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial column 21 may have a sacrificial material and may include amorphous carbon. According to another embodiment of the present invention, a column cover layer may also be formed on the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. Forming the sacrificial column 21 may include depositing a sacrificial material and planarizing the sacrificial material. A planarization operation for forming the sacrificial column 21 may be performed until the uppermost horizontal conductive layer 35C is exposed. Subsequently, the uppermost second dielectric layer 20 may also be planarized until the uppermost horizontal conductive layer 35C is exposed. The sacrificial column 21 may not be formed between the vertically stacked horizontal conductive layers 35C.

[0214] The second dielectric layer 20 and the sacrificial column 21 may form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 filling the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The first sacrificial column structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial column structure SV2 may fill the second sacrificial vertical opening V2. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present invention, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From the perspective of the top view, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be sacrificial columns.

[0215] Return to reference Fig.27C , a horizontal conductive layer 35C may be formed between the preliminary horizontal layers 14A, and the second dielectric layer 20 may be disposed inside the horizontal conductive layer 35C. The horizontal conductive layer 35C may surround the second dielectric layer 20. The horizontal conductive layer 35C may include a first surrounding portion and a second surrounding portion. The first surrounding portion may surround the preliminary horizontal layer 14A in the AA' direction, and the second surrounding portion may surround the second dielectric layer 20 in the BB' direction.

[0216] Through the above 4A to 7C and FIG. 27A to FIG. 27C The series of processes shown, the sub-stack of the stack SB can be replaced with a unit mold. The first layer 12A, the second layer 13 and the third layer 12B can be replaced with a horizontal conductive layer 35C and a second dielectric layer 20. The fourth layer 14 can be turned into a preliminary horizontal layer 14A through a recess process. The horizontal conductive layer 35C can be referred to as a trimming target layer.

[0217] Fig.28A is a plan view showing a method for forming cell isolation openings 22A and 22B and a horizontal layer 14B, Fig.28B is along Fig.28A A cross-sectional view taken along line BB' is shown.

[0218] Reference Fig.28A and Fig.28B , the cell isolation openings 22A and 22B may be formed by removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. While removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be covered by the mask layer. The side surfaces of the horizontal conductive layer 35C and the preliminary horizontal layer 14A may be exposed in the BB' direction through the cell isolation openings 22A and 22B.

[0219] Subsequently, the side surface of the preliminary horizontal layer 14A may be trimmed in the second direction D2 and the third direction D3 by the cell isolation openings 22A and 22B. As a result, a trimmed horizontal layer 14B may be formed. A horizontal level gap 14R may be formed on the side surface of the horizontal layer 14B. The horizontal level gap 14R and the horizontal layer 14B may be disposed between the interlayer dielectric layer 34. The horizontal layer 14B may be referred to as a "trimmed horizontal layer pattern".

[0220] When the horizontal layer 14B is formed, the surface of the lower structure 11 , for example, the bottom surface of the cell isolation openings 22A and 22B may be extended.

[0221] The horizontal layer 14B may be disposed between the first sacrificial column structure SV1 and the second sacrificial column structure SV2 along the second direction D2. From the perspective of the top view, the horizontal layer 14B may have a cross shape. The horizontal layer 14B may have a cross shape that is smaller in size than the preliminary horizontal layer 14A. The preliminary horizontal layer 14A may have a shape in which a plurality of cross shapes are merged, while the horizontal layer 14B may have a shape in which the cross shapes are separated separately in the third direction D3. A horizontal level gap 14R may be formed between the horizontal layers 14B disposed along the third direction D3. The first sacrificial column structure SV1 and the second sacrificial column structure SV2 may be disposed between the horizontal layers 14B along the second direction D2.

[0222] Fig.29A is a plan view showing the formation of a horizontal level spacer 23 and a recessed horizontal conductive layer, Fig.29B is along Fig.29A A cross-sectional view taken along line BB' is shown.

[0223] Reference Fig.29A and Fig.29B , a horizontal level spacer 23 may be formed on the side surface of the horizontal layer 14B. Forming the horizontal level spacer 23 may include forming a spacer material on the side surface of the horizontal layer 14B and etching the spacer material. The horizontal level spacer 23 may include a dielectric material, such as silicon oxide. The horizontal level spacer 23 may fill the horizontal level gap 14R. The horizontal layers 14B disposed in the third direction D3 may be separated from each other by the horizontal level spacer 23.

[0224] Subsequently, a portion of the horizontal conductive layer 35C may be trimmed laterally (eg, horizontally) through the cell isolation openings 22A and 22B. Thus, from the perspective of BB', a pair of horizontal conductive layers 35C may be disposed between the horizontal layers 14B, and a second dielectric layer 20 may be disposed between the pair of horizontal conductive layers 35C.

[0225] according to FIG. 28A to FIG. 29BThe width of the horizontal conductive layer 35C between the cell isolation openings 22A and 22B in the third direction D3 may be greater than the width of the horizontal layer 14B. That is, the trimming depth of the horizontal conductive layer 35C in the third direction D3 may be less than the trimming depth of the preliminary horizontal layer 14A.

[0226] A pair of horizontal conductive layers 35C may vertically overlap one horizontal layer 14B. The trimmed horizontal conductive layers 35C may be referred to as trimmed horizontal conductive layers.

[0227] Fig. 30A is a plan view showing a method for forming cell isolation layers 24A and 24B, Fig. 30B is along Fig. 30A A cross-sectional view taken along line BB' is shown. Fig. 30A It may be a plan view of a horizontal conductive layer 35C level illustrating a method for forming the cell isolation layers 24A and 24B.

[0228] Reference Fig. 30A and Fig. 30B , cell isolation layers 24A and 24B filling the cell isolation openings 22A and 22B may be formed. The cell isolation layers 24A and 24B may include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B may include the same material. The first cell isolation layer 24A and the second cell isolation layer 24B may be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxide, silicon nitride, silicon oxycarbide, silicon carbonitride, or a combination thereof. From the perspective of the top view, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B may include silicon oxycarbide.

[0229] Forming the first cell isolation layer 24A and the second cell isolation layer 24B may include forming a cell isolation material filling the cell isolation openings 22A and 22B and planarizing the cell isolation material and the uppermost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first cell isolation layer 24A and the second cell isolation layer 24B may have different sizes or different volumes. The first cell isolation layer 24A and the second cell isolation layer 24B may include a dual structure of silicon oxide and silicon oxycarbide. For example, silicon oxycarbide may be deposited after silicon oxide is deposited. According to another embodiment of the present invention, the first cell isolation layer 24A and the second cell isolation layer 24B may include an embedded air gap, and the embedded air gap may be provided when silicon oxycarbide is deposited. The second sacrificial column structure SV2 may be disposed between the first cell isolation layer 24A along the third direction D3, and the first sacrificial column structure SV1 may be disposed between the second cell isolation layer 24B along the third direction D3. The first cell isolation layer 24A and the second cell isolation layer 24B may extend vertically in the first direction D1.

[0230] The first cell isolation layer 24A and the second cell isolation layer 24B may correspond to Figures 2 to 3B The cell isolation layers ISOA and ISOB are shown.

[0231] The first and second cell isolation layers 24A and 24B and the horizontal conductive layer 35C may directly contact each other. A horizontal level spacer 23 may be disposed between the horizontal layer 14B and the first and second cell isolation layers 24A and 24B.

[0232] Fig.31 is a plan view showing a method for forming a first hole-type vertical opening 32, FIG. 32A to FIG. 32C is along Fig.31 A cross-sectional view taken along line AA' is shown.

[0233] First, refer to Fig.32A , the hard mask layer pattern 17 and the uppermost horizontal conductive layer 35C may be removed to form a hard mask level recess 25 .

[0234] Reference Fig.32B , a top dielectric layer 26 filling the hard mask level recess 25 may be formed. The top dielectric layer 26 may include silicon oxide.

[0235] Reference Fig.32C In order to form the first hole-type vertical opening 32, the sacrificial column 21 of the first sacrificial column structure SV1 can be removed. Subsequently, the second dielectric layer 20 on the bottom surface of the first hole-type vertical opening 32 can be etched to expose the dummy horizontal conductive layer 35C'. Subsequently, the dummy horizontal conductive layer 35C' can be replaced with the lower passivation layer 35P. Forming the lower passivation layer 35P may include forming a lower-level gap by removing the dummy horizontal conductive layer 35C' and filling the lower-level gap with the lower passivation layer 35P. The lower passivation layer 35P may include silicon oxide. The dummy interlayer dielectric layer 34D may remain between the lower passivation layer 35P and the lower structure 11.

[0236] Subsequently, the second dielectric layer 20 may be horizontally cut through the first hole-type vertical opening 32 .

[0237] Subsequently, the first side surface of the horizontal conductive layer 35C may be selectively recessed from the first hole-type vertical opening 32. A portion of the interlayer dielectric layer 34 may be exposed by the recessed portion of the horizontal conductive layer 35C.

[0238] The recessing process of the horizontal conductive layer 35C may be referred to as a first-side recessing process of the horizontal conductive layer 35C.

[0239] Fig.33A is a plan view showing a method for forming the first cover layer 36, Fig.33B is along Fig.33A A cross-sectional view taken along line AA' is shown. Fig.33A It may be a plan view of a horizontal conductive layer 35C level illustrating a method for forming the first capping layer 36 .

[0240] Reference Fig.33A and Fig.33B The first capping layer 36 may be formed on the recessed side surface of the horizontal conductive layer 35C. The first capping layer 36 may include silicon oxide, silicon nitride, silicon oxycarbide, an embedded air gap, or a combination thereof. The capping material may be deposited and etched back to form the first capping layer 36.

[0241] A portion of the interlayer dielectric layer 34 may be cut while forming the first capping layer 36. As a result, a first edge portion of each horizontal layer 14B may be exposed.

[0242] While the first cover layer 36 is being formed or after the first cover layer 36 is formed, the first hole-type vertical opening 32 may be enlarged.

[0243] Fig.34A is a plan view showing a method for forming a vertical conductive line 39, Fig.34B is along Fig.34A A cross-sectional view taken along line AA' is shown. Fig.34A It may be a plan view of a horizontal conductive layer 35C level illustrating a method for forming vertical conductive lines 39 .

[0244] Reference Fig.34A and Fig.34B , a vertical wire 39 coupled to a first edge portion of each horizontal layer 14B may be formed. The vertical wire 39 may fill the first hole-type vertical opening 32. The vertical wire 39 may be commonly coupled to the horizontal layers 14B arranged along the first direction D1. The vertical wire 39 may include titanium nitride, tungsten, or a combination thereof. The vertical wire 39 may be referred to as a bit line or a vertical bit line.

[0245] Before forming the vertical conductive line 39, a first doped region 37 and a first contact node 38 may be formed. The first doped region 37 may be formed in a first edge portion of the horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the first doped region 37 may be formed by a doping process of impurities.

[0246] The first contact node 38 may include doped polysilicon. The first doping region 37 may include impurities diffused from the first contact node 38.

[0247] The vertical conductors 39 may correspond to Figures 1A to 1D The first wire BL is shown.

[0248] Fig.35A is a plan view showing a method for forming a preliminary second hole type vertical opening 29V, Fig.35B is along Fig.35A A cross-sectional view taken along line AA' is shown. Fig.35A It may be a plan view of the horizontal conductive layer 35C level showing a method for forming the preliminary second hole type vertical opening 29V.

[0249] Reference Fig.35A and Fig.35B In order to form the preliminary second hole type vertical opening 29V, a portion of the second sacrificial pillar structure SV2 may be removed. The first side surface of the horizontal conductive layer 35C may be exposed through the preliminary second hole type vertical opening 29V, and the second dielectric layer 20 may be cut.

[0250] Fig.36A is a plan view showing a method for forming a horizontal conductive line 35, Fig.36B is along Fig.36A A cross-sectional view taken along line AA' is shown.

[0251] Reference Fig.36A and Fig.36B The second side surface of the horizontal conductive layer 35C may be selectively recessed by the preliminary second hole-type vertical opening 29V. As a result, the horizontal conductive line 35 may be formed.

[0252] The horizontal conductor 35 may include a pair of first horizontal conductors 35A and second horizontal conductors 35B facing each other, with the horizontal layer 14B located therebetween. The first horizontal conductor 35A and the second horizontal conductor 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal conductor 35A and the second horizontal conductor 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal conductor 35A and the second horizontal conductor 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductor 35A and the second horizontal conductor 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, and the P-type work function material may have a high work function of about 4.5 eV or more.

[0253] The horizontal conductor 35 may correspond to Figures 1A to 1D The second wire DWL shown in FIG. 1A and the first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal wire G1 and the lower horizontal wire G2. Figures 1A to 1D, each of the first horizontal conductive line 35A and the second horizontal conductive line 35B may have a cross shape, and each of the first horizontal conductive line 35A and the second horizontal conductive line 35B may include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0254] As described above with reference to a series of processes, forming the horizontal conductive line 35 may include forming an interlayer dielectric layer 34 covering the surface of the preliminary horizontal layer 14B, forming a horizontal conductive layer 35C surrounding the preliminary horizontal layer 14B on the interlayer dielectric layer 34, and performing a first side recess process and a second side recess process on the horizontal conductive layer 35C. Fig.31 and Fig.32C The "E1" in FIG. 1 may be defined by a first side recess process, and the second edge portion of the horizontal conductive line 35 (see Fig.36A and Fig.36B "E2" in the figure can be defined by a second side recess process.

[0255] Since the horizontal conductive line 35 is formed using the first side recess process and the second side recess process, the gate oxide strength (GOI) characteristics of the interlayer dielectric layer 34 can be improved. The thickness of the interlayer dielectric layer 34 can be kept uniform.

[0256] According to another embodiment of the present invention, the first horizontal conductive line 35A and the second horizontal conductive line 35B of the horizontal conductive line 35 may have a triple work function electrode structure. Therefore, gate induced drain leakage (GIDL) may be improved.

[0257] After forming the horizontal conductive line 35 , the preliminary second hole type vertical opening may be enlarged, as shown by reference numeral “ 40 .” Hereinafter, the expanded preliminary second hole type vertical opening may be referred to as the second hole type vertical opening 40 .

[0258] Fig.37A is a plan view showing a method for forming the storage opening 41, Fig.37B is along Fig.37A A cross-sectional view taken along line AA' is shown.

[0259] Reference Fig.37A and Fig.37B To form the second capping layer 29C, a capping material may be deposited and etched. The second capping layer 29C may include silicon oxide, silicon nitride, or a combination thereof.

[0260] After forming the second capping layer 29C, the interlayer dielectric layer 34 may be recessed laterally (eg, horizontally) in the second direction D2. Subsequently, the second edge portion of the horizontal layer 14B may be recessed horizontally in the second direction D2. As a result, the horizontal layer may remain, as indicated by reference symbol "HL".

[0261] The horizontal layer HL may include a first edge and a second edge. The first edge may refer to a portion coupled to the first contact node 38 and the vertical conductive line 39 , and the second edge may refer to a portion exposed by the storage opening 41 .

[0262] The storage opening 41 may be disposed between the second dielectric layers 20. The second cover layers 29C may be disposed on lower and upper portions of the horizontal layer HL, respectively.

[0263] As described above, when the second cover layer 29C and the horizontal layer HL are formed, a storage opening 41 extending laterally (eg, horizontally) from the second hole-type vertical opening 40 may be formed. The storage opening 41 may be referred to as a capacitor opening.

[0264] Fig.38A is a plan view showing a method for forming a second contact node 38 and a data storage element CAP, Fig.38B is along Fig.38A For a detailed description of the method of forming the second contact node 38 and the data storage element CAP, reference may be made to FIG. 23A to FIG. 26B .

[0265] Reference Fig.38A and Fig.38B , the second doped region 43 may be formed in the second edge of the horizontal layer HL. Forming the second doped region 43 may include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped region 43 may include impurities diffused from the doped polysilicon. According to another embodiment of the present invention, the doped polysilicon may remain after the heat treatment.

[0266] Subsequently, a second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doping region 43 may include impurities diffused from the second contact node 42.

[0267] The horizontal layer HL may include a first doping region 37, a second doping region 43, and a channel 44 disposed laterally (eg, horizontally) in the second direction D2. The channel 44 may be defined between the first doping region 37 and the second doping region 43. The channel 44 may vertically overlap the horizontal conductive line 35. Figures 1A to 1C As shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0268] Subsequently, a first electrode 45 of a data storage element may be formed over the second contact node 42. The first electrode 45 may have a horizontally oriented cylindrical shape.

[0269] Then, refer to Fig.25A and Fig.25B, the second dielectric layer 20 may be laterally (eg, horizontally) recessed (refer to reference numeral 46 ). As a result, the outer surface of the first electrode 45 may be exposed.

[0270] Subsequently, a dielectric layer 47 and a second electrode 48 may be sequentially formed over the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 may become the data storage element CAP.

[0271] According to reference FIG. 27A to FIG. 38B According to another embodiment of the present invention, a method for manufacturing a semiconductor device may include: forming a preliminary horizontal layer 14A, which is vertically stacked on the lower structure 11 in a first direction D1 and extends laterally (e.g., horizontally) in a second direction D2 intersecting the first direction D1; forming a conductive target layer disposed in the upper and lower portions of each preliminary horizontal layer 14A; forming a horizontal layer 14B by trimming the preliminary horizontal layer 14A in a third direction D3 intersecting the second direction D2; forming a trimmed conductive target layer by trimming the conductive target layer in the third direction D3; and forming a pair of horizontal conductive wires 35 disposed in the upper and lower surfaces of the horizontal layer 14B by horizontally recessing edge portions of both sides of each trimmed conductive target layer in the second direction D2. The conductive target layer may correspond to FIG. 27A to FIG. 27C The horizontal conductive layer 35C shown. The trimmed conductive target layer may correspond to Fig.29A and Fig.29B The trimmed horizontal conductive layer 35C is shown.

[0272] FIG. 39A to FIG. 39C is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0273] Reference Fig.39A The stacked body SB10 may be formed on the lower structure 11. The stacked body SB10 may include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, in the alternating stack, a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' may be alternately stacked by an epitaxial growth process. The silicon germanium layer 12 may be a sacrificial layer, and the single crystal silicon layer 14' may be a recessed target layer. The silicon germanium layer 12 may correspond to Figure 4B The first layer 12A or the third layer 12B, and the single crystal silicon layer 14 'may correspond to Figure 4B The fourth layer 14. Figure 4B Different from the stacked body SB of FIG. 1 , the stacked body SB10 may be formed by alternately stacking silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0274] Then, execute FIG. 4A to FIG. 5BFor example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B may be formed in the stacked body SB10.

[0275] Then, refer to Fig.39B , a hard mask layer pattern 17 may be formed over the stacked body SB10.

[0276] Subsequently, the stacked body SB may be etched by using the hard mask layer pattern 17 as an etch barrier. As a result, a plurality of first sacrificial vertical openings V1 ′ and second sacrificial vertical openings V2 ′ may be formed in the stacked body SB10 .

[0277] Reference Fig.39C , a preliminary horizontal layer 14A' and a horizontal depression 18 can be formed. The preliminary horizontal layer 14A' and the horizontal depression 18 can be formed by Fig.39B The recess process of the silicon germanium layer 12 and the single crystal silicon layer 14' is formed. After removing the silicon germanium layer 12, the recess process of the single crystal silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to Figure 7B A preliminary horizontal layer 14A.

[0278] In order to recess the silicon germanium layer 12, a wet etching process or a dry etching process may be used. The silicon germanium layer 12 may be etched by using an etchant or an etching gas having selectivity with respect to the single crystal silicon layer 14'.

[0279] The recessing process of the single crystal silicon layer 14' for forming the preliminary horizontal layer 14A' may use, for example, HSC1 (Hot SC-1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) mixed in a ratio of about 1:4:20. The single crystal silicon layer 14' may be selectively etched by using HSC1.

[0280] After forming the preliminary horizontal layer 14A', the first sacrificial vertical opening and the second sacrificial vertical opening may be enlarged, as shown in the reference numerals "V1" and "V2". The preliminary horizontal layer 14A' may be spaced apart from each other in the second direction D2 by the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A' may have a shape in which a plurality of cross shapes are merged in the third direction D3. When forming the preliminary horizontal layer 14A', the surface of the lower structure 11 may be recessed to a predetermined depth (see reference numeral "11A"). As a result, the depths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be increased.

[0281] Then, you can execute FIG. 8A to FIG. 26B A series of processes shown.

[0282] According to an embodiment of the present invention, bridging between vertically adjacent horizontal conductive lines can be prevented when forming a 3D memory cell.

[0283] According to the embodiments of the present invention, the yield of 3D memory cells can be improved.

[0284] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming preliminary horizontal layers, the preliminary horizontal layers being vertically stacked on a lower structure in a first direction, each preliminary horizontal layer extending in a second direction intersecting the first direction; forming a trimming target layer around each of the preliminary horizontal layers; forming a horizontal layer by trimming the preliminary horizontal layer in a third direction intersecting the second direction; forming a trimmed target layer by trimming the trimming target layer in the third direction; as well as The trimmed target layer is replaced with a conductive layer.

2. The method according to claim 1, further comprising: After forming the horizontal layer, Spacers are formed on side surfaces of the horizontal layer.

3. The method according to claim 1, wherein: A trimming depth of the preliminary horizontal layer is greater than a trimming depth of the trimming target layer.

4. The method according to claim 3, wherein: The trimming target layer includes a dielectric material.

5. The method according to claim 1, wherein: Replacing the trimmed target layer with the conductive layer comprises: forming a horizontal level recess by removing the trimmed target layer, the horizontal level recess exposing a portion of the horizontal layer; forming an interlayer dielectric layer over the exposed portion of the horizontal layer; and A conductive material filling the horizontal level recess is formed over the interlayer dielectric layer.

6. The method according to claim 1, wherein: Forming the preliminary horizontal layer comprises: forming a stack by alternately stacking a plurality of sacrificial layers and a plurality of recessed target layers on the lower structure; forming sacrificial vertical openings spaced apart from each other in the second direction by etching the stack; removing the sacrificial layer from the sacrificial vertical opening; and The recess target layer is recessed from the sacrificial vertical opening to form the preliminary horizontal layer.

7. The method according to claim 6, wherein: The sacrificial layer includes a silicon germanium layer, and The recessed target layer includes a single crystal silicon layer.

8. The method according to claim 6, wherein: The sacrificial layer includes a stack of a silicon germanium layer and a first single crystal silicon layer, and Wherein, the recessed target layer comprises a second single crystal silicon layer, and The second single crystal silicon layer is formed to be thicker than the first single crystal silicon layer.

9. The method according to claim 1, further comprising: After forming the trimming target layer, An inter-cell dielectric layer is formed around the trimming target layer.

10. A method for manufacturing a semiconductor device, the method comprising: forming a preliminary horizontal layer vertically stacked on a lower structure in a first direction and horizontally extending in a second direction intersecting the first direction; forming a conductive target layer disposed in an upper portion and a lower portion of each of the preliminary horizontal layers; forming a horizontal layer by trimming the preliminary horizontal layer in a third direction intersecting the second direction; forming a trimmed conductive target layer by trimming the conductive target layer in the third direction; as well as A pair of horizontal conductive lines respectively disposed on the upper and lower surfaces of the horizontal layer are formed by horizontally recessing edge portions of both sides of the trimmed conductive target layer in the second direction.

11. The method according to claim 10, further comprising: After forming the horizontal layer, Spacers are formed on side surfaces of the horizontal layer.

12. The method according to claim 10, wherein: The trimming depth of the preliminary horizontal layer is greater than the trimming depth of the conductive target layer.

13. The method according to claim 10, wherein: The conductive target layer includes polysilicon, a metal-based material, a work function material or a combination thereof.

14. The method according to claim 10, further comprising: Before forming the conductive target layer, An interlayer dielectric layer is formed in an upper portion and a lower portion of each of the preliminary horizontal layers.

15. The method according to claim 10, wherein: Forming the preliminary horizontal layer comprises: forming a stack by alternately stacking a plurality of sacrificial layers and a plurality of recessed target layers on the lower structure; forming sacrificial vertical openings spaced apart from each other in the second direction by etching the stack; removing the sacrificial layer from the sacrificial vertical opening; and The recess target layer is recessed from the sacrificial vertical opening to form the preliminary horizontal layer.

16. The method according to claim 15, wherein: The sacrificial layer includes a silicon germanium layer, and The recessed target layer includes a single crystal silicon layer.

17. The method according to claim 15, wherein: The sacrificial layer includes a stack of a silicon germanium layer and a first single crystal silicon layer, and Wherein, the recessed target layer comprises a second single crystal silicon layer, and The second single crystal silicon layer is formed to be thicker than the first single crystal silicon layer.

18. The method according to claim 10, wherein: In the step of forming the conductive target layer provided in the upper portion and the lower portion of each of the preliminary horizontal layers, The conductive target layer surrounds the preliminary horizontal layer in the second direction.

19. The method according to claim 10, wherein: Forming the preliminary horizontal layer comprises: forming a stack by alternately stacking a plurality of sacrificial layers and a plurality of recessed target layers on the lower structure; forming sacrificial isolation layers spaced apart from each other in the third direction by etching the stack; forming sacrificial vertical openings spaced apart from each other in the second direction by etching the stack; removing the sacrificial layer from the sacrificial vertical opening; recessing the recess target layer from the sacrificial vertical opening to form the preliminary horizontal layer; and Cell isolation openings spaced apart from each other in the third direction are formed by removing the sacrificial isolation layer to expose a desired trimming portion of the conductive target layer.

20. The method according to claim 10, further comprising: After forming the horizontal conductive line, forming vertical conductive lines commonly coupled to a first edge of the horizontal layer; as well as A data storage element is formed coupled to each second edge of the horizontal layer.

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