Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the semiconductor device are provided. A semiconductor device includes: a lower structure; a plurality of horizontal conductive layers oriented in a direction parallel to a surface of the lower structure; a plurality of storage capacitors commonly coupled to a first side end of the horizontal conductive layer, where each of the plurality of storage capacitors is vertically stacked over the lower structure and includes a cylindrical storage node; and a vertical conductive line commonly coupled to a second side end of the horizontal conductive layer opposite the first side end, extending in a direction perpendicular or substantially perpendicular to a surface of the lower structure, and including a plurality of electrode portions, each electrode portion being symmetrical to a cylindrical storage node of a corresponding storage capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0105588, filed on August 11, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention generally relate to a semiconductor device, and more particularly, to a semiconductor device having a three-dimensional structure and a method for manufacturing the semiconductor device. Background Art

[0004] The size of memory cells is constantly decreasing to increase the net die of memory devices. As the size of memory cells is miniaturized, it is necessary to reduce the parasitic capacitance Cb and increase the capacitance. However, due to the structural limitations of memory cells, it is difficult to increase the net die.

[0005] Recently, three-dimensional semiconductor memory devices have been proposed in which memory cells are stacked in a three-dimensional array. Extensive research efforts are currently underway to develop three-dimensional semiconductor devices that are smaller, higher capacity, and exhibit improved performance characteristics. Summary of the invention

[0006] Embodiments of the present invention relate to a highly integrated three-dimensional semiconductor device (hereinafter referred to as a semiconductor device) and a method for manufacturing the same.

[0007] According to an embodiment of the present invention, a semiconductor device includes: a lower structure; a plurality of horizontal conductive layers oriented in a direction parallel to the surface of the lower structure; a plurality of storage capacitors commonly coupled to a first side end of the horizontal conductive layers, wherein each of the plurality of storage capacitors is vertically stacked on the lower structure and includes a tubular storage node; and a vertical conductive line, which: is commonly coupled to a second side end of the horizontal conductive layer opposite to the first side end, extends in a direction perpendicular or substantially perpendicular to the surface of the lower structure, and includes a plurality of electrode portions, each electrode portion being symmetrical with the tubular storage node of the corresponding storage capacitor.

[0008] According to another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a plurality of horizontal conductive layers, the plurality of horizontal conductive layers being oriented in a direction parallel to a surface of a lower structure; forming a plurality of tubular storage nodes and a plurality of electrode portions, the plurality of tubular storage nodes and the plurality of electrode portions being coupled to both ends of the horizontal conductive layers and being bilaterally symmetrical; forming a dielectric layer and a sacrificial layer, the dielectric layer and the sacrificial layer being suitable for covering the tubular storage nodes and the electrode portions; exposing the electrode portions by removing the sacrificial layer; and forming a storage capacitor by forming a plate node and a conductive layer on the dielectric layer and the electrode portions, respectively, the storage capacitor being stacked on the lower structure and extending in a direction perpendicular or substantially perpendicular to the surface of the lower structure.

[0009] According to another embodiment of the present invention, a semiconductor device includes: a lower structure; a first array including first vertically stacked capacitors arranged on the lower structure; and a second array, which is horizontally spaced apart from the first array and includes second vertically stacked capacitors and shared parts commonly connected to the second vertically stacked capacitors; wherein, of the shared part of the second array, a horizontal part is connected to each second vertically stacked capacitor; a barrel part, which includes an inner surface, an upper outer surface, a lower outer surface connected to the horizontal part, and a vertical outer surface located between the upper outer surface and the lower outer surface; an inner part, which is arranged on the inner surface of the barrel part; and an outer part, which is arranged on the upper outer surface and the lower outer part of the barrel part.

[0010] According to another embodiment of the present invention, a semiconductor device includes: a first peripheral circuit, which includes a plurality of control circuits; a memory cell array, which includes vertically stacked memory cells arranged on the first peripheral circuit; and a second peripheral circuit, which is horizontally spaced apart from the memory cell array and includes a second vertically stacked capacitor and a shared portion commonly connected to the vertically stacked capacitor; wherein, of the shared portion of the second peripheral circuit, a horizontal portion is connected to each vertically stacked capacitor; a barrel portion, which includes an inner surface, an upper outer surface, a lower outer surface connected to the horizontal portion, and a vertical outer surface located between the upper outer surface and the lower outer surface; an inner portion, which is arranged on the inner surface of the barrel portion; and an outer portion, which is arranged on the upper outer surface and the lower outer portion of the barrel portion.

[0011] These and other features and advantages of the present invention will be better understood by those skilled in the art from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic block diagram showing a semiconductor device according to an embodiment of the present invention.

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line BB' is shown.

[0014] Figure 3 and Figure 4 Semiconductor devices according to other embodiments of the present invention are shown.

[0015] Figures 5A to 5P is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] FIG. 6A to FIG. 6Q is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0017] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in multiple drawings and embodiments of the present invention.

[0018] The drawings are not necessarily drawn to scale, and in some cases, the scale may be exaggerated to clearly illustrate features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or substrate, but also to the case where a third layer exists between the first layer and the second layer or substrate.

[0019] The following embodiments of the present invention are directed to semiconductor devices including vertically stacked memory cells, which feature increased memory cell density and reduced parasitic capacitance.

[0020] In some embodiments, the semiconductor device can be implemented as a dynamic random access memory (DRAM), which includes not only a memory cell array but also a capacitor for stable power supply or stability of transmission signals. Specifically, in order to stabilize the voltage from factors such as noise, a storage capacitor with a large capacitance can be formed in an empty space of a peripheral circuit.

[0021] Figure 1 is a schematic block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2 is along Figure 1 A cross-sectional view taken along line BB' is shown. Figure 3 and Figure 4 Semiconductor devices according to other embodiments of the present invention are shown.

[0022] Reference Figure 1 and Figure 2, the semiconductor device 100 according to the embodiment of the present invention may include a lower structure LS, a memory cell array MCA, and a storage capacitor array CAR. The memory cell array MCA and the storage capacitor array CAR may be arranged above the lower structure LS. Each of the memory cell array MCA and the storage capacitor array CAR may be arranged above the lower structure LS in a first direction D1. The first direction D1 may be a vertical direction perpendicular to the top surface of the lower structure LS. The memory cell array MCA and the storage capacitor array CAR may be arranged adjacent to each other in a second direction D2. The second direction D2 may be a first horizontal direction. The second direction D2 may be a horizontal direction parallel to the top surface of the lower structure LS. The third direction may be a second horizontal direction. The third direction may be a horizontal direction parallel to the top surface of the lower structure LS. The second direction D2 and the third direction D3 may be orthogonal. The first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other.

[0023] The memory cell array MCA may include a plurality of memory cells MC arranged in three dimensions. Each memory cell MC may include a switching element TR and a data storage element CAP operably coupled to each other. The data storage element CAP may be coupled to the bit line BL through the switching element TR. The switching element TR may be a transistor (e.g., a field effect transistor, FET), and the data storage element CAP may be a capacitor. Hereinafter, the switching element TR may be referred to as a transistor, and the data storage element CAP may be referred to as a cell capacitor. The transistor TR and the capacitor CAP may be disposed between a word line WL and a bit line BL arranged to cross each other. The bit line BL may be referred to as a "first conductive line", and the word line WL may be referred to as a "second conductive line".

[0024] The transistor TR of the individual memory cell MC may include a horizontal active layer ACT, and the horizontal active layer ACT may be coupled to the cell capacitor CAP and the bit line BL. The horizontal active layer ACT may be referred to as a "horizontal layer ACT". The horizontal active layer ACT may include a first source / drain region DR, a second source / drain region SR, and a channel CH horizontally arranged between the first source / drain region DR and the second source / drain region SR. The transistor TR may also include a word line WL or a gate electrode GE overlapping the channel CH. The gate electrode GE may be a part of the word line WL, the first source / drain region DR may be coupled to the bit line BL, and the second source / drain region SR may be coupled to the cell capacitor CAP. In this way, one side of the horizontal active layer ACT may be coupled to the bit line BL, and the other side of the horizontal active layer ACT may be coupled to the cell capacitor CAP. The horizontal active layer ACT may also be referred to as a horizontal active layer or a thin body active layer.

[0025] The individual memory cell MC may include a single transistor TR and a single cell capacitor CAP. This may be referred to as a "1T1C cell". The single cell capacitor CAP of the 1T1C cell may store data, and the single transistor TR may be used as an access device for reading data from or writing data into the single cell capacitor CAP. According to another embodiment of the present invention, the single transistor TR may be used as a selection device.

[0026] The memory cell array MCA may include a plurality of bit lines BL, a plurality of transistors TR, and a plurality of cell capacitors CAP. The cell capacitors CAP may be stacked along a first direction D1.

[0027] The memory cell array MCA may include a plurality of memory cells MC stacked along a first direction D1. The memory cells MC may be arranged in a second direction D2 and a third direction D3. The memory cell array MCA may include a three-dimensional array of memory cells MC. The memory cell array MCA may also include a three-dimensional array of cell capacitors CAP. The memory cell array may be referred to as a "first array".

[0028] The storage capacitor array CAR may include a plurality of storage capacitors RCAP stacked along the first direction D1 and also arranged along the second direction D2 and the third direction D3. The storage capacitor array may be referred to as a “second array.” The storage capacitor array CAR may include at least one three-dimensional array of storage capacitors RCAP.

[0029] The storage capacitor RCAP may have the same or substantially the same structure as the cell capacitor CAP. The storage capacitor RCAP may be formed at the same level as the cell capacitor CAP. The storage capacitor RCAP may be formed to have the same size as the cell capacitor CAP. The storage capacitor RCAP and the cell capacitor CAP may have the same or substantially the same capacitance.

[0030] The memory cell array MCA may be a first column array including cell capacitors CAP stacked along a first direction D1. The cell capacitors CAP of the first column array may be referred to as a cell capacitor array. The storage capacitor array CAR may be a second column array including storage capacitors RCAP stacked along the first direction D1. In the first column array and the second column array, each of the cell capacitors CAP and the storage capacitors RCAP may include storage nodes SN and SN1 separated from each other. Each of the cell capacitors CAP and the storage capacitors RCAP may include plate nodes PN and PN1 coupled to each other.

[0031] The individual transistor TR may include a horizontal active layer ACT and a word line WL. Each word line WL may include a first word line G1 and a second word line G2 facing each other, with the horizontal active layer ACT disposed between the first word line G1 and the second word line G2. A gate dielectric layer GD may be disposed between the horizontal active layer ACT and the word line WL. The gate dielectric layer GD may be formed between the first word line G1 and the horizontal active layer ACT and also between the second word line G2 and the horizontal active layer ACT. The cell capacitor CAP and the storage capacitor RCAP may include storage nodes SN and SN1, dielectric layers DE and DE1, and plate nodes PN and PN1, respectively.

[0032] The bit line BL of the memory cell array MCAR may have a column shape extending in the first direction D1. The cross-sectional shape of the column may be different and may be, for example, rectangular, circular, or elliptical. The lateral active layer ACT may have a strip shape, the major axis of which extends in the second direction D2. The word line WL may have a line shape extending in the third direction D3. The bit line BL may be vertically oriented in the first direction D1. The bit line BL may be referred to as a vertically oriented bit line or a columnar bit line.

[0033] The bit line BL may be made of a conductive material including, for example, a silicon-based material, a metal-based material, or a combination thereof. The bit line BL may be made of silicon, a metal, a metal nitride, a metal silicide, or a combination thereof, or include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. In some embodiments, the bit line BL may be made of polysilicon, titanium nitride, tungsten, or a combination thereof, or include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line BL may be made of polysilicon or titanium nitride (TiN) doped with N-type impurities, or include polysilicon or titanium nitride (TiN) doped with N-type impurities. The bit line BL may be made of a TiN / W stack, or include a TiN / W stack including a titanium nitride layer and a tungsten layer formed on the titanium nitride layer.

[0034] The bit line contact node BLC may surround the outer sidewall of the bit line BL. The bit line contact node BLC may be coupled to the first source / drain region DR of the active layer ACT. The bit line contact node BLC may be made of a conductive material, or include a conductive material, such as a silicon-based material, a metal-based material, or a combination thereof. In some embodiments, the bit line contact node BLC may be made of silicon, metal, metal nitride, metal silicide, or a combination thereof, or include silicon, metal, metal nitride, metal silicide, or a combination thereof. The bit line contact node BLC may be made of polysilicon, titanium nitride, tungsten, or a combination thereof, or include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the bit line contact node BLC may be made of polysilicon doped with N-type impurities (N-type doped polysilicon) or titanium nitride (TiN), or include polysilicon doped with N-type impurities (N-type doped polysilicon) or titanium nitride (TiN). The bit line BL may be made of or include a TiN / W stack including titanium nitride or tungsten over titanium nitride, and the bit line contact node BLC may be made of or include N-type doped polysilicon.

[0035] The word lines WL may extend along the third direction D3, and the horizontal active layer ACT may extend along the second direction D2. The horizontal active layer ACT may be horizontally arranged from the bit line BL along the second direction D2. The word lines WL may each include a pair of word lines, i.e., a first word line G1 and a second word line G2. The first word line G1 and the second word line G2 in each pair may face each other in the first direction D1, and the horizontal active layer ACT is disposed between the first word line G1 and the second word line G2. The gate dielectric layer GD may be formed on the upper and lower surfaces of the horizontal active layer ACT.

[0036] In the word line WL, the first word line G1 and the second word line G2 may have the same potential. For example, the first word line G1 and the second word line G2 may form a pair, and the same word line drive voltage may be applied to the first word line G1 and the second word line G2. As described above, the semiconductor device 100 according to this embodiment of the present invention may have a double word line structure in which two first word lines G1 and second word lines G2 are disposed adjacent to one horizontal active layer ACT. The double word line structure may also be referred to as a double gate structure.

[0037] The horizontal active layer ACT may be made of a semiconductor material, or include a semiconductor material. The horizontal active layer ACT may be made of a silicon-containing layer or a silicon-germanium-containing layer, or include a silicon-containing layer or a silicon-germanium-containing layer. For example, the horizontal active layer ACT may be made of silicon, single crystal silicon, doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, silicon germanium, or a combination thereof, or include silicon, single crystal silicon, doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, silicon germanium, or a combination thereof. According to another embodiment of the present invention, the horizontal active layer ACT may be made of nanowires or nanosheets, or include nanowires or nanosheets. Nanowires and nanosheets may be formed of semiconductor materials, or include semiconductor materials. According to another embodiment of the present invention, the horizontal active layer ACT may be made of oxide semiconductor materials, or include oxide semiconductor materials. The first source / drain region DR and the second source / drain region SR may be formed in the horizontal active layer ACT by an ion implantation process of impurities or a plasma doping process.

[0038] The horizontal active layer ACT may have a thickness smaller than that of the first word line G1 and the second word line G2. The vertical thickness of the horizontal active layer ACT in the first direction D1 may be thinner than the vertical thickness of each of the first word line G1 and the second word line G2 in the first direction D1. Here, the thin horizontal active layer ACT may be referred to as a thin-body horizontal active layer.

[0039] The gate dielectric layer GD may be made of silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof, or include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material or a combination thereof. For example, the gate dielectric layer GD may be made of SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof, or include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO or a combination thereof.

[0040] The first word line G1 and the second word line G2 of the word line WL may be made of a metal-based material, a semiconductor material, or a combination thereof, or include a metal-based material, a semiconductor material, or a combination thereof. The first word line G1 and the second word line G2 of the word line WL may be made of titanium nitride, tungsten, polysilicon, or a combination thereof, or include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first word line G1 and the second word line G2 of the word line WL may be made of a TiN / W stack in which titanium nitride and tungsten are sequentially stacked, or include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first word line G1 and the second word line G2 of the word line WL may be made of a high work function material, a low work function material, or a combination thereof, or include a high work function material, a low work function material, or a combination thereof. The low work function material may have a low work function of about 4.5 eV or less, and the high work function material may have a high work function of about 4.5 eV or more. For example, the low work function material may be made of or include N-type doped polysilicon, and the high work function material may include tungsten, titanium nitride, or a combination thereof. According to another embodiment of the present invention, the first word line G1 and the second word line G2 of the word line WL may have a dual work function structure combining a low work function material and a high work function material.

[0041] The unit capacitor CAP may be arranged horizontally from the transistor TR in the second direction D2. The unit capacitor CAP may include a first storage node SN extending horizontally from the horizontal active layer ACT in the second direction D2. The unit capacitor CAP may also include a first dielectric layer DE and a first plate node PN formed on the first storage node SN. The first storage node SN, the first dielectric layer DE, and the first plate node PN may be arranged horizontally in the second direction D2. The first storage node SN may have a horizontally oriented barrel shape. The first dielectric layer DE may conformally cover the barrel inner wall and barrel outer wall of the first storage node SN. The first plate node PN may have a shape extending toward the barrel inner wall and barrel outer wall of the first storage node SN above the first dielectric layer DE. The first storage node SN may be electrically connected to the horizontal active layer ACT.

[0042] The first storage node SN may have a three-dimensional structure. The first storage node SN may have a horizontal three-dimensional structure oriented along the second direction D2. As an example of a three-dimensional structure, the first storage node SN may have a barrel shape. According to another embodiment of the present invention, the first storage node SN may have a column shape or a pylinder shape. The pylinder shape may refer to a structure in which a column shape and a barrel shape are merged.

[0043] The first storage node SN and the first plate node PN may be made of or include noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first storage node SN and the first plate node PN may be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack, or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack. The first plate node PN may include a combination of a metal-based material and a silicon-based material. For example, the first plate node PN may be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the interior of the barrel of the first storage node SN over titanium nitride, and titanium nitride (TiN) may be used as the first plate node PN of the unit capacitor CAP, while tungsten nitride may be a low resistance material.

[0044] The first dielectric layer DE may be made of silicon oxide, silicon nitride, a high-k material, or a combination thereof, or may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the first dielectric layer DE may include a high-k material having a dielectric constant of about 4 or more. The high-k material may have a dielectric constant of about 20 or more. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O 3) , lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanate (SrTiO3). According to another embodiment of the present invention, the first dielectric layer DE may be formed of a composite layer including two or more layers of the aforementioned high-k materials.

[0045] The first dielectric layer DE may be formed of a zirconium-based oxide (Zr-based oxide). The first dielectric layer DE may have a stacked structure containing at least zirconium oxide (ZrO2). The first dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-based layer (ZrO2-based layer). According to another embodiment of the present invention, the first dielectric layer DE may be formed of a hafnium-based oxide (Hf-based oxide). The first dielectric layer DE may have a stacked structure containing at least hafnium oxide (HfO2). The first dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked sequentially. The HA stack and the HAH stack may be referred to as a hafnium oxide-based layer (HfO2-based layer). In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy (which may be referred to as a band gap hereinafter) greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the first dielectric layer DE may include a stack of a high-k material and a high-bandgap material having a bandgap larger than the high-k material. The first dielectric layer DE may be made of silicon oxide (SiO2), which is a high-bandgap material different from aluminum oxide (Al2O3), or include silicon oxide (SiO2). Since the first dielectric layer DE includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material may be thinner than the high-k material. According to another embodiment of the present invention, the first dielectric layer DE may include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the first dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above-mentioned stacked structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0046] According to another embodiment of the present invention, the first dielectric layer DE may include a stack structure, a layered structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0047] According to another embodiment of the present invention, the first dielectric layer DE may be made of a ferroelectric material or an antiferroelectric material, or include a ferroelectric material or an antiferroelectric material. The ferroelectric material may include HfZrO, HfSiO or a combination thereof. Each of the unit capacitor CAP and the storage capacitor RCAP may be made of a ferroelectric capacitor, or include a ferroelectric capacitor.

[0048] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the first storage node SN and the first dielectric layer DE. The interface control layer may be made of or include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the first plate node PN and the first dielectric layer DE.

[0049] The unit capacitor CAP may include a metal-insulator-metal (MIM) capacitor. The first storage node SN and the first plate node PN may be made of a metal-based material, or include a metal-based material.

[0050] The storage contact node SNC may be formed between the first storage node SN and the second source / drain region SR. The storage contact node SNC may be coupled to the second source / drain region SR. The storage contact node SNC may be made of a conductive material, or include a conductive material. The storage contact node SNC may be made of silicon, a silicon-based material, a metal-based material, or a combination thereof, or include silicon, a silicon-based material, a metal-based material, or a combination thereof. The storage contact node SNC may be made of silicon, a metal, a metal nitride, a metal silicide, or a combination thereof, or include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The storage contact node SNC may be made of polysilicon, titanium nitride, tungsten, or a combination thereof, or include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the storage contact node SNC may be made of polysilicon doped with N-type impurities (N-type doped polysilicon) or titanium nitride (TiN), or include polysilicon doped with N-type impurities (N-type doped polysilicon) or titanium nitride (TiN).

[0051] The first source / drain region DR may include impurities diffused from the bit line contact node BLC, and the second source / drain region SR may include impurities diffused from the storage contact node SNC.

[0052] The storage capacitor array CAR may include a horizontal conductive layer LCL coupled to the storage capacitor RCAP. The horizontal conductive layer LCL may be referred to as a "horizontal portion LCL". Although the memory cell array MCA includes a word line WL extending in a direction crossing each horizontal active layer ACT, the storage capacitor array CAR may not include a material crossing the horizontal conductive layer ACT. The storage capacitor array CAR may be word line-less or transistor-less.

[0053] The storage capacitors RCAP may be coupled to first sides of the horizontal conductive layers LCL, respectively. The second sides of the horizontal conductive layers LCL may be coupled to the vertical conductive lines VCL. The vertical conductive lines VCL may extend along the first direction D1. The vertical conductive lines VCL may include a column portion VP, a plurality of extension portions VE, and a plurality of electrode portions VN. A first contact node CN1 may be formed between the vertical conductive lines VCL and the horizontal conductive layer LCL. A second contact node CN2 may be formed between the horizontal conductive layer LCL and the storage capacitors RCAP.

[0054] The horizontal conductive layer LCL may be made of a semiconductor material, or include a semiconductor material. The horizontal conductive layer LCL may be made of a silicon-containing layer or a silicon-germanium-containing layer, or include a silicon-containing layer or a silicon-germanium-containing layer. For example, the horizontal conductive layer LCL may be made of silicon, single crystal silicon, doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, silicon germanium, or a combination thereof, or include silicon, single crystal silicon, doped polycrystalline silicon, undoped polycrystalline silicon, amorphous silicon, silicon germanium, or a combination thereof. According to another embodiment of the present invention, the horizontal conductive layer LCL may be made of nanowires or nanosheets, or include nanowires or nanosheets. The nanowires and nanosheets may be formed of semiconductor materials, or include semiconductor materials. According to another embodiment of the present invention, the horizontal conductive layer LCL may be made of oxide semiconductor materials, or include oxide semiconductor materials.

[0055] The horizontal conductive layer LCL may be doped. The conductive layer LCL may be doped with N-type impurities or P-type impurities. For example, the horizontal conductive layer LCL may be doped with at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In) and a combination thereof. The horizontal conductive layer LCL may be a silicon material doped with N-type impurities. The horizontal conductive layer LCL may be polysilicon doped with N-type impurities. The horizontal conductive layer LCL may be an impurity region. According to another embodiment of the present invention, the horizontal conductive layer LCL may have a structure in which two impurity regions are in contact with each other.

[0056] The length of the horizontal conductive layer LCL may be shorter than that of the horizontal active layer ACT. Unlike the horizontal active layer ACT, the horizontal conductive layer LCL may not include the channel CH, so it may be as short as a length obtained by subtracting the length of the channel CH from the total length of the horizontal active layer ACT. The horizontal conductive layer LCL may have a length such that the doped regions into which the impurities diffuse from the first contact node CN1 and the second contact node CN2 at both ends of the contact contact each other. The length of the horizontal conductive layer LCL may be adjusted in such a manner that the doped regions into which the impurities diffuse from both ends contact each other so that the entire horizontal conductive layer LCL is conductive.

[0057] According to another embodiment of the present invention, referring to Figure 3 , the storage capacitor array of the semiconductor device 200 may include a horizontal conductive layer LCL, a storage capacitor RCAP, and a vertical conductive line VCL arranged along the second direction, wherein the horizontal conductive layer LCL is located between the storage capacitor RCAP and the vertical conductive line VCL. The horizontal conductive layer LCL may be made of a metal-based material, or include a metal-based material. For example, the horizontal conductive layer LCL may be made of tungsten (W), or include tungsten (W).

[0058] The vertical conductive line VCL may be vertically oriented along the first direction D1. The vertical conductive line VCL may be referred to as a vertically oriented conductive line or a column-type conductive line. The vertical conductive line VCL may include a column portion VP and an extension portion VE. The column portion VP of the vertical conductive line VCL may be vertically oriented in the first direction D1. The extension portion VE may extend from the column portion VP in the second direction D2. The electrode portion VN may cover a portion of the extension portion VE. Specifically, according to this embodiment of the present invention, the electrode portion VN may have the same structure as the storage node SN of the storage capacitor RCAP, and may be symmetrical with respect to the storage node SN of the opposite storage capacitor RCAP.

[0059] The vertical conductive line VCL may be made of a conductive material, or include a conductive material. The vertical conductive line VCL may be made of silicon, a silicon-based material, a metal-based material, or a combination thereof, or include silicon, a silicon-based material, a metal-based material, or a combination thereof. The vertical conductive line VCL may be made of silicon, a metal, a metal nitride, a metal silicide, or a combination thereof, or include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The vertical conductive line VCL may be made of polycrystalline silicon, titanium nitride, tungsten, or a combination thereof, or include polycrystalline silicon, titanium nitride, tungsten, or a combination thereof. For example, the vertical conductive line VCL may be made of polycrystalline silicon or titanium nitride (TiN) doped with N-type impurities, or include polycrystalline silicon or titanium nitride (TiN) doped with N-type impurities. The vertical conductive line VCL may be made of a TiN / W stack, or include a TiN / W stack. The TiN / W stack may be a titanium nitride layer and a tungsten layer formed on the titanium nitride layer. The column portion VP and the extension portion VE of the vertical conductive line VCL may be formed of the same material. The column portion VP and the extension portion VE of the vertical conductive line VCL may have a single integrated structure made of the same material without an interface between the column portion and the extension portion. The electrode portion VN of the vertical conductive line VCL may be in direct contact with the column portion VP and the extension portion VE of the vertical conductive line VCL. The electrode portion VN of the vertical conductive line VCL may be formed simultaneously with the storage node SN of the storage capacitor RCAP. The electrode portion VN may be made of a material different from that of the vertical conductive line VCL and may therefore have a structure different from that of the column portion VP and the extension portion VE of VCL.

[0060] The first contact node CN1 may be coupled to the first side of the horizontal conductive layer LCL. The first contact node CN1 may be made of a conductive material, or include a conductive material. The first contact node CN1 may be made of a silicon-based material, a metal-based material, or a combination thereof, or include a silicon-based material, a metal-based material, or a combination thereof. The first contact node CN1 may be made of silicon, a metal, a metal nitride, a metal silicide, or a combination thereof, or include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first contact node CN1 may be made of polysilicon, titanium nitride, tungsten, or a combination thereof, or include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first contact node CN1 may be made of polysilicon doped with N-type impurities (N-type doped polysilicon), or include polysilicon doped with N-type impurities (N-type doped polysilicon). The vertical conductive line VCL may be made of or include a TiN / W stack including a titanium nitride layer and a tungsten layer on the titanium nitride, and the first contact node CN1 may be made of or include N-type doped polysilicon.

[0061] The storage capacitor RCAP may be formed to have the same structure and the same material as the capacitor CAP of the memory cell array MCA.

[0062] The storage capacitor RCAP may be horizontally disposed from the horizontal conductive layer LCL along the second direction D2. The storage capacitor RCAP may include a second storage node SN1 horizontally extending from the horizontal conductive layer LCL along the second direction D2. The storage capacitor RCAP may also include a second dielectric layer DE1 and a second plate node PN1 above the second storage node SN1. The second storage node SN1 of the storage capacitor RCAP may have the same structure as the electrode portion VN of the vertical conductive line VCL and may be formed of the same material.

[0063] The second storage node SN1, the second dielectric layer DE1, and the second plate node PN1 may be arranged horizontally along the second direction D2. The second storage node SN1 may have a horizontally oriented barrel shape. The second dielectric layer DE1 may conformally cover the barrel inner wall and barrel outer wall of the second storage node SN1. The second plate node PN1 may have a shape extending into the barrel inner wall of the second storage node SN1 above the second dielectric layer DE1 and extending above the barrel outer wall of the second storage node SN1. The second plate node PN1 may be conformally formed on the second dielectric layer DE1. Therefore, the second plate node PN1 may be in direct contact with the second dielectric layer DE1. The second storage node SN1 may be electrically connected to the horizontal conductive layer LCL. According to this embodiment of the present invention, the electrode portion VN of the vertical conductive line VCL may have the same structure (i.e., shape and material) as the second storage node SN1 of the storage capacitor RCAP, i.e., a horizontally oriented barrel shape.

[0064] The second storage node SN1 may have a three-dimensional structure, and the second storage node SN1 may have a horizontal three-dimensional structure oriented along the second direction D2. As an example of a three-dimensional structure, the second storage node SN1 may have a barrel shape. According to another embodiment of the present invention, the second storage node SN1 may have a column shape or a cylindrical barrel shape. The cylindrical barrel shape may refer to a structure in which the column shape and the barrel shape are merged.

[0065] The second storage node SN1 and the second plate node PN1 may be made of or include noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second storage node SN1 and the second plate node PN1 can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack, or include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, or tungsten nitride / tungsten (WN / W) stack. For example, the second plate node PN1 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN), silicon germanium may be a gap-filling material filling the inside of the barrel of the second storage node SN1 above titanium nitride, and tungsten nitride may be a low-resistance material.

[0066] The second dielectric layer DE1 may be made of silicon oxide, silicon nitride, a high-k material, or a combination thereof, or may include silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the second dielectric layer DE1 may include a high-k material having a dielectric constant of about 4 or more. The high-k material may have a dielectric constant of about 20 or more. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O 3) , lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5) or strontium titanate (SrTiO3). According to another embodiment of the present invention, the second dielectric layer DE1 may be formed of a composite layer including two or more layers of the aforementioned high-k material.

[0067] The second dielectric layer DE1 may be formed of a zirconium-based oxide (Zr-based oxide). The second dielectric layer DE1 may have a stacked structure containing at least zirconium oxide (ZrO2). The second dielectric layer DE1 may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may have a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may have a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked sequentially. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-based layer (ZrO2-based layer). According to another embodiment of the present invention, the second dielectric layer DE1 may be formed of a hafnium-based oxide (Hf-based oxide). The second dielectric layer DE1 may have a stacked structure containing at least hafnium oxide (HfO2). The second dielectric layer DE1 may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may have a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may have a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked sequentially. The HA stack and the HAH stack may be referred to as a hafnium oxide-based layer (HfO2-based layer). In the ZA stack, the ZAZ stack, the HA stack and the HAH stack, aluminum oxide (Al2O3) may have a band gap energy (which may be referred to as a band gap hereinafter) greater than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Aluminum oxide (Al2O3) may have a lower dielectric constant than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the second dielectric layer DE1 may include a stack of a high-k material and a high-bandgap material having a bandgap larger than that of the high-k material. In addition to aluminum oxide (Al2O3), the second dielectric layer DE1 may include silicon oxide (SiO2) as a high-bandgap material. Since the second dielectric layer DE1 includes a high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present invention, the second dielectric layer DE1 may include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the second dielectric layer DE1 may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above-mentioned stacked structure, aluminum oxide (Al2O3) may be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0068] According to another embodiment of the present invention, the second dielectric layer DE1 may include a stacked structure, a layered structure, or a mixed structure including zirconium oxide, hafnium oxide, and aluminum oxide.

[0069] According to another embodiment of the present invention, the second dielectric layer DE1 may be made of or include a ferroelectric material or an antiferroelectric material. The ferroelectric material may include HfZrO, HfSiO or a combination thereof. The cell capacitor CAP and the storage capacitor RCAP may be ferroelectric capacitors.

[0070] According to another embodiment of the present invention, an interface control layer for improving leakage current may be further formed between the second storage node SN1 and the second dielectric layer DE1. The interface control layer may be made of or include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the second plate node PN1 and the second dielectric layer DE1.

[0071] The storage capacitor RCAP may include a MIM (Metal-Insulator-Metal) capacitor. The second storage node SN1 and the second plate node PN1 may be made of or include a metal-based material.

[0072] The second contact node CN2 may be formed between the second storage node SN1 and the horizontal conductive layer LCL. The second contact node CN2 may be coupled to the second side of the horizontal conductive layer LCL. The second contact node CN2 may be made of a conductive material, or include a conductive material. The second contact node CN2 may be made of a silicon-based material, a metal-based material, or a combination thereof, or include a silicon-based material, a metal-based material, or a combination thereof. The second contact node CN2 may be made of silicon, a metal, a metal nitride, a metal silicide, or a combination thereof, or include silicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The second contact node CN2 may be made of polysilicon, titanium nitride, tungsten, or a combination thereof, or include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the second contact node CN2 may be made of polysilicon doped with N-type impurities (N-type doped polysilicon), or include polysilicon doped with N-type impurities (N-type doped polysilicon).

[0073] According to another embodiment of the present invention, the storage capacitor RCAP and the vertical conductive line VCL may directly contact the horizontal conductive layer LCL without the presence of the first contact node CN1 and the second contact node CN2.

[0074] Figure 1 and Figure 2 The semiconductor device 100 may be, for example, a dynamic random access memory (DRAM) or a ferroelectric memory (FeRAM).

[0075] According to other embodiments of the present invention, the cell capacitor CAP and the storage capacitor RCAP may be replaced with other data storage structures or materials, such as phase change materials, magnetic tunnel junctions (MTJs), or variable resistance materials.

[0076] The horizontal active layers ACT adjacent to each other in the first direction D1 may contact one bit line BL. The horizontal active layers ACT disposed adjacent to each other in the third direction D3 may share a word line WL.

[0077] In the memory cell array MCA, a plurality of word lines WL may be vertically stacked in a first direction D1. Each word line WL may include a pair of a first word line G1 and a second word line G2. A plurality of horizontal active layers ACT may be arranged between the first word line G1 and the second word line G2 in a second direction D2 and horizontally spaced apart from each other. According to another embodiment of the present invention, the word line WL may be replaced with a single word line structure formed only of the first word line G1 or the second word line G2.

[0078] The lower structure LS may be a material suitable for semiconductor processing. The lower structure LS may include at least one of a conductive material, a dielectric material, and a semiconductor material. The lower structure LS may be made of or include a semiconductor substrate, and the semiconductor substrate may be formed of a material containing silicon. The lower structure LS may be made of or include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, combinations thereof, and multilayers thereof. The lower structure LS may also be made of or include other semiconductor materials, such as germanium. The lower structure LS may be made of or include a III / V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The lower structure LS may be made of or include a silicon-on-insulator (SOI) substrate.

[0079] According to another embodiment of the present invention, the lower structure LS may include a peripheral circuit. The peripheral circuit may include a plurality of peripheral circuit transistors. The peripheral circuit may be arranged at a level lower than the memory cell array MCA and the storage capacitor array CAR. This may be referred to as a PUC (Peripheral Circuit Under Unit) structure. The peripheral circuit may include at least one control circuit, which is used to drive the memory cell array MCA and the storage capacitor array CAR. The lower structure LS may be referred to as a "first peripheral circuit" and the storage capacitor array CAR may be referred to as a "second peripheral circuit". At least one or more control circuits of the peripheral circuit may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion PERI may include an address decoder circuit, a read circuit, and a write circuit, etc. At least one control circuit of the peripheral circuit may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, and a fin channel transistor (FinFET), etc.

[0080] For example, the peripheral circuit may include a sub-word line driver SWD, a sense amplifier SA, and a storage capacitor control circuit CL_RCAP. The word line WL may be coupled to the sub-word line driver SWD. The bit line BL may be coupled to the sense amplifier SA. The storage capacitor RCAP may be coupled to the storage capacitor control circuit CL_RCAP.

[0081] According to another embodiment of the present invention, referring to Figure 4 , the lower structure LS of the semiconductor device 300 may be arranged at a higher level than the storage capacitor array CAR. This may be referred to as a POC (on-cell peripheral circuit) structure. In the POC structure, the peripheral circuit may be arranged at a higher level than the storage capacitor array CAR. Although not shown, the lower structure LS may be arranged at a higher level than the storage cell array CAR, and the storage cell array CAR is arranged at the same level as the storage capacitor array CAR.

[0082] According to another embodiment of the present invention, the lower structure LS may be referred to as a first peripheral circuit portion, and the storage capacitor array CAR may be referred to as a second peripheral circuit portion. Therefore, the first peripheral circuit portion may be arranged at a lower level than the memory cell array MCA, and the second peripheral circuit portion may be arranged horizontally with the memory cell array MCA. The first peripheral circuit portion may include a control circuit for controlling the memory cell array MCA, such as a sense amplifier and a sub-word line driver. The second peripheral circuit portion may include a storage capacitor array CAR, and the control circuit for controlling the storage capacitor array CAR may be arranged in the first peripheral circuit portion.

[0083] The components of the cell capacitor CAP and the storage capacitor RCAP may have the same shape and may be formed of the same material. For example, the first storage node SN of the cell capacitor CAP and the second storage node SN1 of the storage capacitor RCAP may have a barrel shape.

[0084] The bit lines BL of the memory cell array MCA and the vertical conductive lines VCL of the storage capacitor array CAR may be formed of the same material.

[0085] The bit line contact node BLC of the memory cell array MCA and the first contact node CN1 of the storage capacitor array CAR may have the same shape and may be formed of the same material.

[0086] The storage contact node SNC of the memory cell array MCA and the second contact node CN2 of the storage capacitor array CAR may have the same shape and may be formed of the same material.

[0087] The memory cell array MCA and the storage capacitor array CAR may have similar components except for the word lines WL. The memory cell array MCA may include the word lines WL, while the storage capacitor array CAR may not have the word lines.

[0088] According to the above-described embodiments of the present invention, the bias of VPP and the like can be stabilized by forming the storage capacitor RCAP.

[0089] Furthermore, since the three-dimensional array of storage capacitors is formed horizontally from the memory cell array in the same structure as the unit capacitors of the memory cell array, the capacitance of the storage capacitors can be increased by securing the area of ​​the storage capacitors.

[0090] Figures 5A to 5P is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 5A to 5P Shows the formation Figure 1 and Figure 2 The method of the storage capacitor array CAR is shown.

[0091] Reference Figure 5A, an interlayer dielectric layer 12 may be formed on the lower structure 11, and a stack SB may be formed on the interlayer dielectric layer 12. The stack SB may be formed by repeatedly stacking sub-stacks, each sub-stack including a dielectric layer 13', a first sacrificial layer 14', a semiconductor layer 15', and a second sacrificial layer 16' in the order mentioned. For example, the dielectric layer 13' may be silicon oxide, and the first sacrificial layer 14' and the second sacrificial layer 16' may be silicon nitride. For example, the semiconductor layer 15' may be a silicon layer, a single crystal silicon layer, or a polycrystalline silicon layer. The uppermost layer of the stack SB may be the dielectric layer 13'. According to another embodiment of the present invention, the semiconductor layer 15' may be made of an oxide semiconductor material, or include an oxide semiconductor material.

[0092] A hard mask layer 17 may be formed on the stacked body SB. The hard mask layer 17 may be made of a material having an etching selectivity relative to the dielectric layer 13', the first sacrificial layer 14', the semiconductor layer 15', and the second sacrificial layer 16' forming the stacked body SB, or include a material having the etching selectivity. For example, the hard mask layer 17 may be made of SiCO, or include SiCO.

[0093] The lower structure 11 may be made of a semiconductor substrate or a peripheral circuit, or include a semiconductor substrate or a peripheral circuit. The interlayer dielectric layer 12 may be made of silicon oxide, silicon nitride, or a combination thereof, or include silicon oxide, silicon nitride, or a combination thereof.

[0094] Reference Figure 5B , a plurality of openings 18 and 19 may be formed in the stacked body SB. The openings 18 and 19 may have a hole shape. To form the openings 18 and 19, the hard mask layer 17 may be etched using a mask pattern (not shown), and the stacked body SB may be etched using the hard mask layer 17, and the interlayer dielectric layer 12 may be continuously etched. The openings 18 and 19 may include a first opening 18 and a second opening 19. The first opening 18 and the second opening 19 may have the same size or may have different sizes.

[0095] The mask pattern (not shown) for forming the first opening 18 and the second opening 19 may be a mask pattern for forming a bit line contact and a storage node contact in the memory cell region. Since the mask pattern for forming the first opening 18 and the second opening 19 may be formed using the same pattern (also referred to as a mask plate) as the mask pattern in the memory cell region, the formation of an additional mask plate may be omitted.

[0096] Reference Figure 5C, the dielectric layer 13' may be partially recessed by the first opening 18 and the second opening 19. For example, partial etching of the dielectric layer 13' may be performed. Due to the partial etching of the dielectric layer 13', a dielectric layer pattern 13" may be formed, wherein sacrificial recesses 20' are also formed on both sides of the dielectric layer pattern 13".

[0097] Reference Figure 5D , a sacrificial cover layer 20 may be formed to fill the sacrificial recess 20'. The sacrificial cover layer 20 may be formed of the same material as the first sacrificial layer 14' and the second sacrificial layer 16'. The sacrificial cover layer 20 may be, for example, silicon nitride. The sacrificial cover layer 20 may not fill the first opening 18 and the second opening 19.

[0098] Reference Figure 5E , the semiconductor layer 15' may be horizontally recessed through the first opening 18 and the second opening 19. Therefore, the semiconductor layer pattern 15 may be formed, and the horizontal recess 21 is also formed on both sides of the semiconductor layer pattern 15. When the semiconductor layer pattern 15 is formed, the sacrificial capping layer 20 and the first sacrificial layer 14' and the second sacrificial layer 16' may not be lost. The length of the semiconductor layer pattern 15 may be longer than the horizontal active layer ACT of the memory cell (see Figure 1 ) is short in length.

[0099] Reference Fig. 5F , enlarged horizontal recesses 22A and 22B may be formed. In order to form the enlarged horizontal recesses 22A and 22B, the sacrificial cover layer 20 and the first sacrificial layer 14' and the second sacrificial layer 16' may be partially etched. When the sacrificial cover layer 20 and the first sacrificial layer 14' and the second sacrificial layer 16' are etched, the dielectric layer pattern 13" may not be etched. By partially etching the first sacrificial layer 14' and the second sacrificial layer 16', the first horizontal insulation line 14 and the second horizontal insulation line 16 may be formed in the upper and lower portions of the semiconductor layer pattern 15, respectively. The horizontal lengths of the first horizontal insulation line 14 and the second horizontal insulation line 16 may be equal to the horizontal length of the semiconductor layer pattern 15.

[0100] Reference Figure 5G , a preliminary contact layer 23' may be formed to cover the enlarged horizontal recesses 22A and 22B (see Fig. 5F ) inner wall. The preliminary contact layers 23' may be formed to be separated from each other by the dielectric layer pattern 13". The preliminary contact layer 23' may contact both ends of the semiconductor layer pattern 15. For example, the preliminary contact layer 23' may be made of polysilicon doped with N-type impurities, or include polysilicon doped with N-type impurities.

[0101] Subsequently, a third sacrificial layer 24 may be formed to fill the expanded horizontal recesses 22A and 22B above the preliminary contact layer 23' (see Fig. 5F). The third sacrificial layer 24 may include a material having an etch selectivity with respect to the dielectric layer pattern 13 ″ and the preliminary contact layer 23 ′. The third sacrificial layer 24 may include, for example, silicon nitride.

[0102] Reference Figure 5H , the preliminary contact layer 23' disposed between the dielectric layer pattern 13" and the third sacrificial layer 24 can be etched. When the preliminary contact layer 23' disposed between the dielectric layer pattern 13" and the third sacrificial layer 24 is etched, the first contact node 23 and the second contact node 30 respectively contacting both ends of the semiconductor layer pattern 15 can be formed. The first contact node 23 and the second contact node 30 can be separated from each other by the dielectric layer pattern 13".

[0103] Reference Fig.5I , the third sacrificial layer 24 can be removed (see Figure 5H ). When the third sacrificial layer 24 (see Figure 5H ) is removed, the first contact nodes 23 and the second contact nodes 30 respectively contacting both ends of the semiconductor layer pattern 15 may be exposed.

[0104] Reference Figure 5J , the semiconductor layer pattern 15 may be replaced by a horizontal conductive layer 15D. The horizontal conductive layer 15D may be doped with impurities. For example, the horizontal conductive layer 15D may be doped with impurities diffused from the first contact node 23 and the second contact node 30. In order to form the horizontal conductive layer 15D, the semiconductor layer pattern 15 may be heat-treated at an effective temperature so that the impurities diffuse from the first contact node 23 and the second contact node 30 into the horizontal conductive layer 15D. When the first contact node 23 and the second contact node 30 include polysilicon doped with N-type impurities, the horizontal conductive layer 15D may become a doped region with N-type impurities. The horizontal conductive layer 15D may contact the doped region into which the impurities diffuse from the first contact node 23 and the second contact node 30, so that the entire horizontal conductive layer 15D may be replaced by the doped region.

[0105] Reference Figure 5K , the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may be formed on the first contact node 23 and the second contact node 30, respectively. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may conformally cover the enlarged horizontal recesses 22A and 22B (see Figure 5J ).

[0106] The electrode portion 31N of the vertical conductive line may be coupled to the horizontal conductive layer 15D through the first contact node 23. The storage node 31 of the storage capacitor may be coupled to the horizontal conductive layer 15D through the second contact node 30.

[0107] The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may be formed in a symmetrical structure. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor facing each other may have a bilaterally symmetrical structure.

[0108] Reference Figure 5L , dielectric layer pattern 13" (see Figure 5K ) can be horizontally recessed through the first opening 18 and the second opening 19. The dielectric layer pattern 13 can be partially etched (see Figure 5K ) to form a separation portion 13.

[0109] Meanwhile, the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may have outer walls exposed to form a barrel shape. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor facing each other may have a barrel shape of a symmetrical structure.

[0110] Reference Figure 5M , the fourth sacrificial layer 25 and the dielectric layer 32 may be formed to cover the entire surface including the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor.

[0111] Reference Figure 5N A mask pattern 26 that opens the first opening 18 may be formed on the hard mask layer 17 .

[0112] Subsequently, the fourth sacrificial layer 25 in the first opening 18 may be removed. As a result, the electrode portion 31N of the vertical conductive line having a barrel shape may be exposed in the first opening 18 .

[0113] Reference Fig.5O , the mask pattern 26 can be removed (see Figure 5N ). When the mask pattern 26 is formed of a photoresist, the mask pattern 26 may be removed by an oxygen stripping process.

[0114] Reference Figure 5P , a column portion 27P and an extension portion 27E of a vertical conductive line filling the first opening 18 over the electrode portion 31N of the vertical conductive line, and a plate node 33 filling the second opening 19 over the storage node 31 of the storage capacitor may be formed.

[0115] Therefore, a vertical conductive line in which the electrode portion 31N, the extension portion 27E, and the pillar portion 27P are stacked may be formed in the first opening 18 (see Fig.5O ), and a storage capacitor RCAP in which a storage node 31, a dielectric layer 32, and a plate node 33 are stacked may be formed in the second opening 19 (see Fig.5O )middle.

[0116] As described above, according to the embodiment of the present invention, the line width of the semiconductor layer pattern 15 can be reduced by performing a recess process for forming the semiconductor layer pattern 15 on both sides through the first opening 18 and the second opening 19. As a result, due to impurities diffused through the first contact node CN1 and the second contact node CN2, a horizontal conductive layer 15D can be formed and a MIM structure can be formed.

[0117] Furthermore, a recess process for forming the isolation portion 13 may be performed on both sides through the first opening 18 and the second opening 19 to increase the volume of the vertical conductive line and reduce the resistance of the vertical conductive line.

[0118] Furthermore, since the first opening 18 and the second opening 19 are formed using a mask pattern using the same mask as the mask used to form the bit line contact and the storage node contact of the memory cell, most processes including the semiconductor layer pattern 15 can be performed with the first opening 18 and the second opening 19 simultaneously opened. Therefore, the MIM structure can be formed using only the mask used to form the memory cell array and the process margin can be ensured without forming an additional mask for the storage capacitor.

[0119] FIG. 6A to FIG. 6Q is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 6A to FIG. 6Q Shows the formation Figure 3 The method of the storage capacitor array CAR is shown.

[0120] 6A to 6F The process can be FIG. 5A to FIG. 5F The processes are performed in the same manner, so their description will be omitted here.

[0121] Reference Figure 6G , by removing the semiconductor layer pattern 15 (see Fig. 6F ) to form the recess 15R.

[0122] Reference Figure 6H , a horizontal metal conductive layer 15M may be formed by gap-filling each recess 15R with a conductive material. The horizontal metal conductive layer 15M may be formed by a series of processes of forming a conductive material to gap-fill the recess 15R and etching the conductive material so that the conductive material remains only in the recess 15R. For example, the horizontal metal conductive layer 15M may be formed of tungsten (W), but the concept of the present invention is not limited thereto.

[0123] Reference Fig.6I , the preliminary contact layer 23' may be formed to cover the inner walls of the enlarged horizontal recesses 22A and 22B (see Figure 6H). The preliminary contact layers 23' may be formed to be separated from each other by the dielectric layer pattern 13". The preliminary contact layer 23' may contact both ends of each horizontal metal conductive layer 15M. For example, the preliminary contact layer 23' may be made of polysilicon doped with N-type impurities, or include polysilicon doped with N-type impurities.

[0124] Subsequently, a third sacrificial layer 24 may be formed to fill the expanded horizontal recesses 22A and 22B above the preliminary contact layer 23' (see Figure 6H ). The third sacrificial layer 24 may include a material having an etch selectivity with respect to the dielectric layer pattern 13 ″ and the preliminary contact layer 23 ′. The third sacrificial layer 24 may include, for example, silicon nitride.

[0125] Reference Figure 6J , the preliminary contact layer 23' placed between the dielectric layer pattern 13" and the third sacrificial layer 24 can be etched. When the preliminary contact layer 23' placed between the dielectric layer pattern 13" and the third sacrificial layer 24 is etched, the first contact node 23 and the second contact node 30 respectively contacting the two ends of each horizontal metal conductive layer 15M can be formed. The first contact node 23 and the second contact node 30 can be separated from each other by the dielectric layer pattern 13".

[0126] Reference Figure 6K , the third sacrificial layer 24 can be removed (see Figure 6J By removing the third sacrificial layer 24 (see Figure 6J ), the first contact node 23 and the second contact node 30 respectively contacting both ends of each horizontal metal conductive layer 15M may be exposed.

[0127] Reference Figure 6L , the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may be formed above the first contact node 23 and the second contact node 30. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may conformally cover the enlarged horizontal recesses 22A and 22B (see Figure 6K ).

[0128] The electrode portion 31N of the vertical conductive line may be coupled to the horizontal metal conductive layer 15M through the first contact node 23. The storage node 31 of the storage capacitor may be coupled to the horizontal metal conductive layer 15M through the second contact node 30.

[0129] The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may be formed in a symmetrical structure. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor facing each other may have a bilaterally symmetrical structure.

[0130] Reference Figure 6M , dielectric layer pattern 13" (see Fig.6I ) can be horizontally recessed through the first opening 18 and the second opening 19. The isolation portion 13 can be formed by partially etching the dielectric layer pattern 13 (see Fig.6I ) to form.

[0131] Meanwhile, the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor may have outer walls exposed to have a barrel shape. The electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor facing each other may have a bilaterally symmetrical barrel shape.

[0132] Reference Figure 6N , the fourth sacrificial layer 25 and the dielectric layer 32 may be formed to cover the entire surface including the electrode portion 31N of the vertical conductive line and the storage node 31 of the storage capacitor.

[0133] Reference Fig.6O A mask pattern 26 that opens the first opening 18 may be formed on the hard mask layer 17 .

[0134] Subsequently, the fourth sacrificial layer 25 in the first opening 18 may be removed. As a result, the electrode portion 31N of the vertical conductive line having a barrel shape may be exposed in the first opening 18.

[0135] Reference Figure 6P , the mask pattern 26 can be removed (see Fig.6O ). When the mask pattern 26 is formed of a photoresist, the mask pattern 26 may be removed by an oxygen stripping process.

[0136] Reference Figure 6Q , a column portion 27P and an extension portion 27E of a vertical conductive line filling the first opening 18 over the electrode portion 31N of the vertical conductive line, and a plate node 33 filling the second opening 19 over the storage node 31 of the storage capacitor may be formed.

[0137] Therefore, a vertical conductive line in which the electrode portion 31N, the extension portion 27E, and the pillar portion 27P are stacked may be formed in the first opening 18 (see Figure 6P ), and a storage capacitor RCAP in which a storage node 31, a dielectric layer 32, and a plate node 33 are stacked may be formed in the second opening 19 (see Figure 6P ).

[0138] According to an embodiment of the present invention, a storage capacitor of an MIM structure may be formed using the same mask as a memory cell array, thereby preventing a reduction in process margin that may be caused by forming an additional mask.

[0139] According to an embodiment of the present invention, a three-dimensional array of storage capacitors may be formed horizontally with a memory cell array in the same structure as a cell capacitor of a three-dimensional memory cell array, thereby ensuring an area of ​​the storage capacitors and increasing the capacitance of the storage capacitors.

[0140] According to an embodiment of the present invention, the resistance of the vertical conductive line may be reduced by increasing the volume of the vertical conductive line.

[0141] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Lower structure; a plurality of horizontal conductive layers oriented in a direction parallel to a surface of the underlying structure; a plurality of storage capacitors commonly coupled to the first side end of the horizontal conductive layer, wherein each of the plurality of storage capacitors is vertically stacked on the lower structure and includes a tubular storage node; and A vertical conductive line, which: is commonly coupled to a second side end of the horizontal conductive layer opposite to the first side end, extends in a direction perpendicular or substantially perpendicular to the surface of the lower structure, and includes a plurality of electrode portions, each electrode portion being symmetrical with the tubular storage node of the corresponding storage capacitor.

2. The semiconductor device according to claim 1, wherein Each of said storage capacitors comprises: cylindrical storage nodes, respectively coupled to the first side ends of the horizontal conductive layer; a dielectric layer covering the storage node; and A plate node is above the dielectric layer.

3. The semiconductor device according to claim 2, wherein: The plate nodes are oriented vertically in the direction that is perpendicular or substantially perpendicular to the surface of the underlying structure.

4. The semiconductor device according to claim 1, wherein The horizontal conductive layer includes a semiconductor material, a doped semiconductor material, an oxide semiconductor material or a metal-based material.

5. The semiconductor device according to claim 1, wherein The horizontal conductive layer includes a doped silicon material doped with N-type impurities.

6. The semiconductor device according to claim 1, wherein The horizontal conductive layer includes a metal material.

7. The semiconductor device according to claim 1, wherein The horizontal conductive layer includes tungsten.

8. The semiconductor device according to claim 1, further comprising: a first contact node disposed between the horizontal conductive layer and the electrode portion of the vertical conductive line; as well as A second contact node is disposed between the horizontal conductive layer and the storage capacitor.

9. The semiconductor device according to claim 8, wherein: The first contact node and the second contact node include polysilicon doped with N-type impurities.

10. The semiconductor device according to claim 1, wherein The vertical conductive line comprises: a column portion vertically oriented in a direction perpendicular or substantially perpendicular to the surface of the underlying structure; an extension portion extending horizontally from the column portion; and A cylindrical electrode portion covers at least a portion of each of the extension portions.

11. The semiconductor device according to claim 10, wherein: The cylindrical electrode portion is arranged to be bilaterally symmetrical based on the pillar portion.

12. The semiconductor device according to claim 1, wherein The lower structure includes a control circuit for controlling the storage capacitor.

13. The semiconductor device according to claim 1, further comprising: A memory cell array is disposed above the lower structure and horizontally disposed with respect to the storage capacitor.

14. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of horizontal conductive layers oriented in a direction parallel to a surface of an underlying structure; forming a plurality of tubular storage nodes and a plurality of electrode portions, wherein the plurality of tubular storage nodes and the plurality of electrode portions are coupled to both ends of the horizontal conductive layer and are symmetrical on both sides; forming a dielectric layer and a sacrificial layer, the dielectric layer and the sacrificial layer being adapted to cover the tubular storage node and the electrode portion; exposing the electrode portion by removing the sacrificial layer; as well as A storage capacitor is formed by forming a plate node and a conductive layer over the dielectric layer and the electrode portion, respectively, the storage capacitor being stacked over the lower structure and extending in a direction perpendicular or substantially perpendicular to the surface of the lower structure.

15. The method according to claim 14, wherein: The cylindrical storage node and the electrode portion are formed simultaneously.

16. The method according to claim 14, wherein: The cylindrical storage node and the electrode portion have the same material and the same bilaterally symmetrical structure.

17. The method according to claim 14, wherein: The dielectric layer and the sacrificial layer are formed simultaneously.

18. The method according to claim 14, wherein: The dielectric layer and the sacrificial layer include the same material.

19. The method according to claim 14, wherein: The plate nodes are oriented vertically in a direction that is perpendicular or substantially perpendicular to the surface of the underlying structure.

20. The method of claim 14, further comprising: Before forming the cylindrical storage node and the electrode portion, A first contact node and a second contact node coupled to both ends of the horizontal conductive layer are formed.

21. The method according to claim 14, wherein: The horizontal conductive layer includes a doped silicon material doped with N-type impurities.

22. The method according to claim 14, wherein: The horizontal conductive layer includes a metal material.

23. The method according to claim 14, wherein: The horizontal conductive layer includes tungsten.

Images