Semiconductor device and data storage system including the same

Abstract

The invention provides a semiconductor device and a data storage system. The semiconductor device includes: a peripheral circuit structure; a stack structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating the stack structure. The stacked structure includes a plurality of blocks spaced apart from each other by a first portion of the separation structure, each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and the plurality of blocks includes first blocks, and a plurality of capacitor blocks disposed between first blocks adjacent to each other among the first blocks.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0105422 filed in the Korean Intellectual Property Office on August 11, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some example embodiments of the present disclosure relate to a semiconductor device and / or a data storage system including the semiconductor device. Background Art

[0004] There is a demand for semiconductor devices capable of storing large amounts of data in data storage systems. Therefore, methods for increasing the data storage capacity of semiconductor devices have been studied. For example, as a method for increasing the data storage capacity of semiconductor devices, a semiconductor device including three-dimensionally arranged storage cells rather than two-dimensionally arranged storage cells has been proposed. Summary of the invention

[0005] Example embodiments of the present disclosure provide a semiconductor device with increased integration density.

[0006] Example embodiments of the present disclosure provide a data storage system including a semiconductor device having an increased integration density.

[0007] According to an example embodiment of the present disclosure, a semiconductor device includes: a peripheral circuit structure; a stacking structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating the stacking structure, wherein the stacking structure includes a plurality of blocks separated from each other by the separation structure, wherein each of the plurality of blocks includes an insulating layer and a conductive layer alternately stacked in a vertical direction, and wherein the plurality of blocks include a first block and a plurality of capacitor blocks, and the plurality of capacitor blocks are arranged between first blocks adjacent to each other in the first block.

[0008] According to an example embodiment of the present disclosure, a semiconductor device includes: a first chip structure; and a second chip structure vertically overlapping the first chip structure, wherein the first chip structure includes a peripheral circuit, wherein the second chip structure includes: a stacking structure; a separation structure penetrating the stacking structure; a plurality of contact plugs; and an input / output pad, wherein the stacking structure includes a plurality of blocks spaced apart from each other, wherein each of the plurality of blocks includes an insulating layer and a conductive layer alternately stacked in a vertical direction, wherein the plurality of blocks include a plurality of memory blocks and a capacitor block, wherein the first chip structure and the second chip structure further include a routing interconnect structure between the peripheral circuit and the stacking structure, wherein the plurality of contact plugs include a first input / output contact plug penetrating the stacking structure and electrically connected to a first input / output pad among the input / output pads, wherein the capacitor block includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode includes a plurality of first conductive layers among the conductive layers, the second capacitor electrode includes a plurality of second conductive layers among the conductive layers, and wherein the first capacitor electrode is electrically connected to the first input / output pad through the first input / output contact plug and the routing interconnect structure.

[0009] According to an example embodiment of the present disclosure, a data storage system includes: a semiconductor device including an input / output pad; and a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device, wherein the semiconductor device also includes: a peripheral circuit structure; a stacking structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating the stacking structure, wherein each of a plurality of blocks includes an insulating layer and a conductive layer alternately stacked in a vertical direction, wherein the plurality of blocks include a first block and a plurality of capacitor blocks, the plurality of capacitor blocks are arranged between first blocks adjacent to each other among the first blocks, and wherein the plurality of capacitor blocks are spaced apart from each other by the separation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0011] FIG. 1A to FIG. 8D is a diagram showing a semiconductor device according to an example embodiment of the present disclosure;

[0012] Fig. 9 is a diagram of a modified example of the semiconductor device according to the example embodiment of the present disclosure, viewed from above;

[0013] Fig. 10A is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0014] Fig. 10Bis an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0015] Fig. 10C is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0016] Fig. 10D is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0017] Fig. 10E is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0018] Fig.10F is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0019] Figure 10G is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0020] Fig.11 is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0021] Fig. 12A is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0022] Fig. 12B is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0023] Fig. 12C is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0024] Fig.12D is an enlarged cross-sectional view showing a modified example of a portion of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0025] Fig.13 , Fig.14A and Fig. 14B is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0026] Fig.15 , Fig.16A and Fig. 16B is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0027] Fig.17 is a cross-sectional view showing a modified example of the semiconductor device according to the example embodiment of the present disclosure;

[0028] Fig.18 is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0029] Fig.19 is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure viewed from above;

[0030] Fig. 20 is a perspective view showing a modified example of the semiconductor device according to the example embodiment of the present disclosure;

[0031] Fig.21A and Fig.21B is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure;

[0032] Fig.22A , Fig. 22B and Fig.23 is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure;

[0033] Fig.24 , Fig.25 , Fig.26A , Fig.26B , Fig.26C , Fig.27A and Fig.27B is a diagram showing a modified example of the semiconductor device according to the example embodiment of the present disclosure;

[0034] Fig.28 is a flowchart illustrating an example of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure; and

[0035] Fig.29 is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Hereinafter, the embodiments of the present disclosure will be described with reference to the accompanying drawings as follows. Hereinafter, terms such as "upper portion", "middle portion" and "lower portion" may be replaced by other terms (e.g., "first", "second" and "third") to describe the elements of the specification. Terms such as "first", "second" and "third" may be used to describe different elements, but these elements are not limited by these terms, and the "first element" may be referred to as the "second element".

[0037] Will refer to Figures 1A to 7C A semiconductor device according to example embodiments is described. Figure 1A is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment, Figure 1B is a perspective view showing a semiconductor device according to an example embodiment, Figure 1C is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment, Figure 1D is a block diagram illustrating a semiconductor device according to an example embodiment, Figure 2 is a diagram showing a portion of a semiconductor device according to an example embodiment, Figure 3 is a perspective view showing a portion of a semiconductor device according to an example embodiment, Figure 4A It shows Figure 2 A magnified view of area "A" in Figure 4B It shows Figure 4A A magnified view of area "C" in Figure 5 It shows Figure 2 Figure 2 shows the region "B" in the graph. Fig. 6A is shown along Figure 4A A cross-sectional view of the area cut by line II' in FIG. Figure 6B is shown along Figure 4A A cross-sectional view of the area cut by line II-II' in FIG. Figure 6C is along Figure 5 A cross-sectional view of the area cut along line III-III' in FIG. Fig. 7A is shown along Figure 4A A cross-sectional view of the region cut along line IV-IV' in FIG. Figure 7B is shown along Figure 4A A cross-sectional view of the region taken along line V-V' in FIG. Figure 7C is shown along Figure 5 A cross-sectional view of the area taken along line VI-VI'.

[0038] refer to Figure 1A , Figure 1B and Figure 1C, a data storage system 1 according to an example embodiment may include a main substrate 5, a controller 10 mounted on the main substrate 5, one or more semiconductor packages 15, and a DRAM 20. The semiconductor package 15 and the DRAM 20 may be connected to the controller 10 through an interconnection pattern 25 formed on the main substrate 5.

[0039] The main substrate 5 may include a connector 30, the connector 30 including a connector coupled to an external host ( Figure 1C The number of the plurality of pins in the connector 30 and the arrangement of the plurality of pins can change the communication interface between the data storage system 1 and the external host HOST.

[0040] In example embodiments, the data storage system 1 may communicate with an external host according to an interface such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS).

[0041] In an exemplary embodiment, the data storage system 1 can be accessed by an external host ( Figure 1C The HOST in the device is operated by power supplied via connector 30.

[0042] The data storage system 1 may further include a power management integrated circuit (PMIC) that distributes power supplied from an external host HOST to the controller 10 and the semiconductor package 15 .

[0043] The controller 10 may write data to or read data from the semiconductor package 15 , and may increase the operation speed of the data storage system 1 .

[0044] The DRAM 20 may be configured as a buffer memory for alleviating a speed difference between the semiconductor package 15 as a data storage space and an external host. The DRAM 20 included in the data storage system 1 may also operate as a high-speed cache memory and may provide a space for temporarily storing data during a control operation for the semiconductor package 15. When the data storage system 1 includes the DRAM 20, the controller 10 may include a DRAM controller for controlling the DRAM 20 in addition to a NAND controller for controlling the semiconductor package 15.

[0045] The semiconductor package 15 may include a first semiconductor package 15a and a second semiconductor package 15b spaced apart from each other. Each of the first semiconductor package 15a and the second semiconductor package 15b may be configured as a semiconductor package including a plurality of semiconductor devices CH.

[0046] The semiconductor device CH may also be referred to as a semiconductor chip.

[0047] Each of the first semiconductor package 15a and the second semiconductor package 15b may include a packaging substrate 50, a semiconductor device CH on the packaging substrate 50, an adhesive layer 60 arranged on the lower surface of each semiconductor device CH, a connection structure 70 that electrically connects the semiconductor device CH to the packaging substrate 50, and a molding layer 80 on the packaging substrate 50 that covers the semiconductor device CH and the connection structure 70.

[0048] The package substrate 50 may be configured as a printed circuit board including the package on-pads 55. Each semiconductor device CH may include an input / output pad IOP.

[0049] In an example embodiment, the connection structure 70 may be configured as a bonding wire that electrically connects the input / output pad IOP to the package on-pad 55. Therefore, in each of the first semiconductor package 15a and the second semiconductor package 15b, the semiconductor devices CH may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package on-pad 55 of the package substrate 50. In an example embodiment, in each of the first semiconductor package 15a and the second semiconductor package 15b, the semiconductor devices CH may be electrically connected to each other through a connection structure including a through silicon via (TSV), rather than being electrically connected to each other through the connection structure 70 of the bonding wire method.

[0050] In example embodiments, the controller 10 and the semiconductor device CH may be included in a package. For example, the controller 10 and the semiconductor device CH may be mounted on an interposer substrate different from the main substrate 5, and the controller 10 and the semiconductor device CH may be connected to each other through interconnections formed on the interposer substrate.

[0051] Each semiconductor device CH may include a first chip structure CH_L and a second chip structure CH_U on the first chip structure CH_L.

[0052] In each semiconductor device CH, the second chip structure CH_U may include a plurality of memory array tiles MAT spaced apart from each other. In each semiconductor device CH, the second chip structure CH_U may include an input / output pad IOP.

[0053] Each semiconductor device CH may include a memory cell array MCA and a peripheral circuit PC. In each semiconductor device CH, each of the plurality of memory array tiles MAT of the second chip structure CH_U may include a memory cell array MCA, and a portion of the second chip structure CH_U and the first chip structure CH_L may include a peripheral circuit PC.

[0054] In the following description, the semiconductor device CH will be mainly described. In addition, the memory storage array tile among the plurality of memory storage array tiles MAT of the semiconductor device CH will be mainly described.

[0055] The controller 10 may write data DATA to the semiconductor device CH, or may read data DATA stored in the semiconductor device CH. The controller 10 may send a command CMD, an address ADDR, a control signal CTRL, and data DATA to the semiconductor device CH so as to write the data DATA to the semiconductor device CH. The controller 10 may send a command CMD, an address ADDR, and a control signal CTRL to the semiconductor device CH so as to read data DATA stored in the semiconductor device CH.

[0056] The semiconductor device CH may include a nonvolatile memory device (e.g., a NAND flash memory, a phase change memory (PRAM), a resistive memory (ReRAM), or a magnetoresistive memory (MRAM)). The semiconductor device CH may perform operations such as writing, reading, and erasing data DATA in response to a signal received from the controller 10.

[0057] In the second chip structure CH_U, the memory cell array MCA may be three-dimensionally arranged and may include memory cells for storing data.

[0058] refer to Figure 1D as well as Figure 1A , Figure 1B and Figure 1C In the semiconductor device CH, the second chip structure CH_U may include a plurality of memory blocks mBLK and a plurality of capacitor blocks cBLK. The plurality of memory blocks mBLK may be included in the memory cell array MCA. The plurality of capacitor blocks cBLK may be included in the capacitor array CPA. Each of the plurality of capacitor blocks cBLK may include at least one capacitor CAP.

[0059] The semiconductor device CH may include an address decoder 93 , a control logic 94 , a page buffer 95 , an input / output circuit 96 , and a voltage generator circuit 97 .

[0060] Peripheral circuits ( Figure 1C The PC in the embodiment may include an address decoder 93, a control logic 94, a page buffer 95, an input / output circuit 96, and a voltage generator circuit 97.

[0061] At least one of the address decoder 93, the control logic 94, the page buffer 95, the input / output circuit 96, and the voltage generator circuit 97 in the first chip structure CH_L may be included in a circuit together with the capacitor CAP in the second chip structure CH_U. For example, the voltage generator circuit 97 may be included in a circuit including a capacitor CAP in at least one capacitor block cBLK among a plurality of capacitor blocks cBLK. For example, the voltage generator circuit 97 may convert an externally input voltage into a level most suitable for the operation of the semiconductor device CH, and may supply power to drive each circuit. Therefore, the peripheral circuit ( Figure 1C The first chip structure CH_L may include an address decoder 93, a control logic 94, a page buffer 95, an input / output circuit 96, a voltage generator circuit 97, and a capacitor CAP. Portions of the address decoder 93, the control logic 94, the page buffer 95, the input / output circuit 96, and the voltage generator circuit 97 provided in the first chip structure CH_L may be electrically connected through a plurality of capacitor blocks cBLK and a capacitor routing interconnect CAR provided in the second chip structure CH_U.

[0062] The second chip structure CH_U may further include word lines WL, string selection lines SSL, ground selection lines GSL, bit lines BL, erase control lines ECL, and common source lines CSL. The memory cell array MCA may be connected to the word lines WL, string selection lines SSL, ground selection lines GSL, bit lines BL, erase control lines ECL, and common source lines CSL.

[0063] The memory cell array MCA may be connected to the address decoder 93 through word lines WL, string selection lines SSL, ground selection lines GSL, and common source lines CSL, and may be connected to the page buffer 95 through bit lines BL.

[0064] The address decoder 93 may select one of the plurality of memory blocks mBLK of the memory cell array MCA. The address decoder 93 may select one of the word lines WL of the selected memory block. The address decoder 93 may send a voltage provided by the voltage generator circuit 97 to the word lines WL or the selection lines SSL and GSL of the selected memory block. The address decoder 93 may transmit a positive (+) high voltage program voltage to the selected word line during a program operation, and may transmit a positive (+) high voltage erase voltage to the bulk of the selected memory block during an erase operation.

[0065] The control logic 94 may receive a command CMD and a control signal CTRL from the controller 10, and may control the address decoder 93, the page buffer 95, and the input / output circuit 96 in response to the received signals. The control logic 94 may control the voltage generator circuit 97 to generate various voltages required for the operation of the semiconductor device CH. For example, when performing a memory operation such as a program operation or an erase operation, the control logic 94 may adjust the voltage level provided through the word line WL and the bit line BL.

[0066] The voltage generator circuit 97 (which may be included in a circuit including capacitors in at least one capacitor block among the plurality of capacitor blocks cBLK) may generate voltages of various levels (e.g., a plurality of selected read voltages, a plurality of non-selected read voltages, a plurality of program pulses, a plurality of pass voltages, and a plurality of erase pulses) under the control of the control logic 94, and may provide voltages to the address decoder 93 and the memory cell array MCA. For example, the voltage generator circuit 97 may generate a positive (+) high voltage corresponding to a plurality of program pulses or a plurality of erase pulses.

[0067] The voltage generator circuit 97 may include a charge pump including at least one pumping capacitor to generate voltages of various levels as described above. The pumping capacitor of the voltage generator circuit 97 may be configured as a capacitor in at least one capacitor block among the plurality of capacitor blocks cBLK1, cBLK2, ..., cBLKm in the second chip structure CH_U.

[0068] The page buffer 95 can operate as a write driver or a sense amplifier according to the operation mode. During the read operation, the page buffer 95 can read the bit line BL of the selected memory cell under the control of the control logic 94. The read data can be stored in a latch provided in the page buffer 95. The page buffer 95 can dump the data stored in the latch to the input / output circuit 96 under the control of the control logic 94.

[0069] The input / output circuit 96 can temporarily store a command CMD, an address ADDR, a control signal CTRL, and data DATA provided from an external entity existing outside the semiconductor device CH through the input / output pad IOP. The input / output circuit 96 can temporarily store read data of the semiconductor device CH, and can output the data to the external entity through the input / output pad IOP at a specified time point.

[0070] The input / output pads IOP may include first input / output pads IOP1 connected to first capacitors in a first capacitor block among the plurality of capacitor blocks cBLK, and second input / output pads IOP2 not connected to capacitors in the plurality of capacitor blocks cBLK.

[0071] By connecting the first capacitor in the first capacitor block cBLK to the first input / output pad IOP1, noise of a signal transmitted through the first input / output pad IOP1 can be reduced. By connecting the first capacitor in the first capacitor block cBLK to the first input / output pad IOP1, the first capacitor can act as a damper when the input / output speed (IO speed) increases.

[0072] In the following description, reference will be made to Figure 2 and Figure 3 A part of the elements of the semiconductor device CH is described. Figure 2 A portion of the second chip structure CH_U is shown, mainly showing the input / output pad IOP and Figure 1B a memory cell array MCA of a memory storage array sheet adjacent to the input / output pad IOP among the plurality of memory storage array sheets MAT, and Figure 3 : is a perspective view showing a part of the elements of the semiconductor device CH.

[0073] refer to Figure 2 and Figure 3 as well as Figures 1A to 1D , the second chip structure of the semiconductor device CH ( Figure 1B The CH_U in the figure may include a stack structure ST, which includes a conductive stack region STc and an insulating stack region STi.

[0074] The second chip structure of the semiconductor device CH ( Figure 1B The CH_U) in the embodiment may further include a separation structure SP penetrating the stack structure ST in the vertical direction Z.

[0075] The separation structure SP may include a first horizontal portion SP_H extending in the first direction X, and second and third horizontal portions SP_Va and SP_Vb extending in a second direction Y perpendicular to the first direction X.

[0076] The conductive stack region STc may include a plurality of blocks mBLK, dBLK, cBLK, and STe spaced apart from one another by a separation structure SP.

[0077] The plurality of blocks mBLK, dBLK, cBLK, and STe may include reference Figure 1D A plurality of memory blocks mBLK and a plurality of capacitor blocks cBLK are described.

[0078] The plurality of blocks mBLK, dBLK, cBLK, and STe may further include at least one dummy block dBLK and an edge block STe.

[0079] The edge block STe may have a quadrangular ring shape surrounding the outside of the separation structure SP and may be in contact with the insulating stack region STi. The edge block STe may surround a plurality of memory blocks mBLK, a plurality of capacitor blocks cBLK, and at least one dummy block dBLK.

[0080] The plurality of blocks mBLK, dBLK, cBLK, and STe may include first blocks mBLK and dBLK. The plurality of capacitor blocks cBLK may be disposed between first blocks adjacent to each other among the first blocks mBLK and dBLK.

[0081] At least one dummy block dBLK may include a first dummy block dBLK_1 and a second dummy block dBLK_2. Each of the plurality of memory blocks mBLK, the first dummy block dBLK_1, and the second dummy block dBLK_2 may have a line shape extending in the first direction X. Each of the plurality of capacitor blocks cBLK may have a line shape or a bar shape extending in the first direction X. In the first direction X, a length of each of the plurality of memory blocks mBLK may be greater than a length of each of the plurality of capacitor blocks cBLK.

[0082] A plurality of memory blocks mBLK and a plurality of capacitor blocks cBLK may be disposed between the first dummy block dBLK_1 and the second dummy block dBLK_2 .

[0083] Each of the plurality of memory blocks mBLK may include a memory area MA and at least one connection area CA. For example, the at least one connection area CA may include a first connection area CA1 and a second connection area CA2 disposed on both sides of the memory area MA.

[0084] The plurality of capacitor blocks cBLK may be arranged to be spaced apart from each other in the first direction X. The plurality of capacitor blocks cBLK may include a first capacitor block cBLK1 , a second capacitor block cBLK2 , a third capacitor block cBLK3 , and a fourth capacitor block cBLK4 .

[0085] The plurality of capacitor blocks cBLK may be spaced apart from one another by the vertical portions SP_V of the separation structures SP.

[0086] A side surface of at least one capacitor block among the plurality of capacitor blocks cBLK may be surrounded by the separation structure SP. For example, an entire side surface of each capacitor block among the plurality of capacitor blocks cBLK may be surrounded by the separation structure SP.

[0087] Among the first dummy block dBLK_1 and the second dummy block dBLK_2, the first dummy block dBLK_1 may be adjacent to the plurality of capacitor blocks cBLK in the second direction Y. Among the plurality of memory blocks mBLK, the first memory block mBLKa may be adjacent to the plurality of capacitor blocks cBLK in the second direction Y. The plurality of capacitor blocks cBLK may be disposed in the second direction Y between the first memory block mBLKa and the first dummy block dBLK_1.

[0088] The first chip structure CH_L may include a plurality of lower circuits PC_1, PC_2, PC_3, and CAP_C. The plurality of lower circuits PC_1, PC_2, PC_3, and CAP_C may include a first lower circuit PC_1, a second lower circuit PC_2, a third lower circuit PC_3, and a fourth lower circuit CAP_C. The plurality of lower circuits PC_1, PC_2, PC_3, and CAP_C may be included in a peripheral circuit structure, and the plurality of lower circuits PC_1, PC_2, PC_3, and CAP_C may be configured as a peripheral circuit.

[0089] The plurality of lower circuits PC_1 , PC_2 , PC_3 , and CAP_C may overlap the plurality of blocks mBLK, cBLK, and dBLK in the vertical direction Z.

[0090] Each of the plurality of capacitor blocks cBLK may include the above-mentioned capacitor ( Figure 1D CAP in .

[0091] The first lower circuit PC_1 and the second lower circuit PC_2 may include the page buffer ( Figure 1D 95) and the address decoder ( Figure 1D For example, the first lower circuit PC_1 may include an address decoder ( Figure 1D 93), and the second lower circuit PC_2 may be included in the page buffer ( Figure 1D 95).

[0092] The third lower circuit and the fourth lower circuit ( Figure 3 At least one of PC_3 and CAP_C in the embodiment and a plurality of capacitor blocks ( Figure 3 The capacitors in the cBLK) may be included together in forming the control logic of the circuit ( Figure 1D 94 in), input / output circuit ( Figure 1D 96) and the voltage generator circuit ( Figure 1D 97) in at least one of the above, the circuit includes the above-mentioned plurality of capacitor blocks ( Figure 1D The capacitor in cBLK ( Figure 1D For example, the third lower circuit PC_3 may be included in the input / output circuit ( Figure 1D 96), and the fourth lower circuit CAP_C may be included in the control logic ( Figure 1D 94) and / or a voltage generator circuit ( Figure 1D 97).

[0093] can be configured to be electrically connected to the capacitors in the plurality of capacitor blocks cBLK ( Figure 1D The fourth lower circuit CAP_C of the CAP in the first capacitor block cBLK1 may include a first capacitor connection circuit CAP_C1 that may be configured to be electrically connected to the first capacitor in the first capacitor block cBLK1, a second capacitor connection circuit CAP_C2 that may be configured to be electrically connected to the second capacitor in the second capacitor block cBLK2, a third capacitor connection circuit CAP_C3 that may be configured to be electrically connected to the third capacitor in the third capacitor block cBLK3, and a fourth capacitor connection circuit CAP_C4 that may be configured to be electrically connected to the fourth capacitor in the fourth capacitor block cBLK4. Among the peripheral circuits, the first capacitor connection circuit CAP_C1 may be configured as a first peripheral circuit, the second capacitor connection circuit CAP_C2 may be configured as a second peripheral circuit, the third capacitor connection circuit CAP_C3 may be configured as a third peripheral circuit, and the fourth capacitor connection circuit CAP_C4 may be configured as a fourth peripheral circuit.

[0094] In the first chip structure CH_L, at least a portion of at least one of the fourth lower circuits CAP_C configured to be electrically connected to the capacitors CAP in the plurality of capacitor blocks cBLK may vertically overlap at least a portion of at least one of the plurality of capacitor blocks cBLK. For example, the first capacitor connection circuit CAP_C1 among the fourth lower circuit CAP_C, which may be a peripheral circuit, may form a circuit by being electrically connected to the first capacitor in the first capacitor block cBLK1, and the first capacitor connection circuit CAP_C1 may vertically overlap at least a portion of the first capacitor in the first capacitor block cBLK1.

[0095] In the following description, reference will be made to Figures 1A to 3 , Figure 4A , Figure 4B , Figure 5 , Fig. 6A , Figure 6B , Figure 6C , Fig. 7A , Figure 7B and Figure 7C An example embodiment of the semiconductor device CH is described below.

[0096] refer to Figures 1A to 3 , Figure 4A , Figure 4B , Figure 5 , FIG. 6A to FIG. 6C as well as 7A to 7C , the first chip structure CH_L may include a substrate SUB, a peripheral active region 203a on the substrate SUB, and a peripheral device separation region 203s defining the peripheral active region 203a on the substrate SUB. The substrate SUB may be configured as a semiconductor substrate.

[0097] The first chip structure CH_L may further include a peripheral transistor PTR, a lower interconnection structure 208 , a lower insulation structure 220 , and a lower bonding pad 214 on the substrate SUB.

[0098] Each peripheral transistor PTR may include peripheral source / drain regions pSD spaced apart from each other in the peripheral active region 203 a , a peripheral channel region PCH disposed between the peripheral source / drain regions pSD in the peripheral active region 203 a , and a peripheral gate pG on the peripheral channel region PCH.

[0099] The lower interconnect structure 208 may be electrically connected to the peripheral transistor PTR.

[0100] Will refer to it later FIG. 8A to FIG. 8D Describe the electrical connection relationship between the peripheral transistors PTR.

[0101] The lower interconnect structure 208 may include a plurality of lower horizontal portions 210 disposed at different levels and a plurality of lower vertical portions 212 disposed at different levels.

[0102] Each of the plurality of lower horizontal portions 210 may be configured as a lower interconnection line or a lower pad. For example, the plurality of lower horizontal portions 210 may be referred to as a lower interconnection or a lower pad. The plurality of lower vertical portions 212 may be referred to as a lower via or a lower contact plug.

[0103] The plurality of lower horizontal portions 210 may include a first lower horizontal portion 210 a , a second lower horizontal portion 210 b on the first lower horizontal portion 210 a , and a third lower horizontal portion 210 c on the second lower horizontal portion 210 b .

[0104] The plurality of lower vertical portions 212 may include a first lower vertical portion 212a below the first lower horizontal portion 210a, a second lower vertical portion 212b between the first lower horizontal portion 210a and the second lower horizontal portion 210b, a third lower vertical portion 212c between the second lower horizontal portion 210b and the third lower horizontal portion 210c, and a fourth lower vertical portion 212d on the third lower horizontal portion 210c.

[0105] The lower bonding pad 214 may be electrically connected to the lower interconnect structure 208 on the lower interconnect structure 208 .

[0106] The lower insulating structure 220 may cover the peripheral transistor PTR and the lower interconnection structure 208 on the peripheral active region 203a and the peripheral device separation region 203s, and may cover the side surface of the lower bonding pad 214. The upper surface of the lower insulating structure 220 may be coplanar with the upper surface of the lower bonding pad 214.

[0107] The second chip structure CH_U may include a reference Figure 2 The stacked structure ST and separated structure SP described. Figure 2 As described, the stack structure ST may include the conductive stack region STc and the insulating stack region STi, and the conductive stack region STc may include a plurality of blocks mBLK, dBLK, cBLK, and STe spaced apart from each other by the separation structure SP.

[0108] The stack structure ST may vertically overlap the peripheral circuit structure (ie, the plurality of lower circuits PC_1 , PC_2 , PC_3 , and CAP_C).

[0109] The conductive stack region STc may include insulating layers 124 and conductive layers 126 alternately and repeatedly stacked in the vertical direction Z. The insulating layer 124 may include silicon oxide. Among the insulating layers 124 and the conductive layers 126, the lowermost layer may be the lowermost insulating layer, and the uppermost layer may be the uppermost insulating layer.

[0110] In the conductive stack region STc, the conductive layer 126 disposed in the memory block mBLK may be a gate electrode, and the conductive layer 126 disposed in the capacitor block cBLK may be a capacitor electrode.

[0111] The insulating stack region STi may include a first insulating layer 120 and a second insulating layer 122 alternately and repeatedly stacked in a vertical direction Z. The first insulating layer 120 may be disposed at the same level as that of the insulating layer 124, and may include the same material as that of the insulating layer 124. The second insulating layer 122 may be disposed at the same level as that of the conductive layer 126, and may include a material different from that of the first insulating layer 120. For example, the first insulating layer 120 may include silicon oxide, and the second insulating layer 122 may include silicon nitride.

[0112] refer to Figure 2 The described separation structure SP may penetrate the conductive stack region STc in the vertical direction Z. The plurality of blocks mBLK, dBLK, cBLK, and STe may be spaced apart from each other by the separation structure SP. Therefore, the separation structure SP may separate the plurality of blocks mBLK, dBLK, cBLK, and STe.

[0113] At least one of the plurality of blocks mBLK, dBLK, cBLK, and STe may have a side surface surrounded by a separation structure SP. For example, each of the plurality of blocks mBLK, dBLK, cBLK, and STe may have a side surface surrounded by a separation structure SP. Therefore, the plurality of blocks mBLK, dBLK, cBLK, and STe may be limited by the separation structure SP.

[0114] The second chip structure CH_U may further include a plurality of vertical structures VSm, VSmd1 , VSmd2 , VScd, VSdd, VSde, and VSdi penetrating the stack structure ST.

[0115] The multiple vertical structures VS may include a vertical memory structure VSm that penetrates the storage area MA of the memory block mBLK, a vertical support structure VSmd2 that is arranged between the vertical memory structures VSm and penetrates the storage area MA of the memory block mBLK, a vertical support structure VSmd1 that penetrates the connection area CA of the memory block mBLK, a vertical support structure VSdd that penetrates at least one dummy block dBLK, a vertical support structure VScd that penetrates multiple capacitor blocks cBLK, a vertical support structure VSde that penetrates the edge block STe, and a vertical support structure VSdi that penetrates the insulating stack area STi.

[0116] In the figure observed from above, each vertical memory structure VSm may include a channel layer 108 having a ring shape, a data storage structure 106 surrounding the outer side surface of the channel layer 108, and a pad layer 112 in contact with the channel layer 108. The channel layer 108 may include a semiconductor material such as silicon. The pad layer 112 may include at least one of doped polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W, etc.), and metal-semiconductor compound (e.g., TiSi, etc.). The data storage structure 106 may include a first dielectric layer 106c, a second dielectric layer 106a, and a data storage layer 106b between the first dielectric layer 106c and the second dielectric layer 106a. The first dielectric layer 106c may include silicon oxide or silicon oxide doped with impurities. The second dielectric layer 106a may include at least one of silicon oxide and a high-k material. The data storage layer 106b may include a material (e.g., silicon nitride) that can store data by trapping charges. The data storage layer 106 b may include a region where data may be stored in a semiconductor device such as a flash memory device.

[0117] In example embodiments, the data storage structure 106 may include a data storage layer 106b that stores data by trapping charges, but example embodiments are not limited thereto. For example, the data storage structure 106 may be configured as a data storage structure used in a ferroelectric memory that can store data using remanent polarization through a dipole.

[0118] The second chip structure CH_U may further include a separation pattern 103 penetrating the conductive layer 126 or one of the plurality of lower conductive layers in the plurality of memory blocks mBLK. Figure 4B , in the figure viewed from above, the separation pattern 103 may be disposed between horizontal portions SP_H of a pair of separation structures SP adjacent to each other along the second direction Y, the vertical memory structure VSm may be disposed between the horizontal portion SP_H and the separation pattern 103, and the vertical support structure VSmd2 may be disposed in the middle region between the horizontal portions SP_H. The separation pattern 103 may vertically overlap the vertical support structure VSmd2. Each vertical memory structure VSm may vertically overlap two bit lines BL among the bit lines BL, and may be electrically connected to one of the two vertically overlapping bit lines BL.

[0119] The second chip structure CH_U may further include an upper interconnect structure 140 disposed below the stack structure ST, an upper bonding pad 148 below the upper interconnect structure 140 , and an upper insulating structure 150 covering the upper interconnect structure 140 below the stack structure ST and covering side surfaces of the upper bonding pad 148 .

[0120] The upper interconnection structure 140 may include a plurality of upper horizontal portions 142 disposed at different levels, and a plurality of upper vertical portions 144 disposed at different levels.

[0121] Each of the plurality of upper horizontal portions 142 may be an upper interconnection line or an upper pad. For example, the plurality of upper horizontal portions 142 may be referred to as an upper interconnection or an upper pad. The plurality of upper vertical portions 144 may be referred to as an upper via or an upper contact plug.

[0122] The plurality of upper horizontal portions 142 may include a first upper horizontal portion 142 a , a second upper horizontal portion 142 b below the first upper horizontal portion 142 a , and a third upper horizontal portion 142 c below the second upper horizontal portion 142 b .

[0123] The plurality of upper vertical portions 144 may include a first upper vertical portion 144a of the first upper horizontal portion 142a, a second upper vertical portion 144b between the first upper horizontal portion 142a and the second upper horizontal portion 142b, a third upper vertical portion 144c between the second upper horizontal portion 142b and the third upper horizontal portion 142c, and a fourth upper vertical portion 144d below the third upper horizontal portion 142c.

[0124] The upper bonding pad 148 may be electrically connected to the upper interconnect structure 140 under the upper interconnect structure 140 .

[0125] The upper insulating structure 150 may cover the upper interconnection structure 140 below the stacked structure ST, and may cover side surfaces of the upper bonding pads 148. A lower surface of the upper insulating structure 150 may be coplanar with a lower surface of the upper bonding pads 148.

[0126] A lower surface of the upper insulation structure 150 may contact and be bonded to an upper surface of the lower insulation structure 220 .

[0127] The lower surface of the upper bonding pad 148 may contact and bond to the upper surface of the lower bonding pad 214. The upper bonding pad 148 may include the same material as the lower bonding pad 214. For example, the upper bonding pad 148 and the lower bonding pad 214 may include copper.

[0128] The second chip structure CH_U may further include an upper plate pattern 160 c and a pad pattern 160 p on the stack structure ST, an insulating layer 170 on side surfaces of the upper plate pattern 160 c , and a capping insulating layer 174 on the plate pattern 160 c , the pad pattern 160 p , and the insulating layer 170 .

[0129] The upper plate pattern 160c may include a portion disposed on the conductive stack region STc and a portion disposed on the insulating stack region STi. The upper plate pattern 160c may be connected to the vertical memory structures VSm of the plurality of memory blocks mBLK.

[0130] Each of the upper plate pattern 160c and the pad pattern 160p may include a first layer 162 and a second layer 164 on the first layer 162. The first layer 162 may be configured as a polysilicon layer having an N-type conductivity type, and the second layer 164 may be configured as a conductive layer including at least one of a metal-semiconductor compound, a metal nitride, and a metal.

[0131] Among the upper plate pattern 160 c , a portion (eg, the first layer 162 ) connected to the vertical memory structure VSm may be configured as a common source or a common source region.

[0132] The insulating layer 170 may include an insulating material (eg, silicon oxide, a low-k material, or silicon nitride).

[0133] The second chip structure CH_U may also include the above reference Figure 1A , Figure 1B , Figure 1D and Figure 2 The input / output pad IOP may penetrate at least a portion of the capping insulating layer 174. The input / output pad IOP may be connected to the pad pattern 160p.

[0134] The second chip structure CH_U may further include contact plugs CPc1 , CPc2 , CPio, and insulating spacers 132 surrounding side surfaces of the contact plugs CPc1 , CPc2 , and CPio.

[0135] The contact plugs CPg, CPc1, CPc2, and CPio may include a gate contact plug CPg, capacitor contact plugs CPc1, CPc2, and an input / output contact plug CPio.

[0136] The gate contact plug CPg may be electrically connected to the conductive layer 126 (ie, the gate electrode) disposed in the connection area CA in the memory block mBLK.

[0137] The gate contact plug CPg may extend to different lengths below the conductive stack structure STc in a direction toward the conductive stack structure STc to contact the conductive layer 126 disposed at different levels. Fig. 7A When observing the cross-sectional structure shown in , the gate contact plug CPg may have a lower surface set at the same level below the memory block mBLK, and may extend at different lengths to contact the conductive layer 126 set at different levels relative to the level of the lower surface, and the upper surface of the gate contact plug CPg in contact with the conductive layer 126 set at different levels may be set at different levels.

[0138] The capacitor contact plugs CPc1 and CPc2 may be electrically connected to a conductive layer 126 (ie, capacitor electrodes) provided in the capacitor block cBLK.

[0139] The capacitor contact plugs CPc1 and CPc2 may extend to different lengths in a direction toward the conductive stack structure STc under the conductive stack structure STc to contact the conductive layer 126 disposed at different levels. Figure 7B and Figure 7C When observing the cross-sectional structure shown in , the capacitor contact plugs CPc1 and CPc2 may have lower surfaces set at the same level below the capacitor block cBLK, may extend at different lengths to contact the conductive layer 126 set at different levels relative to the lower surface, and the upper surfaces of the capacitor contact plugs CPc1 and CPc2 in contact with the conductive layer 126 set at different levels may be set at different levels.

[0140] The capacitor contact plugs CPc1 and CPc2 may include a capacitor contact plug CPc1 electrically connected to a first capacitor electrode of the capacitor block cBLK, and a capacitor contact plug CPc2 electrically connected to a second capacitor electrode of the capacitor block cBLK.

[0141] In the following description, for convenience of description, the first capacitor block cBLK1 and the second capacitor block cBLK2 among the capacitor blocks cBLK will be mainly described.

[0142] The capacitor contact plugs CPc1 and CPc2 may include a first capacitor contact plug CPc1a connected to a conductive layer forming a first capacitor electrode among the conductive layer 126 of the first capacitor block cBLK1, a second capacitor contact plug CPc2a connected to a conductive layer forming a second capacitor electrode among the conductive layer 126 of the first capacitor block cBLK1, a third capacitor contact plug CPc1b connected to a conductive layer forming a first capacitor electrode among the conductive layer 126 of the second capacitor block cBLK2, and a fourth capacitor contact plug CPc2b connected to a conductive layer forming a second capacitor electrode among the conductive layer 126 of the second capacitor block cBLK2.

[0143] Among the conductive layers 126 of each capacitor block cBLK, when an odd conductive layer is included in the first capacitor electrode, the first capacitor contact plug CPc1 may be connected to the odd conductive layer, and when an even conductive layer is included in the second capacitor electrode, the second capacitor contact plug CPc2 may be connected to the even conductive layer. In example embodiments, the odd layers and the even layers may be defined based on the lowest conductive layer among the conductive layers 126 stacked in the vertical direction Z.

[0144] In the example embodiment, an example is described in which the odd-numbered conductive layers form the first capacitor electrode and the even-numbered conductive layers form the second capacitor electrode among the conductive layers 126 of each capacitor block cBLK, but the example embodiment is not limited thereto. In the example, among the conductive layers 126 of each capacitor block cBLK, among a pair of conductive layers adjacent to each other in the vertical direction Z, a pair of odd-numbered conductive layers may form the first capacitor electrode, and a pair of even-numbered conductive layers provided may form the second capacitor electrode.

[0145] In example embodiments, each capacitor in the capacitor block cBLK may include a capacitor electrode and a dielectric between the capacitor electrodes, and includes the capacitor electrode ( Fig.8D CAP_E1, CAP_E2) and capacitor dielectric ( Fig.8D The capacitor of 124c ( Fig.8D The CAP in Fig.8D to understand. FIG. 8A to FIG. 8D Example embodiments of capacitors including capacitor electrodes and capacitor dielectrics are described.

[0146] The input / output contact plug CPio may penetrate the insulating stack region STi.

[0147] The upper interconnect structure 140 , the lower interconnect structure 208 , the lower bonding pads 214 , and the upper bonding pads 148 may be included in a routing interconnect structure RWS.

[0148] The input / output contact plug CPio may include a first input / output contact plug CPio1 electrically connected to the first input / output pad IOP1. The first capacitor electrode of the first capacitor in the first capacitor block cBLK1 may be electrically connected to the first input / output pad IOP1 through the first input / output contact plug CPio1 and the routing interconnect structure RWS, and the second capacitor electrode may be grounded to the ground region GND of the first chip structure CH_L through the routing interconnect structure RWS. When the input / output speed (IO speed) increases through the first input / output pad IOP1, the first capacitor in the first capacitor block cBLK1 may act as a damper.

[0149] The second chip structure CH_U may include a portion of the horizontal portions 142a, 142b and 142c of the upper interconnect structure 140 (for example, a bit line BL may include the first upper horizontal portion 142a), and a bit line contact plug BCP, which may include the first upper vertical portion 144a among the vertical portions 144a, 144b, 144c and 144d of the upper interconnect structure 140.

[0150] Each of the bit lines BL may extend in the second direction Y, and the bit lines BL may be spaced apart from each other in the first direction X. The bit lines BL may be electrically connected to the vertical memory structure VSm.

[0151] The bit line contact plug BCP may be disposed between the bit line BL and the vertical memory structure VSm, and may electrically connect the bit line BL to the vertical memory structure VSm.

[0152] The second chip structure CH_U may include a first capacitor electrode interconnect CW1a, a second capacitor electrode interconnect CW2a, a third capacitor electrode interconnect CW1b, and a fourth capacitor electrode interconnect CW2b, which may include at least a portion of the routing interconnect structure RWS. For example, the first capacitor electrode interconnects to the fourth capacitor electrode interconnects CW1a, CW2a, CW1b, and CW2b may include a portion of the horizontal portions 142a, 142b, and 142c of the upper interconnect structure 140 (e.g., the first upper horizontal portion 142a).

[0153] The first capacitor electrode interconnect CW1a may be electrically connected to the first capacitor contact plug CPc1a, and the second capacitor electrode interconnect CW2a may be electrically connected to the second capacitor contact plug CPc2a.

[0154] The third capacitor electrode interconnect CW1 b may be electrically connected to the third capacitor contact plug CPc1 b , and the fourth capacitor electrode interconnect CW2 b may be electrically connected to the fourth capacitor contact plug CPc2 b .

[0155] The input / output contact plug CPio may be electrically connected to the transistor PTRIo electrically connected to the input / output pad IOP among the peripheral transistors PTR through the routing interconnect structure RWS. The input / output contact plug CPio may include a first input / output contact plug CPio1 electrically connected to the first input / output pad IOP1, and a second input / output contact plug CPio2 electrically connected to the second input / output pad IOP2. The first input / output pad IOP1 may be electrically connected to the first peripheral transistor PTRIo1 through the first input / output contact plug CPio1 and the routing interconnect structure RWS. The second input / output pad IOP2 may be electrically connected to the second peripheral transistor PTRIo2 through the second input / output contact plug CPio2 and the routing interconnect structure RWS.

[0156] In the following description, reference will be made to Fig. 8A , Figure 8B , Figure 8C and Fig.8D describe Figures 1A to 7C The electrical connection relationship of the elements of the semiconductor device CH shown in FIG. Fig. 8A Shown is a reference Figures 1A to 7C The electrical connection relationship between the conductive layer 126 in the memory block mBLK, the electrical connection relationship between the vertical memory structures VSm, and the electrical connection relationship between the upper plate patterns 160c which may include a common source among the elements of the semiconductor device CH described, Figure 8B It shows Fig. 8A An enlarged view of a portion of area "D" in FIG. Figure 8C It shows Figures 1A to 7C A cross-sectional view of the electrical connection relationship between the conductive layers 126 in the capacitor block cBLK among the elements of the semiconductor device CH described in FIG. Fig.8D It shows Figure 8C Magnified view of area "E".

[0157] refer to Figures 1A to 7C and FIG. 8A to FIG. 8D As described above, the routing interconnect structure RWS may include the upper interconnect structure 140 , the lower interconnect structure 208 , the lower bonding pad 214 , and the upper bonding pad 148 .

[0158] The vertical memory structure VSm may be electrically connected to the first peripheral transistor PTRb among the peripheral transistors PTR through the routing interconnect structure RWS. The bit line BL may be electrically connected to the vertical memory structure VSm and may be configured as a portion of the routing interconnect structure RWS (eg, the first upper horizontal portion 142a).

[0159] The first peripheral transistor PTRb may be configured to be included in the above-mentioned peripheral circuit ( Figure 1C The page buffer in the PC Figure 1D 95) in the transistor.

[0160] In the memory block mBLK, the conductive layer 126 may include lower conductive layers 126L1 and 126L2, upper conductive layers 126U1 and 126U2, and an intermediate conductive layer 126M between the lower conductive layers 126L1 and 126L2 and the upper conductive layers 126U1 and 126U2. The lower conductive layers 126L1 and 126L2 may include a first lower conductive layer 126L1 and a second lower conductive layer 126L2 on the first lower conductive layer 126L1. The upper conductive layers 126U1 and 126U2 may include a first upper conductive layer 126U1 and a second upper conductive layer 126U2 on the first upper conductive layer 126U1.

[0161] The first lower conductive layer 126L1 and the second upper conductive layer 126U2 may be reference Figure 1D Describes the erase control line ( Figure 1D in ECL).

[0162] The second lower conductive layer 126L2 may be a reference Figure 1D Describe the string selection line SSL.

[0163] The middle conductive layer 126M may be a reference Figure 1D Described word line ( Figure 1D in WL).

[0164] The first upper conductive layer 126U1 may be a reference Figure 1D Described ground select line GSL.

[0165] The gate contact plug CPg electrically connected to the conductive layer 126 in the memory block mBLK may be electrically connected to the second transistor PTRg among the peripheral transistors PTR through the routing interconnect structure RWS.

[0166] Accordingly, a reference can be formed Figure 1D Describes the erase control line ( Figure 1D ECL in), string selection line SSL, word line ( Figure 1DThe conductive layer 126 of the ground selection line WL) and the ground selection line GSL may be electrically connected to the second transistor PTRg through the gate contact plug CPg and the routing interconnect structure RWS.

[0167] The upper plate pattern 160 c may be electrically connected to the third transistor PTRs among the peripheral transistors PTR through the source contact plug CPs and the routing interconnection structure RWS penetrating the insulating stack region STi.

[0168] The first layer 162 of the upper plate pattern 160c may be a reference Figure 1D The common source described ( Figure 1D Accordingly, the first layer 162 of the upper plate pattern 160c may be electrically connected to the third transistor PTRs through the source contact plug CPs and the routing interconnect structure RWS.

[0169] The second transistor PTRg and the third transistor PTRs may be transistors included in the address decoder 93 .

[0170] Each capacitor block cBLK may include a reference Figure 1D Here, due to the capacitor CAP Figure 8C 2 is a cross-sectional view mainly showing one capacitor block cBLK among the capacitor blocks cBLK, and thus the capacitor block cBLK will be mainly described.

[0171] In the capacitor block cBLK, the conductive layer 126 may include a first lower conductive layer 126_1, a second lower conductive layer 126_2, a third lower conductive layer 126_3, a fourth lower conductive layer 126_4, a fifth lower conductive layer 126_5, a sixth lower conductive layer 126_6, a seventh lower conductive layer 126_7, an eighth lower conductive layer 126_8, and a ninth lower conductive layer 126_9 stacked in sequence. In the drawings, nine conductive layers 126 are shown as an example embodiment, but in an example embodiment, the number of the conductive layers 126 may be more than 9.

[0172] The capacitor CAP in the capacitor block cBLK may include a first capacitor electrode CAP_E1 , a second capacitor electrode CAP_E2 , and a capacitor dielectric layer 124 c .

[0173] In the capacitor block cBLK, the first capacitor electrode CAP_E1 may include odd-numbered conductive layers 126_1, 126_3, 126_5, 126_7, and 126_9 among the conductive layer 126, and the second capacitor electrode CAP_E2 may include even-numbered conductive layers 126_2, 126_4, 126_6, and 126_8 among the conductive layer 126. In this case, the capacitor dielectric layer 124c may be an insulating layer disposed between the odd-numbered conductive layers 126_1, 126_3, 126_5, 126_7, 126_9 and the even-numbered conductive layers 126_2, 126_4, 126_6, and 126_8 among the insulating layer 124.

[0174] In example embodiments, odd numbers and even numbers may be defined with respect to a lowermost conductive layer among the conductive layers 126 stacked in the vertical direction Z.

[0175] In example embodiments, an example is described in which, among the conductive layers 126 of each capacitor block cBLK, odd conductive layers 126_1, 126_3, 126_5, 126_7, and 126_9 may be included in the first capacitor electrode CAP_E1, and even conductive layers 126_2, 126_4, 126_6, and 126_8 may be included in the second capacitor electrode CAP_E2, but example embodiments thereof are not limited thereto.

[0176] For example, among the conductive layers 126 of each capacitor block cBLK, a plurality of conductive layers included in the first capacitor electrode CAP_E1 and adjacent to each other in the vertical direction, and another pair of conductive layers included in the second capacitor electrode CAP_E2 and adjacent to each other in the vertical direction may be alternately arranged in the vertical direction. For example, the first conductive layer 126_1 and the second conductive layer 126_2, and the fifth conductive layer 126_5 and the sixth conductive layer 126_6 adjacent to each other may be included in the first capacitor electrode CAP_E1, and the third conductive layer 126_3 and the fourth conductive layer 126_4 adjacent to each other, and the seventh conductive layer 126_7 and the eighth conductive layer 126_8 adjacent to each other may be included in the second capacitor electrode CAP_E2. Here, the ninth conductive layer 126_9 may be an electrically isolated dummy layer.

[0177] In the following description, for convenience of description, an example will be described in which, among the conductive layers 126 of each capacitor block cBLK, odd conductive layers 126_1, 126_3, 126_5, 126_7, and 126_9 may be included in the first capacitor electrode CAP_E1, and even conductive layers 126_2, 126_4, 126_6, and 126_8 may be included in the second capacitor electrode CAP_E2.

[0178] The conductive layer 126 of each capacitor block cBLK may be electrically connected to the capacitor contact plug CPc.

[0179] The capacitor contact plugs CPc may include first capacitor contact plugs CPc1 connected to odd conductive layers 126_1, 126_3, 126_5, 126_7, 126_9 forming the first capacitor electrode CAP_E1, and second capacitor contact plugs CPc2 connected to even conductive layers 126_2, 126_4, 126_6, and 126_8 included in the second capacitor electrode CAP_E2.

[0180] The first capacitor contact plug CPc1 may be electrically connected through the first capacitor electrode interconnect CW1 , and the second capacitor contact plug CPc2 may be electrically connected through the second capacitor electrode interconnect CW2 .

[0181] The conductive via CCP including the first upper vertical portion 144a of the upper interconnect structure 140 of the routing interconnect structure RWS may be disposed between the first and second capacitor contact plugs CPc1 and CPc2 and the first and second capacitor electrode interconnects CW1 and CW2. Here, the conductive via CCP may also be referred to as a contact plug or a conductive pillar.

[0182] The insulating spacer 132 covering the side surface of the capacitor contact plug CPc may be disposed at a level lower than that of the conductive layer in contact with the capacitor contact plug CPc. Fig.8D The capacitor contact plug CPc shown in FIG. 1 can be electrically connected to the fifth conductive layer 126_5, the insulating spacer 132 can be provided at a level lower than that of the fifth conductive layer 126_5, and the first to fourth conductive layers 126_1, 126_2, 126_3, 126_4 provided at a level lower than that of the fifth conductive layer 126_5 and the capacitor contact plug CPc can be separated from each other. Accordingly, the capacitor contact plug CPc can be electrically connected to the conductive layer in a desired position through the insulating spacer 132.

[0183] The first capacitor electrode interconnect CW1 and the second capacitor electrode interconnect CW2 may be configured as part of the routing interconnect structure RWS. For example, the first capacitor electrode interconnect CW1 and the second capacitor electrode interconnect CW2 may include a portion of the horizontal portions 142a, 142b, and 142c of the upper interconnect structure 140 of the routing interconnect structure RWS (e.g., the first upper horizontal portion 142a).

[0184] At least one of the first capacitor electrode interconnects CW1 and the second capacitor electrode interconnects CW2 may be electrically connected to the circuit PTRc through a routing interconnect structure RWS.

[0185] The circuit PTRc configured to be electrically connected to the capacitor CAP through the first capacitor electrode interconnect CW1 and the second capacitor electrode interconnect CW2 and the routing interconnect structure RWS may include a transistor or a PN diode. Figure 8C , a portion of the circuit PTRc electrically connected to the first capacitor electrode CAP_E1 of the capacitor CAP is illustrated as a transistor, but in example embodiments, a portion of the circuit PTRc electrically connected to the first capacitor electrode CAP_E1 may be a PN diode.

[0186] The conductive stack region STc may further include a dielectric layer 127 covering the upper and lower surfaces of each conductive layer 126 and at least a portion of each side surface of the conductive layer 126. For example, the dielectric layer 127 may cover the upper and lower surfaces of the conductive layer 126, may extend to a region between the side surface of the conductive layer 126 and the side surfaces of the vertical structures VSm, VSmd1, VSmd2, VScd, VSdd, and VSde penetrating the conductive stack region STc, and may extend to a region between the insulating spacer 132 and the side surface of the conductive layer 126 horizontally adjacent to the insulating spacer 132. The contact plugs CPg and CPc may penetrate the dielectric layer 127 covering the lower surface of the conductive layer 126 and may contact the conductive layer 126.

[0187] Various modified examples of the elements of the above-described example embodiments will be described below. Various modified examples of the elements of the above-described example embodiments described below will be described focusing on the modified or replaced elements. Here, the above-described elements may be directly cited without detailed description, or the description may not be provided. In addition, the elements described below that may be modified or replaced will be described with reference to the accompanying drawings, and these elements may be combined with each other or with the above-described elements to form a semiconductor device according to an example embodiment.

[0188] In the following description, reference will be made to Fig. 9 describe Figure 4B An example in which the arrangement shape of the elements in the figure is modified. Fig. 9 It shows that Figure 4B A diagram showing an example in which the arrangement shape of elements in the figure viewed from above is modified.

[0189] refer to Fig. 9, a plurality of separation patterns 103 may be disposed between horizontal portions SP_H of a pair of separation structures SP adjacent to each other in the second direction Y. The vertical memory structures VSm may be arranged in a zigzag form in the first direction X, and may be arranged to be spaced apart from each other in the second direction Y at the same time. The distance between the centers of the bit lines BL may be substantially the same as the distance between the centers of the vertical memory structures VSm arranged in a zigzag form in the first direction X. Therefore, each of the vertical memory structures VSm arranged in a zigzag form in the first direction X may be electrically connected while vertically overlapping one of the bit lines BL.

[0190] In the following description, reference will be made to Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F and Figure 10G Various modified examples of the semiconductor device according to example embodiments are described. Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig. 10E , Fig.10F and Figure 10G It shows Fig.8D FIG. 1 is an enlarged cross-sectional view of a modified example of the enlarged cross-sectional view in FIG. In the following description, one contact plug among the capacitor contact plugs CPc will be mainly described. In the following description, the contact plug described may be one of the capacitor contact plugs CPc, but in example embodiments, the contact plug may also be one of the gate contact plugs CPg.

[0191] In the modified example, refer to Fig. 10A , the above insulating spacer ( Fig.8D The contact plug 132 may include a vertical portion 132V covering a side surface of the contact plug CPc, and a protruding portion 132P extending to a region between the insulating layers 124 adjacent to the vertical portion 132V.

[0192] In the modified example, refer to Fig. 10B , the vertical support structure VScd may include a first vertical support structure VScda that contacts an upper region of the contact plug CPc and penetrates the conductive layer 126 and the insulating layer 124 disposed at a level higher than that of the contact plug CPc. The first vertical support structure VScda may penetrate the conductive layer 126_5 in contact with the contact plug CPc and may contact the contact plug CPc.

[0193] Fig. 10B Shown as Fig. 10A The insulating spacer 132a in FIG. 1 is shown in FIG. Fig.8D In the drawings, when an element that can be modified or replaced as described above is shown, the element can be understood from the above-described modified example even if there is no description thereof.

[0194] In the modified example, refer to Fig. 10C , Fig. 10B 1 and 2 show one contact plug CPc in contact with one first vertical support structure VScda, but example embodiments thereof are not limited thereto. For example, a single contact plug CPc may be modified to contact a plug CPc_1 in contact with a plurality of first vertical support structures VScdb. Each of the plurality of first vertical support structures VScdb may be in contact with a reference Fig. 10B The described first vertical support structure VScda is essentially the same.

[0195] In the modified example, refer to Fig. 10D , the first vertical support structure ( Fig. 10C The VScdb) in FIG. 1 may be modified into a first vertical support structure VScdc extending downward from an upper region of the contact plug CPc_1 to a level lower than that of the first conductive layer 126_1.

[0196] In the modified example, refer to Fig. 10E , the contact plug ( Fig. 10C The contact plug CPc_1) in FIG. 1 may be replaced with a contact plug CPc_2 having a shape covering the side surface and the upper surface of the insulating pillar 181. The contact plug CPc_2 may have a shape covering the lower surface of the first vertical support structure VScdb.

[0197] In the modified example, refer to Fig.10F The contact plug CPc_2 may make contact with a conductive pad 183 covering a lower surface of the insulating pillar 181. The conductive pad 183 may be disposed at a level lower than that of the first conductive layer 126_1 and may be electrically connected to the conductive via CCP.

[0198] In the modified example, refer to Figure 10G , the contact plug ( Fig. 10BCPc) in the figure can be replaced by an insulating column 181, a first contact plug CPc_3b covering the side surface and the upper surface of the insulating column 181 and in contact with the desired conductive layer 126_6, an insulating spacer 131 covering the outer surface of the first contact plug CPc_3b, and a second contact plug CPc_3a disposed on the outer surface of the insulating spacer 131 and in contact with a conductive layer 126_5 disposed immediately below the conductive layer 126_6 in contact with the first contact plug CPc_3b. Therefore, the conductive layers 126_5 and 126_6 adjacent to each other in the vertical direction can be connected to the contact structure including the first contact plug CPc_3b and the second contact plug CPc_3a. Figure 10G In the embodiment, the first contact plug CPc_3b and the second contact plug CPc_3a may be electrically connected to the conductive via CCP, respectively. However, in example embodiments, the first contact plug CPc_3b and the second contact plug CPc_3a may be electrically connected to one conductive via CCP.

[0199] In the following description, reference will be made to Fig.11 Describes the vertical memory structure described previously ( Figure 8B VSm in) and the first layer of the upper plate pattern 160c ( Figure 8B A modified example of 162) in FIG. Fig.11 It shows Figure 8B An enlarged sectional view of a modified example of the enlarged view in FIG.

[0200] In the modified example, refer to Fig.11 , the first layer of the upper plate pattern 160c ( Figure 8B 162) in the embodiment may include a first material layer 161a, a second material layer 161b on the first material layer 161a, and a third material layer 161c on the second material layer 161b.

[0201] In the vertical memory structure VSm, the data storage structure 106a can cover the side surface and the upper surface of the channel layer 108, the first material layer 161a can cover the side surface of the data storage structure 106a on the uppermost insulating layer among the insulating layers 124, the second material layer 161b can penetrate the data storage structure 106a and can contact the channel layer 108, and the third material layer 161c can be separated from the channel layer 108 through the data storage structure 106a.

[0202] At least one of the first to third material layers 161 a , 161 b , and 161 c may include doped silicon.

[0203] In the following description, reference will be made to FIG. 12A to FIG. 12C The description may include the above capacitor routing interconnect ( Figure 6BVarious examples of routing interconnect structure RWS in CAR). FIG. 12A to FIG. 12C It shows Figure 6B Cross-sectional views of various modified examples of the cross-sectional structure in, Figure 6B shows where the “capacitor routing interconnect ( Figure 6B The CAR in FIG. 1 may form an example of a first upper horizontal portion 142a" of the horizontal portions 142a, 142b, and 142c of the upper interconnect structure 140 among the routing interconnect structure RWS.

[0204] In the modified example, refer to Fig. 12A , capacitor routing interconnect ( Figure 6B The CAR in the routing interconnect structure RWS may include a second horizontal portion 142b of the horizontal portions 142a, 142b, and 142c of the upper interconnect structure 140 among the routing interconnect structure RWS.

[0205] In the modified example, refer to Fig. 12B , capacitor routing interconnect ( Figure 6B The CAR in the routing interconnect structure RWS may include a third horizontal portion 142c of the horizontal portions 142a, 142b and 142c of the upper interconnect structure 140 among the routing interconnect structure RWS.

[0206] In the modified example, refer to Fig. 12C , capacitor routing interconnect ( Figure 6B The CAR in the routing interconnect structure RWS may include a third horizontal portion 210c of the horizontal portions 210a, 210b and 210c of the lower interconnect structure 208 among the routing interconnect structure RWS.

[0207] In the modified example, refer to Fig.12D , capacitor routing interconnect ( Figure 6B The CAR in the routing interconnect structure RWS may include a second horizontal portion 210b among the horizontal portions 210a, 210b and 210c of the lower interconnect structure 208 among the routing interconnect structure RWS.

[0208] In the following description, reference will be made to Fig.13 , Fig.14A and Fig. 14B Modified examples of the capacitor block cBLK in the semiconductor device according to example embodiments are described. Fig.13 It is shown that Figure 4A The diagram of the modified element in the corresponding figure, Fig.14A Shown along Fig.13 The area intercepted by the line Ia-Ia' in FIG. Fig. 6A A cross-sectional view of the modified element in the corresponding cross-sectional structure, and Fig. 14B Shown along Fig.13 The area intercepted by line IIa-IIa' in FIG. Figure 6B Cross-sectional view of the modifying element in the corresponding cross-sectional structure.

[0209] refer to Fig.13 , Fig.14A and Fig. 14B , in the capacitor block cBLK, the capacitor contact plugs CPc1' electrically connected to the conductive layer 126 may be electrically connected to each other through the first capacitor electrode interconnect CW1'. Accordingly, in the capacitor block cBLK, the conductive layer 126 may be a first capacitor electrode.

[0210] In the capacitor block cBLK, the support structure VScd penetrating the conductive stack region STc in the capacitor block cBLK may be replaced with an electrode plug CPc2' and a dielectric layer 133 covering the side and upper surfaces of the electrode plug CPc2'. The electrode plug CPc2' may be electrically connected through the second capacitor electrode interconnect CW2'. Accordingly, the electrode plug CPc2' may be a second capacitor electrode.

[0211] Accordingly, the capacitors in the capacitor block cBLK ( Figure 1D The CAP in FIG. 1 may include a first capacitor electrode including a conductive layer 126, a second capacitor electrode including an electrode plug CPc2′, and a dielectric layer 133 between the first capacitor electrode and the second capacitor electrode.

[0212] The above-described upper plate pattern 160 c may cover the capacitor CAP of the capacitor block cBLK, but in example embodiments, the upper plate pattern 160 c may be modified to not cover the upper plate pattern 160 c ′ of the capacitor CAP of the capacitor block cBLK.

[0213] In the following description, reference will be made to Fig.15 , Fig.16A and Fig. 16B Modified examples of the memory block mBLK and the capacitor block cBLK in the semiconductor device according to example embodiments are described. Fig.15 It shows that according to Figure 4A The corresponding figure is the figure of the element modified, Fig.16A Shown along Fig.15 The area intercepted by line IVa-IVa' in Fig. 16B Shown along Fig.15 The area intercepted by line Vb-Vb' in.

[0214] refer to Fig.15 , Fig.16A and Fig. 16B, wherein the conductive stack region STc provided with the above-mentioned gate contact plug CPg and capacitor contact plug CPc may be modified into a conductive stack region STc', the conductive stack region STc' being arranged in a staircase shape and including a conductive layer 126 having pad regions PADg and PADc connected to the contact plugs CPg and CPc. Accordingly, the above-mentioned memory block mBLK may be modified into a memory block mBLK', the memory block mBLK' including a conductive layer 126 including a gate pad region PADg arranged in a staircase shape, and the above-mentioned capacitor block cBLK may be modified into a capacitor block cBLK', the capacitor block cBLK' including a conductive layer 126 including a capacitor pad region PADc arranged in a staircase shape.

[0215] The capacitor pad region PADc may be electrically connected to the capacitor contact plug CPc, and the gate pad region PADg may be electrically connected to the gate contact plug CPg.

[0216] In the following description, reference will be made to Fig.17 Modified examples of the capacitor block cBLK in the semiconductor device according to example embodiments are described. Fig.17 It can be shown along Fig.15 The area intercepted by line Vb-Vb' in.

[0217] refer to Fig.17 , refer to above Figures 1A to 16B In the described exemplary embodiment, the capacitor (FIG. 1 and Fig.8D The conductive layer 126 in the capacitor block cBLK can be used as the above capacitor electrode (CAP) Fig.8D CAP_E1, CAP_E2 in FIG. 1 ), but the exemplary embodiments are not limited thereto. For example, in order to adjust the capacitor ( FIG. 1 and Fig.8D The above capacitor block cBLK can be modified to use only a portion of the conductive layer 126 as a capacitor electrode ( Fig.8D For example, among the conductive layers 126 in the capacitor block cBLK', the lower conductive layer disposed in the lower region may be used as a capacitor electrode ( Fig.8D CAP_E1 and CAP_E2 in the capacitor block cBLK', and among the conductive layers 126 in the capacitor block cBLK', the upper conductive layer disposed in the upper region may be not used as a capacitor electrode ( Fig.8D A dummy conductive layer of CAP_E1 and CAP_E2 in FIG.

[0218] In the following description, reference will be made to Fig.18 and Fig.19 A modified example of the capacitor block cBLK is described. Fig.18 and Fig.19 It shows Figure 2 FIG. 1 is a diagram of a modified example of the capacitor block cBLK in FIG.

[0219] In the modified example, refer to Fig.18 , at least a portion of the first to fourth capacitor blocks cBLK1, cBLK2, cBLK3, and cBLK4 among the capacitor blocks cBLK may have different lengths in the first direction X. For example, in the first direction X, the second capacitor block cBLK2 may have a first length L1, and the third capacitor block cBLK3 may have a second length L2 that is smaller than the first length L1.

[0220] In the modified example, refer to Fig.19 , in the second direction Y, each memory block mBLK may have a first width W1, and at least one of the first to fourth capacitor blocks cBLK1, cBLK2, cBLK3, and cBLK4 of the capacitor blocks cBLK may have a second width W2 different from the first width W1. The second width W2 may be greater than the first width W1, but example embodiments thereof are not limited thereto. For example, the second width W2 may be less than the first width W1.

[0221] In the following description, reference will be made to Fig. 20 A modified example of the capacitor block cBLK is described. Fig. 20 is shown in which a device is provided which can be electrically connected to Figure 3 The perspective view of the capacitors in the multiple capacitor blocks cBLK ( Figure 1D 0 is a perspective view of a modified example of a region of a fourth lower circuit CAP_C of the CAP in FIG.

[0222] In the modified example, refer to Fig. 20 , a portion of the first capacitor connection circuit CAP_C1', which can be configured to be electrically connected to the capacitors in the first capacitor block cBLK1, a second capacitor connection circuit CAP_C2', which can be configured to be electrically connected to the capacitors in the second capacitor block cBLK2, a third capacitor connection circuit CAP_C3', which can be configured to be electrically connected to the capacitors in the third capacitor block cBLK3, and a fourth capacitor connection circuit CAP_C4', which can be configured to be electrically connected to the capacitors in the fourth capacitor block cBLK4, may vertically overlap with a portion of the capacitor block cBLK, and another portion may not vertically overlap with the capacitor block cBLK.

[0223] For example, it may be configured to be electrically connected to the capacitors in the first capacitor block cBLK1 ( Figure 1DThe first capacitor connection circuit CAP_C1′ of the capacitor block cBLK1 may vertically overlap with the first capacitor block cBLK1, and the second to fourth capacitor connection circuits CAP_C2′, CAP_C3′, and CAP_C4′ may not vertically overlap with the capacitor block cBLK1.

[0224] At least one of the second capacitor connecting circuit CAP_C2 ′ and the third capacitor connecting circuit CAP_C3 ′ may be adjacent to the first lower circuit PC_1 or surrounded by the first lower circuit PC_1 .

[0225] The fourth capacitor connecting circuit CAP_4 ′ may be adjacent to the second lower circuit PC_2 or may be surrounded by the second lower circuit PC_2 .

[0226] Reference above Figures 2 to 20 The example embodiments described are centered around the Figure 1B The semiconductor device CH described herein has a plurality of memory storage array chips ( Figure 1B The present invention is described with reference to a memory storage array slice MAT in the MAT in the embodiment of the present invention. However, the exemplary embodiments thereof are not limited thereto. In the following description, the first memory array slice and the second memory array slice adjacent to each other in the first direction will be mainly described.

[0227] First, in reference Figure 1B Described multiple memory storage array slices ( Figure 1B In MAT), reference Fig.21A and Fig.21B An exemplary embodiment of a semiconductor device CH including a first memory array tile MAT1 and a second memory array tile MAT2 adjacent to each other in a first direction is described. Fig.21A and Fig.21B middle, Fig.21A is a diagram showing an example embodiment of a semiconductor device CH, and Fig.21B is a perspective view showing an example embodiment of a semiconductor device CH.

[0228] refer to Fig.21A and Fig.21B The semiconductor device CH may include a first memory array chip MAT1 and a second memory array chip MAT2 adjacent to each other in a first direction X. Each of the first memory array chip MAT1 and the second memory array chip MAT2 may include a reference Figures 2 to 20 The first chip structure CH_L and the second chip structure CH_U are described.

[0229] As reference Figures 2 to 20 As described, the second chip structure CH_U may include reference Figures 2 to 20 The multiple blocks cBLK, mBLK and dBLK are described.

[0230] The second chip structure CH_U may further include an intermediate block iBLK disposed between the first memory array tile MAT1 and the second memory array tile MAT2 .

[0231] refer to Figures 2 to 20 The described separation structure SP may be modified to define a plurality of blocks cBLK, mBLK, and dBLK within the first memory array tile MAT1 and the second memory array tile MAT2, extend to an area between the first memory array tile MAT1 and the second memory array tile MAT2, and define a separation structure SPi of an intermediate block iBLK. Figures 2 to 20 The conductive stack area STc described may be modified to a conductive stack area STca including a plurality of blocks cBLK, mBLK, and dBLK in the first memory array sheet MAT1 and the second memory array sheet MAT2, an intermediate block iBLK, and an edge block STe having a quadrangular ring shape surrounding the outer side surface of the separation structure SPi. Each of the plurality of blocks cBLK, mBLK, dBLK, the intermediate block iBLK, and the edge block STe may include a reference Figures 2 to 20 The insulating layer 124 and the conductive layer 126 are described. The insulating stack region STi may have a shape surrounding the outer side of the conductive stack region STca. Accordingly, the semiconductor device CH may include a stack structure ST' including the conductive stack region STca and the insulating stack region STi.

[0232] The plurality of lower circuits PC_1 , PC_2 , PC_3 and CAP_C may be disposed under the first memory array chip MAT1 and the second memory array chip MAT2 , respectively.

[0233] In example embodiments, the intermediate block iBLK may be a dummy block, but example embodiments thereof are not limited thereto. At least a portion of the intermediate block iBLK may be configured as a capacitor block cBLK.

[0234] Therefore, when at least a portion of the intermediate block iBLK is a capacitor block, the capacitor block ( Figure 1D The capacitor block cBLK in the first memory array tile MAT1 and the second memory array tile MAT2 may include a capacitor block cBLK included in the first memory array tile MAT1 and the second memory array tile MAT2, and a capacitor block iBLK provided between the first memory array tile MAT1 and the second memory array tile MAT2.

[0235] In the following description, reference will be made to Fig.22A , Fig. 22B and Fig.23 Describe the middle block ( Fig.21A and Fig. 21B iBLK) is included in the capacitor ( Figure 1DAn example embodiment in which the capacitor block cBLK of the CAP in FIG. 5 is replaced. Fig.22A is a diagram showing an example embodiment of a semiconductor device CH, Fig. 22B is a perspective view showing an example embodiment of a semiconductor device CH, and Fig.23 is shown along Fig. 22B A cross-sectional view of the area intercepted by line XX'.

[0236] refer to Fig.22A , Fig. 22B and Fig.23 ,refer to Fig.21A and Fig. 21B The middle block described ( Fig.21A and Fig. 21B At least one of the iBLK in the capacitor block can be replaced by a capacitor block cBLK. Fig.22A , Fig. 22B and Fig.23 In the embodiment, the first memory array tile MAT1 and the second memory array tile MAT2 may not include the capacitor block cBLK, but as described in the aforementioned example embodiments, in example embodiments, the first memory array tile MAT1 and the second memory array tile MAT2 may include the capacitor block cBLK.

[0237] The capacitor block cBLK may be disposed between the blocks mBLK and dBLK of the first memory array tile MAT1 and the blocks mBLK and dBLK of the second memory array tile MAT2 .

[0238] Each of the capacitor blocks cBLK may have a bar shape extending in the first direction X. The capacitor blocks cBLK may be spaced apart from each other in the second direction Y by the separation structures SPi.

[0239] Each capacitor block cBLK disposed between the first memory array tile MAT1 and the second memory array tile MAT2 may include a capacitor block cBLK as shown in FIG. Figures 2 to 20 The insulating layer 124 and the conductive layer 126.

[0240] As described above, the conductive layer 126 that may form the capacitor electrode in the capacitor block cBLK may be electrically connected to the capacitor contact plug CPc. The capacitor contact plug CPc may be electrically connected through the capacitor electrode interconnect CW.

[0241] Each of the first and second memory array chips MAT1 and MAT2 may include the upper plate pattern 160c described above. The upper plate pattern 160c of the first and second memory array chips MAT1 and MAT2 may be spaced apart from each other in the first direction X.

[0242] As described above, the first chip structure CH_L may include a fourth lower circuit CAP_C, which may be configured to be electrically connected to the capacitors in the plurality of capacitor blocks cBLK ( Figure 1D At least a portion of the fourth lower circuit CAP_C may vertically overlap at least a portion of the plurality of capacitor blocks cBLK.

[0243] In the following description, reference will be made to Fig.24 , Fig.25 , Fig.26A , Fig.26B , Fig.26C , Fig.27A and Fig.27B Modified examples of the semiconductor device according to the example embodiment are described. Fig.24 is a diagram showing a modified example of the semiconductor device CH, Fig.25 is a perspective view showing a modified example of the semiconductor device CH, Fig.26A It shows Fig.24 A magnified view of area "Aa" in Fig.26B It shows Fig.24 A magnified view of region “Ba” in Fig.26C It shows Fig.26B Magnified view of area “Baa” in FIG. Fig.27A is shown along Fig.26A A cross-sectional view of the region taken along line VI-VI' in FIG. Fig.27B is shown along Fig.26B A cross-sectional view of the area cut along line VII-VII' in FIG.

[0244] refer to Figures 24 to 27B ,refer to Figures 2 to 20 The capacitor block cBLK described above may be disposed between the dummy block dBLK and the first memory block mBLKa adjacent to each other in the second direction Y, but example embodiments thereof are not limited thereto. Figures 24 to 27B As shown in the figure, the capacitor block ( Figure 1D The memory blocks mBLK in the second direction Y may be disposed between the plurality of memory blocks mBLK, and the plurality of memory blocks mBLK in the memory blocks mBLK are parallel to each other and spaced apart from each other in the second direction Y.

[0245] As described above, in the first chip structure CH_L, the capacitors ( Figure 1D At least a portion of a fourth lower circuit CAP_C of the capacitor block CAP in the capacitor block CAP_C may vertically overlap at least a portion of the plurality of capacitor blocks cBLK and may be disposed between the first lower circuit PC_1 and the second lower circuit PC_2.

[0246] The above-mentioned upper plate pattern 160 c may cover an upper portion of the stack region STc in the memory block mBLK, and may cover an upper portion of the stack region STc of the capacitor block cBLK.

[0247] The above-mentioned bit line BL may intersect the plurality of memory blocks mBLK in the second direction Y. Therefore, the bit line BL may intersect the plurality of memory blocks mBLK and the capacitor block cBLK disposed between the plurality of memory blocks mBLK.

[0248] Each capacitor block cBLK may include a reference Figures 2 to 20 The insulating layer 124 and the conductive layer 126. As described above, the conductive layer 126 that may form the capacitor electrode in the capacitor block cBLK may be electrically connected to the capacitor contact plug CPc. The capacitor contact plug CPc may be electrically connected through the capacitor electrode interconnects CW1 and CW2.

[0249] The upper interconnection structure 140 may further include an upper horizontal portion 142c that may be disposed at a level higher than that of the first upper horizontal portion 142a that may be included in the bit line BL. The upper horizontal portion 142c may be included in the capacitor electrode interconnections CW1 and CW2.

[0250] The vertical portion 144 of the upper interconnect structure 140 may also include a first upper vertical portion and a second upper vertical portion, wherein the first upper vertical portion forms a first contact plug CP between the capacitor electrode interconnects CW1 and CW2 and the capacitor contact plug CPc to electrically connect the capacitor electrode interconnects CW1 and CW2 to the capacitor contact plug CPc, and the second upper vertical portion passes between the bit lines BL under the capacitor electrode interconnects CW1 and CW2 and forms a second contact plug cPL electrically connected to the interconnect including the second horizontal portion 142b.

[0251] The bit lines BL may be parallel to each other at a predetermined distance in the memory block mBLK, and the distance between the bit lines BL may be increased so that the second contact plug cPL may pass between the bit lines BL in the region where the second contact plug cPL is disposed. Accordingly, among the bit lines BL, the bit line BL adjacent to the second contact plug cPL may have a line shape extending in the second direction Y on the memory block mBLK, and may have a bent shape on the capacitor block cBLK.

[0252] In the following description, reference will be made to Fig.28 An example embodiment of a method of forming the above-described semiconductor device CH is described.

[0253] refer to Fig.28 Figures 1 to Fig.27B , a first semiconductor chip may be formed (S10). The first semiconductor chip may be a semiconductor chip as shown in FIG. Fig.27B The first chip structure CH_L in the example embodiment described above may be formed into a second semiconductor chip (S20). The second semiconductor chip may include the semiconductor structure CH_L in the example embodiment described above. Fig.27B 1 to 3. Fig.27B The stacked structure ST, the vertical structure VS, the upper bonding pad 148 and the upper interconnect structure 140 in the second chip structure CH_U in the described example embodiment, the stacked structure ST includes an insulating stack region STi and a conductive stack region STc, and the conductive stack region STc includes a plurality of blocks mBLK, dBLK and cBLK.

[0254] The first semiconductor chip and the second semiconductor chip may be bonded to each other (S30). Bonding the first semiconductor chip to the second semiconductor chip may include: bonding a lower bonding pad ( Fig. 6A 214 in) and the upper bonding pad ( Fig. 6A 148) performs a metal-to-metal bonding process.

[0255] An upper structure including an input / output pad IOP may be formed (S40). The upper structure may further include an upper plate pattern 160c.

[0256] Will refer to Fig.29 An electronic system including a semiconductor device according to example embodiments is described. Fig.29 is a diagram illustrating an electronic system including a semiconductor device according to example embodiments.

[0257] refer to Fig.29 , an electronic system 1000 according to an example embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be configured as a storage device including one or more semiconductor devices 1100, or an electronic device including a storage device. For example, the electronic system 1000 may be configured as a solid state drive device (SSD device), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0258] The semiconductor device 1100 may be configured as described in reference to FIG. Fig.28 A nonvolatile memory device according to one of the example embodiments is described. A semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0259] In example embodiments, the first structure 1100F may be the first chip structure CH_L of any one of the above-described example embodiments, and the second structure 1100S may be the second chip structure CH_U of one of the above-described example embodiments.

[0260] The first chip structure 1100F may be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. In example embodiments, the peripheral circuit 14 of the first chip structure 1100F of one of the above-described example embodiments may be configured as a peripheral circuit structure including the decoder circuit 1110, the page buffer 1120, and the logic circuit 1130.

[0261] The second chip structure 1100S may be configured as a memory vertical structure including a bit line BL, a common source line CSL, a word line WL, first and second gate upper lines UL1 and UL2, first and second gate lower lines LL1 and LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0262] In example embodiments, at least a portion of the above-mentioned upper plate pattern 160 c may be included in the common source line CSL.

[0263] In example embodiments, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be the conductive layer 126 of the memory block mBLK of any one of the above-described example embodiments. Accordingly, the conductive layer 126 of the memory block mBLK may include the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2. The first and second gate lower lines LL1 and LL2 and at least a portion of the first and second gate upper lines UL1 and UL2 may be selected gate electrodes.

[0264] In the second chip structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In example embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be modified in various ways. The plurality of memory cell transistors MCT may include a data storage area in which data DATA may be stored.

[0265] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The gate lower lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0266] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used in an erase operation to erase data stored in the memory cell transistor MCT using a gate induced drain leakage (GIDL) phenomenon.

[0267] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first interconnect 1115 extending from the first chip structure 1100F to the second chip structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second interconnect 1125 extending from the first structure 1100F to the second structure 1100S.

[0268] In the first chip structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by the logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output interconnect 1135 extending from the first chip structure 1100F to the second chip structure 1100S. The input / output pad 1101 may be the above-mentioned input / output pad IOP.

[0269] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0270] The processor 1210 may control the overall operation of the electronic system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a NAND interface 1221 that processes communication with the semiconductor device 1100. A control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be transmitted through the NAND interface 1221. The host interface 1230 may provide a communication function between the electronic system 1000 and an external host. When a control command is received from an external host through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0271] According to the aforementioned example embodiments, a semiconductor device including a capacitor block disposed at the same level as that of a memory block, and a data storage system including the semiconductor device can be provided. Since the capacitor block can form a capacitor electrode using a conductive layer disposed at the same level as that of a conductive layer in the memory block, a high-capacity capacitor can be provided. Accordingly, in a plan view, the area occupied by the high-capacity capacitor can be reduced, thereby improving the integration density of the semiconductor device.

[0272] In addition, since the capacitors in the capacitor block and the peripheral circuits can be arranged to overlap vertically, the signal path electrically connecting the capacitors to the peripheral circuits can be reduced. Therefore, RC (resistance-capacitance) delay can be reduced, so that the performance of the semiconductor device can be improved.

[0273] In addition, among the plurality of capacitor blocks, the first capacitor in the first capacitor block may be configured to be electrically connected to the first input / output pad. Therefore, when the input / output speed (IO speed) increases, the first capacitor in the first capacitor block electrically connected to the first input / output pad may act as a damper.

[0274] In addition, the blocks including the capacitor block, the dummy block, and the memory block can be spaced apart from each other by the separation structure. Therefore, the distance between the blocks can be reduced, so that the integration density of the semiconductor device can be improved.

[0275] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

[0276] As used herein, expressions such as "at least one of..." following a list of elements modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination of two or more of A, B, and C. Similarly, A and / or B means A, B, or A and B.

[0277] Any functional blocks shown in the figures and described above may be implemented in a processing circuit (e.g., hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof). For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0278] In various example embodiments herein, reference may be made to various circuit elements, including but not limited to capacitors, resistors, inductors, switches, amplifiers, comparators, filters, and transistors. Various types of digital components, analog components, active components, and / or passive components may be used to implement example embodiments. For example, as described above, pseudo resistors may replace passive resistors. In addition, various transistor types may be used depending on the implementation, whether positive or negative logic is used, the manufacturing process employed, etc. In addition, unless otherwise specifically described herein, there are filters, comparators, switches, etc. of many available types that may be used to implement example embodiments.

Claims

1. A semiconductor device, comprising: Peripheral circuit structure; a stacked structure vertically overlapping the peripheral circuit structure; as well as A separation structure, penetrating the stacking structure, wherein the stacked structure comprises a plurality of blocks separated from each other by the first portion of the separation structure, wherein each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and The plurality of blocks include a first block and a plurality of capacitor blocks, and the plurality of capacitor blocks are arranged between first blocks adjacent to each other among the first blocks.

2. The semiconductor device according to claim 1, in, The plurality of capacitor blocks are spaced apart from each other by a second portion of the separation structure, wherein each of the plurality of capacitor blocks comprises a capacitor, and The capacitor includes a capacitor electrode and a capacitor dielectric layer, the capacitor electrode includes the conductive layer, and the capacitor dielectric layer includes the insulating layer.

3. The semiconductor device according to claim 2, in, The peripheral circuit structure includes a first peripheral circuit, and The first peripheral circuit is included in a circuit by being electrically connected to a first capacitor in a first capacitor block among the plurality of capacitor blocks, and the first peripheral circuit vertically overlaps at least a portion of the first capacitor.

4. The semiconductor device according to claim 1, wherein: A side surface of at least one capacitor block among the plurality of capacitor blocks is surrounded by the separation structure.

5. The semiconductor device according to claim 1, wherein Each of the plurality of blocks has a side surface surrounded by the separation structure.

6. The semiconductor device according to claim 1, in, The first block includes a plurality of memory blocks and at least one dummy block, and The conductive layers in the plurality of memory blocks include word lines.

7. The semiconductor device according to claim 6, in, The plurality of memory blocks include a first memory block adjacent to the plurality of capacitor blocks, and The plurality of capacitor blocks are disposed between the first memory block and the at least one dummy block.

8. The semiconductor device according to claim 6, further comprising: a vertical memory structure penetrating the plurality of memory blocks; a first vertical support structure penetrating the plurality of capacitor blocks; as well as A bit line electrically connected to the vertical memory structure, At least a portion of the plurality of capacitor blocks does not overlap with the bit line in the vertical direction.

9. The semiconductor device according to claim 6, in, The plurality of memory blocks include a plurality of first memory blocks and a plurality of second memory blocks, and The plurality of capacitor blocks are disposed between the plurality of first memory blocks and the plurality of second memory blocks.

10. The semiconductor device according to claim 9, further comprising: a vertical memory structure penetrating the memory block; as well as A bit line electrically connected to the vertical memory structure, At least one of the plurality of capacitor blocks overlaps the bit line in the vertical direction.

11. The semiconductor device according to claim 1, in, Each of the first blocks extends in a first direction, wherein the plurality of capacitor blocks are arranged between first blocks adjacent to each other along a second direction perpendicular to the first direction, and The plurality of capacitor blocks are spaced apart from each other in the second direction.

12. The semiconductor device according to claim 1, further comprising: A signal path connects the peripheral circuit structure to a capacitor block of the plurality of capacitor blocks.

13. A semiconductor device comprising: A first chip structure; as well as a second chip structure vertically overlapping the first chip structure, Wherein, the first chip structure includes a peripheral circuit, Wherein, the second chip structure comprises: Stacked structure; A separation structure penetrating the stacking structure; a plurality of contact plugs; and Input / output pads, wherein the stacked structure comprises a plurality of blocks spaced apart from each other, wherein each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, wherein the plurality of blocks include a plurality of memory blocks and capacitor blocks, Wherein, the first chip structure and the second chip structure further include a routing interconnection structure between the peripheral circuit and the stacking structure, wherein the plurality of contact plugs include a first input / output contact plug penetrating the stack structure, and the first input / output contact plug is electrically connected to a first input / output pad among the input / output pads, wherein the capacitor block includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode includes a plurality of first conductive layers among the conductive layers, and the second capacitor electrode includes a plurality of second conductive layers among the conductive layers, and Wherein, the first capacitor electrode is electrically connected to the first input / output pad through the first input / output contact plug and the routing interconnect structure.

14. The semiconductor device according to claim 13, wherein: The second capacitor electrode is grounded to a ground region of the first chip structure through the routing interconnect structure.

15. The semiconductor device according to claim 13, in, The routing interconnect structure of the first chip structure includes a lower interconnect structure, the lower interconnect structure includes a lower vertical portion disposed at different levels, and a lower horizontal portion disposed at different levels, The routing interconnect structure of the second chip structure includes an upper interconnect structure, the upper interconnect structure includes an upper vertical portion arranged at different levels, and an upper horizontal portion arranged at different levels, and Wherein, at least one of the lower horizontal portion and the upper horizontal portion of the routing interconnect structure is included in a capacitor routing interconnect that electrically connects the first capacitor electrode to the first input / output pad.

16. The semiconductor device according to claim 15, in, The plurality of contact plugs include: a first capacitor contact plug connected to the plurality of first conductive layers included in the first capacitor electrode; and a second capacitor contact plug connected to the plurality of second conductive layers included in the second capacitor electrode, and Wherein, the routing interconnection structure of the second chip structure further includes: first capacitor interconnects electrically connecting the first capacitor contact plugs to each other, and The second capacitor interconnects electrically connect the second capacitor contact plugs to each other.

17. The semiconductor device according to claim 15, in, The routing interconnect structure of the first chip structure further includes a lower bonding pad on the lower interconnect structure, and The routing interconnect structure of the second chip structure further includes an upper bonding pad, which is disposed below the upper interconnect structure and bonded to the lower bonding pad.

18. The semiconductor device according to claim 15, in, The separation structure surrounds the side surface of the capacitor block, and Among the plurality of blocks, a block adjacent to the capacitor block is separated from the capacitor block by the separation structure.

19. A data storage system comprising: A semiconductor device including an input / output pad; as well as a controller electrically connected to the semiconductor device through the input / output pad and controlling the semiconductor device, Wherein, the semiconductor device further comprises: Peripheral circuit structure; a stacked structure vertically overlapping the peripheral circuit structure; and A separation structure, penetrating the stacking structure, wherein the stacked structure comprises a plurality of blocks spaced apart from each other by the separation structure, wherein each of the plurality of blocks comprises an insulating layer and a conductive layer alternately stacked in a vertical direction, wherein the plurality of blocks include a first block and a plurality of capacitor blocks, the plurality of capacitor blocks are arranged between first blocks adjacent to each other among the first blocks, and The plurality of capacitor blocks are separated from each other by the separation structure.

20. The data storage system according to claim 19, in, Each of the plurality of capacitor blocks includes a capacitor, wherein the capacitor comprises a capacitor electrode and a capacitor dielectric layer, the capacitor electrode comprises the conductive layer, the capacitor dielectric layer comprises the insulating layer, and Wherein, a side surface of at least one capacitor block among the plurality of capacitor blocks is surrounded by the separation structure.

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