A three-dimensional memory manufacturing process

Abstract

The present invention provides a process for fabricating a three-dimensional memory device, comprising: forming a first hard mask layer on a three-dimensional memory substrate; forming a first mesh mask layer on the first hard mask layer, wherein the mesh width is a and the grid width is b; anisotropically etching the first hard mask layer using the first mesh mask layer as a mask to form a circular through-hole array; etching the three-dimensional memory substrate using the first hard mask layer as a mask to form a circular through-hole array; forming a fourth hard mask layer on the three-dimensional memory substrate; forming an annular cylinder array above the fourth hard mask layer, wherein a line connecting the centers of any four adjacent annular cylinders forms a rhombus with a height of e; depositing a third filling layer, exposing the tops of the annular cylinder array using a planarization technique, selectively removing the annular cylinder array, and etching the fourth hard mask layer using the remaining third filling layer as a mask to form an annular groove array, wherein the height of the rhombus is e = a + b. The present invention enables the fabrication of smaller memory devices.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a three-dimensional memory manufacturing process. Background Art

[0002] Currently, 1S1C memory has become a very likely candidate for the next generation of DRAM (Dynamic Random Access Memory). However, the scaling of the annular and circular dimensions of 1S1C memory still faces certain difficulties, which limits further increases in 1S1C memory density and reduces its potential for further application. Therefore, research is needed on the scaling process for the critical annular and circular dimensions of 1S1C memory.

[0003] Since the diffraction limit of the lithography system is a circular spot, this means that when fabricating a ring structure, a diffraction-limited circular spot must be used to form a circle. Therefore, the inner diameter of the ring structure will be much larger than the diffraction limit of the lithography system. In addition, the ring width of the ring structure directly affects the capacitance of the capacitor in the fabricated 1S1C: the wider the ring width, the lower the capacitance. According to traditional fabrication processes, the minimum ring width is the diameter of the circular spot at the diffraction limit of the lithography system, which will significantly reduce the capacitance of the storage unit. Therefore, it is necessary to develop a specific fabrication process for 1S1C memory to produce higher-density three-dimensional 1S1C memory. Summary of the Invention

[0004] The present invention provides a three-dimensional memory preparation process to solve the size miniaturization defect faced by 1S1C memory in the prior art, realize the preparation of smaller 1S1C memory devices, and provide a solution for further size miniaturization and improved storage density of 3D 1S1C memory.

[0005] The present invention provides a three-dimensional memory manufacturing process, comprising:

[0006] forming a first hard mask layer on a three-dimensional memory substrate, and forming a first mesh mask layer above the first hard mask layer, wherein the mesh line width of the first mesh mask layer is a and the mesh width is b;

[0007] Using the first mesh mask layer as a mask, anisotropically etching the first hard mask layer to form a circular through-hole array in the first hard mask layer; and using the first hard mask layer having the circular through-hole array as a mask, etching the three-dimensional memory substrate to form a circular through-hole array in the three-dimensional memory substrate;

[0008] forming a fourth hard mask layer on the three-dimensional memory substrate, and forming an annular cylinder array above the fourth hard mask layer, wherein each annular cylinder in the annular cylinder array has a ring width of c and an inner diameter of d, and a line connecting the centers of the cylinder openings of any four adjacent annular cylinders forms a rhombus, and the height of the rhombus is e;

[0009] Depositing a third filling layer on the surface of the substrate formed in the previous step and flattening the substrate surface by a planarization technique to expose the tops of the annular cylinder array, selectively removing the annular cylinder array, and etching the fourth hard mask layer using the remaining third filling layer as a mask to form an annular groove array in the fourth hard mask layer;

[0010] Using the fourth hard mask layer having the annular groove array as a mask, etching the three-dimensional memory substrate to form an annular groove array in the three-dimensional memory substrate;

[0011] Among them, the annular cylinders in the annular cylinder array correspond one-to-one to the grids in the first mesh mask layer, and the center of the cross section of the corresponding annular cylinder is aligned with the center point of the grid in the vertical direction, the circular through hole of each storage unit prepared is cocentric with the annular groove, and the height e of the rhombus is e=a+b.

[0012] According to a three-dimensional memory manufacturing process provided by the present invention, forming a first mesh mask layer above the first hard mask layer includes:

[0013] forming a first sacrificial layer and a second hard mask layer in sequence on a surface of the first hard mask layer;

[0014] Photolithographically forming a first photolithographic pattern layer on the surface of the second hard mask layer, wherein the first photolithographic pattern layer includes a plurality of mutually parallel lines, and the line width in the first photolithographic pattern layer is f and the line spacing is g;

[0015] Using the first photolithography pattern layer as a mask, etching the second hard mask layer and the first sacrificial layer, stopping the etching when the first sacrificial layer is etched through in the vertical direction to form a first stripe groove array, depositing a first filling layer in the first stripe groove array, and flattening the substrate surface by a planarization technique to expose the top of the first sacrificial layer;

[0016] At this time, a second sacrificial layer and a third hard mask layer continue to be deposited on the surface of the substrate;

[0017] Photolithographically forming a second photolithographic pattern layer on the surface of the third hard mask layer, wherein the second photolithographic pattern layer includes a plurality of parallel lines, the line width of the second photolithographic pattern layer is f, the line spacing is g, and the lines of the second photolithographic pattern layer and the first photolithographic pattern layer form an angle in the horizontal direction;

[0018] Using the second photolithography pattern layer as a mask, etching the third hard mask layer and the second sacrificial layer, stopping the etching when the second sacrificial layer is etched through in the vertical direction to form a second strip groove array, depositing the second filling layer in the second strip groove array, and flattening the substrate surface by a planarization technique to expose the top of the second sacrificial layer;

[0019] The second filling layer and the first filling layer are selectively removed to form the first mesh mask; or the second filling layer material and the first filling layer material are selectively retained and the remaining material on the surface of the three-dimensional memory substrate is removed to form the first mesh mask.

[0020] According to a three-dimensional memory manufacturing process provided by the present invention, if the second filling layer material and the first filling layer material are selectively removed, the line width f is equal to the mesh width a, and the line spacing g is equal to the mesh width b;

[0021] If the second filling layer material and the first filling layer material are selectively retained and the remaining materials on the surface of the three-dimensional memory substrate are removed, the line spacing g is equal to the mesh width a, and the line width f is equal to the grid width b.

[0022] According to a three-dimensional memory manufacturing process provided by the present invention, an annular cylinder array is formed above the fourth hard mask layer, comprising:

[0023] forming a third sacrificial layer and a fifth hard mask layer in sequence over the fourth hard mask layer;

[0024] forming a third photolithography pattern layer on the surface of the fifth hard mask layer, wherein the third photolithography pattern layer comprises a plurality of circular protrusions, each of which has a diameter h, and a line connecting the top centers of any four adjacent circular protrusions forms a rhombus, and the height of the rhombus is i;

[0025] Using the third photolithography pattern layer as a mask, etching the fifth hard mask layer and the third sacrificial layer, stopping the etching when the third sacrificial layer is etched through in a vertical direction, to form a column array;

[0026] Depositing a first covering layer on the substrate surface formed in the previous step to cover the top, sidewalls and exposed surface of the fourth hard mask layer of the cylindrical array, wherein the thickness of the first covering layer on the sidewall is w1;

[0027] performing anisotropic etching on the substrate surface formed in the previous step, leaving only the first covering layer on the side walls of the cylinders in the cylinder array;

[0028] The third sacrificial layer and the fifth hard mask layer are all selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

[0029] According to a three-dimensional memory manufacturing process provided by the present invention, the ring width c of the ring cylinder in the ring cylinder array is equal to the thickness w1 of the first covering layer of the side wall, the inner diameter d of the ring cylinder is equal to the diameter h of the circle, and the height i of the rhombus is equal to e.

[0030] According to a three-dimensional memory manufacturing process provided by the present invention, an annular cylinder array is formed above the fourth hard mask layer, comprising:

[0031] forming a fourth sacrificial layer and a sixth hard mask layer in sequence above the fourth hard mask layer;

[0032] forming a fourth photolithography pattern layer on the surface of the sixth hard mask layer, wherein the fourth photolithography pattern layer includes a plurality of circular holes, each of which has a diameter j, and a line connecting the centers of any four adjacent circular holes forms a rhombus, and the height of the rhombus is k;

[0033] Using the fourth photolithography pattern layer as a mask, etching the sixth hard mask layer and the fourth sacrificial layer, stopping the etching when the fourth sacrificial layer is etched through in a vertical direction, to form a circular hole array;

[0034] Depositing a second covering layer on the substrate surface formed in the previous step to cover the bottom, sidewalls and exposed surface of the fourth hard mask layer of the circular hole, wherein the thickness of the second covering layer on the sidewalls is w2;

[0035] Anisotropically etching the substrate surface formed in the previous step to retain only the second covering layer on the side walls of the circular holes in the circular hole array;

[0036] All of the fourth sacrificial layer and the sixth hard mask layer are selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

[0037] According to a three-dimensional memory preparation process provided by the present invention, the ring width c of the annular cylinder in the annular cylinder array is equal to the thickness w2 of the second covering layer of the side wall, the inner diameter d of the annular cylinder is equal to j-2*w2, and the height k of the rhombus is equal to e.

[0038] According to a three-dimensional memory manufacturing process provided by the present invention, the manufacturing process of the third photolithography pattern layer includes:

[0039] forming a second mesh mask layer on the surface of the fifth hard mask layer, wherein the second mesh mask layer is prepared using the same process as that of the first mesh mask layer;

[0040] uniformly depositing a seventh hard mask layer on the surface of the substrate formed in the previous step, and flattening the substrate surface by a planarization technique to expose the top of the second mesh mask layer;

[0041] The remaining second mesh mask layer is selectively removed, and the cylinder array formed by the seventh hard mask layer on the surface of the fifth hard mask layer is used as the third photolithography pattern layer.

[0042] According to a three-dimensional memory manufacturing process provided by the present invention, the manufacturing process of the fourth photolithography pattern layer is the same as that of the first mesh mask layer.

[0043] According to a three-dimensional memory manufacturing process provided by the present invention, the three-dimensional memory includes dielectric materials and electrode materials alternately stacked and grown on a substrate, with the top layer being the dielectric material.

[0044] The present invention provides a three-dimensional memory preparation process, in which the structure of the three-dimensional memory mainly consists of circular through holes and annular grooves. The preparation of the circular through holes relies on a mesh mask layer. A mesh mask layer with a smaller size and denser mesh is used to realize the preparation of circular holes with small diameters; the preparation of the annular grooves relies on an annular cylinder array to realize the preparation of circular rings with small diameters and ring widths. Under the same lithography limit, smaller memory devices can be prepared, thereby improving the storage density of the memory and providing a solution for further miniaturization of the memory and improving the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 This is a schematic diagram of the process flow for preparing a circular through-hole array in the three-dimensional memory manufacturing process provided by the present invention;

[0047] Figure 2 It is a schematic diagram of the process flow for preparing an annular groove array in the three-dimensional memory manufacturing process provided by the present invention;

[0048] Figure 3 It is a schematic diagram of the process flow of forming a first mesh mask layer above a first hard mask layer in the three-dimensional memory manufacturing process provided by the present invention. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0050] The following combination Figures 1 to 3 The present invention describes a three-dimensional memory manufacturing process, which mainly includes a circular through-hole array manufacturing process and an annular groove array manufacturing process. Figure 1 As shown, the circular through hole array preparation process includes the following steps:

[0051] Sa1, forming a first hard mask layer on the three-dimensional memory substrate;

[0052] Sa2. Forming a first mesh mask layer above the first hard mask layer, wherein the mesh line width of the first mesh mask layer is a and the mesh width is b;

[0053] The structure of the first mesh mask layer is similar to a fishing net when viewed from above, and is composed of two groups of parallel lines crossing each other. These two groups of parallel lines may be made of the same material or different materials, and may be prepared together, or the first group of parallel lines may be prepared first, and then the second group of parallel lines.

[0054] Sa3. Using the first mesh mask layer as a mask, anisotropically etching the first hard mask layer to form a circular through-hole array in the first hard mask layer;

[0055] Although the mesh holes in the first mesh mask layer are not necessarily circular, due to the edge effect of etching, in the case of small sizes, the etched shape will be circular.

[0056] Sa4. Using the first hard mask layer obtained in the previous step as a mask, the three-dimensional memory substrate is etched to form a circular through-hole array in the three-dimensional memory substrate; the bottom of the circular through-hole array needs to penetrate the bottommost electrode layer of the three-dimensional memory substrate;

[0057] like Figure 2 As shown, the annular groove array preparation process includes the following steps:

[0058] Sb1, forming a fourth hard mask layer on the three-dimensional memory substrate;

[0059] Sb2. Forming an annular cylinder array above the fourth hard mask layer, wherein the annular cylinder array is composed of periodically arranged identical annular cylinders, each annular cylinder having a ring width of c and an inner diameter of d, and a line connecting the centers of the cylinder openings of any four adjacent annular cylinders forms a rhombus, and the height of the rhombus is e;

[0060] The interior of each cylinder in the annular cylinder array is hollow, and the bottom of the interior of the cylinder is the surface of the fourth hard mask layer.

[0061] Sb3, depositing a third filling layer on the surface of the substrate formed in the previous step, and flattening the substrate surface by a planarization technique to expose the top of the annular cylinder array;

[0062] Sb4, selectively removing the annular cylinder array;

[0063] Sb5. Etching the fourth hard mask layer using the remaining third filling layer as a mask to form an annular groove array in the fourth hard mask layer;

[0064] Sb6. Using the fourth hard mask layer having the annular groove array as a mask, etching the three-dimensional memory substrate to form an annular groove array in the three-dimensional memory substrate;

[0065] Among them, the annular cylinders in the annular cylinder array correspond one-to-one to the grids in the first mesh mask layer, and the center of the cross section of the corresponding annular cylinder is aligned with the center point of the grid in the vertical direction. The circular through hole of each storage unit prepared is cocentric with the annular groove, and the height e of the rhombus is a+b.

[0066] The circular through-hole array fabrication process can precede or follow the annular groove array fabrication process. Regardless of which process is performed first, an overlay alignment mark must be left to allow for alignment in the subsequent process, ensuring that the circular through-holes of each storage cell are concentric with the annular grooves. Furthermore, the circular through-holes can be fabricated after the rings are filled with the required material, or the annular grooves can be fabricated after the circular through-holes are filled with the required material.

[0067] The structure of the three-dimensional memory in this embodiment is mainly composed of circular through holes and annular grooves. The preparation of the circular through holes relies on a mesh mask layer. A mesh mask layer with a smaller size and denser mesh is used to realize the preparation scheme of circular holes with small diameters; the preparation of the annular grooves relies on an annular cylinder array to realize the preparation scheme of circular rings with small diameters and ring widths. Under the same lithography limit, smaller storage devices can be prepared, thereby improving the storage density of the memory and providing a solution for further miniaturization of the memory and improving the storage density.

[0068] Based on the above embodiments, Figure 3As shown, in this embodiment, forming a first mesh mask layer above the first hard mask layer includes:

[0069] Sc1, forming a first sacrificial layer and a second hard mask layer in sequence on the surface of the first hard mask layer;

[0070] Sc2. Photolithographically forming a first photoresist pattern layer on the surface of the second hard mask layer, wherein the first photoresist pattern layer includes a plurality of mutually parallel lines, and the line width in the first photoresist pattern layer is f and the line spacing is g;

[0071] Sc3. Using the first photolithography pattern layer as a mask, etching the second hard mask layer and the first sacrificial layer, stopping the etching when the first sacrificial layer is etched vertically to form a first stripe groove array, depositing a first filling layer in the first stripe groove array, and flattening the substrate surface using a planarization technique to expose the top of the first sacrificial layer. The first filling layer is located in the first stripe groove array;

[0072] Sc4, continuing to deposit a second sacrificial layer and a third hard mask layer on the surface of the substrate formed in the previous step;

[0073] Sc5. Photolithographically forming a second photoresist pattern layer on the surface of the third hard mask layer, wherein the second photoresist pattern layer has the same pattern and material as the first photoresist pattern layer, and lines between the second photoresist pattern layer and the first photoresist pattern layer form an angle in the horizontal direction, and the angle is generally greater than 30°;

[0074] Sc6. Using the second photolithography pattern layer as a mask, etching the third hard mask layer and the second sacrificial layer, stopping the etching when the second sacrificial layer is etched through in the vertical direction, to form a second strip groove array;

[0075] Sc7. Depositing the second filling layer in the second strip groove array and flattening the substrate surface by a planarization technique to expose the top of the second sacrificial layer. The second filling layer is present in the second strip groove array.

[0076] Sc8. Selectively remove the second filling layer and the first filling layer, and the remaining material above the first hard mask layer forms the first mesh mask; or selectively retain the second filling layer material and the first filling layer material, remove the remaining material on the surface of the three-dimensional memory substrate, and the remaining material above the first hard mask layer forms the first mesh mask.

[0077] When viewing the first mesh mask from a vertical direction, there are cavities formed by the removed material. When etching is performed using the first mesh mask, the material directly below the cavities will be etched away.

[0078] On the basis of the above embodiment, in this embodiment, if the second filling layer material and the first filling layer material are selectively removed, the line width f is equal to the mesh width a, and the line spacing g is equal to the mesh width b;

[0079] If the second filling layer material and the first filling layer material are selectively retained and the remaining materials on the surface of the three-dimensional memory substrate are removed, the line spacing g is equal to the mesh width a, and the line width f is equal to the grid width b.

[0080] Based on the above embodiment, in this embodiment, an annular cylinder array is formed above the fourth hard mask layer, including:

[0081] forming a third sacrificial layer and a fifth hard mask layer in sequence over the fourth hard mask layer;

[0082] forming a third photolithographic pattern layer on the surface of the fifth hard mask layer, wherein the third photolithographic pattern layer is composed of periodically arranged identical circular protrusions, wherein the diameter of each circular protrusion is h, and a line connecting the top centers of any four adjacent circular protrusions forms a rhombus, and the height of the rhombus is i;

[0083] Using the third photolithography pattern layer as a mask, etching the fifth hard mask layer and the third sacrificial layer, stopping the etching when the third sacrificial layer is etched through in a vertical direction, to form a column array;

[0084] Depositing a first covering layer on the substrate surface formed in the previous step to cover the top, sidewalls and exposed surface of the fourth hard mask layer of the cylindrical array, wherein the thickness of the first covering layer on the sidewall is w1;

[0085] performing anisotropic etching on the substrate surface formed in the previous step, leaving only the first covering layer on the side walls of the cylinders in the cylinder array;

[0086] The third sacrificial layer and the fifth hard mask layer are all selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

[0087] Based on the above embodiment, in this embodiment, the width c of the annular cylinder in the annular cylinder array is equal to the thickness w1 of the first covering layer of the side wall, the inner diameter d of the annular cylinder is equal to the diameter h of the circle, and the height i of the rhombus is equal to e.

[0088] Based on the above embodiment, in this embodiment, an annular cylinder array is formed above the fourth hard mask layer, including:

[0089] forming a fourth sacrificial layer and a sixth hard mask layer in sequence above the fourth hard mask layer;

[0090] forming a fourth photolithographic pattern layer on the surface of the sixth hard mask layer, wherein the fourth photolithographic pattern layer is composed of a plurality of identical circular holes periodically arranged in a whole mask layer, wherein the diameter of each circular hole is j, and a line connecting the centers of any four adjacent circular holes forms a rhombus, and the height of the rhombus is k;

[0091] Using the fourth photolithography pattern layer as a mask, etching the sixth hard mask layer and the fourth sacrificial layer, stopping the etching when the fourth sacrificial layer is etched through in a vertical direction, to form a circular hole array;

[0092] Depositing a second covering layer on the substrate surface formed in the previous step to cover the bottom, sidewalls and exposed surface of the fourth hard mask layer of the circular hole, wherein the thickness of the second covering layer on the sidewalls is w2;

[0093] Anisotropically etching the substrate surface formed in the previous step to retain only the second covering layer on the side walls of the circular holes in the circular hole array;

[0094] All of the fourth sacrificial layer and the sixth hard mask layer are selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

[0095] Based on the above embodiment, in this embodiment, the ring width c of the annular cylinder in the annular cylinder array is equal to the thickness w2 of the second covering layer of the side wall, the inner diameter d of the annular cylinder is equal to j-2*w2, and the height k of the rhombus is equal to e.

[0096] Based on the above embodiment, the preparation process of the third photolithography pattern layer in this embodiment includes:

[0097] forming a second mesh mask layer on the surface of the fifth hard mask layer, wherein the second mesh mask layer is prepared using the same process as that of the first mesh mask layer;

[0098] uniformly depositing a seventh hard mask layer on the surface of the substrate formed in the previous step, and flattening the substrate surface by a planarization technique to expose the top of the second mesh mask layer;

[0099] The remaining second mesh mask layer is selectively removed, and the cylinder array formed by the seventh hard mask layer on the surface of the fifth hard mask layer is used as the third photolithography pattern layer.

[0100] On the basis of the above embodiment, the preparation process of the fourth photolithography pattern layer in this embodiment is the same as that of the first mesh mask layer.

[0101] On the basis of the above embodiments, the three-dimensional memory in this embodiment includes dielectric materials and electrode materials alternately stacked and grown on a substrate, with the top layer being the dielectric material.

[0102] The following is further described in detail with reference to the preferred embodiments:

[0103] SiO2 and W are grown alternately on the substrate, with the top layer being SiO2, forming a three-dimensional memory substrate;

[0104] Depositing 50 nm of Al2O3 on the three-dimensional memory substrate as a first hard mask layer;

[0105] 50nm SiO2 and 50nm Cr are sequentially formed on the surface of the first hard mask layer as a first sacrificial layer and a second hard mask layer respectively;

[0106] forming a first photoresist pattern layer on the surface of the second hard mask layer by photolithography, wherein the first photoresist pattern layer is composed of periodically arranged parallel photoresist lines, the width of the photoresist lines is 50 nm, and the line spacing is 50 nm;

[0107] Using the photoresist as a mask, etch the 50nm Cr and 50nm SiO2 of the second hard mask layer and the first sacrificial layer until the bottom of the etching exposes the 50nm Al2O3 of the first hard mask layer, and remove the remaining Cr in the second hard mask layer with a Cr etching solution;

[0108] 100 nm SiN was deposited as the first filling layer by magnetron sputtering, and the surface was smoothed by CMP (Chemical-Mechanical Planarization) to remove the protruding SiN and expose the top of the first sacrificial SiO2 layer;

[0109] Continue to deposit 50nm SiO2 and 50nm Cr as the second sacrificial layer and the third hard mask layer respectively;

[0110] A second photoresist pattern layer is formed on the surface of the third hard mask layer by photolithography. The second photoresist pattern layer is composed of periodically arranged parallel photoresist lines. The width of the photoresist lines is 50 nm and the line spacing is 50 nm. The parallel lines of the second photoresist pattern layer and the first photoresist pattern layer are at a 90° angle in the horizontal direction.

[0111] Using a photoresist as a mask, etch the 50nm Cr and 50nm SiO2 layers of the third hard mask layer and the second sacrificial layer until the alternating first sacrificial layer SiO2 and first filling layer SiN are exposed at the bottom of the etching process. Use a Cr etching solution to remove the remaining Cr in the third hard mask layer.

[0112] 100nm SiN was deposited as the second filling layer by magnetron sputtering, and the surface was smoothed by CMP, and the protruding SiN was removed to expose the top of the second sacrificial layer SiO2;

[0113] Buffered oxide etchant (Buffered Oxide EtchBOE) is used to remove all SiO2 in the first sacrificial layer and the second sacrificial layer, leaving the SiN in the first filling layer and the second filling layer. The remaining SiN forms a first mesh mask layer. The line width in the first mesh mask layer is 50nm and the line spacing is 50nm.

[0114] Using the remaining SiN as a mask, the first hard mask layer Al2O3 is etched to form a circular through-hole array in the Al2O3; wherein the center lines of four adjacent circular holes can form a square;

[0115] Using the circular through-hole array formed in the first hard mask layer Al2O3 as a mask, etching the three-dimensional memory substrate to form a circular through-hole array in the three-dimensional memory substrate, and then removing the first hard mask layer Al2O3. The diameter of the circular through-hole is 50nm.

[0116] 30nm GeTe9 film and 50nm W film were deposited on the sidewalls of the circular through-holes by magnetron sputtering.

[0117] Continuing to form 50nm Al2O3 on the three-dimensional memory substrate as a fourth hard mask layer;

[0118] Sequentially forming 50nm SiO2 and 50nm Cr as a third sacrificial layer and a fifth hard mask layer on the Al2O3 of the fourth hard mask layer;

[0119] A second mesh mask layer composed of SiO2 is formed on the fifth hard mask layer Cr. The second mesh mask layer is prepared using the same process as the first mesh mask layer. The center line of each line in the second mesh mask layer is aligned with the center line of a line in the first mesh mask layer. The lines in the second mesh mask layer have a width of 30 nm and a line spacing of 70 nm.

[0120] 100 nm SiN is deposited on the second mesh mask layer as the seventh hard mask layer. The surface is smoothed by CMP and the protruding SiN is removed to expose the top of the second mesh mask layer SiO2.

[0121] Using a buffered oxide etchant (BOE) to remove all SiO2 of the second mesh mask layer, leaving the SiN of the seventh hard mask layer, with the remaining SiN forming a third photolithography pattern layer;

[0122] Using the third photolithography pattern layer composed of SiN as a mask, the fifth hard mask layer and the Cr and SiO2 of the third sacrificial layer are etched until the SiO2 is etched through and Al2O3 is exposed, and the etching stops;

[0123] The Cr layer of the fifth hard mask layer is removed using a Cr etching solution, leaving a plurality of SiO2 cylinders to form a cylinder array, and the cylinder diameter is 70 nm;

[0124] A 10nm SiN layer is grown on the substrate surface using an ALD process as a first capping layer, uniformly covering the top and sidewalls of the cylinders and the exposed surface of the fourth hard mask layer Al2O3;

[0125] Anisotropic etching was performed using Cl2+O2 by ICP to remove SiN from the top of the cylinder and the surface of Al2O3, leaving only SiN on the sidewall of the cylinder. The thickness of SiN on the sidewall was 10nm.

[0126] Using a buffered oxide etchant (BOE), all SiO2 of the third sacrificial layer is removed. The remaining material on the surface of the fourth hard mask layer Al2O3 forms an annular cylinder array, and each ring has an inner diameter of 70nm and a ring width of 10nm.

[0127] 100 nm SiO2 was further deposited as the third filling layer by magnetron sputtering. The surface was then smoothed by CMP and the protruding SiO2 was removed, exposing the top of the annular cylindrical array SiN.

[0128] Use SiN etching solution to remove all the SiN in the annular cylinder array;

[0129] Using the remaining third filling layer SiO2 as a mask, etching the fourth hard mask layer Al2O3 to form an annular groove array in the fourth hard mask Al2O3 layer;

[0130] Using the annular groove array formed in the fourth hard mask Al2O3 layer as a mask, the three-dimensional memory substrate is etched to form an annular groove array in the three-dimensional memory substrate. Each ring has an inner diameter of 70nm and a ring width of 10nm. A circular hole with a diameter of 50nm is located at the center of each ring.

[0131] ALD is used to fill the annular groove array with 2nmAl2O3 and 3nmZrO2, just filling the ring and completing the preparation of the memory array.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A three-dimensional memory manufacturing process, characterized in that: include: forming a first hard mask layer on a three-dimensional memory substrate, and forming a first mesh mask layer above the first hard mask layer, wherein the mesh line width of the first mesh mask layer is a and the grid width is b; Using the first mesh mask layer as a mask, anisotropically etching the first hard mask layer to form a circular through-hole array in the first hard mask layer; and using the first hard mask layer having the circular through-hole array as a mask, etching the three-dimensional memory substrate to form a circular through-hole array in the three-dimensional memory substrate; forming a fourth hard mask layer on the three-dimensional memory substrate, and forming an annular cylinder array above the fourth hard mask layer, wherein each annular cylinder in the annular cylinder array has a ring width of c and an inner diameter of d, and a line connecting the centers of the cylinder openings of any four adjacent annular cylinders forms a rhombus, and the height of the rhombus is e; Depositing a third filling layer on the surface of the substrate formed in the previous step and flattening the substrate surface by a planarization technique to expose the tops of the annular cylinder array, selectively removing the annular cylinder array, and etching the fourth hard mask layer using the remaining third filling layer as a mask to form an annular groove array in the fourth hard mask layer; Using the fourth hard mask layer having the annular groove array as a mask, etching the three-dimensional memory substrate to form an annular groove array in the three-dimensional memory substrate; Among them, the annular cylinders in the annular cylinder array correspond one-to-one to the grids in the first mesh mask layer, and the center of the cross section of the corresponding annular cylinder is aligned with the center point of the grid in the vertical direction, the circular through hole of each storage unit prepared is cocentric with the annular groove, and the height e of the rhombus is e=a+b.

2. The three-dimensional memory manufacturing process according to claim 1, characterized in that: The step of forming a first mesh mask layer above the first hard mask layer comprises: forming a first sacrificial layer and a second hard mask layer in sequence on a surface of the first hard mask layer; Photolithographically forming a first photolithographic pattern layer on the surface of the second hard mask layer, wherein the first photolithographic pattern layer includes a plurality of mutually parallel lines, and the line width in the first photolithographic pattern layer is f and the line spacing is g; Using the first photolithography pattern layer as a mask, etching the second hard mask layer and the first sacrificial layer, stopping the etching when the first sacrificial layer is etched through in the vertical direction to form a first stripe groove array, depositing a first filling layer in the first stripe groove array, and flattening the substrate surface by a planarization technique to expose the top of the first sacrificial layer; At this time, a second sacrificial layer and a third hard mask layer continue to be deposited on the surface of the substrate; Photolithographically forming a second photolithographic pattern layer on the surface of the third hard mask layer, wherein the second photolithographic pattern layer includes a plurality of parallel lines, the line width of the second photolithographic pattern layer is f, the line spacing is g, and the lines of the second photolithographic pattern layer and the first photolithographic pattern layer form an angle in the horizontal direction; Using the second photolithography pattern layer as a mask, etching the third hard mask layer and the second sacrificial layer, stopping the etching when the second sacrificial layer is etched through in the vertical direction to form a second strip groove array, depositing a second filling layer in the second strip groove array, and flattening the substrate surface by a planarization technique to expose the top of the second sacrificial layer; The second filling layer and the first filling layer are selectively removed to form the first mesh mask; or the second filling layer material and the first filling layer material are selectively retained and the remaining material on the surface of the three-dimensional memory substrate is removed to form the first mesh mask.

3. The three-dimensional memory manufacturing process according to claim 2, characterized in that: If the second filling layer material and the first filling layer material are selectively removed, the line width f is equal to the mesh width a, and the line spacing g is equal to the mesh width b; If the second filling layer material and the first filling layer material are selectively retained and the remaining materials on the surface of the three-dimensional memory substrate are removed, the line spacing g is equal to the mesh width a, and the line width f is equal to the grid width b.

4. The three-dimensional memory manufacturing process according to claim 1, characterized in that: forming an annular cylinder array above the fourth hard mask layer, comprising: forming a third sacrificial layer and a fifth hard mask layer in sequence over the fourth hard mask layer; forming a third photolithography pattern layer on the surface of the fifth hard mask layer, wherein the third photolithography pattern layer comprises a plurality of circular protrusions, each of which has a diameter h, and a line connecting the top centers of any four adjacent circular protrusions forms a rhombus, and the height of the rhombus is i; Using the third photolithography pattern layer as a mask, etching the fifth hard mask layer and the third sacrificial layer, stopping the etching when the third sacrificial layer is etched through in a vertical direction, to form a column array; Depositing a first covering layer on the substrate surface formed in the previous step to cover the top, sidewalls and exposed surface of the fourth hard mask layer of the cylindrical array, wherein the thickness of the first covering layer on the sidewall is w1; performing anisotropic etching on the substrate surface formed in the previous step, leaving only the first covering layer on the side walls of the cylinders in the cylinder array; The third sacrificial layer and the fifth hard mask layer are all selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

5. The three-dimensional memory manufacturing process according to claim 4, characterized in that: The ring width c of the annular cylinder in the annular cylinder array is equal to the thickness w1 of the first covering layer of the side wall, the inner diameter d of the annular cylinder is equal to the diameter h of the circle, and the height i of the rhombus is equal to e.

6. The three-dimensional memory manufacturing process according to claim 1, characterized in that: forming an annular cylinder array above the fourth hard mask layer, comprising: forming a fourth sacrificial layer and a sixth hard mask layer in sequence above the fourth hard mask layer; forming a fourth photolithography pattern layer on the surface of the sixth hard mask layer, wherein the fourth photolithography pattern layer includes a plurality of circular holes, each of which has a diameter j, and a line connecting the centers of any four adjacent circular holes forms a rhombus, and the height of the rhombus is k; Using the fourth photolithography pattern layer as a mask, etching the sixth hard mask layer and the fourth sacrificial layer, stopping the etching when the fourth sacrificial layer is etched through in a vertical direction, to form a circular hole array; Depositing a second covering layer on the substrate surface formed in the previous step to cover the bottom, sidewalls and exposed surface of the fourth hard mask layer of the circular hole, wherein the thickness of the second covering layer on the sidewalls is w2; Anisotropically etching the substrate surface formed in the previous step to retain only the second covering layer on the side walls of the circular holes in the circular hole array; All of the fourth sacrificial layer and the sixth hard mask layer are selectively removed, and the remaining material on the surface of the fourth hard mask layer constitutes the annular cylinder array.

7. The three-dimensional memory manufacturing process according to claim 6, characterized in that: The ring width c of the annular cylinder in the annular cylinder array is equal to the thickness w2 of the second covering layer of the side wall, and the inner diameter d of the annular cylinder is equal to , the height of the rhombus is k=e.

8. The three-dimensional memory manufacturing process according to claim 4, characterized in that: The preparation process of the third photolithography pattern layer includes: forming a second mesh mask layer on the surface of the fifth hard mask layer, wherein the second mesh mask layer is prepared using the same process as that of the first mesh mask layer; uniformly depositing a seventh hard mask layer on the surface of the substrate formed in the previous step, and flattening the substrate surface by a planarization technique to expose the top of the second mesh mask layer; The remaining second mesh mask layer is selectively removed, and the cylinder array formed by the seventh hard mask layer on the surface of the fifth hard mask layer is used as the third photolithography pattern layer.

9. The three-dimensional memory manufacturing process according to claim 6, characterized in that: The fourth photolithography pattern layer is prepared using the same process as that of the first mesh mask layer.

10. The three-dimensional memory manufacturing process according to any one of claims 1 to 9, characterized in that: The three-dimensional memory includes dielectric materials and electrode materials alternately stacked and grown on a substrate, with the top layer being the dielectric material.

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