A three-dimensional memory manufacturing process based on self-aligned dual imaging

Abstract

The present invention provides a three-dimensional memory manufacturing process based on self-aligned double imaging, including: forming a first mesh mask layer on a three-dimensional memory substrate, and transferring the pattern of the first mesh mask layer to the three-dimensional memory substrate through etching to form a circular hole array; forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate through etching to form an annular groove array; the annular grooves in the annular groove array correspond one by one to the circular holes in the circular hole array, and the circular holes are located at the centers of the corresponding annular grooves; the first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer is composed of a third strip mask layer and a fourth strip mask layer; the first strip mask layer, the second strip mask layer, the third strip mask layer, and the fourth strip mask layer are all prepared through self-aligned double imaging. The present invention miniaturizes the size of the storage unit and improves the storage density.

Description

Technical Field

[0001] The present invention relates to the technical field of memories, and in particular, to a preparation process for a three-dimensional memory based on self-aligned double imaging. Background Art

[0002] At present, the 1S1C memory has become a very likely candidate for the next-generation DRAM (Dynamic Random Access Memory). However, the miniaturization of the ring and circular sizes of the 1S1C memory still faces certain difficulties at present, which limits the further improvement of the 1S1C memory density and thus reduces the possibility of its further application. Therefore, it is necessary to study the key circular ring size and circular size miniaturization process for the 1S1C memory.

[0003] Since the lithographic diffraction limit of the lithography system is a circular light spot, it means that when preparing a ring structure, a circular light spot with the diffraction limit needs to be used to enclose a circle. Therefore, the inner diameter of the ring structure will be much larger than the diffraction limit of the lithography system, and the ring width of the ring structure will directly affect the capacitance value of the capacitor in the prepared 1S1C. The wider the ring width, the lower the capacitance value. According to the traditional preparation process, the minimum value of the ring width is the diameter of the circular light spot with the lithography system diffraction limit, which will greatly reduce the capacitance value of the storage unit. Therefore, it is necessary to develop a specific preparation process for the 1S1C memory to prepare a three-dimensional 1S1C memory with a higher density. Summary of the Invention

[0004] The present invention provides a preparation process for a three-dimensional memory based on self-aligned double imaging, which is used to solve the defect of size miniaturization faced by the 1S1C memory in the prior art, introduce the multiple exposure technology into the preparation of the three-dimensional 1S1C, improve the storage unit density of the three-dimensional 1S1C, and further improve the overall performance of the memory.

[0005] The present invention provides a preparation process for a three-dimensional memory based on self-aligned double imaging, including:

[0006] Form a first mesh mask layer on the three-dimensional memory substrate, and transfer the pattern of the first mesh mask layer to the three-dimensional memory substrate through etching to form a circular hole array;

[0007] Form a second mesh mask layer on the three-dimensional memory substrate, and transfer the pattern of the second mesh mask layer to the three-dimensional memory substrate through etching to form an annular groove array;

[0008] The annular grooves in the annular groove array correspond to the circular holes in the circular hole array one by one, and the circular holes are located at the centers of the corresponding annular grooves;

[0009] The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer is composed of a third strip mask layer and a fourth strip mask layer;

[0010] The first strip mask layer, the second strip mask layer, the third strip mask layer, and the fourth strip mask layer are all prepared by self-aligned double patterning;

[0011] The spacing between all strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a;

[0012] The spacing between all strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d;

[0013] Wherein, a + c = d + f, d < a, and f > c.

[0014] According to a three-dimensional memory manufacturing process based on self-aligned double patterning provided by the present invention, the manufacturing process of the first strip mask layer includes:

[0015] A first sacrificial layer, a first hard mask layer, a second sacrificial layer, and a second hard mask layer are sequentially formed on the three-dimensional memory substrate;

[0016] A plurality of parallel first strip photoresists are left on the second hard mask layer by photolithography, the strip width of the first strip photoresist is a, and the spacing is b;

[0017] Using the first strip photoresist as a mask to etch the second hard mask layer and the second sacrificial layer;

[0018] A first covering layer is uniformly deposited, and the first covering layer grows uniformly on the surface and the side, and the thickness of the first covering layer is c;

[0019] The first covering layer on the surface is removed, and the first covering layer on the side is retained;

[0020] Using the first covering layer as a mask to etch the first hard mask layer and the first sacrificial layer;

[0021] A first filling layer is deposited, and the surface is flattened by a planarization technique, and the surface of the first sacrificial layer is exposed. The strip width of the first sacrificial layer is c, and the strip width of the first filling layer is a.

[0022] According to a three-dimensional memory manufacturing process based on self-aligned double patterning provided by the present invention, the thickness c of the first covering layer has a relationship with the strip width a and the spacing b: a = b - 2c.

[0023] A three-dimensional memory fabrication process based on self-aligned dual imaging according to the present invention, wherein the fabrication process and dimensions of the second strip mask layer are the same as those of the first strip mask layer;

[0024] The angle α between the lines in the horizontal direction in the second strip mask layer and the first strip mask layer is greater than 30°;

[0025] A three-dimensional memory fabrication process based on self-aligned dual imaging according to the present invention, wherein the fabrication process of the first mesh mask layer includes:

[0026] Forming a first strip mask layer on the three-dimensional memory substrate;

[0027] Forming a second strip mask layer on the first strip mask layer;

[0028] Selectively removing the first sacrificial layer in the first strip mask layer and the second strip mask layer, and the remaining first filling layer constitutes the first mesh mask layer.

[0029] A three-dimensional memory fabrication process based on self-aligned dual imaging according to the present invention, wherein the fabrication process of the third strip mask layer is the same as that of the first strip mask layer;

[0030] In the fabrication process of the third strip mask layer, the strip width of the first strip photoresist is d, the pitch is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d;

[0031] Wherein, d + e = a + b.

[0032] A three-dimensional memory fabrication process based on self-aligned dual imaging according to the present invention, wherein the thickness f of the first covering layer has a relationship with the strip width d and the pitch e: d = e - 2f.

[0033] A three-dimensional memory fabrication process based on self-aligned dual imaging according to the present invention, wherein the fabrication process and dimensions of the fourth strip mask layer are the same as those of the third strip mask layer;

[0034] The angle α between the lines in the horizontal direction in the fourth strip mask layer and the third strip mask layer is greater than 30°;

[0035] The lines in the third strip mask layer and the first strip mask layer are parallel to each other, and their projection centers coincide in the vertical direction;

[0036] The lines in the fourth strip mask layer and the second strip mask layer are parallel to each other, and their projection centers coincide in the vertical direction.

[0037] A three-dimensional memory fabrication process based on self-aligned dual imaging provided by the present invention, the fabrication process of the second mesh mask layer includes:

[0038] Form the third strip mask layer on the three-dimensional memory substrate;

[0039] Form the fourth strip mask layer on the third strip mask layer;

[0040] Selectively remove the first sacrificial layer in the third strip mask layer and the fourth strip mask layer, and the remaining first filling layer constitutes the second mesh mask layer.

[0041] A three-dimensional memory fabrication process based on self-aligned dual imaging provided by the present invention, the fabrication process of the annular groove array includes:

[0042] Deposit a third hard mask layer, a third sacrificial layer and a fourth hard mask layer on the three-dimensional memory substrate in sequence, and form the second mesh mask layer on the fourth hard mask layer;

[0043] Use the second mesh mask layer as a template to etch the fourth hard mask layer and the third sacrificial layer to form a plurality of circular holes;

[0044] Uniformly deposit a second covering layer, the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g;

[0045] Remove the second covering layer on the surface, retain the second covering layer on the side, and remove the remaining fourth hard mask layer and the third sacrificial layer on the surface;

[0046] Deposit a second filling layer, and make the surface flat through a planarization technique, and expose the surface of the second covering layer, and the strip ring width of the second covering layer is g;

[0047] Selectively remove the second covering layer, use the remaining second filling layer as a template to etch the third hard mask layer and the three-dimensional memory substrate, and form the annular groove array on the three-dimensional memory substrate, and the ring width of the annular groove is g.

[0048] The three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention. The structure of the three-dimensional memory mainly consists of circular through-holes and annular grooves. The preparation of the circular through-holes and the annular grooves both rely on a mesh mask layer. A mesh mask layer with smaller size and denser mesh can be prepared, which means that the feature size of the memory cells can be reduced and the storage density of the memory can be increased. Using the self-aligned double imaging process to manufacture the three-dimensional memory can continue to miniaturize the size of the memory cells and improve the storage density without using a more advanced lithography system, thereby improving the overall performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0050] Figure 1 It is a schematic process flow diagram for the preparation of a circular through-hole array in the three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention;

[0051] Figure 2 It is a schematic process flow diagram for the preparation of an annular groove array in the three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention;

[0052] Figure 3 It is a schematic process flow diagram for the three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0053] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention with reference to the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present invention belong to the scope of protection of the present invention.

[0054] The following will describe Figures 1 to 3 a three-dimensional memory manufacturing process based on self-aligned double imaging provided by the present invention, including:

[0055] Form a first mesh mask layer on the three-dimensional memory substrate, and transfer the pattern of the first mesh mask layer to the three-dimensional memory substrate through etching to form a circular hole array;

[0056] A second mesh mask layer is formed on the three-dimensional memory substrate, and the pattern of the second mesh mask layer is transferred to the three-dimensional memory substrate by etching to form an array of annular grooves;

[0057] The annular grooves in the array of annular grooves correspond one-to-one with the circular holes in the array of circular holes, and the circular holes are located at the centers of the corresponding annular grooves;

[0058] The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer includes a third strip mask layer and a fourth strip mask layer;

[0059] The first strip mask layer, the second strip mask layer, the third strip mask layer, and the fourth strip mask layer are all prepared by self-aligned double imaging;

[0060] The pitch of all strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a;

[0061] The pitch of all strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d;

[0062] Wherein, a + c = d + f, d < a, f > c.

[0063] When the self-aligned double imaging process is required to fabricate the three-dimensional memory, the order of fabricating the array of annular grooves and the array of circular holes can be adjusted according to the actual process requirements, and the growth of other thin film materials in the circular holes or annular grooves does not affect the alignment process of the array of annular grooves and the array of circular holes, and it can ensure that there is a circular hole at the center of each annular groove, and the circular through hole is almost located at the exact center of the annular groove.

[0064] Although the first mesh mask layer is used to fabricate the array of circular holes and the second mesh mask layer is used to fabricate the array of annular grooves, in order to ensure that there is a circular hole at the center of each annular groove, it is necessary to ensure that the line periods of the first mesh mask layer and the second mesh mask layer are consistent, so a + c = d + f is required. In addition, since the circular hole is located at the center of the ring, it means that the size of the ring needs to be larger than that of the circular hole, so d c are required.

[0065] It is necessary to satisfy d < a, which means that starting from the first layer of photoresist lines, it is necessary to ensure that the photoresist lines for fabricating the ring are narrower than the photoresist lines for fabricating the hole. f > c means that the thickness of the second covering layer deposited on the sidewall for fabricating the ring is thicker than the thickness of the first covering layer deposited on the sidewall for fabricating the hole, so that the inner diameter of the annular groove is larger than the circular hole, and the circular hole is located at the center of the annular groove.

[0066] In this embodiment, the structure of the three-dimensional memory mainly consists of circular through-holes and annular grooves. The preparation of the circular through-holes and the annular grooves both rely on a mesh mask layer. The ability to fabricate a mesh mask layer with smaller dimensions and denser mesh openings means that the feature size of the memory cells can be reduced, improving the storage density of the memory. Using a self-aligned double patterning process to fabricate the three-dimensional memory allows the size of the memory cells to be further reduced and the storage density to be increased without using a more advanced lithography system, thereby enhancing the overall performance of the memory.

[0067] Based on the above embodiment, as Figure 1 shown, the preparation process of the first strip-shaped mask layer in this embodiment includes:

[0068] Sequentially form a first sacrificial layer, a first hard mask layer, a second sacrificial layer, and a second hard mask layer on the three-dimensional memory substrate;

[0069] Through lithography, leave multiple parallel first strip-shaped photoresists on the second hard mask layer. The strip width of the first strip-shaped photoresist is a, and the spacing is b;

[0070] Use the first strip-shaped photoresist as a mask to etch the second hard mask layer and the second sacrificial layer;

[0071] Uniformly deposit a first covering layer. The first covering layer grows uniformly on the surface and sides. The thickness of the first covering layer is c;

[0072] Remove the first covering layer on the surface and retain the first covering layer on the sides;

[0073] Use the first covering layer as a mask to etch the first hard mask layer and the first sacrificial layer;

[0074] Deposit a first filling layer and use planarization technology to make the surface flat and expose the surface of the first sacrificial layer. The strip width of the first sacrificial layer is c, and the strip width of the first filling layer is a.

[0075] Figure 1 1.1 to 1.7 in

[0076] Figure 1 is the process flow chart for the preparation of the first strip-shaped mask layer, where:

[0077] Figure 1 1.1 is to form a first sacrificial layer, a first hard mask layer, a second sacrificial layer, and a second hard mask layer on a given three-dimensional memory substrate and leave parallel first strip-shaped photoresists on the second hard mask layer through lithography. The strip width is a and the spacing is b;

[0078] Figure 1 In 1.3, a first covering layer is evenly deposited, and the first covering layer grows evenly on the surface and the side surface;

[0079] In 1.4, the first covering layer on the surface is removed, and the first covering layer on the side surface is retained. The thickness of the first covering layer is c, and a = b - 2c;

[0080] Figure 1 In 1.5, the first hard mask layer and the first sacrificial layer are etched using the first covering layer as a mask;

[0081] Figure 1 In 1.6, a first filling layer is deposited, and the strip width of the first filling layer is a;

[0082] Figure 1 In 1.7, the surface of the substrate is flattened by a planarization technique to expose the surface of the first sacrificial layer.

[0083] Based on the above embodiments, in this embodiment, the thickness c of the first covering layer has the relationship a = b - 2c with the strip width a and the spacing b.

[0084] For the lines prepared by the self - aligned double - imaging technique, there are two possible spacings between the lines. However, when manufacturing memory cells, it is necessary to ensure that the shape of each memory cell is as consistent as possible to improve the consistency of the memory cells. Since the spacing between the lines directly affects the size of the memory cells, it is necessary to make these two possible spacings tend to be the same through special design.

[0085] The thickness c of the first covering layer has the following relationship with the strip width a and the spacing b: a = b - 2c. The purpose is to make the two possible line spacings of the lines prepared by the self - aligned double - imaging technique consistent.

[0086] Based on the above embodiments, in this embodiment, the manufacturing process and dimensions of the second strip - shaped mask layer are the same as those of the first strip - shaped mask layer;

[0087] The angle α between the lines in the horizontal direction of the second strip - shaped mask layer and the first strip - shaped mask layer is α > 30°.

[0088] Figure 1 In 1.8 to 1.13 is the process flow chart for manufacturing the second strip - shaped mask layer. The second strip - shaped mask layer and the first strip - shaped mask layer have an angle α in the horizontal direction, and α > 30°. α refers to the angle of the minimum angle between the lines in the horizontal direction. The remaining manufacturing process flow of the second strip - shaped mask layer is the same as that of the first strip - shaped mask layer and will not be elaborated here.

[0089] Based on the above embodiments, the preparation process of the first mesh mask layer in this embodiment includes:

[0090] Form a first strip-shaped mask layer on the three-dimensional memory substrate;

[0091] Form a second strip-shaped mask layer on the first strip-shaped mask layer;

[0092] Selectively remove the first sacrificial layer in the first strip-shaped mask layer and the second strip-shaped mask layer, and the remaining first filling layer constitutes the first mesh mask layer.

[0093] Figure 1 1.14 in [description] is to selectively remove the first sacrificial layer in the first strip-shaped mask layer and the second strip-shaped mask layer, and the remaining first filling layer constitutes the first mesh mask layer.

[0094] Figure 1 1.15 in [description] is to transfer the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching using the first mesh mask layer as a template to form a circular hole array, and then remove the surface residues.

[0095] Based on the above embodiments, as Figure 2 shown, the preparation process of the third strip-shaped mask layer in this embodiment is the same as that of the first strip-shaped mask layer;

[0096] In the preparation process of the third strip-shaped mask layer, the strip width of the first strip-shaped photoresist is d, the spacing is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d;

[0097] Wherein, d + e = a + b.

[0098] The preparation process of the third strip-shaped mask layer only modifies the strip width of the first strip-shaped photoresist to d, the spacing to e, and the thickness of the first covering layer to f in the preparation process of the first strip-shaped mask layer; the final strip width of the first sacrificial layer is f, and the strip width of the first filling layer is d.

[0099] d + e = a + b means that it is necessary to ensure that the line period of the preparation ring for preparing holes remains consistent during the first-layer lithography. d < a means that during the first-layer lithography, it is necessary to ensure that the photoresist lines for preparing the ring are narrower than the photoresist lines for preparing the holes.

[0100] Figure 2 2.1 to 2.7 in [description] are the process flow diagrams of the preparation process of the third strip-shaped mask layer, including:

[0101] First, deposit a third hard mask layer, a third sacrificial layer, and a fourth hard mask layer on the given three-dimensional memory substrate in sequence;

[0102] Figure 2 In 2.1, the first sacrificial layer, the first hard mask layer, the second sacrificial layer and the second hard mask layer are continuously deposited in sequence, and parallel first strip-shaped photoresist is left on the second hard mask layer by lithography, the strip width thereof is d, the spacing is e, and d + e = a + b;

[0103] Figure 2 In 2.2, the second hard mask layer and the second sacrificial layer are etched using the first strip-shaped photoresist as a mask;

[0104] Figure 2 In 2.3, a first covering layer is uniformly deposited, and the first covering layer grows uniformly on the surface and the side surface;

[0105] Figure 2 In 2.4, the first covering layer on the surface is removed, and the first covering layer on the side surface is retained, the thickness of the first covering layer is f, and d = e - 2f;

[0106] Figure 2 In 2.5, the first hard mask layer and the first sacrificial layer are etched using the first covering layer as a mask;

[0107] Figure 2 In 2.6, a first filling layer is deposited, and the strip width of the first filling layer is d;

[0108] Figure 2 In 2.7, the surface of the substrate is flattened by a planarization technique to expose the surface of the first sacrificial layer.

[0109] Based on the above embodiments, in this embodiment, the thickness f of the first covering layer has a relationship with the strip width d and the spacing e as d = e - 2f.

[0110] d = e - 2f means that for the lines prepared by the self-aligned double imaging technique, the two possible line spacings are consistent.

[0111] Based on the above embodiments, in this embodiment, the preparation process and dimensions of the fourth strip-shaped mask layer are the same as those of the third strip-shaped mask layer;

[0112] The angle α between the lines in the fourth strip-shaped mask layer and the third strip-shaped mask layer in the horizontal direction is > 30°;

[0113] The lines in the third strip-shaped mask layer and the first strip-shaped mask layer are parallel to each other, and the projection centers thereof coincide in the vertical direction;

[0114] The lines in the fourth strip-shaped mask layer and the second strip-shaped mask layer are parallel to each other, and the projection centers of the lines coincide in the vertical direction.

[0115] Figure 2 Among them, 2.8 - 2.14 is the process flow chart for the preparation of the fourth strip mask layer. The fourth strip mask layer and the third strip mask layer have an included angle α in the horizontal direction, where α > 30°, and α refers to the angle of the minimum included angle between the lines in the horizontal direction. The remaining preparation process flow of the fourth strip mask layer is the same as that of the third strip mask layer, and will not be elaborated here.

[0116] The coincidence of the projection centers means that the widths of the lines can be different, but from a top-down perspective, the center lines of the lines need to coincide.

[0117] Based on the above embodiments, the preparation process of the second mesh mask layer in this embodiment includes:

[0118] Form the third strip mask layer on the three-dimensional memory substrate;

[0119] Form the fourth strip mask layer on the third strip mask layer;

[0120] Selectively remove the first sacrificial layer in the third strip mask layer and the fourth strip mask layer, and the remaining first filling layer constitutes the second mesh mask layer.

[0121] Based on the above embodiments, as Figure 2 shown, the preparation process of the annular groove array in this embodiment includes:

[0122] Deposit a third hard mask layer, a third sacrificial layer, and a fourth hard mask layer on the three-dimensional memory substrate in sequence, and form the second mesh mask layer on the fourth hard mask layer;

[0123] Etch the fourth hard mask layer and the third sacrificial layer using the second mesh mask layer as a template to form a plurality of circular holes;

[0124] Deposit a second covering layer uniformly, and the second covering layer grows uniformly on the surface and the side, and the thickness of the second covering layer is g;

[0125] Remove the second covering layer on the surface, retain the second covering layer on the side, and remove the remaining fourth hard mask layer and third sacrificial layer on the surface;

[0126] Deposit a second filling layer and make the surface flat through planarization technology, and expose the surface of the second covering layer. The strip ring width of the second covering layer is g;

[0127] Selectively remove the second covering layer, and etch the third hard mask layer and the three-dimensional memory substrate using the remaining second filling layer as a template to form the annular groove array on the three-dimensional memory substrate, and the ring width of the annular groove is g.

[0128] Figure 2 In 2.15, the first sacrificial layer in the third strip mask layer and the fourth strip mask layer is selectively removed, and the remaining first filling layer forms a second mesh mask layer. Using the second mesh mask layer as a template, the fourth hard mask layer and the third sacrificial layer are etched to form a plurality of circular holes;

[0129] Figure 2 In 2.16, a second covering layer is uniformly deposited. The second covering layer grows uniformly on the surface and the side surfaces, and the thickness of the second covering layer is g;

[0130] Figure 2 In 2.17, the second covering layer on the surface is removed, and the second covering layer on the side surfaces is retained;

[0131] Figure 2 In 2.18, the remaining fourth hard mask layer and the third sacrificial layer on the surface are removed; a second filling layer is deposited;

[0132] Figure 2 In 2.19, the surface of the substrate is planarized by a planarization technique to expose the surface of the second covering layer. The width of the strip ring of the second covering layer is g;

[0133] Figure 2 In 2.20, the second covering layer is selectively removed;

[0134] Figure 2 In 2.21, using the remaining second filling layer as a template, the third hard mask layer and the three-dimensional memory substrate are etched;

[0135] Figure 2 In 2.22, the surface residues are removed to form an array of annular grooves on the three-dimensional memory substrate.

[0136] Figure 3 This is a schematic diagram of the preparation process flow provided by the present invention. Among them, Figure 3 In 3.1 to 3.14 are the preparation process flows of the circular holes, including:

[0137] Figure 3 In 3.1, the bottom layer is a three-dimensional memory substrate formed by alternately stacking 50 nm W and 100 nm SiO2, and the top layer of the three-dimensional memory substrate is 100 nm SiO2; 50 nm SiO2, 20 nm Cr, 50 nm SiO2, and 20 nm Cr are sequentially grown on the three-dimensional memory substrate, and the top layer is a photoresist line with a line width of 50 nm and a pitch of 80 nm;

[0138] Figure 3In 3.2, using the photoresist line as a mask, etch the topmost 50 nm SiO2 and 20 nm Cr;

[0139] Figure 3 In 3.3, uniformly deposit a 15 nm SiN layer using the ALD process;

[0140] Figure 3 In 3.4, use ICP etching with good anisotropy to remove the surface SiN, and use wet etching to selectively remove the remaining SiO2 and Cr, retaining the SiN on the sidewalls. The remaining strip-shaped SiN is parallel to each other, with a strip width of 15 nm, a spacing of 50 nm, and a period of 65 nm;

[0141] Figure 3 In 3.5, using the SiN on the sidewalls as a mask, etch the underlying 50 nm SiO2 and 20 nm Cr;

[0142] Figure 3 In 3.6, deposit a 100 nm SiN layer using PVD and use CMP to remove the surface SiN, exposing the upper surface of SiO2;

[0143] Figure 3 Repeat the processes in 3.7 to 3.13; Figure 3 Repeat the processes in 3.1 to 3.6, with the only difference being that the topmost photoresist line forms a 45° angle with the photoresist line in 3.1;

[0144] Figure 3 In 3.14, use buffered oxide etchant (BOE) to selectively remove SiO2, and etch the three-dimensional memory substrate using the remaining SiN as a template to form an array of circular holes on the substrate, with a diameter of 23 nm for the circular holes;

[0145] Figure 3 The processes in 3.15 to 3.36 are the process flow for preparing the annular grooves;

[0146] Figure 3 In 3.15, sequentially deposit 20 nm Cr, 50 nm SiO2, 20 nm Cr, 50 nm SiO2, 20 nm Cr, 50 nm SiO2, 20 nm Cr on the surface of the three-dimensional memory substrate with the circular hole array prepared, and the topmost layer is a photoresist line with a line width of 30 nm and a spacing of 100 nm, and the projection center line of the topmost photoresist line coincides with the projection center line of the topmost photoresist line in 3.1;

[0147] Figure 3 In 3.16, using the photoresist line as a mask, etch the topmost 50 nm SiO2 and 20 nm Cr;

[0148] Figure 3 In 3.17, a 35-nm SiN layer is uniformly deposited using the ALD process;

[0149] Figure 3 In 3.18, the surface SiN is removed using ICP etching with better anisotropy, and the remaining SiO2 and Cr are selectively removed using wet etching, leaving the SiN on the sidewalls. The remaining strip-shaped SiN is parallel to each other, with a strip width of 35 nm and a spacing of 30 nm, and a period of 65 nm;

[0150] Figure 3 In 3.19, the underlying 50-nm SiO2 and 20-nm Cr are etched using the SiN on the sidewalls as a mask;

[0151] Figure 3 In 3.20, a 100-nm SiN layer is deposited using PVD;

[0152] Figure 3 In 3.21, the surface SiN is removed using CMP, exposing the upper surface of the SiO2;

[0153] Figure 3 The processes from 3.22 to 3.28 in [] are repeated Figure 3 The processes from 3.15 to 3.21 in [] are repeated, with the only difference being that the top-layer photoresist lines are at a 45° angle to the photoresist lines in 3.15;

[0154] Figure 3 In 3.29, the SiO2 is selectively removed using buffered oxide etchant (BOE), and the underlying 20-nm Cr and 50-nm SiO2 are etched using the remaining SiN as a template to form a circular hole array with a hole diameter of 53 nm;

[0155] Figure 3 In 3.30, a 10-nm SiN layer is uniformly deposited using the ALD process;

[0156] Figure 3 In 3.31, the surface SiN is removed using ICP etching with better anisotropy, and the SiO2 is selectively removed using buffered oxide etchant (BOE), leaving the SiN on the sidewalls;

[0157] Figure 3 In 3.32, a 100-nm SiO2 layer is deposited using PVD;

[0158] Figure 3 In 3.33, the surface SiO2 is removed using CMP, exposing the upper surface of the SiN;

[0159] Figure 3 In 3.34, selectively remove SiN;

[0160] Figure 3 In 3.35, using the remaining SiO2 as a template, etch Cr and the 3D memory substrate;

[0161] Figure 3 In 3.36, obtain an annular groove array and a circular hole array prepared on the 3D memory substrate, where the diameter of the circular hole is 23 nm, the inner diameter of the annular groove is 33 nm, and the width of the annular groove is 10 nm.

Claims

1. A three-dimensional memory fabrication process based on self-aligned dual imaging, characterized in that, Comprising: Forming a first mesh mask layer on a three-dimensional memory substrate, and transferring the pattern of the first mesh mask layer to the three-dimensional memory substrate by etching to form an array of circular holes; Forming a second mesh mask layer on the three-dimensional memory substrate, and transferring the pattern of the second mesh mask layer to the three-dimensional memory substrate by etching to form an array of annular grooves; The annular grooves in the array of annular grooves correspond one-to-one with the circular holes in the array of circular holes, and the circular holes are located at the centers of the corresponding annular grooves; The first mesh mask layer includes a first strip mask layer and a second strip mask layer, and the second mesh mask layer is composed of a third strip mask layer and a fourth strip mask layer; The first strip mask layer, the second strip mask layer, the third strip mask layer, and the fourth strip mask layer are all prepared by self-aligned double imaging; The pitch of all strip lines in the first strip mask layer and the second strip mask layer is c, and the width of the strip lines is a; The pitch of all strip lines in the third strip mask layer and the fourth strip mask layer is f, and the width of the strip lines is d; Wherein, a + c = d + f, d < a, f > c.

2. The three-dimensional memory fabrication process based on self-aligned dual imaging according to claim 1, wherein The preparation process of the first strip mask layer includes: Successively forming a first sacrificial layer, a first hard mask layer, a second sacrificial layer, and a second hard mask layer on the three-dimensional memory substrate; Leaving a plurality of parallel first strip photoresists on the second hard mask layer by photolithography, the strip width of the first strip photoresist being a and the pitch being b; Etching the second hard mask layer and the second sacrificial layer using the first strip photoresist as a mask; Uniformly depositing a first covering layer, the first covering layer growing uniformly on the surface and the side surfaces, and the thickness of the first covering layer being c; Removing the first covering layer on the surface and retaining the first covering layer on the side surfaces; Etching the first hard mask layer and the first sacrificial layer using the first covering layer as a mask; Depositing a first filling layer, and making the surface flat by a planarization technique, and exposing the surface of the first sacrificial layer, the strip width of the first sacrificial layer being c, and the strip width of the first filling layer being a.

3. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 2, wherein The thickness c of the first covering layer has a relationship with the strip width a and the pitch b: a = b - 2c.

4. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 2, characterized in that, The preparation process and dimensions of the second strip mask layer are the same as those of the first strip mask layer; The angle α between the lines in the second strip mask layer and the first strip mask layer in the horizontal direction is > 30°; 5. The three-dimensional memory fabrication process based on self-aligned dual imaging according to claim 2, wherein, The preparation process of the first mesh mask layer includes: Forming a first strip mask layer on the three-dimensional memory substrate; Forming a second strip mask layer on the first strip mask layer; Selectively removing the first sacrificial layer in the first strip mask layer and the second strip mask layer, and the remaining first filling layer constitutes the first mesh mask layer.

6. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 2, wherein The preparation process of the third strip mask layer is the same as that of the first strip mask layer; In the preparation process of the third strip-shaped mask layer, the strip width of the first strip-shaped photoresist is d, the spacing is e, the thickness of the first covering layer is f, the final strip width of the first sacrificial layer is f, and the final strip width of the first filling layer is d; wherein, d + e = a + b.

7. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 6, characterized in that, The thickness f of the first covering layer has a relationship with the strip width d and the spacing e: d = e - 2f.

8. The three-dimensional memory fabrication process based on self-aligned dual imaging according to claim 6, wherein The preparation process and dimensions of the fourth strip-shaped mask layer are the same as those of the third strip-shaped mask layer; The angle α between the lines in the horizontal direction of the fourth strip-shaped mask layer and the third strip-shaped mask layer is greater than 30°; The lines in the third strip-shaped mask layer and the first strip-shaped mask layer are parallel to each other, and their projection centers coincide in the vertical direction; The lines in the fourth strip-shaped mask layer and the second strip-shaped mask layer are parallel to each other, and their projection centers coincide in the vertical direction.

9. The three-dimensional memory manufacturing process based on self-aligned dual imaging according to claim 8, characterized in that, The preparation process of the second mesh mask layer includes: Forming the third strip-shaped mask layer on the three-dimensional memory substrate; Forming the fourth strip-shaped mask layer on the third strip-shaped mask layer; Selectively removing the first sacrificial layer in the third strip-shaped mask layer and the fourth strip-shaped mask layer, and the remaining first filling layer constitutes the second mesh mask layer.

10. The three-dimensional memory fabrication process based on self-aligned dual imaging according to any one of claims 1-9, characterized in that, The preparation process of the annular groove array includes: Sequentially depositing a third hard mask layer, a third sacrificial layer, and a fourth hard mask layer on the three-dimensional memory substrate, and forming the second mesh mask layer on the fourth hard mask layer; Using the second mesh mask layer as a template to etch the fourth hard mask layer and the third sacrificial layer to form a plurality of circular holes; Uniformly depositing a second covering layer, which grows uniformly on the surface and the side, and the thickness of the second covering layer is g; Removing the second covering layer on the surface, retaining the second covering layer on the side, and removing the remaining fourth hard mask layer and the third sacrificial layer on the surface; Depositing a second filling layer and making the surface flat through a planarization technique, and exposing the surface of the second covering layer. The strip ring width of the second covering layer is g; Selectively removing the second covering layer, and using the remaining second filling layer as a template to etch the third hard mask layer and the three-dimensional memory substrate to form the annular groove array on the three-dimensional memory substrate, and the ring width of the annular groove is g.

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