Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. According to the semiconductor device, the body lines are led out from the body contact areas in the transistors, the body lines serve as carrier channels, and carriers induced by different vertical transistors are transmitted. Therefore, the semiconductor structure has extremely low off-state current in a relatively wide grid-controlled voltage range, the floating body effect of the semiconductor structure is effectively reduced, the positive conduction of a parasitic PN junction is prevented, and the leakage current is remarkably reduced. Besides, not only part of the body lines are located in the body contact region in the transistor without occupying extra area, but also the bit lines, the word lines and the body lines are arranged in the channel region in an overlapping manner in the first direction, and the connection among the bit lines, the word lines and the body lines is blocked through the isolation material. Inherent intervals among a bit line, a word line and a body line in a DRAM array structure of a traditional gate-all-around transistor are eliminated, and size miniaturization of a semiconductor device is facilitated.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In the field of DRAM (Dynamic Random Access Memory), the mainstream process development direction will adopt a vertical transistor structure with vertical distribution of source, gate and drain as a 4F with higher storage density. 2 The DRAM memory cell is constructed to improve the integration of DRAM. However, the floating body effect (FBE) and gate induced drain leakage (GIDL) of traditional vertical channel transistors will increase the off-state current of the device, which to some extent hinders its further application in high-performance DRAM. Summary of the invention

[0003] In view of this, the present application provides a semiconductor device and a method for manufacturing the same, which can achieve further miniaturization of DRAM memory cells while having extremely low off-state current within a wider gate control voltage range by leading out body lines through body contacts in a vertical channel region.

[0004] According to one aspect of the present application, there is provided a semiconductor device, comprising:

[0005] substrate;

[0006] A transistor is formed on a substrate, a channel region is formed between adjacent transistors, the transistor comprises a surrounding gate layer, a source layer, a drain layer and a body contact layer, the surrounding gate layer is in contact with the source layer and the drain layer, a body contact cavity is provided between the source layer and the drain layer, an opening of the body contact cavity is located at a side of the transistor away from the surrounding gate layer, and the body contact layer is located in the body contact cavity;

[0007] A bit line is formed at the bottom of the channel region and extends along the second direction, and the transistor is coupled to the bit line;

[0008] A word line, on the dielectric layer in the channel region, the word line extending along a first direction and perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line;

[0009] A body line is formed in the body contact cavity and the channel region, the body line contacts the body contact layer and is isolated from the source layer, the drain layer, and the word line, wherein the body line extends along the second direction and is parallel to the bit line.

[0010] Optionally, the transistor further comprises:

[0011] A channel layer is formed on a side of the transistor away from the body contact cavity opening. In the vertical direction of the semiconductor device, the doping concentration of the first part of the channel layer is higher than the doping concentration of the second part of the channel layer. The first part of the channel layer is connected to the body contact layer, the third part of the channel layer is respectively connected to the source layer and the drain layer, and the second part of the channel layer is located between the first part and the third part of the channel layer.

[0012] Optionally, in the vertical direction of the semiconductor device, the height of the first portion of the channel layer is greater than the height of the body contact layer, and the doping type of the channel layer is the same as the doping type of the source layer, the drain layer or the body contact layer in contact with the channel layer.

[0013] Optionally, the channel region extends along the second direction.

[0014] Optionally, along the first direction, a spacing between the bit line and the transistor in the first direction is the same as a width of the transistor, and the spacing between the transistors is less than 50 nm.

[0015] According to another aspect of the present application, there is provided a method for manufacturing a semiconductor device, comprising:

[0016] A matrix-distributed transistor is formed on a substrate, wherein a channel region is formed between adjacent transistors, the transistor comprises a surrounding gate layer, a source layer, a drain layer and a body contact layer, the surrounding gate layer is in contact with the source layer and the drain layer, a body contact cavity is provided between the source layer and the drain layer, the body contact cavity opens toward a side of the transistor away from the surrounding gate layer, and the body contact layer is located in the body contact cavity;

[0017] forming a bit line extending along a second direction at the bottom of the channel region, and depositing a dielectric layer, wherein the dielectric layer covers the substrate and the bit line;

[0018] forming a word line extending along a first direction and perpendicular to the bit line on the dielectric layer;

[0019] A body line is formed in the body contact cavity and the channel region, wherein the body line extends along the second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, the drain layer, and the word line.

[0020] Optionally, the transistors distributed in a matrix are formed on the substrate, and a bit line extending along the second direction is formed at the bottom of the channel region, comprising:

[0021] A device precursor is prepared on a substrate, wherein the device precursor includes a source-drain structure and a first etched sacrificial layer distributed along a first direction, a first trench or a second trench deep into the substrate is provided between adjacent source-drain structures, the first etched sacrificial layer covers the source-drain structure and fills the first trench and the second trench, the source-drain structure includes a source layer, a drain layer, a body contact sacrificial layer and a body contact layer, the body contact sacrificial layer is located between the source layer and the drain layer, the body contact layer is sandwiched in the body contact sacrificial layer, and a channel layer is formed on the inner wall of the first trench;

[0022] Etching the first etched sacrificial layer and the source-drain structure located at a designated side of the second trench according to the device region, and retaining a portion of the source layer on the substrate as a bit line;

[0023] Etching the remaining first etched sacrificial layer, and depositing a dielectric layer on the substrate and the bit line to form a channel region;

[0024] Removing the body contact sacrificial layer in the source-drain structure to form a body contact cavity opening toward a side of the source-drain structure away from the channel layer;

[0025] A high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source-drain structure, and the high dielectric constant material and the metal gate material on the side of the source-drain structure close to the body contact cavity opening are removed according to a preset width to form a surrounding gate layer to form a transistor, wherein the body contact layer is exposed outside the surrounding gate layer.

[0026] Optionally, preparing a device precursor on a substrate includes:

[0027] Growing a source layer, a first body contact sacrificial layer, a body contact layer, a second body contact sacrificial layer and a drain layer in sequence on the substrate along the vertical direction of the semiconductor device to form a stacked structure;

[0028] A patterned structure is formed on the stacked structure by a graphic process, and sidewalls are made on both sides of the patterned structure, wherein the patterned structure includes a core mold sacrificial layer and a second etched sacrificial layer grown in sequence;

[0029] Etching the stacked structure with the boundary of the sidewall as a barrier to form a first trench deep into the substrate;

[0030] epitaxially growing a channel layer on an inner wall of the first trench;

[0031] grinding the second etched sacrificial layer to expose the mandrel sacrificial layer, and removing the mandrel sacrificial layer;

[0032] The stacked structure is etched using the boundary of the sidewall generated after removing the sacrificial layer of the core mold as a mask to form a second trench deep into the substrate and a source-drain structure;

[0033] A first etched sacrificial layer is deposited on the first trench, the second trench, and the source-drain structure to form a device precursor.

[0034] Optionally, epitaxially growing a channel layer on an inner wall of the first trench includes:

[0035] epitaxially growing a single crystal channel on the inner wall of the first trench;

[0036] The single crystal channel is subjected to thermal annealing treatment so that the stacked structure is doped and driven into the single crystal channel to form a channel layer.

[0037] Optionally, an angle between the device region and the second direction is 55° to 65°.

[0038] Optionally, along the first direction, the width of the core mold sacrificial layer is the spacing between transistors, the width of the transistor is the sum of the width of the side wall and the thickness of the channel layer, the width of the first groove is the sum of the width of the core mold sacrificial layer and twice the thickness of the channel layer, and the spacing between transistors or the width of the transistor is less than 50nm.

[0039] Optionally, forming a word line extending along a first direction and perpendicular to the bit line on the dielectric layer in the channel region includes:

[0040] sequentially depositing a high dielectric constant material and a metal gate material on the dielectric layer;

[0041] The high dielectric constant material and the metal gate material on the dielectric layer are etched according to the word line region to form a word line.

[0042] Optionally, forming a body line in the body contact cavity and the channel region comprises:

[0043] growing an etch stop layer on the word line and surrounding gate layer;

[0044] removing a portion of the etching stop layer covering the word line to form a gap exposing the word line;

[0045] Filling the isolation layer in the body contact cavity and gap, and keeping the body contact layer exposed outside the isolation layer;

[0046] depositing a conductive material over the transistor and channel regions;

[0047] The conductive material in contact with the transistor and part of the conductive material covering the etch stop layer are removed to form a body line.

[0048] By means of the above technical solution, the body line is led out in the body contact area inside the transistor to ensure that the body line can connect to the transistor, and the body line is used as a carrier channel to transmit the carriers induced by different vertical transistors. On the one hand, the problem of unstable threshold voltage of the vertical transistor caused by the existence of excess carriers is avoided, and the off-state current is extremely low in a wider gate control voltage range, which effectively reduces the floating body effect of the semiconductor structure, prevents the parasitic PN junction from forward conduction, and significantly reduces the leakage current. On the other hand, the source, gate and drain are arranged in a vertical direction perpendicular to the substrate surface, and part of the body line is located in the body contact area inside the transistor, without the need for additional area. At the same time, the bit line, word line and body line are all arranged in the channel area in an overlapping form in the first direction, and the connection between the three is blocked by an isolation material, eliminating the inherent spacing between the bit line, word line and body line in the DRAM array structure of the traditional ring gate transistor, which is conducive to the miniaturization of the size of the semiconductor device.

[0049] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0051] Figure 1 A partial cross-sectional view of a semiconductor device provided by an embodiment of the present application in a first direction is shown;

[0052] Figure 2 A cross-sectional view of a stacked structure provided by an embodiment of the present application in a first direction is shown;

[0053] Figure 3 A cross-sectional view of the structure along a first direction after manufacturing the side wall provided by an embodiment of the present application is shown;

[0054] Figure 4 A cross-sectional view of a structure along a first direction after a first groove is formed provided in an embodiment of the present application is shown;

[0055] Figure 5 A structural cross-sectional view along a first direction after epitaxial growth of a single crystal channel provided by an embodiment of the present application is shown;

[0056] Figure 6 A cross-sectional view of a structure along a first direction after a channel layer is grown according to an embodiment of the present application is shown;

[0057] Figure 7 A partial cross-sectional view of a device precursor provided by an embodiment of the present application in a first direction is shown;

[0058] Figure 8 A top view of a device precursor provided by an embodiment of the present application is shown;

[0059] Fig. 9 A cross-sectional view of a structure along a first direction after a channel region is formed according to an embodiment of the present application is shown;

[0060] Fig.10 A cross-sectional view of the structure along the photoresist angle after the body contact sacrificial layer is removed provided in an embodiment of the present application is shown;

[0061] Fig.11 A cross-sectional view of a structure along a first direction after a high dielectric constant material and a conductive material are sequentially deposited on a dielectric layer provided by an embodiment of the present application is shown;

[0062] Fig.12 A cross-sectional view of a structure along a first direction after forming transistors and word lines provided in an embodiment of the present application is shown;

[0063] Fig.13 A cross-sectional view of the structure along a first direction after filling an isolation layer provided in an embodiment of the present application is shown;

[0064] Fig.14 A structural cross-sectional view along the first direction of a deposition body line provided by an embodiment of the present application is shown.

[0065] Reference numerals:

[0066] 110 substrate, 121 source and drain structure, 122 channel layer, 123 single crystal channel, 124 patterned structure, 125 sidewall, 126 surrounding gate layer, 130 bit line, 140 word line, 150 body line, 160 first etching sacrificial layer, 170 third etching sacrificial layer, 180 fourth etching sacrificial layer, 190 channel region, 210 first trench, 221 dielectric layer, 220 second trench, 230 etch stop layer, 240 photoresist, 250 isolation layer, 1212 source layer, 1213 drain layer, 1214 body contact layer, 1215 first body contact sacrificial layer, 1216 second body contact sacrificial layer, 1221 first part of the channel layer, 1222 second part of the channel layer, 1223 third part of the channel layer, 1241 oxide layer, 1242 core mold sacrificial layer, 1243 second etching sacrificial layer. DETAILED DESCRIPTION

[0067] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0068] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0069] It will be understood by those skilled in the art that, unless otherwise stated, the singular forms "one", "an", "and", and "the" used herein may also include plural forms. It should be further understood that the term "including" used in the specification of the present application refers to the presence of features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. In addition, the term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items. The terms "first", "second", "third", etc. used herein are only used for descriptive purposes and cannot be understood as indicating or implying relative importance; the term "multiple" used herein refers to two or more, unless otherwise clearly defined. The terms "installed", "connected", "connected", "fixed" and the like used herein should be understood in a broad sense, for example, "connected" can be a fixed connection, a detachable connection, or an integral connection; "connected" can be directly connected or indirectly connected through an intermediate medium. When we say that an element is "connected" or "connected" to another element, it can be directly connected or connected to other elements, or there can be intermediate elements. For those skilled in the art, the specific meanings of the above terms in the embodiments of the invention can be understood according to specific circumstances. The terms "upper", "lower", "left", "right", "front", "rear", etc. used herein indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the invention and simplifying the description, and do not indicate or imply that the devices or units referred to must have a specific direction, be constructed and operated in a specific direction, and therefore, cannot be understood as limiting the embodiments of the invention.

[0070] Now, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0071] In this embodiment, a semiconductor device is provided, such as Figure 1As shown, a semiconductor device is a DRAM transistor array as an example for description. The semiconductor device includes: a substrate 110 , transistors (not shown in the figure), a bit line 130 , a word line 140 , and a body line 150 .

[0072] Among them, Figure 1 and Fig. 9 As shown, transistors are formed on a substrate 110 and arranged in a matrix, with channel regions 190 between adjacent transistors, so that the channel regions 190 can extend along the second direction.

[0073] The transistor includes a surrounding gate layer 126, a source layer 1212, a drain layer 1213 and a body contact layer 1214. The surrounding gate layer 126 is connected to the source layer 1212 and the drain layer 1213. A body contact cavity is provided between the source layer 1212 and the drain layer 1213. The opening of the body contact cavity is located at a side of the transistor away from the surrounding gate layer 126. The body contact layer 1214 is located in the body contact cavity and extends along the second direction.

[0074] The bit line 130 is formed at the bottom of the channel region 190 and extends along the second direction. The transistor is coupled to the bit line 130 .

[0075] The word line 140 is formed on the dielectric layer 221 in the channel region 190 and extends along a first direction and is perpendicular to the bit line 130. The dielectric layer 221 covers the substrate 110 and the bit line 130 to isolate the word line 140 from the substrate 110 and the bit line 130.

[0076] The body line 150 is formed in the body contact cavity and the channel region 190 , and contacts the body contact layer 1214 , and is isolated from the source layer 1212 , the drain layer 1213 , and the word line 140 . The body line 150 extends along the second direction and is parallel to the bit line 130 .

[0077] In this embodiment, the body line is led out in the body contact area inside the transistor to ensure that the body line can connect to the transistor, and the body line is used as a carrier channel to transmit the carriers induced by different vertical transistors. On the one hand, the problem of unstable threshold voltage of the vertical transistor caused by the presence of excess carriers is avoided, and an extremely low off-state current is provided in a wider gate control voltage range, which effectively reduces the floating body effect of the semiconductor structure, prevents the parasitic PN junction from forward conduction, and significantly reduces the leakage current. On the other hand, the source, gate and drain are arranged in a vertical direction perpendicular to the substrate surface, and part of the body line is located in the body contact area inside the transistor, without the need for additional area. At the same time, the bit line, word line and body line are all arranged in the channel area in an overlapping form in the first direction, and the connection between the three is blocked by an isolation material, thereby eliminating the inherent spacing between the bit line, word line and body line in the DRAM array structure of the traditional ring-gate transistor, which is conducive to the miniaturization of the size of the semiconductor device.

[0078] It can be understood that along the first direction, the spacing between the bit lines and the transistors in the first direction is the same as the width of the transistors, and the spacing between the transistors is less than 50nm, such as 10nm, 15nm, 26nm, etc., which helps to reduce the size of the semiconductor device.

[0079] Specifically, the substrate can be formed of a silicon-containing semiconductor material, for example, a combination or multiple layers of silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, and carbon-doped silicon. Taking a P-well / NMOS device as an example, a P-type well region is implanted on single crystal silicon to form a substrate with a P-type well region.

[0080] The body contact layer can be a conductive material such as metal, metal nitride, metal silicide, for example, heavily doped P-type silicon (P+Si). The bit line can be a semiconductor material, a metal-based material or a combination thereof, for example, heavily doped N-type silicon. The word line, body line, and surrounding gate layer can include silicon oxide, silicon nitride, silicon oxynitride, high dielectric material or a combination thereof. The source layer and the drain layer can be made of semiconductor materials doped with P-type impurities or N-type impurities. For example, for a p-type device, the source layer and the drain layer can have p-type doped silicon or silicon germanium, and for an n-type device, the source layer and the drain layer can have n-type doped silicon or silicon germanium.

[0081] In one embodiment, if Figure 1 As shown, the transistor is provided with a channel layer 122 at the side where the surrounding gate layer 126 is located (the side of the transistor away from the body contact cavity opening). The channel layer 122 can be connected to the source layer 1212, the drain layer 1213 and the body contact layer 1214, so as to form a sidewall of the body contact cavity away from the opening, and at least part of the channel layer 122 is located between the surrounding gate layer 126 and at least one of the source layer 1212, the drain layer 1213 and the body contact layer 1214.

[0082] Specifically, Figure 6 As shown, in the vertical direction of the semiconductor device, the doping concentration of the first portion 1221 of the channel layer is higher than the doping concentration of the second portion 1222 of the channel layer, the first portion 1221 of the channel layer is connected to the body contact layer 1214, the third portion 1223 of the channel layer is respectively connected to the source layer 1212 and the drain layer 1213, and the second portion 1222 of the channel layer is located between the first portion 1221 and the third portion 1223 of the channel layer. The thickness of the channel layer 122 is between 3nm and 20nm, for example, 5nm, 8nm, 10nm, 15nm, etc., and can be reasonably set according to the size of the transistor.

[0083] It will be appreciated that the channel layer may be formed by epitaxial growth.

[0084] In this embodiment, due to the characteristics that the first part of the channel layer has a high doping concentration and the second part of the channel layer has a low doping concentration, the second part of the channel layer with a low doping concentration can reduce the energy band barrier along the channel direction, obtain a more stable electric field and energy band, thereby inhibiting inter-band tunneling and reducing gate-induced drain leakage.

[0085] It is worth mentioning that Figure 6 As shown, in the vertical direction of the semiconductor device, the height of the first portion 1221 of the channel layer is greater than the height of the body contact layer 1214. In this way, since the body contact layer 1214 is connected to the first portion 1221 with a high doping concentration, and at the same time ensures that the first portion 1221 of the channel layer does not affect the region where gate-induced drain leakage is generated, there can be an obvious depletion region, thereby achieving the control of the off-state current of the semiconductor device by the body contact layer bias voltage.

[0086] Furthermore, the channel layer can be symmetrical or asymmetrical relative to the body contact layer, that is, the extension heights of the first, second and third parts of the channel layer above the body contact layer are the same as or different from the extension heights of the corresponding first, second and third parts below the body contact layer.

[0087] In this embodiment, a method for manufacturing a semiconductor device is provided, the method comprising:

[0088] Step 301, forming transistors distributed in a matrix on a substrate.

[0089] A channel region is formed between adjacent transistors, and the transistor includes a surrounding gate layer, a source layer, a drain layer and a body contact layer. The surrounding gate layer contacts the source layer and the drain layer for isolation. A body contact cavity is provided between the source layer and the drain layer. The body contact cavity opens toward a side of the transistor away from the surrounding gate layer. The body contact layer is located in the body contact cavity to form a body-contacted vertical channel transistor (BCVCT).

[0090] Step 302: forming a bit line extending along a second direction at the bottom of the channel region, and depositing a dielectric layer.

[0091] The dielectric layer covers the substrate and the bit line.

[0092] In this embodiment, the bit line is first made at the bottom of the channel region between the transistors. This not only ensures the connectivity between the transistors and the bit line, but also enables the bit line layout to be combined with the transistors distributed in a matrix, so that the bit line can connect multiple transistors in a regular manner, reducing the space occupied by the bit line on the chip and optimizing the space utilization of the semiconductor device. Then, a dielectric layer is deposited in the channel region so that the dielectric layer can cover the substrate and the bit line in the channel region, thereby effectively isolating the transistor and the bit line from other conductive structures, helping to reduce parasitic capacitance and resistance, and preventing electromagnetic interference and signal crosstalk, thereby improving the working efficiency and response speed of the semiconductor device.

[0093] Further, as a refinement and extension of the specific implementation of the above embodiment, in order to fully illustrate the specific implementation process of this embodiment, step 301 and step 302, that is, forming transistors distributed in a matrix on the substrate, forming a bit line extending along the second direction at the bottom of the channel region, specifically include:

[0094] A device precursor is prepared on a substrate; a first etching sacrificial layer and a source-drain structure located on a specified side of a second groove are etched according to the device region, and a portion of the source layer on the substrate is retained as a bit line; the remaining first etching sacrificial layer is etched, and a dielectric layer is deposited on the substrate and the bit line to form a channel region; the body contact sacrificial layer in the source-drain structure is removed to form a body contact cavity opening toward a side of the source-drain structure away from the channel layer; a high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source-drain structure, and the high dielectric constant material and the metal gate material on a side of the source-drain structure close to the body contact cavity opening are removed according to a preset width to form a surrounding gate layer to form a transistor.

[0095] The body contact layer is exposed outside the surrounding gate layer to facilitate subsequent connection with the body line. Figure 7 , Figure 8 and Fig. 9 As shown, the device precursor includes a source-drain structure 121 and a first etched sacrificial layer 160 distributed along a first direction, and a first trench 210 or a second trench 220 deep to the substrate 110 is provided between adjacent source-drain structures 121, and the first etched sacrificial layer 160 covers the source-drain structure 121 and fills the first trench 210 and the second trench 220, and the source-drain structure 121 includes a source layer 1212, a drain layer 1213, a body contact sacrificial layer and a body contact layer 1214, the body contact sacrificial layer is located between the source layer 1212 and the drain layer 1213, the body contact layer 1214 is sandwiched in the body contact sacrificial layer, and a channel layer 122 is formed on the inner wall of the first trench 210. Specifically, the angle α between the device region and the second direction is 55° to 65°, and the angle can be flexibly determined according to process conditions and product requirements, and is not specifically limited in the embodiments of the present application.

[0096] Furthermore, preparing a device precursor on a substrate specifically includes: growing a source layer, a first body contact sacrificial layer, a body contact layer, a second body contact sacrificial layer and a drain layer in sequence on the substrate along the vertical direction of the semiconductor device to form a stacked structure; using a graphical process to form a patterned structure on the stacked structure, and making side walls on both sides of the patterned structure, wherein the patterned structure includes a core mold sacrificial layer and a second etching sacrificial layer grown in sequence; etching the stacked structure with the boundary of the side wall as a barrier to form a first groove deep to the substrate; epitaxially growing a channel layer on the inner wall of the first trench; polishing the second etching sacrificial layer to expose the core mold sacrificial layer, and removing the core mold sacrificial layer; etching the stacked structure with the boundary of the side wall generated after removing the core mold sacrificial layer as a mask to form a second groove deep to the substrate and a source-drain structure; depositing the first etching sacrificial layer on the first trench, the second trench, and the source-drain structure to form a device precursor.

[0097] The graphic process includes steps such as deposition, exposure, and etching.

[0098] In this embodiment, after one etching is completed using the core mold sacrificial layer, the stacked structure is further etched using the remaining spacer layer as a mask, thereby achieving spatial frequency doubling of the pattern and avoiding edge placement errors that may occur when separate cutting is performed at two locations.

[0099] Further, epitaxially growing a channel layer on the inner wall of the first trench specifically includes: epitaxially growing a single crystal channel on the inner wall of the first trench; and thermally annealing the single crystal channel to drive doping of the stacked structure into the single crystal channel to form a channel layer.

[0100] For example, Figure 2 As shown, an N-type or P-type well region is implanted on a suitable substrate 110 to serve as a corresponding subsequent P-type transistor or N-type transistor device region.

[0101] For N / NMOS devices, P-type implantation is performed, and for N-well / NMOS devices, N-type implantation is performed. The doping concentration can be adjusted accordingly depending on the doping type. Taking the P-well / NMOS device as an example, the well region (P-Si) of the substrate 110 is epitaxially stacked with the following materials from bottom to top along the vertical direction of the semiconductor device to form a stacked structure: heavily doped N-type silicon (N+Si), intrinsic silicon (i-Si), intrinsic germanium silicon (i-SiGe), thin heavily doped P-type germanium silicon (P+SiGe), thin heavily doped P-type silicon (P+Si), thin heavily doped P-type germanium silicon (P+SiGe), intrinsic germanium silicon (i-SiGe), intrinsic silicon (i-Si), and heavily doped N-type silicon (N+Si). Among them, the first layer of heavily doped N-type silicon and the first layer of intrinsic silicon are used to make the source layer 1212. The first layer of intrinsic silicon is also heavily doped after being diffused by heavily doped N-type silicon after thermal annealing to prevent the N-type heavy doping from diffusing into the intrinsic channel by thermal annealing, thereby preventing the channel from being shortened and avoiding the short channel effect. The intrinsic germanium silicon and the thin layer of heavily doped P-type germanium silicon on the source layer 1212 are used to make the first body contact sacrificial layer 1215 of the source layer 1212, the thin layer of heavily doped P-type silicon is used to make the body contact layer 1214, the intrinsic germanium silicon and the thin layer of heavily doped P-type germanium silicon on the body contact layer 1214 are used to make the second body contact sacrificial layer 1216, and the last layer of intrinsic silicon and the last layer of heavily doped N-type silicon are used to make the drain layer 1213. Specifically, the thickness of the thin layer can be adjusted according to the specific device performance requirements, so as to form a low-doped region corresponding to the channel layer through thermal annealing. The heavy doping concentration is approximately 1e19cm-3~1e20cm-3, which can be adjusted according to the specific device performance requirements.

[0102] like Figure 3 As shown, a thin oxide layer 1241, a core mold sacrificial layer 1242 (amorphous silicon can be used as a raw material) and a second etched sacrificial layer 1243 (silicon oxide can be used as a raw material) are continuously deposited on the stacked structure to form a patterned structure 124. Then, a patterning process and a silicon oxide sidewall 125 process are sequentially used to make sidewalls 125 on both sides of the patterned structure 124, so as to define the source and drain regions under the sidewall 125 structure. Figure 4As shown, the width of the core mold sacrificial layer 1242 is the spacing (a) of the transistors to be made. For an array of equal-width devices with equal spacing, the spacing between transistors is the same as the width of the transistor. It can be seen that the width (a) of the transistor is the sum of the width of the sidewall 125 and the thickness (b) of the channel layer 122. In this way, after the channel layer 122 is deposited in the first groove 210, the width of the remaining space in the first groove 210 can be the same as the width of the transistor, thereby ensuring the formation of an array of equal-width devices with equal spacing, wherein an array of equal-width devices with equal spacing means that the device spacings are equal to each other and the device widths are equal to each other. The device spacing and device width can be set to any value as required, and the two can be the same or different. In this embodiment, the device spacing and device width are the same. For example, the spacing of the transistors or the width of the transistor is about 15nm.

[0103] like Figure 3 and Figure 4 As shown, the sidewall 125 is used as a barrier layer for etching to complete the pattern transfer of the stacked structure below, thereby forming a first trench 210. Figure 4 and Figure 5 As shown, a single crystal Si is epitaxially grown on the inner surface of the newly formed first trench 210 to form a single crystal channel 123. The width of the first trench 210 is the sum of the width (a) of the mandrel sacrificial layer 1242 and twice the thickness of the channel layer 122 (2b), so as to ensure that the distance between the two epitaxial single crystal channels 123 is also the width (a) of the mandrel sacrificial layer 1242. Figure 6 As shown, by moderate thermal annealing Figure 2 The stacked structure is doped and driven into the single crystal channel 123 formed by epitaxy to form a channel layer 122 with low doping at both ends of the channel and uniform high doping in the middle. After the first etching sacrificial layer 160 is filled and the surface of the core mode sacrificial layer 1242 is exposed by chemical mechanical polishing and planarization, the core mode sacrificial layer 1242 is wet removed, and the Si layer and SiGe layer in the stacked structure are etched using the sidewall formed by removing the core mode sacrificial layer 1242 as a mask, exposing the entire SiGe layer from the side, forming a second trench 220 deep on the substrate 110 and a source-drain structure 121. After the sacrificial layer is filled, the following is formed: Figure 7 and Figure 8 Device precursor shown.

[0104] like Figure 8 As shown, a single device region is defined by photolithography on the device precursor. The angle α between the photoresist 240 pattern and the vertical direction (the second direction in which the bit line 130 extends) in the figure is about 60°. For ease of understanding, Figure 8 Only two photoresist layers 240 are drawn, and the plane should be covered with equal spacing in reality; in addition, in order to facilitate understanding of the positional relationship between the source and drain structure 121 and the trench, the first etched sacrificial layer 160 above the source and drain structure 121 is hidden, and in fact, in order to protect the source and drain structure 121, such as Figure 7The first etched sacrificial layer 160 can cover the source-drain structure 121. The area covered by the photoresist 240 is used as the required device unit area, and the etched sacrificial layer outside the photoresist 240 is opened, and only the source layer 1212 at the bottom is retained to be connected as the bit line 130 (Bitline). Fig. 9 As shown, after removing the photoresist 240, the first etched sacrificial layer 160 is filled and etched back to remove the remaining first etched sacrificial layer 160, and a dielectric layer 221 is deposited on the substrate 110 and the bit line 130 in the second trench 220, thereby forming a channel region 190 between the source and drain structures 121. Fig.10 As shown, SiGe, ie, the body contact sacrificial layer, is removed by selective dry or wet etching, thereby forming a device structure with a thin body contact layer 1214, uniform doping in the center of a wide channel, and low doping on both sides of the channel.

[0105] Step 303: forming a word line extending along a first direction and perpendicular to the bit line on the dielectric layer.

[0106] In this embodiment, a word line extending in a first direction is formed on a dielectric layer covering the bit line. An isolated and vertically crossed bit line-word line layout is constructed, so that the overlapping area between the bit line and the word line is relatively small, effectively reducing the parasitic capacitance between them, reducing the scattering and leakage of the electric field. In addition, more transistors can be accommodated on a given substrate area, which facilitates the positioning and operation of each transistor through the corresponding bit line and word line, and achieves a higher storage density.

[0107] Further, as a refinement and extension of the specific implementation method of the above embodiment, in order to fully illustrate the specific implementation process of this embodiment, step 303 specifically includes: depositing a high dielectric constant material and a metal gate material on the dielectric layer in sequence; etching the high dielectric constant material and the metal gate material on the dielectric layer according to the word line area to form a word line.

[0108] Step 304 , forming a body line in the body contact cavity and the channel region.

[0109] The body line extends along the second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, the drain layer, and the word line.

[0110] In this embodiment, the body line is led out in the body contact area inside the transistor to ensure that the body line can connect to the transistor, and the body line is used as a carrier channel to transmit the carriers induced by different vertical transistors. On the one hand, the problem of unstable threshold voltage of the vertical transistor caused by the presence of excess carriers is avoided, and the off-state current is extremely low in a wider gate control voltage range, which effectively reduces the floating body effect of the semiconductor structure, prevents the parasitic PN junction from forward conduction, and significantly reduces the leakage current. On the other hand, the source, gate and drain are arranged in a vertical direction perpendicular to the substrate surface, and part of the body line is located in the body contact area inside the transistor, without the need for additional area. At the same time, the bit line, word line and body line are all arranged in the channel area in an overlapping form in the first direction, and the connection between the three is blocked by an isolation material, eliminating the inherent spacing between the bit line, word line and body line in the DRAM array structure of the traditional ring gate transistor, which is conducive to the miniaturization of the size of the semiconductor device.

[0111] Further, as a refinement and extension of the specific implementation methods of the above-mentioned embodiment, in order to fully illustrate the specific implementation process of this embodiment, step 304 specifically includes: growing an etch stop layer on the word line and the surrounding gate layer; removing a portion of the etch stop layer covering the word line to form a gap exposing the word line; filling an isolation layer in the body contact cavity and the gap, and keeping the body contact layer exposed outside the isolation layer; depositing a conductive material on the transistor and the channel region; removing the conductive material in contact with the transistor and a portion of the conductive material covering the etch stop layer to form a body line.

[0112] For example, Fig.11 As shown, HKMG ALD (High-kMetal Gate Atomic Layer Deposition) is grown on the dielectric layer 221 and the source-drain structure 121, and the VGAA (Vertical Gate-All-Around) structure of the device is formed. Thereafter, the word line 140 (Word Line) area is defined by photolithography. Anisotropic etching is performed in the word line area, the glue is removed, and an etch stop layer 230 is grown on the VGAA structure. The etch stop layer 230 can be made of silicon nitride (SiN). The third etch sacrificial layer 170 is filled to protect the device, and chemical mechanical polishing is performed for planarization.

[0113] like Fig.12As shown, the third etched sacrificial layer 170 on one side of the channel layer 122 is protected by the photoresist 240, and the exposed third etched sacrificial layer 170 is removed to a certain depth. After the degumming, isotropic etching is performed again to sequentially remove the metal gate and the high dielectric material to expose part of the word line 140, the source layer 1212, the drain layer 1213 and the body contact layer 1214. At this time, the remaining high dielectric material and the metal gate connected to the source and drain structure 121 and the channel layer 122 constitute the surrounding gate layer 126 of the transistor, and the remaining high dielectric material and the metal gate in the channel region 190 constitute the word line 140. Among them, the metal gate can be composed of a layer that modulates the work function (such as AlO) and a conductive material (such as W, Al).

[0114] like Fig.13 As shown, after HK-ALD is performed again, anisotropic high dielectric material etching and a small amount of isotropic etching are sequentially performed to expose the body contact layer 1214 to form the isolation layer 250. Finally, the exposed third etched sacrificial layer 170 is removed by wet method.

[0115] like Fig.14 As shown, a conductive material, such as tungsten, is deposited in the channel region 190 to deposit the body line 150 (Baseline), and the fourth etched sacrificial layer 180 is etched back to protect the subsequent body line 150 formation. The etching stop layer 230 and the fourth etched sacrificial layer 180 are used as stop layers for etching back. After removing the exposed fourth etched sacrificial layer 180, the remaining tungsten on the etch stop layer 230 that can be connected to the body contact layer 1214 constitutes the body line 150. The body line 150 is parallel to the bit line 130, and the body line 150 is defined by photolithography, thereby forming a structure as shown in FIG. Figure 1 The entire electrical structure of the front and middle sections is shown. The word line 140 extends along a first direction and is perpendicular to the bit line 130 and the body line 150, and the bit line 130 and the body line 150 are parallel to each other and extend along a second direction perpendicular to the first direction.

[0116] Optionally, the top n-Si can be removed anisotropically to ensure that there is no short circuit. In this embodiment, the material for etching the sacrificial layer can be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc. The conductive material can also be a metal such as aluminum, Figure 1 and Fig.14 Tungsten (W) is used as an example for illustration. In addition, a metal gate material may also be selected to make the body line.

[0117] It should be noted that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0118] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred implementation scenario, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present application.

[0119] In the description of this specification, the description of the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the invention embodiment. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0120] The above serial numbers of this application are only for description and do not represent the advantages and disadvantages of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of this application, but this application is not limited to them, and any changes that can be thought of by technicians in this field should fall within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that: include: substrate; A transistor is formed on the substrate, a channel region is formed between adjacent transistors, the transistor comprises a surrounding gate layer, a source layer, a drain layer and a body contact layer, the surrounding gate layer is in contact with the source layer and the drain layer, a body contact cavity is provided between the source layer and the drain layer, an opening of the body contact cavity is located at a side of the transistor away from the surrounding gate layer, and the body contact layer is located in the body contact cavity; A bit line formed at the bottom of the channel region and extending along the second direction, the transistor being coupled to the bit line; A word line is formed on the dielectric layer in the channel region, the word line extends along a first direction and is perpendicular to the bit line, wherein the dielectric layer covers the substrate and the bit line; A body line is formed in the body contact cavity and the channel region, the body line contacts the body contact layer and is isolated from the source layer, the drain layer, and the body line of the word line, wherein the body line extends along the second direction and is parallel to the bit line.

2. The semiconductor device according to claim 1, wherein: The transistor further comprises: A channel layer is formed on a side of the transistor away from the body contact cavity opening, the doping concentration of a first portion of the channel layer in the vertical direction of the semiconductor device is higher than the doping concentration of a second portion of the channel layer, the first portion of the channel layer is connected to the body contact layer, the third portion of the channel layer is respectively connected to the source layer and the drain layer, and the second portion of the channel layer is located between the first portion and the third portion of the channel layer; Wherein, in the vertical direction of the semiconductor device, the height of the first part of the channel layer is greater than the height of the body contact layer, and the doping type of the channel layer is the same as the doping type of the source layer, the drain layer or the body contact layer in contact with it.

3. The semiconductor device according to claim 1, wherein: The channel region extends along the second direction; Along the first direction, a distance between the bit line and the transistor in the first direction is the same as a width of the transistor, and a distance between the transistors is less than 50 nm.

4. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Forming transistors distributed in a matrix on a substrate, wherein a channel region is formed between adjacent transistors, the transistors include a surrounding gate layer, a source layer, a drain layer and a body contact layer, the surrounding gate layer is in contact with the source layer and the drain layer, a body contact cavity is provided between the source layer and the drain layer, the body contact cavity opens toward a side of the transistor away from the surrounding gate layer, and the body contact layer is located in the body contact cavity; forming a bit line extending along a second direction at the bottom of the channel region, and depositing a dielectric layer, wherein the dielectric layer covers the substrate and the bit line; forming a word line extending along a first direction and perpendicular to the bit line on the dielectric layer; A body line is formed in the body contact cavity and the channel region, wherein the body line extends along the second direction and is parallel to the bit line, contacts the body contact layer, and is isolated from the source layer, the drain layer, and the word line.

5. The method for manufacturing a semiconductor device according to claim 4, wherein: The transistors distributed in a matrix are formed on the substrate, and a bit line extending along a second direction is formed at the bottom of the channel region, comprising: A device precursor is prepared on the substrate, wherein the device precursor comprises a source-drain structure and a first etched sacrificial layer distributed along a first direction, a first trench or a second trench deep to the substrate is provided between adjacent source-drain structures, the first etched sacrificial layer covers the source-drain structure and fills the first trench and the second trench, the source-drain structure comprises the source layer, the drain layer, a body contact sacrificial layer and a body contact layer, the body contact sacrificial layer is located between the source layer and the drain layer, the body contact layer is sandwiched in the body contact sacrificial layer, and the channel layer is formed on the inner wall of the first trench; Etching the first etched sacrificial layer and the source-drain structure located at a designated side of the second trench according to the device region, and retaining a portion of the source layer on the substrate as the bit line; Etching the remaining first etching sacrificial layer, and depositing a dielectric layer on the substrate and the bit line to form the channel region; Removing the body contact sacrificial layer in the source-drain structure to form the body contact cavity opening toward a side of the source-drain structure away from the channel layer; A high dielectric constant material and a metal gate material are deposited in the body contact cavity and on the surface of the source-drain structure, and the high dielectric constant material and the metal gate material on the source-drain structure close to the body contact cavity opening are removed according to a preset width to form the surrounding gate layer to form the transistor, wherein the body contact layer is exposed outside the surrounding gate layer.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: The preparing a device precursor on the substrate comprises: Growing the source layer, the first body contact sacrificial layer, the body contact layer, the second body contact sacrificial layer and the drain layer in sequence on the substrate along the vertical direction of the semiconductor device to form a stacked structure; A patterned structure is formed on the stacked structure by a graphic process, and sidewalls are made on both sides of the patterned structure, wherein the patterned structure includes a core mold sacrificial layer and a second etched sacrificial layer grown in sequence; Etching the stacked structure with the boundary of the sidewall as a barrier to form the first trench deep into the substrate; epitaxially growing the channel layer on the inner wall of the first trench; grinding the second etched sacrificial layer to expose the mandrel sacrificial layer, and removing the mandrel sacrificial layer; Using the boundary of the sidewall generated after removing the core mold sacrificial layer as a mask, the stacked structure is etched to form the second trench and the source-drain structure deep into the substrate; The first etching sacrificial layer is deposited on the first trench, the second trench, and the source-drain structure to form the device precursor.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The epitaxially growing the channel layer on the inner wall of the first trench comprises: Epitaxially growing a single crystal channel on the inner wall of the first trench; The single crystal channel is subjected to thermal annealing treatment so that the stacked structure is doped and driven into the single crystal channel to form the channel layer.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: The angle between the device region and the second direction is 55° to 65°; Along the first direction, the width of the core mold sacrificial layer is the spacing of the transistors, the width of the transistor is the sum of the width of the side wall and the thickness of the channel layer, the width of the first groove is the sum of the width of the core mold sacrificial layer and twice the thickness of the channel layer, and the spacing of the transistors is less than 50nm.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming a word line extending along a first direction and perpendicular to the bit line on the dielectric layer in the channel region comprises: Depositing a high dielectric constant material and a metal gate material sequentially on the dielectric layer; The high dielectric constant material and the metal gate material on the dielectric layer are etched according to the word line region to form the word line.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a body line in the body contact cavity and the channel region comprises: growing an etch stop layer on the word line and the surrounding gate layer; removing a portion of the etch stop layer covering the word line to form a gap exposing the word line; Filling the body contact cavity and the gap with an isolation layer, and keeping the body contact layer exposed outside the isolation layer; depositing a conductive material over the transistor and the channel region; The conductive material in contact with the transistor and a portion of the conductive material covering the etch stop layer are removed to form the body line.

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