Device structure and forming method thereof

Abstract

The device structure comprises a first metal interconnection structure formed in a first dielectric material layer; the etching stop dielectric layer is positioned on the first dielectric material layer and is provided with an opening, and the opening has a first width along the first horizontal direction; and a resistive memory cell comprising a stack of a bottom electrode, a memory material layer, and a top electrode. The bottom electrode includes a plate portion and a via portion within an opening in the etch stop dielectric layer. A layer of memory material overlies the bottom electrode and is configured to provide at least two states having different resistances. A top electrode is over the memory material layer. The hard mask plate is located above the top electrode. The periphery of the top surface of the hard mask plate has a second width along the first horizontal direction, and the second width is greater than the first width. The embodiment of the invention also relates to a device structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to device structures and methods for forming the same. Background Art

[0002] A resistive memory cell comprises a resistive memory element in which a data bit can be encoded in a low resistance state or in a high resistance state. A plurality of resistive memory cells can be arranged in a two-dimensional array or in a three-dimensional array to provide random access to the resistive memory cells, in which case an array of resistive random access memory (RRAM) cells is provided. Summary of the invention

[0003] Some embodiments of the present application provide a device structure, including: a first metal interconnect structure formed in a first dielectric material layer; an etch stop dielectric layer located above the first dielectric material layer and having an opening, the opening having a first width along a first horizontal direction; a resistive memory cell, including a stack of a bottom electrode, a memory material layer, and a top electrode, wherein the bottom electrode includes a plate portion located above the etch stop dielectric layer and a through-hole portion located within the opening in the etch stop dielectric layer, the memory material layer is located above the bottom electrode, and the top electrode is located above the memory material layer; and a hard mask template located above the top electrode, wherein the periphery of a top surface of the hard mask template has a second width along the first horizontal direction that is greater than the first width.

[0004] Some other embodiments of the present application provide a device structure, including: an etch stop dielectric layer, including an annular portion having a first thickness and including an opening therethrough, and a planar layer portion having a second thickness less than the first thickness and laterally spaced from the opening by the annular portion, wherein the opening has a first width along a first horizontal direction; a resistive memory cell, including a stack of a bottom electrode, a memory material layer, and a top electrode, the bottom electrode including a through-hole portion extending vertically downward into the opening in the etch stop dielectric layer; and a hard mask template located above the top electrode, wherein a periphery of a top surface of the hard mask template has a second width greater than the first width along the first horizontal direction, wherein a tapered surface extends straight from the periphery of the top surface of the hard mask template at least to the top surface of the bottom electrode at a tapered angle relative to a vertical direction.

[0005] Some other embodiments of the present application provide a method for forming a device structure, comprising: forming an etch stop dielectric layer above a first metal interconnect structure formed in a first dielectric material layer; forming an opening having a first width along a first horizontal direction through the etch stop dielectric layer; forming a layer stack including a bottom electrode material layer, a continuous memory material layer, a top electrode material layer and a hard mask material layer above the etch stop dielectric layer; forming a patterned photoresist material portion above the layer stack so that the patterned photoresist material portion has a second width along the first horizontal direction, and the second width is greater than the first width; patterning the hard mask material layer into a hard mask template using the patterned photoresist material portion as an etching mask; and patterning the top electrode material layer, the continuous memory material layer and the bottom electrode material layer into a resistive memory cell including a top electrode, a memory material layer and a bottom electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a vertical cross-sectional view of the first embodiment structure after forming a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure formed in a dielectric material layer, and a lower connecting via level dielectric layer according to an embodiment of the present disclosure.

[0008] Figure 2A is a vertical cross-sectional view of the first embodiment structure after depositing and patterning an etch stop dielectric layer according to an embodiment of the present disclosure.

[0009] Figure 2B yes Figure 2A An enlarged vertical cross-sectional view of a region of the structure of the first embodiment.

[0010] Figure 2C Shows Figure 2A and Figure 2B Top views of various configurations of the first embodiment structure.

[0011] FIG. 3A to FIG. 3C are sequential vertical cross-sectional views of regions of the first embodiment structure during formation of a resistive memory cell according to an embodiment of the present disclosure.

[0012] Figure 3D Shows Figure 3C Top views of various configurations of the first embodiment structure.

[0013] Figure 4A is a vertical cross-sectional view of the first embodiment structure after forming a dielectric cap layer, a memory level dielectric layer, and a dielectric pad layer according to an embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A An enlarged view of a region of the structure of the first embodiment.

[0015] Figure 5A is a vertical cross-sectional view of the first embodiment structure after patterning the dielectric pad layer according to an embodiment of the present disclosure.

[0016] Figure 5B yes Figure 5A An enlarged vertical cross-sectional view of a region of the structure of the first embodiment.

[0017] Fig. 6A is a vertical cross-sectional view of the first embodiment structure after forming a via cavity according to an embodiment of the present disclosure.

[0018] Figure 6B yes Fig. 6A An enlarged vertical cross-sectional view of a region of the structure of the first embodiment.

[0019] Fig. 7A is a vertical cross-sectional view of the first embodiment structure after forming a contact via structure according to an embodiment of the present disclosure.

[0020] Figure 7B yes Fig. 7A An enlarged vertical cross-sectional view of a region of the structure of the first embodiment.

[0021] Figure 7C yes Fig. 7A A top view of the structure of the first embodiment. The vertical plane A-A' is Fig. 7A The vertical plane B-B' is Figure 7B A cut plane of a vertical cross-section.

[0022] Fig. 8A is a vertical cross-sectional view of the first embodiment structure after forming a metal line structure according to an embodiment of the present disclosure.

[0023] Figure 8B yes Fig. 8A An enlarged vertical cross-sectional view of a region of the structure of the first embodiment.

[0024] Figure 8C yes Fig. 8A A top view of the structure of the first embodiment. The vertical plane A-A' is Fig. 8A The vertical plane B-B' is Figure 8B A cut plane of a vertical cross-section.

[0025] Fig. 9 is a vertical cross-sectional view of an alternative configuration of the first embodiment structure after forming a peripheral via cavity in accordance with an embodiment of the present disclosure.

[0026] Fig. 10A is a vertical cross-sectional view of an alternative configuration of the first embodiment structure after patterning the dielectric pad layer according to an embodiment of the present disclosure.

[0027] Fig. 10B yes Fig. 10A An enlarged vertical cross-sectional view of a region of the structure of the second embodiment.

[0028] Fig.11A is a vertical cross-sectional view of an alternative configuration of the first embodiment structure after forming the vertical extensions of the line cavity and the peripheral via cavity according to an embodiment of the present disclosure.

[0029] Fig. 11B yes Fig.11A An enlarged vertical cross-sectional view of a region of the structure of the second embodiment.

[0030] Fig. 12A is a vertical cross-sectional view of an alternative configuration of the first embodiment structure after forming metal lines and integrated line and via structures according to an embodiment of the present disclosure.

[0031] Fig. 12B yes Fig. 12A A first enlarged vertical cross-sectional view of a region of the second embodiment structure.

[0032] Fig. 12C yes Fig. 12A FIG. 2 is a second enlarged vertical cross-sectional view of a region of the second embodiment structure.

[0033] Fig.12D yes Fig. 12A A top view of the structure of the second embodiment. The vertical plane A-A' is Fig. 12A The vertical plane B-B' is Fig. 12B The vertical plane C-C' is Fig. 12C A cut plane of a vertical cross-section.

[0034] Fig.13 is a vertical cross-sectional view of an alternative configuration of the first embodiment structure after forming additional metal interconnect structures according to an embodiment of the present disclosure.

[0035] FIG. 14A to FIG. 14F are sequential vertical cross-sectional views of regions of the second embodiment structure during formation of a resistive memory cell according to an embodiment of the present disclosure.

[0036] Figure 14Gis a vertical cross-sectional view of an alternative configuration of a second embodiment structure according to an embodiment of the present disclosure.

[0037] FIG. 15A to FIG. 15J are sequential vertical cross-sectional views of regions of the third embodiment structure during formation of a resistive memory cell according to an embodiment of the present disclosure.

[0038] Figure 15K is a vertical cross-sectional view of an alternative configuration of a third embodiment structure according to an embodiment of the present disclosure.

[0039] FIG. 16A to FIG. 16F are sequential vertical cross-sectional views of regions of a fourth embodiment structure during formation of a resistive memory cell according to an embodiment of the present disclosure.

[0040] Figure 16G is a vertical cross-sectional view of an alternative configuration of a fourth embodiment structure according to an embodiment of the present disclosure.

[0041] Fig.17 is a flow chart showing a sequence of processing steps for manufacturing a resistive memory device of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. The accompanying drawings are not drawn to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range unless otherwise expressly stated. Embodiments in which multiple instances of any described element are repeated are expressly contemplated, unless otherwise expressly stated. Embodiments in which non-essential elements are omitted are expressly contemplated, even if such embodiments are not expressly disclosed, but are known in the art.

[0043] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0044] For advanced resistive memory devices, the shape and critical dimensions of the resistive memory cell are the main factors affecting the yield, because the device leakage current and the top electrode contact yield are sensitive to the morphology and size of the top electrode. The various embodiments disclosed herein provide improvements in the morphological profile of the resistive memory cell to enhance the manufacturing yield and device reliability. The embodiments of the present disclosure relate to a resistive memory device, in which the corrosion and corner rounding of the hard mask cap located above the top electrode of the resistive memory cell are eliminated or reduced. The vertical cross-sectional profile of the resistive memory cell can be enhanced in a manner that reduces the taper angle of the sidewall of the resistive memory cell. For example, the taper angle of the resistive memory cell can be in the range of from 70 degrees to 87 degrees. The area of ​​the top surface of the top electrode of the resistive memory cell can be increased by 2 times or more, providing a larger contact area for the contact structure formed through the hard mask cover structure to the top surface of the top electrode. The contact yield for the top electrode can be significantly increased. The enhancement of the contact yield can be provided without adversely affecting the device characteristics of the resistive memory cell, thereby enabling the resistive memory cell to be scaled to a technology node using a smaller device size.

[0045] In one embodiment, the lateral dimensions of the bottom surface of the bottom electrode can be reduced, while the lateral dimensions of the top surface of the hard mask and the top surface of the top electrode can be increased, so that the periphery of the hard mask and the top electrode can be formed outside the area of ​​the contour surface of the bottom electrode and the memory material layer. The hard mask can be patterned without rounded corners, and the hard mask and the top electrode can be patterned to have straight sidewalls with a small taper angle relative to the vertical direction. Therefore, during patterning of the resistive memory cell, during patterning of the top electrode, the memory material layer, and the bottom electrode, corner corrosion can be avoided or minimized. Various embodiments disclosed herein can provide a large top electrode area, which provides a large overlay tolerance for the top electrode contact structure relative to the pattern of the top electrode, and thus can enhance the contact yield for the top electrode contact structure. In addition, eliminating or reducing corner corrosion during patterning of the resistive memory cell allows for enhanced uniformity of the lateral dimensions of the resistive memory cell, thereby enhancing the uniformity of device characteristics. Aspects of various embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0046] Figure 1is a vertical cross-sectional view of the first embodiment structure along a vertical plane parallel to the first horizontal direction hd1 after forming a complementary metal oxide semiconductor (CMOS) transistor, a metal interconnect structure formed in a lower level dielectric material layer, and a connecting via level dielectric layer according to an embodiment of the present disclosure. The first embodiment structure includes a complementary metal oxide semiconductor (CMOS) transistor and a metal interconnect structure formed in a dielectric material layer. Specifically, the first embodiment structure includes a substrate 9, which can be a semiconductor substrate, such as a commercially available silicon wafer. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide can be formed in an upper portion of the substrate 9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. A field effect transistor can be formed above the top surface of the substrate 9. For example, each field effect transistor can include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source side metal semiconductor alloy region 742 may be formed on each source region 732, and a drain side metal semiconductor alloy region 748 may be formed on each drain region 738. Although planar field effect transistors are shown in the drawings, embodiments in which the field effect transistors may additionally or alternatively include fin field effect transistors (FinFETs), gate all-around field effect (GAA FET) transistors, or any other type of field effect transistor (FET) are expressly contemplated herein.

[0047] The first embodiment structure may include: a memory array region 100, in which a memory element array may be subsequently formed; and a peripheral region 200, in which logic devices supporting the operation of the memory element array may be formed. In one embodiment, the devices (such as field effect transistors) in the memory array region 100 may include a bottom electrode access transistor that provides access to the bottom electrode of the memory cell to be formed subsequently. In this processing step, an upper electrode access transistor that provides access to the upper electrode of the memory cell to be formed subsequently may be formed in the peripheral region 200. The devices (such as field effect transistors) in the peripheral region 200 may provide the functions required to operate the memory cell array to be formed subsequently. Specifically, the devices in the peripheral region may be configured to control the programming operation, the erasing operation, and the sensing (reading) operation of the memory cell array. For example, the devices in the peripheral region may include a sensing circuit and / or an upper electrode bias circuit. The devices formed on the top surface of the substrate 9 may include complementary metal oxide semiconductor (CMOS) transistors and optional additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuits 700.

[0048] Various metal interconnect structures formed in the dielectric material layer may then be formed over the substrate 9 and devices such as field effect transistors. The dielectric material layer may include, for example, a contact level dielectric material layer 601, a first metal line level dielectric material layer 610, a second line and via level dielectric material layer 620, a third line and via level dielectric material layer 630, and a fourth line and via level dielectric material layer 640. The metal interconnect structure may include a device contact via structure 612 formed in the contact level dielectric material layer 601 and contacting corresponding components of the CMOS circuit 700, a first metal line structure 618 formed in the first metal line level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of the second line and via level dielectric material layer 620, a second metal line structure 628 formed in the upper portion of the second line and via level dielectric material layer 620, a second metal via structure 632 formed in the lower portion of the third line and via level dielectric material layer 630, a third metal line structure 638 formed in the upper portion of the third line and via level dielectric material layer 630, a third metal via structure 642 formed in the lower portion of the fourth line and via level dielectric material layer 640, and a fourth metal line structure 648 formed in the upper portion of the fourth line and via level dielectric material layer 640. In one embodiment, the second metal line structure 628 may include a source line connected to a source side power supply for the memory element array. The voltage provided by the source line may be applied to the bottom electrode through an access transistor provided in the memory array region 100.

[0049] Each of the dielectric material layers (601, 610, 620, 630, 640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal filler materials within the contemplated scope of the presently disclosed embodiments may also be used. In one embodiment, the first metal via structure 622 and the second metal line structure 628 may be formed as an integrated line and via structure by a dual damascene process, the second metal via structure 632 and the third metal line structure 638 may be formed as an integrated line and via structure, and / or the third metal via structure 642 and the fourth metal line structure 648 may be formed as an integrated line and via structure. Although the disclosed embodiments are described using embodiments in which a memory cell array is formed above the fourth line and via level dielectric material layer 640, embodiments in which the memory cell array may be formed at a different metal interconnect level are expressly contemplated herein.

[0050] The dielectric material layer (601, 610, 620, 630, 640) may be located at a lower level relative to a memory cell array to be formed subsequently. Therefore, the dielectric material layer (601, 610, 620, 630, 640) is referred to herein as a lower level dielectric material layer, i.e., a dielectric material layer located at a lower level relative to a memory cell array to be formed subsequently. The metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) are referred to herein as lower level metal interconnect structures. A subset of the metal interconnect structures (612, 618, 622, 628, 632, 638, 642, 648) includes lower level metal lines (such as fourth metal line structures 648) formed in the lower level dielectric layer and having a top surface within a horizontal plane including the topmost surface of the lower level dielectric layer. Typically, the total number of metal line levels within the lower level dielectric layer ( 601 , 610 , 620 , 630 , 640 ) may range from 1 to 10.

[0051] A dielectric cap layer 108 and a lower connection via level dielectric layer 110 may be sequentially formed over the metal interconnect structure and the dielectric material layer. The dielectric cap layer 108 and the lower connection via level dielectric layer 110 may be additional lower level dielectric material layers. For example, the dielectric cap layer 108 may be formed on the top surface of the fourth metal line structure 648 and on the top surface of the fourth line and via level dielectric material layer 640. The dielectric cap layer 108 includes a dielectric cap material that can protect the underlying metal interconnect structure (such as the fourth metal line structure 648). In one embodiment, the dielectric cap layer 108 may include a material that can provide high etching resistance, i.e., a dielectric material, and may also be used as an etching stop material during a subsequent anisotropic etching process of etching the lower connection via level dielectric layer 110. For example, the dielectric cap layer 108 may include silicon carbide or silicon nitride and may have a thickness in the range of from 5 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0052] The lower connection via level dielectric layer 110 may include any material that may be used for the dielectric material layers (601, 610, 620, 630, 640). For example, the lower connection via level dielectric layer 110 may include undoped silicate glass or doped silicate glass deposited by decomposition of tetraethyl orthosilicate (TEOS). The thickness of the lower connection via level dielectric layer 110 may range from 50 nm to 200 nm, although lesser and greater thicknesses may also be used. The dielectric cap layer 108 and the lower connection via level dielectric layer 110 may be formed as planar blanket (unpatterned) layers having respective planar top surfaces and respective planar bottom surfaces extending through the memory array region 100 and the peripheral region 200.

[0053] refer to FIG. 2A to FIG. 2C , a through-hole cavity can be formed through the lower connection through-hole level dielectric layer 110 and the dielectric cap layer 108 of the first embodiment structure. For example, a photoresist layer (not shown) can be applied and patterned above the lower connection through-hole level dielectric layer 110 to form an opening in a region of the memory array region 100 located above a corresponding one of the fourth metal line structures 648. Anisotropic etching can be performed to transfer the pattern in the photoresist layer through the lower connection through-hole level dielectric layer 110 and the dielectric cap layer 108. The through-hole cavity formed by the anisotropic etching process is referred to as the lower electrode contact through-hole cavity in this article, because the bottom electrode connection through-hole structure is subsequently formed in the lower electrode contact through-hole cavity. The lower electrode contact through-hole cavity can have a tapered sidewall having a taper angle (relative to the vertical direction) in the range of from 1 degree to 10 degrees. The top surface of the fourth metal line structure 648 can be physically exposed at the bottom of each lower electrode contact through-hole cavity. The photoresist layer can then be removed, for example, by ashing.

[0054] A metal barrier layer may be formed as a material layer. The metal barrier layer may cover the physically exposed top surface of the fourth metal line structure 648, the tapered sidewalls of the lower electrode contact via cavity, and the top surface of the lower connection via level dielectric layer 110 without any holes passing therethrough. The metal barrier layer may include a conductive metal nitride, such as TiN, TaN, and / or WN. Other suitable materials within the contemplated scope of the embodiments of the present disclosure may also be used. The thickness of the metal barrier layer may be in the range of from 3 nm to 20 nm, but smaller and larger thicknesses may also be used.

[0055] A metal fill material such as tungsten or copper may be deposited in the remaining volume of the lower electrode contact via cavity. Portions of the metal fill material and the metal barrier layer located above a horizontal plane including the topmost surface of the lower connection via level dielectric layer 110 may be removed by a planarization process such as chemical mechanical planarization. Each remaining portion of the metal fill material located in a corresponding via cavity includes a metal via fill material portion 24. Each remaining portion of the metal barrier layer located in a corresponding via cavity includes a metal barrier layer 22. Each combination of the metal barrier layer 22 and the metal via fill material portion 24 that fills the via cavity constitutes a bottom connection via structure 20. An array of bottom connection via structures 20 may be formed in the lower connection via level dielectric layer 110 on the underlying metal interconnect structures (i.e., 612, 618, 622, 628, 632, 638, 642, 648). The array of bottom connection via structures 20 may contact the top surface of a subset of the fourth metal line structure 648. Typically, the array of bottom connecting via structures 20 contacts the top surfaces of a subset of lower level metal lines located at the topmost level of the lower level dielectric layers (601, 610, 620, 630, 640). Typically, a first metal interconnect structure (such as bottom connecting via structures 20) formed in a first dielectric material layer (such as lower connecting via level dielectric layer 110) can be formed above a substrate.

[0056] An etch stop dielectric layer 112 may be formed over a first metal interconnect structure (such as a bottom connection via structure 20) in a first dielectric material layer (such as a lower connection via level dielectric layer 110). The etch stop dielectric layer 112 includes a dielectric material that may be effectively used as an etch stop material layer. For example, the etch stop dielectric layer 112 may include a dielectric material such as silicon carbonitride, silicon oxycarbide, silicon carbide, silicon nitride, silicon oxynitride, a dielectric metal oxide such as aluminum oxide, lanthanum oxide, or titanium oxide, or a combination thereof. The thickness of the etch stop dielectric layer 112 (which is referred to herein as a first thickness t1) may be in a range from 10 nm to 60 nm, such as from 20 nm to 40 nm, although smaller and larger thicknesses may also be used.

[0057] A photoresist layer 75 can be applied and patterned by photolithography above the etch stop dielectric layer 112 to form an array of openings therein. The region of the openings in the photoresist layer 75 can be completely located within the region of the top surface of the bottom connection via structure 20. An anisotropic etching process can be implemented to transfer the pattern of the openings in the photoresist layer 75 through the etch stop dielectric layer 112. In one embodiment, the chemical substances of the anisotropic etching process can be selected to generate polymer materials on the physically exposed sidewalls of the etch stop dielectric layer 112. Additionally or optionally, the openings in the photoresist layer 75 can be widened together during the anisotropic etching process. Openings 113 can be formed through the etch stop dielectric layer 112 so that each opening 113 can have a corresponding tapered annular sidewall. In one embodiment, the tapered annular sidewall of the opening 113 can have a convex vertical cross-sectional profile.

[0058] In one embodiment, each opening 113 within the two-dimensional array of openings 113 through the etch stop dielectric layer 112 may have the same shape and the same size. In one embodiment, each opening 113 may have a first width through the etch stop dielectric layer 112 along a first horizontal direction hd1 (which is referred to herein as a bottom electrode via bottom width BVBW). The first width of each opening 113 along the first horizontal direction hd1 may be measured at the bottom of the corresponding opening 113. The second horizontal direction hd2 may be perpendicular to the first horizontal direction hd1.

[0059] Typically, each opening through the etch stop dielectric layer 112 is oriented in a vertical direction (such as in a top view) in a plan view (such as in a top view). Figure 2C ) can have any closed two-dimensional shape. In one embodiment, each opening 113 in the etch stop dielectric layer 112 has a circular, elliptical, or rounded rectangular shape. In one embodiment, the first width (such as the bottom electrode via bottom width BVBW) can be a diameter, a short axis, or a distance between a pair of parallel segments. The area of ​​each opening 113 passing through the etch stop dielectric layer 112 can be completely located within the area of ​​the periphery of the top surface of the corresponding underlying bottom connecting via structure 20. In one embodiment, the bottom electrode via bottom width BVBW can be in the range of from 50nm to 200nm, but smaller or larger sizes can also be used.

[0060] FIG. 3A to FIG. 3C are sequential vertical cross-sectional views of regions of the first embodiment structure during formation of a resistive memory cell 30 according to an embodiment of the present disclosure. Figure 3D Shows Figure 3C Top views of various configurations of the first embodiment structure.

[0061] refer to Figure 3A, a layer stack including a bottom metal barrier material layer 31L, a bottom metal layer 32L, a continuous memory material layer 34L, an optional capping material layer 36L, a top electrode material layer 38L, and a hard mask material layer 52L may be deposited over the physically exposed surface of the bottom connection via structure 20 and over the etch stop dielectric layer 112. The combination of the bottom metal barrier material layer 31L and the bottom metal layer 32L is subsequently used to pattern the bottom electrode, and is therefore referred to herein as a bottom electrode material layer (31L, 32L). Each volume of the opening 113 in the etch stop dielectric layer 112 may be filled with a corresponding portion of the bottom electrode material layer (31L, 32L).

[0062] In one embodiment, the bottom metal barrier material layer 31L may include at least one conductive metal nitride material, such as TaN, TiN or WN. The bottom metal barrier material layer 31L may have a thickness in the range of from 5nm to 100nm, such as from 10nm to 30nm, but smaller and larger thicknesses may also be used. In one embodiment, the bottom metal layer 32L may include and / or may be mainly composed of a metal having a melting point greater than 2000 degrees Celsius. For example, the bottom metal layer 32L may include and / or may be composed of hafnium, ruthenium, iridium, niobium, molybdenum, tantalum, osmium, rhenium or tungsten. Other suitable metal materials may be within the scope of consideration of the embodiments of the present disclosure. In one embodiment, the bottom metal layer 32L may include an 8th group element (such as ruthenium or osmium) or a 9th group element (such as rhodium or iridium). In general, using a metal with a high melting point for the bottom metal layer 32L is advantageous for reducing or eliminating atoms of the first metal in the bottom electrode during operation of the resistive memory cell. In one embodiment, the bottom metal layer 32L may include ruthenium. The bottom metal layer 32L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the bottom metal layer 32L may be in a range from 10 nm to 100 nm, such as from 20 nm to 50 nm and / or from 6 nm to 20 nm, although smaller and larger thicknesses may also be used.

[0063] The continuous memory material layer 34L includes a resistive memory material, which refers to a material that provides at least two different resistance states that provide different resistances. In general, the resistive memory material can be any type of resistive memory material known in the art. In one embodiment, the resistive memory material may include a filament-forming metal oxide material (such as hafnium oxide, titanium oxide, niobium pentoxide, germanium telluride, silver sulfate, zinc oxide, vanadium oxide, tantalum oxide, zirconium oxide, etc.) that provides higher conductivity when a conductive filament is formed therein. In one embodiment, the resistive memory material may include a phase change memory material containing chalcogenide glass (such as an alloy of germanium, antimony and tellurium, and optional additional additives). In one embodiment, the resistive memory material may include a conductive bridge-forming material (such as silver, copper, silver sulfide, mixed ion-electronic conductor material (e.g., yttria-stabilized zirconium oxide), etc.) in which a conductive bridge can be formed or broken. In one embodiment, the resistive memory material may include an organic polymer material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a perovskite-based material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a two-dimensional material that can provide at least two different resistance states, such as molybdenum disulfide (MoS2). In one embodiment, the resistive memory material may include an organic-inorganic hybrid resistive memory material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a rare earth oxide resistive memory material that can provide at least two different resistance states.

[0064] In one embodiment, the continuous memory material layer 34L includes and / or consists primarily of a conductive filament-forming dielectric oxide of at least one transition metal. A conductive filament-forming dielectric oxide refers to a dielectric oxide that can form conductive filaments when an electric field is applied therethrough. Exemplary conductive filament-forming dielectric oxides include hafnium oxide, zirconium oxide, titanium oxide, hafnium zirconium oxide, and strontium cobalt oxide. When conductive filaments are formed therein by applying an electrical bias voltage, the resistivity of the continuous memory material layer 34L along the thickness direction (e.g., along the vertical direction) may change by at least one order of magnitude, such as 2 to 6 orders of magnitude. In an embodiment where the continuous memory material layer 34L includes hafnium oxide, a vertical electric field having an order of magnitude of about 2.6 MV / cm may be used to form conductive filaments therein. An electric field of opposite polarity and having a smaller order of magnitude may be applied to remove conductive filaments from within the continuous memory material layer 34L.

[0065] The continuous memory material layer 34L may be deposited by atomic layer deposition, chemical vapor deposition, or physical vapor deposition. For example, if the continuous memory material layer 34L includes hafnium oxide, atomic layer deposition using a hafnium-containing precursor gas (such as hafnium tetrachloride) and an oxygen source gas (such as H2O, O2, or O3) may be alternately flowed into a process chamber containing the first embodiment structure to deposit the continuous memory material layer 34L. The thickness of the continuous memory material layer 34L may be in a range from 1 nm to 50 nm, such as from 3 nm to 20 nm and / or from 6 nm to 10 nm, although smaller and larger thicknesses may also be used.

[0066] In embodiments where the capping material layer 36L is present, the capping material layer 36L includes a capping material that can enhance the electrical characteristics of the memory material layer in the continuous memory material layer 34L. In embodiments where the capping material layer 36L is used, the capping material layer 36L can be used as a diffusion barrier layer and can be used to modulate the switching characteristics of the resistive memory material in the continuous memory material layer 34L and / or to enhance the durability and device stability of the resistive memory device to be formed subsequently. In one embodiment, the capping material layer 36L can include a conductive metal nitride material such as TiN, TaN, WN and / or MoN, a metal oxide material such as ruthenium oxide or iridium oxide, a metal silicide material such as titanium silicide or tungsten silicide, a thin layer of diamond-like carbon, and / or other suitable liner materials.

[0067] The top electrode material layer 38L may include any material that may be used for the bottom metal layer 32L. The thickness of the top electrode material layer 38L may range from 10 nm to 100 nm, such as from 20 nm to 50 nm and / or from 6 nm to 20 nm, although lesser and greater thicknesses may also be used.

[0068] The hard mask material layer 52L includes a dielectric material suitable as a hard mask material. For example, the hard mask material layer 52L may include and / or may be mainly composed of silicon oxynitride, silicon nitride, silicon carbonitride, silicon oxycarbide and / or a dielectric metal oxide. The hard mask material layer 52L may be formed by chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). The thickness of the hard mask material layer 52L may be in the range of from 30nm to 200nm and / or from 60nm to 120nm, but smaller and larger thicknesses may also be used. The hard mask material layer 52L may include a two-dimensional array of downwardly protruding portions of a two-dimensional array of recesses in the top surface of the top electrode material layer 38L.

[0069] refer to Figure 3B, a photoresist layer may be applied over the top surface of the hard mask material layer 52L and may be photolithographically patterned to form a two-dimensional array of patterned photoresist material portions 77. According to aspects of the disclosed embodiments, each patterned photoresist material portion 77 may have a respective sidewall that is completely within a region of the periphery of the underlying bottom connection via structure 20 and completely outside a region of the opening 113 in the underlying portion of the etch stop dielectric layer 112. In one embodiment, each patterned photoresist material portion 77 has a second width along a first horizontal direction hd1 that is greater than the first width (such as a bottom electrode via bottom width BVBW) and less than a lateral dimension of the top surface of the underlying bottom connection via structure 20. In one embodiment, each patterned photoresist material portion 77 covers the entire region of the corresponding underlying opening 113 in the etch stop dielectric layer 112 in a plan view (i.e., a view along a vertical direction).

[0070] A first anisotropic etching process may be performed to transfer the pattern of the two-dimensional array of patterned photoresist material portions 77 through the hard mask material layer 52L, the top electrode material layer 38L, the optional capping material layer 36L, and the continuous memory material layer 34L using the patterned photoresist material portions 77 as an etching mask. The first anisotropic etching process may include a series of anisotropic etching steps having corresponding etching chemistries and providing sequential etching of the materials of the hard mask material layer 52L, the top electrode material layer 38L, the optional capping material layer 36L, and the continuous memory material layer 34L. A patterned stack of the memory material layer 34, the optional capping material plate 36, the top electrode 38, and the hard mask plate 52 may be formed under each patterned photoresist material portion 77. Each hard mask plate 52 is a patterned portion of the hard mask material layer 52L. Each top electrode 38 is a patterned portion of the top electrode material layer 38L. Each capping material plate 36 is a patterned portion of the capping material layer 36L. Each memory material layer 34 is a patterned portion of a continuous memory material layer 34L.

[0071] According to aspects of an embodiment of the present disclosure, the first anisotropic etching process may use an etching chemistry that minimizes corrosion of the hard mask template 52. In this embodiment, the first anisotropic etching process may use a hydrogen-free etchant such as CF4 or SF6 to maintain a substantially vertical sidewall profile for the hard mask template 52. The tapered surface may extend straight from the periphery of the top surface of the hard mask template 52 to at least the top surface of the bottom electrode material layer (31L, 32L) at a taper angle α relative to the vertical direction. The taper angle α may be in a range from 5 degrees to 20 degrees, such as from 5 degrees to 15 degrees. The array of patterned photoresist material portions 77 may then be removed, for example, by ashing. A planar horizontal portion of the top surface of the bottom electrode material layer (31L, 32L) may be physically exposed after the first anisotropic etching process.

[0072] refer to Figure 3C and Figure 3D , a dielectric material such as silicon nitride, silicon oxide, silicon carbonitride, or silicon oxynitride may be conformally deposited over the two-dimensional array of stacked pieces of memory material layer 34, optional cover material plate 36, top electrode 38, and hard mask template 52 to form a conformal dielectric material layer. A second anisotropic etching process may be performed to remove horizontally extending portions of the conformal dielectric material layer. Each remaining vertically extending portion of the conformal dielectric material layer constitutes a dielectric spacer 56. The second anisotropic etching process may be continued to etch physically exposed portions of the bottom electrode material layer (31L, 32L) using a combination of the two-dimensional array of hard mask template 52 and the two-dimensional array of dielectric spacers 56 as an etching mask. The second anisotropic etching process may also etch unmasked portions of the etch stop dielectric layer 112. The etched portion of the etch stop dielectric layer 112 may have a second thickness t2 that is less than the first thickness t1.

[0073] Each patterned portion of the bottom electrode material layer (31L, 32L) constitutes a bottom electrode (31, 32). Each bottom electrode (31, 32) may include a combination of a bottom metal barrier layer 31 and a bottom metal plate 32. The bottom metal barrier layer 31 may be a patterned portion of the bottom metal barrier material layer 31L, and the bottom metal plate 32 may be a patterned portion of the bottom metal layer 32L. Each dielectric spacer 56 may have a tubular structure with a straight tapered sidewall and an outer sidewall with a wavy profile. Each dielectric spacer 56 may be homeomorphic to the torus topology, i.e., may be continuously deformed into a torus without creating new holes and without destroying any existing holes.

[0074] Each dielectric spacer 56 may have a bottom surface of a planar surface segment that contacts the top surface of the bottom electrode (31, 32) below. The bottom surface of each dielectric spacer 56 may have an inner periphery and an outer periphery, and the outer periphery is laterally offset outwardly relative to the inner periphery by a uniform lateral offset distance, which is the lateral thickness of the dielectric spacer 56 at a horizontal plane including the bottom surface. The bottom periphery of the outer sidewall of each dielectric spacer 56 may coincide with the periphery of the top surface of the corresponding bottom electrode (31, 32) below. Each dielectric spacer 56 may contact the entire tapered surface of the stack of hard mask template 52, top electrode 38, cover material plate 36 and memory material layer 34. Each dielectric spacer 56 may laterally surround the stack of hard mask template 52, top electrode 38, cover material plate 36 and memory material layer 34.

[0075] In one embodiment, each dielectric spacer 56 may have an annular bottom surface in contact with an annular surface segment of the top surface of the bottom electrode (31, 32) below. As used herein, an annular surface refers to a surface having an inner periphery and an outer periphery that is laterally offset outwardly by a uniform lateral offset distance relative to the inner periphery. In one embodiment, each bottom electrode (31, 32) may include a top surface that includes an annular top surface segment and a central recessed horizontal surface segment located below the downwardly protruding portion of the upper memory material layer 34. According to aspects of the embodiments of the present disclosure, the lateral extent of the central recessed horizontal surface segment along the first horizontal direction hd1 is less than the first width of the lower opening 113 in the etch stop dielectric layer 112 (such as the bottom electrode via bottom width BVBW).

[0076] The second anisotropic etching process can also reduce the thickness of the hard mask plate 52. The thickness of the horizontal extension of each hard mask plate 52 can be in the range of from 25nm to 180nm and / or from 40nm to 100nm, but smaller and larger thicknesses can also be used. The periphery of the top surface of each hard mask plate 52 can have a second width along the first horizontal direction hd1, which is referred to herein as the hard mask top width HMTW. The second width is greater than the first width (such as the bottom electrode via bottom width BVBW).

[0077] In general, the top electrode material layer 38L, the continuous memory material layer 34L, and the bottom electrode material layer (31L, 32L) can be patterned into a two-dimensional array of resistive memory cells 30. Each resistive memory cell 30 includes a top electrode 38, an optional cover material plate 36, a memory material layer 34, and a bottom electrode (31, 32). In one embodiment, each bottom electrode (31, 32) includes a plate portion located above the etch stop dielectric layer 112 and a via portion located within the opening 113 in the etch stop dielectric layer 112. In other words, the via portion extends vertically downward into the corresponding opening 113 in the etch stop dielectric layer 112. In one embodiment, the memory material layer 34 is located above the bottom electrode (31, 32) and is configured to provide at least two states with different resistances. In one embodiment, within each resistive memory cell 30, when the memory material layer 34 is patterned, the memory material layer 34 is completely located in a plan view within the area of ​​the top surface of the underlying bottom connection via structure 20 (which is a metal via structure). A top electrode 38 is located above the memory material layer 34 .

[0078] In one embodiment, the etch stop dielectric layer 112 includes: an annular portion laterally surrounding the opening 113 in the etch stop dielectric layer 112 and having a first thickness t1; and a planar layer portion having a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion. Thus, the annular portion has the first thickness t1 and includes the opening 113 therethrough, and the planar layer portion has a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion.

[0079] refer to Figure 4A and Figure 4B , a dielectric cap layer 150 may be optionally conformally deposited over the two-dimensional array of resistive memory cells 30, the two-dimensional array of hard mask plates 52, and the two-dimensional array of dielectric spacers 56. The dielectric cap layer 150 may include a non-porous dielectric material, such as undoped silicate glass, doped silicate glass, silicon oxynitride, or silicon nitride. The dielectric cap layer 150 may be deposited by a conformal deposition process, such as a chemical vapor deposition process. The thickness of the dielectric cap layer 150 may be in a range from 4 nm to 100 nm, such as from 8 nm to 50 nm, although lesser and greater thicknesses may also be used.

[0080] The dielectric cap layer 150 laterally surrounds the two-dimensional array of resistive memory cells 30. The dielectric cap layer 150 contacts the cylindrical sidewall of the etch stop dielectric layer 112, which connects the periphery of the top surface of the corresponding annular portion of the etch stop dielectric layer 112 and the corresponding periphery of the top surface of the planar layer portion having the second thickness t2 of the etch stop dielectric layer 112. The dielectric cap layer 150 may contact the sidewall of each bottom electrode (31, 32) and may contact the top surface of each hard mask plate 52.

[0081] A layer of dielectric material may then be deposited over the dielectric cap layer 150. The layer of dielectric material is referred to herein as a memory-level dielectric layer 162. In one embodiment, the memory-level dielectric layer 162 may include a low-k dielectric material having a dielectric constant of less than 3.9. For example, the memory-level dielectric layer 162 may include a non-porous organosilicate glass or a porous organosilicate glass. Optionally, the top surface of the memory-level dielectric layer 162 may be planarized. The thickness of the memory-level dielectric layer 162 as measured above the topmost surface of the dielectric cap layer 150 located above the resistive memory cell 30 may be in a range from 50 nm to 300 nm, such as from 100 nm to 200 nm, although lesser and greater thicknesses may also be used.

[0082] The memory level dielectric layer 162 is formed around and over the two-dimensional array of resistive memory cells 30. The memory level dielectric layer 162 laterally surrounds the bottom electrodes (31, 32), the memory material layer 34, and the top electrode 38 of each resistive memory cell 30. The memory level dielectric layer 162 is located above the horizontally extending portion of the dielectric cap layer 150 and laterally surrounds each portion of the dielectric cap layer 150 that protrudes above the horizontally extending portion of the dielectric cap layer 150.

[0083] A dielectric pad layer 166 may be deposited over the memory level dielectric layer 162. The dielectric pad layer 166 includes a dielectric material that may be used as a planarization stop layer during a subsequent chemical mechanical polishing process. In one embodiment, the dielectric pad layer 166 may include silicon nitride, silicon carbonitride, or silicon oxycarbide. The thickness of the dielectric pad layer 166 may be in a range from 20 nm to 100 nm, such as from 30 nm to 60 nm, although smaller and larger thicknesses may also be used.

[0084] The combination of all dielectric material layers located at the fourth line-and-via-level dielectric material layer 640 constitutes a fifth line-and-via-level dielectric material layer 650. In one embodiment, the fifth line-and-via-level dielectric material layer 650 may include, from bottom to top, a dielectric cap layer 108, a lower connecting via-level dielectric layer 110, an etch stop dielectric layer 112, a dielectric cap layer 150, a memory-level dielectric layer 162, and a dielectric pad layer 166.

[0085] refer to Figure 5A and Figure 5B , a photoresist layer 79 may be applied over the dielectric pad layer 166 and may be photolithographically patterned to form a two-dimensional array of openings therein. The openings in the photoresist layer 79 may include a first opening formed entirely within a region of the periphery of the top surface of the underlying bottom connecting via structure 20 and formed entirely outside of the region of the underlying opening 113 in the etch stop dielectric layer 112. The openings in the photoresist layer 79 may include a second opening formed in a peripheral region over a corresponding one of the underlying metal interconnect structures, which may be, for example, a corresponding underlying fourth metal line structure 648.

[0086] An anisotropic etching process may be performed to remove portions of the dielectric pad layer 166 that are not masked by the photoresist layer 79. A first opening 81 may be formed through the dielectric pad layer 166 in the memory array region 100, and a second opening 71 may be formed through the dielectric pad layer 166 in the peripheral region 200. In one embodiment, the first opening 81 and the second opening 71 may be discrete openings having a circular or elliptical horizontal cross-sectional shape. The photoresist layer 79 may then be removed, for example, by ashing.

[0087] refer to Fig. 6A and Figure 6B , a first anisotropic etching process may be performed to transfer the pattern of the openings (81, 71) in the dielectric pad layer 166 through the upper portion of the memory level dielectric layer 162. A first contact via cavity 88 may be formed under the first opening in the dielectric pad layer 166 in the memory array region 100. A second contact via cavity 78 may be formed under the second opening in the dielectric pad layer 166 in the peripheral region 200. The first contact via cavity 88 and the second contact via cavity 78 are contact via cavities in which metal contact structures may be subsequently formed.

[0088] The duration of the first anisotropic etching process may be selected so that a surface segment of each top electrode 38 is exposed to a corresponding first contact via cavity 88. In one embodiment, the bottom surface of each first contact via cavity 88 may have a third width along the first horizontal direction hd1, which is referred to herein as the top contact structure bottom width TCBW. The third width may be less than the second width, i.e., the hard mask top width HMTW. In addition, the third width may be greater than the first width, i.e., the bottom electrode via bottom width BVBW.

[0089] Each remaining portion of the hard mask plate 52 located within the recessed region of the top surface of the corresponding top electrode 38 constitutes a hard mask recess filling material portion 52'. Each hard mask recess filling material portion 52' may be located within a recess in the top surface of the top electrode 38, may contact the recessed-shaped segment of the top surface of the top electrode 38, and may be located below a corresponding first contact via cavity 88.

[0090] A photoresist layer (not shown) may be applied over the first embodiment structure and may be photolithographically patterned to cover the memory array region 100 while not covering the peripheral region 200. An anisotropic etching process may be performed to vertically extend the second contact via cavity 78 through the memory level dielectric layer 162, the dielectric cap layer 150, the etch stop dielectric layer 112, the lower connection via level dielectric layer 110, and the lower portion of the dielectric cap layer 108. The top surface of the fourth metal line structure 648 may be physically exposed under each vertically extending second contact via cavity 78. The photoresist layer may then be removed, for example, by ashing.

[0091] refer to 7A to 7C, at least one conductive material may be deposited in the first through hole cavity 88 and the second through hole cavity 78. The at least one conductive material may include a metal barrier liner material and a metal filling material. The metal barrier liner material may include a conductive metal nitride material, such as TiN, TaN, WN and / or MoN. The metal barrier liner material may be deposited by physical vapor deposition and / or chemical vapor deposition. The thickness of the metal barrier liner material may be in a range from 4nm to 50nm, such as from 8nm to 25nm, but smaller and larger thicknesses may also be used. The metal filling material includes a metal, such as Cu, W, Mo, Ru, Co, Al, their alloys and / or their layer stacks. The metal filling material may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, chemical plating, or a combination thereof.

[0092] By performing a planarization process, excess portions of the metal barrier liner material and the metal fill material can be removed from above a horizontal plane including the top surface of the dielectric pad layer 166. The planarization process can use, for example, a chemical mechanical planarization process and / or a groove etching process. Each remaining patterned portion of the at least one conductive material filling the corresponding first contact through-hole cavity 88 constitutes a top electrode contact structure 80, which can be a metal through-hole structure. Each top electrode contact structure 80 may include: a metal barrier line 82, including a metal barrier liner material; and a metal fill material portion 84, including a metal fill material. Each remaining patterned portion of the at least one conductive material filling the corresponding second contact through-hole cavity 78 constitutes a peripheral metal interconnect structure 70, which can be a metal through-hole structure. The dielectric pad layer 166 can be thinned together during the planarization process.

[0093] In one embodiment, each top electrode contact structure 80 may be formed in a corresponding first contact via cavity 88 on a surface segment of a corresponding top electrode 38. The bottom surface of each top electrode contact structure 80 may have a third width (such as a top contact structure bottom width TCBW) along a first horizontal direction hd1. The third width (such as a top contact structure bottom width TCBW) is less than the second width (such as a hard mask top width HMTW) and greater than the first width (such as a bottom electrode via bottom width BVBW). Each top electrode contact structure 80 extends vertically through an upper portion of the memory level dielectric layer 162 and contacts the top surface of the corresponding top electrode 38. The hard mask recess filling material portion 52' may be located within a recess in the top surface of the top electrode 38, may contact a recessed shaped segment of the top surface of the top electrode 38, and may be located below the bottom surface of the top electrode contact structure 80.

[0094] refer to FIG. 8A to FIG. 8C, a line-level dielectric material layer 168, which may be incorporated into the fifth line-and-via level dielectric material layer 650, may be deposited over dielectric pad layer 166. Line trenches through line-level dielectric material layer 168 may be formed, for example, by applying and patterning a photoresist layer over line-level dielectric material layer 168 to form elongated openings in the photoresist layer and by transferring the pattern of the elongated openings through line-level dielectric material layer 168 using an anisotropic etching process. The photoresist layer may be removed, and at least one conductive material may be deposited in the line trenches and may then be planarized to form respective fifth metal line structures 658.

[0095] In one embodiment, a first subset of the fifth metal line structures 658 formed in the memory array region 100 includes top electrode lines TEL for the two-dimensional array of resistive memory cells 30. The top electrode lines TEL may be access lines for accessing rows of resistive memory cells 30 or columns of resistive memory cells 30. Thus, the top electrode lines TEL may include word lines or bit lines for the two-dimensional array of resistive memory cells 30. In the example shown, the top electrode lines TEL may extend laterally along the second horizontal direction hd2 and may be laterally spaced apart from each other along the first horizontal direction hd1. A second subset of the fifth metal line structures 658 may be formed in the peripheral region 200 directly on the top surface of a corresponding one of the peripheral metal interconnect structures 70.

[0096] refer to Fig. 9 By forming a peripheral through hole cavity 69 in the peripheral region 200, Figure 4A and Figure 4B . For example, a photoresist layer (not shown) may be applied over dielectric pad layer 166 and may be photolithographically patterned to form openings in peripheral region 200. An anisotropic etching process may be performed to transfer the pattern of discrete openings in the photoresist layer at least partially through fifth line and via level dielectric material layer 650 to form peripheral via cavity 69. The photoresist layer may then be removed, for example, by ashing.

[0097] refer to Fig. 10A and Fig. 10B , a photoresist layer 79 may be applied over the dielectric pad layer 166. In an alternative configuration of the first embodiment structure, the photoresist layer 79 may be patterned to form linear openings therein. For example, the pattern of the linear openings in the photoresist layer may be similar to FIG. 8A to FIG. 8C The pattern of the fifth metal line structure 658 shown in FIG. 6 is the same.

[0098] An anisotropic etching process may be performed to remove portions of the dielectric pad layer 166 that are not masked by the photoresist layer 79. A first opening 81 may be formed through the dielectric pad layer 166 in the memory array region 100, and a second opening 71 may be formed through the dielectric pad layer 166 in the peripheral region 200. In an alternative configuration of the first embodiment structure, the first opening 81 and the second opening 71 may be linear openings that may be elongated, for example, along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The photoresist layer 79 may then be removed, for example, by ashing.

[0099] refer to Fig.11A and Fig. 11B A photoresist layer (not shown) may be applied over the dielectric pad layer 166 and may be photolithographically patterned to form discrete openings in the peripheral region 200. The discrete openings in the photoresist layer may be formed within the region of the openings in the dielectric pad layer 166 located in the peripheral region 200. An anisotropic etching process may be performed to transfer the pattern of the discrete openings through at least the upper portion of the fifth line and via level dielectric material layer 650 to form a via cavity. The photoresist layer may then be removed, for example, by ashing.

[0100] An anisotropic etching process may be performed to transfer the pattern of the linear openings in the dielectric pad layer 166 through the upper portion of the memory level dielectric layer 162. A first line cavity 83 may be formed under the first opening in the dielectric pad layer 166 in the memory array region 100. A second line cavity may be formed under the second opening in the dielectric pad layer 166 in the peripheral region 200. In addition, the via cavities in the peripheral region may extend vertically so that the bottom surface of the fourth metal line structure 648 is exposed under each via cavity. Each continuous void including at least one via cavity and a second line cavity in the peripheral region 200 constitutes an integrated line and via cavity 73. The first line cavity 83 is a contact via cavity in which a metal contact structure is subsequently formed.

[0101] The duration of the anisotropic etching process may be selected so that a surface segment of each top electrode 38 is exposed to the corresponding first line cavity 83. In one embodiment, the bottom surface of each first line cavity 83 may have a third width along the first horizontal direction hd1, which is referred to herein as the top contact structure bottom width TCBW. The third width may be less than the second width, i.e., the hard mask top width HMTW. In addition, the third width may be greater than the first width, i.e., the bottom electrode via bottom width BVBW.

[0102] Each remaining portion of the hard mask plate 52 located within the recessed region of the top surface of the corresponding top electrode 38 constitutes a hard mask recess filling material portion 52'. Each hard mask recess filling material portion 52' may be located within a recess in the top surface of the top electrode 38, may contact a recessed-shaped segment of the top surface of the top electrode 38, and may be located below a corresponding first line cavity 83. Columns of top electrodes 38 arranged along the second horizontal direction hd2 (which is perpendicular to the first horizontal direction hd1) may be physically exposed below each first line cavity 83 in the memory array region 100.

[0103] refer to FIG. 12A to FIG. 12D , at least one conductive material may be deposited in the first line cavity 83 and in the integrated line and through-hole cavity 73. The at least one conductive material may include a metal barrier liner material and a metal filling material. The metal barrier liner material may include a conductive metal nitride material, such as TiN, TaN, WN and / or MoN. The metal barrier liner material may be deposited by physical vapor deposition and / or chemical vapor deposition. The thickness of the metal barrier liner material may be in a range from 4nm to 50nm, such as from 8nm to 25nm, but smaller and larger thicknesses may also be used. The metal filling material includes a metal, such as Cu, W, Mo, Ru, Co, Al, alloys thereof and / or layer stacks thereof. The metal filling material may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, chemical plating, or a combination thereof.

[0104] By implementing a planarization process, excess portions of the metal barrier liner material and the metal filling material can be removed from above a horizontal plane including the top surface of the dielectric pad layer 166. The planarization process can use, for example, a chemical mechanical planarization process and / or a groove etching process. Each remaining patterned portion of the at least one conductive material filling the corresponding first line cavity 83 constitutes a top electrode contact structure 80, which can be a metal line structure. Each top electrode contact structure 80 may include: a metal barrier line 82, including a metal barrier liner material; and a metal filling material portion 84, including a metal filling material. Each remaining patterned portion of the at least one conductive material filling the corresponding integrated line and through hole cavity 73 constitutes a peripheral metal interconnect structure 70, which can be an integrated line and through hole structure. The dielectric pad layer 166 can be thinned together during the planarization process.

[0105] In one embodiment, each top electrode contact structure 80 may be formed in a corresponding first line cavity 83 on a surface segment of a corresponding top electrode 38. The bottom surface of each top electrode contact structure 80 may have a third width (such as a top contact structure bottom width TCBW) along a first horizontal direction hd1. The third width (such as a top contact structure bottom width TCBW) is less than the second width (such as a hard mask top width HMTW) and greater than the first width (such as a bottom electrode via bottom width BVBW). Each top electrode contact structure 80 extends vertically through an upper portion of the memory level dielectric layer 162 and contacts the top surface of the corresponding top electrode 38. The hard mask recess filling material portion 52' may be located within a recess in the top surface of the top electrode 38, may contact a recessed shaped segment of the top surface of the top electrode 38, and may be located below the bottom surface of the top electrode contact structure 80.

[0106] refer to Fig.13 , a sixth line-and-via-level dielectric material layer 660 may be formed over the fifth line-and-via-level dielectric material layer 650. A fifth metal via structure 662 and a sixth metal line structure 668 may be formed in the sixth line-and-via-level dielectric material layer 660 to provide electrical connections to the top electrode contact structure 80 (which is formed as a metal line structure) and the peripheral metal interconnect structure 70 (which may be formed as an integrated line and via structure including a corresponding metal line structure and a corresponding at least one metal via structure group).

[0107] FIG. 14A to FIG. 14F are sequential vertical cross-sectional views of regions of the second embodiment structure during formation of a resistive memory cell 30 according to an embodiment of the present disclosure. Figure 14G is a vertical cross-sectional view of an alternative configuration of a second embodiment structure according to an embodiment of the present disclosure.

[0108] refer to Fig.14A By performing a second anisotropic etching process after performing a first anisotropic etching process, Figure 3B The first embodiment structure shown in the figure is used to obtain the second embodiment structure of the disclosed embodiment. In this embodiment, the patterned photoresist material portion 77 can be used as an etching mask for a second anisotropic etching process. The unmasked portion of the bottom electrode material layer (31L, 32L) can be etched. The second anisotropic etching process can also etch the unmasked portion of the etching stop dielectric layer 112. The etched portion of the etching stop dielectric layer 112 can have a second thickness t2 that is less than the first thickness t1. The patterned photoresist material portion 77 can then be removed, for example, by ashing.

[0109] Each patterned portion of the bottom electrode material layer (31L, 32L) constitutes a bottom electrode (31, 32). Each bottom electrode (31, 32) may include a combination of a bottom metal barrier layer 31 and a bottom metal plate 32. The bottom metal barrier layer 31 may be a patterned portion of the bottom metal barrier material layer 31L, and the bottom metal plate 32 may be a patterned portion of the bottom metal layer 32L.

[0110] In one embodiment, each bottom electrode (31, 32) may include a top surface including an annular top surface segment and a central recessed horizontal surface segment located below the downwardly protruding portion of the upper memory material layer 34. According to aspects of the disclosed embodiments, the lateral extent of the central recessed horizontal surface segment along the first horizontal direction hd1 is less than a first width (such as a bottom electrode via bottom width BVBW) of the underlying opening 113 in the etch stop dielectric layer 112.

[0111] The thickness of the horizontal extension of each hard mask template 52 can be in the range of from 25nm to 180nm and / or from 40nm to 100nm, but smaller and larger thicknesses can also be used. The periphery of the top surface of each hard mask template 52 can have a second width along the first horizontal direction hd1, which is referred to herein as the hard mask top width HMTW. The second width is greater than the first width (such as the bottom electrode via bottom width BVBW).

[0112] In general, the top electrode material layer 38L, the continuous memory material layer 34L, and the bottom electrode material layer (31L, 32L) can be patterned into a two-dimensional array of resistive memory cells 30. Each resistive memory cell 30 includes a top electrode 38, an optional cover material plate 36, a memory material layer 34, and a bottom electrode (31, 32). In one embodiment, each bottom electrode (31, 32) includes a plate portion located above the etch stop dielectric layer 112 and a via portion located within the opening 113 in the etch stop dielectric layer 112. In other words, the via portion extends vertically downward into the corresponding opening 113 in the etch stop dielectric layer 112. In one embodiment, the memory material layer 34 is located above the bottom electrode (31, 32) and is configured to provide at least two states with different resistances. In one embodiment, within each resistive memory cell 30, when the memory material layer 34 is patterned, the memory material layer 34 is completely located in a plan view within the area of ​​the top surface of the underlying bottom connection via structure 20 (which is a metal via structure). A top electrode 38 is located above the memory material layer 34 .

[0113] As discussed above, the first anisotropic etching process may use an etching chemistry that minimizes corrosion of the hard mask 52. In this embodiment, the first anisotropic etching process may use a hydrogen-free etchant such as CF4 or SF6 to maintain a substantially vertical sidewall profile for the hard mask 52. The tapered surface may extend straight from the periphery of the top surface of the hard mask 52 to at least the periphery of the bottom surface of the bottom electrode (31, 32) at a taper angle α relative to the vertical direction. The taper angle α may be in a range from 5 degrees to 20 degrees, such as from 5 degrees to 15 degrees. The array of patterned photoresist material portions 77 may then be removed, for example, by ashing. In one embodiment, the tapered surface may extend straight from the periphery of the top surface of the hard mask 52 to the periphery of the portion of the etch stop dielectric layer 112 having the second thickness t2 at a taper angle α relative to the vertical direction.

[0114] In one embodiment, the etch stop dielectric layer 112 includes: an annular portion laterally surrounding the opening 113 in the etch stop dielectric layer 112 and having a first thickness t1; and a planar layer portion having a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion. Thus, the annular portion has the first thickness t1 and includes the opening 113 therethrough, and the planar layer portion has a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion.

[0115] refer to Fig. 14B , you can implement reference Figure 4A and Figure 4B The processing steps are described to form the dielectric cap layer 150 , the memory level dielectric layer 162 , and the dielectric pad layer 166 . In this embodiment, the dielectric cap layer 150 may be formed directly on the straight sidewalls of the resistive memory cell 30 .

[0116] refer to Fig. 14C , you can implement reference Figure 5A and Figure 5B The processing steps described above are used to form the first opening 81 and the second opening 71 through the dielectric pad layer 166 (see Figure 5A ).

[0117] refer to Fig.14D , you can implement reference Fig. 6A and Figure 6B The processing steps described above are to form the first contact via cavity 88 and the second contact via cavity 78 (see Fig. 6A ).

[0118] refer to Fig.14E , you can implement reference 7A to 7C The processing steps described above are to form the top electrode contact structure 80 and the peripheral metal interconnect structure 70 (see Fig. 7A and Figure 7C ).

[0119] refer to Fig.14F , you can implement reference FIG. 8A to FIG. 8C The processing steps are described to form a line-level dielectric material layer 168, which can be incorporated into the fifth line and via level dielectric material layer 650. Respective fifth metal line structures 658 can be formed in the line-level dielectric material layer 168 to provide electrical connections to the top electrode contact structure 80 and the peripheral metal interconnect structure 70.

[0120] refer to Figure 14G , by implementing reference Fig. 9 , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B as well as FIG. 12A to FIG. 12D The processing steps described can be obtained from Fig. 14B The second embodiment structure shown in is an alternative configuration of the second embodiment structure.

[0121] FIG. 15A to FIG. 15J are sequential vertical cross-sectional views of regions of the third embodiment structure during formation of a resistive memory cell 30 according to an embodiment of the present disclosure. Figure 15K is a vertical cross-sectional view of an alternative configuration of a third embodiment structure according to an embodiment of the present disclosure.

[0122] refer to Fig.15A , by removing the photoresist layer 75, by depositing a bottom metal barrier material layer 31L, and by depositing a bottom metal layer 32L, the reference FIG. 2A to FIG. 2C The described first embodiment structure results in a third embodiment structure according to an embodiment of the present disclosure. The thickness of the bottom metal layer 32L can be modified so that the bottommost portion of the top surface of the bottom metal layer 32L is formed above a horizontal plane including the topmost portion of the top surface of the bottom metal barrier material layer 31L. In one embodiment, the thickness of the bottom metal layer 32L (as measured outside the area of ​​the opening 113 in the etch stop dielectric layer 112) can be in a range from 40nm to 200nm, such as from 80nm to 150nm, but smaller and larger thicknesses can also be used.

[0123] refer to Fig. 15B , a planarization process may be performed to planarize the top surface of the bottom metal layer 32L. The entire top surface of the bottom metal layer 32L may be formed within a horizontal Euclidean plane. In one embodiment, the thickness of the portion of the bottom metal layer 32L located above the etch stop dielectric layer 112 may be in a range from 20 nm to 150 nm, such as from 40 nm to 100 nm, although smaller and larger thicknesses may also be used.

[0124] refer to Fig. 15C , a continuous memory material layer 34L, an optional cap material layer 36L, a top electrode material layer 38L, and a hard mask material layer 52L may be deposited over the bottom metal layer 32L. Figure 3A Processing steps are described to deposit a continuous memory material layer 34L, an optional capping material layer 36L, a top electrode material layer 38L, and a hard mask material layer 52L.

[0125] refer to Fig.15D , you can implement reference Figure 3B The processing steps described above are to pattern the continuous memory material layer 34L, the optional cap material layer 36L, the top electrode material layer 38L, and the hard mask material layer 52L. As discussed above, the first anisotropic etching process can use an etching chemistry that minimizes corrosion of the hard mask template 52. In this embodiment, the first anisotropic etching process can use a hydrogen-free etchant such as CF4 or SF6 to maintain a substantially vertical sidewall profile for the hard mask template 52. The tapered surface can extend straight from the periphery of the top surface of the hard mask template 52 to the top surface of the bottom electrode material layer (31L, 32L) at a taper angle α relative to the vertical direction. The taper angle α can be in the range of from 5 degrees to 20 degrees, such as from 5 degrees to 15 degrees. The array of patterned photoresist material portions 77 can then be removed, for example, by ashing.

[0126] refer to Fig.15E , you can implement reference Figure 3C The processing steps described are used to pattern the bottom electrode material layer (31L, 32L). The third embodiment structure in this processing step can be compared with the reference Figure 3C The first embodiment structure described is substantially the same, except that the entire top surface of each bottom electrode (31, 32) is formed in a horizontal plane containing the entire bottom surface of the above memory material layer 34, and except that all top and bottom surfaces of the hard mask template 52, the top electrode 38, the cover material plate 36, and the memory material layer 34 are formed as horizontal surfaces. In the third embodiment structure, the dielectric spacer 56 can be in contact with the entire tapered surface of the stack of the memory material layer 34, the cover material plate 36, the top electrode 38, and the hard mask template 52. The dielectric spacer 56 laterally surrounds the stack of the memory material layer 34, the cover material plate 36, the top electrode 38, and the hard mask template 52. In one embodiment, the annular bottom surface of the dielectric spacer 56 is in contact with the annular surface segment of the etch stop dielectric layer 112.

[0127] refer to Fig.15F , you can implement reference Figure 4A and Figure 4BThe processing steps are described to form dielectric cap layer 150, memory level dielectric layer 162 and dielectric pad layer 166. In this embodiment, dielectric cap layer 150 may be formed on the convex outer sidewalls of dielectric spacer 56 and on the sidewalls of bottom electrode (31, 32).

[0128] refer to Figure 15G , you can implement reference Figure 5A and Figure 5B The processing steps described above are used to form the first opening 81 and the second opening 71 through the dielectric pad layer 166 (see Figure 5A ).

[0129] refer to Fig.15H , you can implement reference Fig. 6A and Figure 6B The processing steps described above are to form the first contact via cavity 88 and the second contact via cavity 78 (see Fig. 6A ).

[0130] refer to Fig.15I , you can implement reference 7A to 7C The processing steps described above are to form the top electrode contact structure 80 and the peripheral metal interconnect structure 70 (see Fig. 7A and Figure 7C ).

[0131] refer to Fig.15J , you can implement reference FIG. 8A to FIG. 8C The processing steps are described to form a line-level dielectric material layer 168, which can be incorporated into the fifth line and via level dielectric material layer 650. Respective fifth metal line structures 658 can be formed in the line-level dielectric material layer 168 to provide electrical connections to the top electrode contact structure 80 and the peripheral metal interconnect structure 70.

[0132] refer to Figure 15K , by implementing reference Fig. 9 , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B as well as FIG. 12A to FIG. 12D The processing steps described can be obtained from Fig.15F The third embodiment structure shown in is an alternative configuration of the third embodiment structure.

[0133] FIG. 16A to FIG. 16F are sequential vertical cross-sectional views of regions of the fourth embodiment structure during formation of a resistance memory cell 30 according to an embodiment of the present disclosure. Figure 16G is a vertical cross-sectional view of an alternative configuration of a fourth embodiment structure according to an embodiment of the present disclosure.

[0134] refer to Fig.16ABy performing a second anisotropic etching process after performing a first anisotropic etching process, Fig.15D The third embodiment structure shown in the figure obtains the fourth embodiment structure of the present disclosure embodiment. In this embodiment, the patterned photoresist material portion 77 can be used as an etching mask for the second anisotropic etching process. The unmasked portion of the bottom electrode material layer (31L, 32L) can be etched. The second anisotropic etching process can also etch the unmasked portion of the etching stop dielectric layer 112. The etched portion of the etching stop dielectric layer 112 can have a second thickness t2 less than the first thickness t1. The patterned photoresist material portion 77 can then be removed, for example, by ashing.

[0135] Each patterned portion of the bottom electrode material layer (31L, 32L) constitutes a bottom electrode (31, 32). Each bottom electrode (31, 32) may include a combination of a bottom metal barrier layer 31 and a bottom metal plate 32. The bottom metal barrier layer 31 may be a patterned portion of the bottom metal barrier material layer 31L, and the bottom metal plate 32 may be a patterned portion of the bottom metal layer 32L.

[0136] In one embodiment, each bottom electrode (31, 32) may include a top surface including an annular top surface segment and a central recessed horizontal surface segment located below the downwardly protruding portion of the upper memory material layer 34. According to aspects of the disclosed embodiments, the lateral extent of the central recessed horizontal surface segment along the first horizontal direction hd1 is less than a first width (such as a bottom electrode via bottom width BVBW) of the underlying opening 113 in the etch stop dielectric layer 112.

[0137] The thickness of the horizontal extension of each hard mask template 52 can be in the range of from 25nm to 180nm and / or from 40nm to 100nm, but smaller and larger thicknesses can also be used. The periphery of the top surface of each hard mask template 52 can have a second width along the first horizontal direction hd1, which is referred to herein as the hard mask top width HMTW. The second width is greater than the first width (such as the bottom electrode via bottom width BVBW).

[0138] In general, the top electrode material layer 38L, the continuous memory material layer 34L, and the bottom electrode material layer (31L, 32L) can be patterned into a two-dimensional array of resistive memory cells 30. Each resistive memory cell 30 includes a top electrode 38, an optional cover material plate 36, a memory material layer 34, and a bottom electrode (31, 32). In one embodiment, each bottom electrode (31, 32) includes a plate portion located above the etch stop dielectric layer 112 and a via portion located within the opening 113 in the etch stop dielectric layer 112. In other words, the via portion extends vertically downward into the corresponding opening 113 in the etch stop dielectric layer 112. In one embodiment, the memory material layer 34 is located above the bottom electrode (31, 32) and is configured to provide at least two states with different resistances. In one embodiment, within each resistive memory cell 30, when the memory material layer 34 is patterned, the memory material layer 34 is completely located in a plan view within the area of ​​the top surface of the underlying bottom connection via structure 20 (which is a metal via structure). A top electrode 38 is located above the memory material layer 34 .

[0139] As discussed above, the first anisotropic etching process may use an etching chemistry that minimizes corrosion of the hard mask 52. In this embodiment, the first anisotropic etching process may use a hydrogen-free etchant such as CF4 or SF6 to maintain a substantially vertical sidewall profile for the hard mask 52. The tapered surface may extend straight from the periphery of the top surface of the hard mask 52 to at least the periphery of the bottom surface of the bottom electrode (31, 32) at a taper angle α relative to the vertical direction. The taper angle α may be in a range from 5 degrees to 20 degrees, such as from 5 degrees to 15 degrees. The array of patterned photoresist material portions 77 may then be removed, for example, by ashing. In one embodiment, the tapered surface may extend straight from the periphery of the top surface of the hard mask 52 to the periphery of the portion of the etch stop dielectric layer 112 having the second thickness t2 at a taper angle α relative to the vertical direction.

[0140] In one embodiment, the etch stop dielectric layer 112 includes: an annular portion laterally surrounding the opening 113 in the etch stop dielectric layer 112 and having a first thickness t1; and a planar layer portion having a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion. Thus, the annular portion has the first thickness t1 and includes the opening 113 therethrough, and the planar layer portion has a second thickness t2 less than the first thickness t1 and laterally spaced apart from the opening 113 by the annular portion.

[0141] The fourth embodiment structure in this processing step can be compared with the reference Fig.14AThe structure of the second embodiment described is basically the same, except that the entire top surface of each bottom electrode (31, 32) is formed in a horizontal plane containing the entire bottom surface of the above memory material layer 34, and the difference is that all top and bottom surfaces of the hard mask template 52, the top electrode 38, the covering material plate 36 and the memory material layer 34 are formed as horizontal surfaces.

[0142] refer to Fig. 16B , you can implement reference Figure 4A and Figure 4B The processing steps are described to form the dielectric cap layer 150 , the memory level dielectric layer 162 , and the dielectric pad layer 166 . In this embodiment, the dielectric cap layer 150 may be formed directly on the straight sidewalls of the resistive memory cell 30 .

[0143] refer to Fig. 16C , you can implement reference Figure 5A and Figure 5B The processing steps described above are used to form the first opening 81 and the second opening 71 through the dielectric pad layer 166 (see Figure 5A ).

[0144] refer to Fig.16D , you can implement reference Fig. 6A and Figure 6B The processing steps described above are to form the first contact via cavity 88 and the second contact via cavity 78 (see Fig. 6A ).

[0145] refer to Fig.16E , you can implement reference 7A to 7C The processing steps described above are to form the top electrode contact structure 80 and the peripheral metal interconnect structure 70 (see Fig. 7A and Figure 7C ).

[0146] refer to Fig.16F , you can implement reference FIG. 8A to FIG. 8C The processing steps are described to form a line-level dielectric material layer 168, which can be incorporated into the fifth line and via level dielectric material layer 650. Respective fifth metal line structures 658 can be formed in the line-level dielectric material layer 168 to provide electrical connections to the top electrode contact structure 80 and the peripheral metal interconnect structure 70.

[0147] refer to Figure 16G , by implementing reference Fig. 9 , Fig. 10A and Fig. 10B , Fig.11A and Fig. 11B as well as FIG. 12A to FIG. 12D The processing steps described can be obtained from Fig. 14BThe fourth embodiment structure shown in is an alternative configuration of the fourth embodiment structure.

[0148] refer to Fig.17 , a flow chart showing a series of processing steps for manufacturing a resistive memory device according to an embodiment of the present disclosure.

[0149] Refer to step 1710 and Figure 1 , Figure 2A , Figure 2B and Figure 2C An etch stop dielectric layer 112 may be formed over a first metal interconnect structure (such as the bottom connecting via structure 20 ) in a first dielectric material layer (such as the lower connecting via level dielectric layer 110 ).

[0150] Refer to step 1720 and Figure 2A , Figure 2B and Figure 2C , an opening 113 having a first width (such as a bottom electrode via bottom width BVBW) along a first horizontal direction hd1 may be formed through the etch stop dielectric layer 112 .

[0151] Refer to step 1730 and Figure 3A and FIG. 15A to FIG. 15C , a layer stack including a bottom electrode material layer ( 31L, 32L), a continuous memory material layer 34L, a top electrode material layer 38L, and a hard mask material layer 52L may be formed over the etch stop dielectric layer 112 .

[0152] Refer to step 1740 and Figure 3B , Fig.14A , Fig.15D and Fig.16A , a patterned photoresist material portion 77 may be formed over the layer stack such that the patterned photoresist material portion 77 has a second width (which may or may not be the same as the hard mask top width HMTW) along the first horizontal direction hd1. The second width (such as the hard mask top width HMTW) is greater than the first width (such as the bottom electrode via bottom width BVBW).

[0153] Reference steps 1750 and Figure 3B , Fig.14A , Fig.15D and Fig.16A , the hard mask material layer 52L may be patterned into the hard mask plate 52 using the patterned photoresist material portion 77 as an etching mask.

[0154] Refer to step 1760 and FIG. 3B to FIG. 13 , FIG. 14A to FIG. 14F , FIG. 15D to FIG. 15J and FIG. 16A to FIG. 16FThe top electrode material layer 38L, the continuous memory material layer 34L and the bottom electrode material layer (31L, 32L) may be patterned into a resistive memory cell 30 including a top electrode 38, a memory material layer 34 and bottom electrodes (31, 32).

[0155] With reference to all the drawings and in accordance with various embodiments of the present disclosure, a device structure is provided, which includes: a first metal interconnect structure (such as a bottom connection via structure 20) formed in a first dielectric material layer (such as a lower connection via level dielectric layer 110); an etch stop dielectric layer 112 located above the first dielectric material layer (such as a lower connection via level dielectric layer 110) and having an opening 113, the opening 113 having a first width (such as a bottom electrode via bottom width BVBW) along a first horizontal direction hd1; a resistive memory cell 30 including a stack of bottom electrodes (31, 32), a memory material layer 34, and a top electrode 38, wherein the stack includes: a first metal interconnect structure (such as a bottom connection via structure 20) formed in a first dielectric material layer (such as a lower connection via level dielectric layer 110); an etch stop dielectric layer 112 located above the first dielectric material layer (such as a lower connection via level dielectric layer 110) and having an opening 113, the opening 113 having a first width (such as a bottom electrode via bottom width BVBW) along a first horizontal direction hd1; and a resistive memory cell 30 including a stack of bottom electrodes (31, 32), a memory material layer 34, and a top electrode 38, wherein the first metal interconnect structure (such as a bottom connection via structure 20) is formed in a first dielectric material layer (such as a lower connection via level dielectric layer 110). In the embodiment, the bottom electrode (31, 32) includes a plate portion located above the etch stop dielectric layer 112 and a through hole portion located within the opening 113 in the etch stop dielectric layer 112, the memory material layer 34 is located above the bottom electrode (31, 32) and is configured to provide at least two states with different resistances, and the top electrode 38 is located above the memory material layer 34; and a hard mask template 52 is located above the top electrode 38, wherein the periphery of the top surface of the hard mask template 52 has a second width (such as a hard mask top width HMTW) along the first horizontal direction hd1, and the second width is greater than the first width (such as a bottom electrode through hole bottom width BVBW).

[0156] In one embodiment, the device structure includes: a memory level dielectric layer 162, laterally surrounding the bottom electrode (31, 32), the memory material layer 34 and the top electrode 38; and a top electrode contact structure 80, vertically extending through the upper portion of the memory level dielectric layer 162 and contacting the top surface of the top electrode 38. In one embodiment, the bottom surface of the top electrode contact structure 80 has a third width (such as a top contact structure bottom width TCBW) along the first horizontal direction hd1, the third width is less than the second width (such as a hard mask top width HMTW) and greater than the first width (such as a bottom electrode via bottom width BVBW). In one embodiment, the device structure includes: a hard mask recess filling material portion 52', located in a recess in the top surface of the top electrode 38, contacting the recessed shaped segment of the top surface of the top electrode 38, and located below the bottom surface of the top electrode contact structure 80.

[0157] In one embodiment, the opening 113 in the etch stop dielectric layer 112 has a circular, elliptical, or rounded rectangular shape; and the first width (such as the bottom electrode via bottom width BVBW) is a diameter, a minor axis, or a distance between a pair of parallel segments. In one embodiment, the etch stop dielectric layer 112 includes an annular portion that laterally surrounds the opening 113 and has a first thickness t1, and a planar layer portion that has a second thickness t2 less than the first thickness t1 and is laterally spaced from the opening 113 by the annular portion. In one embodiment, the tapered surface extends straight from the periphery of the top surface of the hard mask template 52 to at least the top surface of the bottom electrode (31, 32) at a tapered angle α relative to the vertical direction. The tapered angle α can be in the range of from 5 degrees to 20 degrees.

[0158] In one embodiment, the device structure includes a dielectric spacer 56 in contact with the entire tapered surface and laterally surrounding the top electrode 38 and the memory material layer 34. In one embodiment, the annular bottom surface of the dielectric spacer 56 is in contact with an annular surface segment of the etch stop dielectric layer 112. In one embodiment, the annular bottom surface of the dielectric spacer 56 is in contact with an annular surface segment of the top surface of the bottom electrode (31, 32).

[0159] According to another aspect of an embodiment of the present disclosure, a device structure is provided, comprising: an etch stop dielectric layer 112, comprising an annular portion having a first thickness t1 and comprising an opening 113 therethrough, and a planar layer portion having a second thickness t2 less than the first thickness t1 and laterally spaced from the opening 113 by the annular portion, wherein the opening 113 has a first width (such as a bottom electrode via bottom width BVBW) along a first horizontal direction hd1; a resistive memory cell 30, comprising a bottom electrode (31, 32), a memory material layer 34, and a top electrode 38 A stack of bottom electrodes (31, 32) including a via portion extending vertically downward into an opening 113 in an etch stop dielectric layer 112; and a hard mask 52 located above the top electrode 38, wherein a periphery of a top surface of the hard mask 52 has a second width (such as a hard mask top width HMTW) greater than a first width (such as a bottom electrode via bottom width BVBW) along a first horizontal direction hd1, wherein a tapered surface extends straightly from a periphery of the top surface of the hard mask 52 to at least a top surface of the bottom electrode (31, 32) at a tapered angle α relative to the vertical direction. The tapered angle α may be in a range from 5 degrees to 20 degrees.

[0160] In one embodiment, the device structure includes: a dielectric cap layer 150, which laterally surrounds the resistive memory cell 30, contacts a cylindrical sidewall of the etch stop dielectric layer 112 connecting a periphery of a top surface of an annular portion of the etch stop dielectric layer 112 and a periphery of a top surface of a planar layer portion of the etch stop dielectric layer 112, contacts a sidewall of the bottom electrode (31, 32), and contacts a top surface of the hard mask template 52.

[0161] In one embodiment, the device structure includes: a memory level dielectric layer 162 located above the horizontally extending portion of the dielectric cap layer 150 and laterally surrounding a portion of the dielectric cap layer 150 protruding above the horizontally extending portion of the dielectric cap layer 150; and a top electrode contact structure 80 vertically extending through an upper portion of the memory level dielectric layer 162, the dielectric cap layer 150, and contacting a top surface of the top electrode 38. In one embodiment, a bottom surface of the top electrode contact structure 80 has a third width (such as a top contact structure bottom width TCBW) along a first horizontal direction hd1, the third width being less than the second width (such as a hard mask top width HMTW) and greater than the first width (such as a bottom electrode via bottom width BVBW).

[0162] In one embodiment, the top surface of the bottom electrode (31, 32) includes an annular top surface segment and a central recessed horizontal surface segment located below the downward protruding portion of the memory material layer 34, wherein the lateral extent of the central recessed horizontal surface area segment along the first horizontal direction hd1 is less than the first width (such as the bottom width BVBW of the bottom electrode through hole).

[0163] Various embodiments of the present disclosure may be used to provide a top electrode contact structure 80 that increases the contact area with the corresponding top electrode 38, and to provide a hard mask 52 with reduced sidewall erosion. Specifically, the sidewalls of the hard mask 52 are formed in a region that is sufficiently laterally offset relative to any topography that may exist around the central region of the resistive memory cell 30. Thus, the sidewalls of the hard mask 52 may be formed to have no profile and to have a reduced taper angle. The use of a hydrogen-free etchant gas may further reduce the taper angle of the sidewalls of the hard mask 52. The absence of a large taper angle in the hard mask 52 provides for the formation of a top electrode contact structure 80 that has a sufficiently large contact area with the top electrode 38, thereby increasing the process yield and the reliability of the electrical contact between the top electrode 38 and the top electrode contact structure 80. The top electrode contact structure 80 may be formed as a metal via structure or a metal line structure.

[0164] Some embodiments of the present application provide a device structure, including: a first metal interconnect structure formed in a first dielectric material layer; an etch stop dielectric layer located above the first dielectric material layer and having an opening, the opening having a first width along a first horizontal direction; a resistive memory cell, including a stack of a bottom electrode, a memory material layer, and a top electrode, wherein the bottom electrode includes a plate portion located above the etch stop dielectric layer and a through-hole portion located within the opening in the etch stop dielectric layer, the memory material layer is located above the bottom electrode, and the top electrode is located above the memory material layer; and a hard mask template located above the top electrode, wherein the periphery of a top surface of the hard mask template has a second width along the first horizontal direction that is greater than the first width.

[0165] In some embodiments, the device structure further comprises: a memory level dielectric layer laterally surrounding the bottom electrode, the memory material layer, and the top electrode; and a top electrode contact structure extending vertically through an upper portion of the memory level dielectric layer and contacting a top surface of the top electrode. In some embodiments, the bottom surface of the top electrode contact structure has a third width along the first horizontal direction, the third width being less than the second width and greater than the first width. In some embodiments, the device structure further comprises: a hard mask recess filling material portion located within the recess in the top surface of the top electrode, contacting a recessed segment of the top surface of the top electrode, and located below the bottom surface of the top electrode contact structure. In some embodiments, the opening in the etch stop dielectric layer has a circular, elliptical, or rounded rectangular shape; and the first width is a diameter, a minor axis, or a distance between pairs of parallel segments. In some embodiments, the memory material layer is configured to provide at least two states with different resistances; and the etch stop dielectric layer comprises an annular portion laterally surrounding the opening and having a first thickness, and a planar layer portion having a second thickness less than the first thickness and laterally spaced from the opening by the annular portion. In some embodiments, the tapered surface extends straight from the periphery of the top surface of the hard mask at least to the top surface of the bottom electrode at a tapered angle relative to the vertical direction, and the tapered angle is in the range of from 5 degrees to 20 degrees. In some embodiments, the device structure further includes: a dielectric spacer in contact with the entire tapered surface and laterally surrounding the top electrode and the memory material layer. In some embodiments, the annular bottom surface of the dielectric spacer is in contact with an annular surface segment of the etch stop dielectric layer. In some embodiments, the annular bottom surface of the dielectric spacer is in contact with an annular surface segment of the top surface of the bottom electrode.

[0166] Some other embodiments of the present application provide a device structure, including: an etch stop dielectric layer, including an annular portion having a first thickness and including an opening therethrough, and a planar layer portion having a second thickness less than the first thickness and laterally spaced from the opening by the annular portion, wherein the opening has a first width along a first horizontal direction; a resistive memory cell, including a stack of a bottom electrode, a memory material layer, and a top electrode, the bottom electrode including a through-hole portion extending vertically downward into the opening in the etch stop dielectric layer; and a hard mask template located above the top electrode, wherein a periphery of a top surface of the hard mask template has a second width greater than the first width along the first horizontal direction, wherein a tapered surface extends straight from the periphery of the top surface of the hard mask template at least to the top surface of the bottom electrode at a tapered angle relative to a vertical direction.

[0167] In some embodiments, the device structure further comprises: a dielectric cap layer laterally surrounding the resistive memory cell, contacting a cylindrical sidewall of the etch stop dielectric layer connecting a periphery of a top surface of the annular portion of the etch stop dielectric layer and a periphery of a top surface of the planar layer portion of the etch stop dielectric layer, contacting a sidewall of the bottom electrode, and contacting the top surface of the hard mask. In some embodiments, the device structure further comprises: a memory level dielectric layer located above the horizontally extending portion of the dielectric cap layer and laterally surrounding a portion of the dielectric cap layer protruding above the horizontally extending portion of the dielectric cap layer; and a top electrode contact structure extending vertically through an upper portion of the memory level dielectric layer, the dielectric cap layer, and contacting a top surface of the top electrode. In some embodiments, a bottom surface of the top electrode contact structure has a third width along the first horizontal direction, the third width being less than the second width and greater than the first width. In some embodiments, the cone angle is in a range from 5 degrees to 20 degrees; and the top surface of the bottom electrode includes an annular top surface segment and a central recessed horizontal surface segment located below the downward protruding portion of the memory material layer, wherein the lateral extent of the central recessed horizontal surface segment along the first horizontal direction is less than the first width.

[0168] Some other embodiments of the present application provide a method for forming a device structure, comprising: forming an etch stop dielectric layer above a first metal interconnect structure formed in a first dielectric material layer; forming an opening having a first width along a first horizontal direction through the etch stop dielectric layer; forming a layer stack including a bottom electrode material layer, a continuous memory material layer, a top electrode material layer and a hard mask material layer above the etch stop dielectric layer; forming a patterned photoresist material portion above the layer stack so that the patterned photoresist material portion has a second width along the first horizontal direction, and the second width is greater than the first width; patterning the hard mask material layer into a hard mask template using the patterned photoresist material portion as an etching mask; and patterning the top electrode material layer, the continuous memory material layer and the bottom electrode material layer into a resistive memory cell including a top electrode, a memory material layer and a bottom electrode.

[0169] In some embodiments, the patterned photoresist material portion covers the entire area of ​​the opening in a plan view. In some embodiments, the method includes: forming a memory level dielectric layer around and above the resistive memory cell; forming a contact via cavity through the memory level dielectric layer so that a surface segment of the top electrode is exposed to the contact via cavity; and forming a top electrode contact structure in the contact via cavity on the surface segment of the top electrode. In some embodiments, the bottom surface of the top electrode contact structure has a third width along the first horizontal direction; and the third width is less than the second width and greater than the first width. In some embodiments, the first metal interconnect structure includes a metal via structure; and when the memory material layer is patterned, the memory material layer is completely located in the area of ​​the top surface of the metal via structure in a plan view.

[0170] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the embodiments of the present disclosure. Each embodiment described using the term "comprising" also inherently discloses that the term "comprising" can be replaced with "mainly consisting of..." or with the term "consisting of..." in some embodiments, unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as optional elements in the same paragraph of different paragraphs, in some embodiments, the Markush group of the list including two or more elements can also be implicitly disclosed. Whenever the auxiliary verb "may" is used in the embodiments of the present disclosure to describe the formation of an element or the implementation of a processing step, it is also possible to explicitly consider embodiments in which such an element or such a processing step is not implemented, as long as the resulting device or device can provide equivalent results. Therefore, whenever the formation of such an element or such a processing step is omitted to provide the same result or an equivalent result, the auxiliary verb "may" applicable to the formation of an element or the implementation of a processing step should also be interpreted as "may" or interpreted as "may or may not", and equivalent results include slightly better results and slightly worse results. Those skilled in the art will appreciate that they can easily use the disclosed embodiments as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosed embodiments, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the disclosed embodiments.

Claims

1. A device structure comprising: a first metal interconnect structure formed in a first dielectric material layer; an etch stop dielectric layer, located above the first dielectric material layer and having an opening, wherein the opening has a first width along a first horizontal direction; a resistive memory cell comprising a stack of a bottom electrode, a memory material layer, and a top electrode, wherein the bottom electrode comprises a plate portion located above the etch stop dielectric layer and a via portion located within the opening in the etch stop dielectric layer, the memory material layer is located above the bottom electrode, and the top electrode is located above the memory material layer; and A hard mask is located above the top electrode, wherein a periphery of a top surface of the hard mask has a second width greater than the first width along the first horizontal direction.

2. The device structure according to claim 1, further comprising: a memory level dielectric layer laterally surrounding the bottom electrode, the memory material layer and the top electrode; as well as A top electrode contact structure vertically extends through an upper portion of the memory level dielectric layer and contacts a top surface of the top electrode.

3. The device structure according to claim 2, wherein: A bottom surface of the top electrode contact structure has a third width along the first horizontal direction, wherein the third width is smaller than the second width and larger than the first width.

4. The device structure according to claim 2, further comprising: A hard mask recess fill material portion is located within the recess in the top surface of the top electrode, contacts the recessed shaped segment of the top surface of the top electrode, and is located below a bottom surface of the top electrode contact structure.

5. The device structure according to claim 1, wherein: The opening in the etch stop dielectric layer has a circular, oval, or rounded rectangular shape; and The first width is a diameter, a minor axis, or a distance between pairs of parallel segments.

6. The device structure according to claim 1, wherein: The memory material layer is configured to provide at least two states having different resistances; as well as The etch stop dielectric layer includes an annular portion laterally surrounding the opening and having a first thickness, and a planar layer portion having a second thickness less than the first thickness and laterally spaced apart from the opening by the annular portion.

7. The device structure according to claim 6, wherein: The tapered surface extends straight from the periphery of the top surface of the hard mask at least to the top surface of the bottom electrode at a tapered angle relative to a vertical direction, the tapered angle being in a range from 5 degrees to 20 degrees.

8. The device structure according to claim 7, further comprising: A dielectric spacer contacts the entire tapered surface and laterally surrounds the top electrode and the memory material layer.

9. A device structure comprising: an etch stop dielectric layer including an annular portion having a first thickness and including an opening therethrough, and a planar layer portion having a second thickness less than the first thickness and laterally spaced apart from the opening by the annular portion, wherein the opening has a first width along a first horizontal direction; a resistive memory cell comprising a stack of a bottom electrode, a memory material layer, and a top electrode, the bottom electrode comprising a via portion extending vertically downward into the opening in the etch stop dielectric layer; and a hard mask plate located above the top electrode, wherein a periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width, The tapered surface extends straightly from the periphery of the top surface of the hard mask at least to the top surface of the bottom electrode at a tapered angle relative to a vertical direction.

10. A method for forming a device structure, comprising: forming an etch stop dielectric layer over a first metal interconnect structure formed in a first dielectric material layer; forming an opening having a first width along a first horizontal direction through the etch stop dielectric layer; forming a layer stack including a bottom electrode material layer, a continuous memory material layer, a top electrode material layer, and a hard mask material layer over the etch stop dielectric layer; forming a patterned photoresist material portion over the layer stack such that the patterned photoresist material portion has a second width along the first horizontal direction, the second width being greater than the first width; patterning the hard mask material layer into a hard mask template using the patterned photoresist material portion as an etch mask; as well as The top electrode material layer, the continuous memory material layer, and the bottom electrode material layer are patterned into a resistive memory cell including a top electrode, a memory material layer, and a bottom electrode.

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