Semiconductor device

Abstract

An object of the present disclosure is to provide a semiconductor device including a diode capable of reducing leakage current. A diode included in a semiconductor device includes: a semiconductor substrate; an n-type diffusion region selectively formed in a surface layer portion of the p-type epitaxial layer; an n-type embedded layer formed by sandwiching the semiconductor substrate and the n-type diffusion region, the n-type embedded layer having a higher impurity concentration than the n-type diffusion region; a p-type anode contact region formed on a surface layer portion of the first main surface; an n-type first cathode contact region formed in a surface layer portion of the n-type diffusion region and in a surface layer portion of the first main surface; and a p-type well region that extends from the first main surface in the depth direction outside the first cathode contact region, reaches the n-type embedded layer, and breaks the n-type diffusion region in the direction along the first main surface.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses a diode including: a p-type semiconductor substrate; an n-type epitaxial layer formed on a surface of the p-type semiconductor substrate; and an n-type buried layer formed at a boundary between the p-type semiconductor substrate and the n-type epitaxial layer.

[0003] [Background Technology Literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2015-115365 Summary of the invention

[0006] [summary]

[0007] One embodiment of the present disclosure provides a semiconductor device including a diode capable of reducing leakage current.

[0008] One embodiment of the present disclosure provides a semiconductor device, comprising: a first conductive type semiconductor substrate; a second conductive type diffusion region selectively formed on the surface portion of the semiconductor substrate; a second conductive type embedded layer formed by sandwiching the semiconductor substrate and the second conductive type diffusion region, and having a higher impurity concentration than the second conductive type diffusion region; a first conductive type anode contact region formed on the surface portion of a main surface; a second conductive type first cathode contact region formed on the surface portion of the second conductive type diffusion region; and a first conductive type layer extending from the main surface of the semiconductor substrate in a depth direction outside the first cathode contact region to reach the second conductive type embedded layer, thereby dividing the second conductive type diffusion region in a direction along the main surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic top view of the semiconductor device according to the first embodiment of the present disclosure.

[0010] Figure 2 This is a diagram showing an example of a planar layout of an impurity diffusion region in a diode region.

[0011] Figure 3 It is a diagram showing an example of the planar shape of the field insulating film in the diode region.

[0012] Figure 4 It is a diagram showing an example of the planar shape of the gate electrode in the diode region.

[0013] Figure 5 is along Figure 4A cross-sectional view taken along line VV is shown.

[0014] Figure 6 Is Figure 5 An enlarged view of the portion surrounded by a dashed line VI.

[0015] Fig. 7A is a diagram showing a part of the manufacturing steps of the semiconductor device, corresponding to Figure 6 .

[0016] Figure 7B Yes means Fig. 7A The next step is shown in Figure 1.

[0017] Figure 7C Yes means Figure 7B The next step is shown in Figure 1.

[0018] Fig.7D Yes means Figure 7C The next step is shown in Figure 1.

[0019] Fig. 7E Yes means Fig.7D The next step is shown in Figure 1.

[0020] Figure 7F Yes means Fig. 7E The next step is shown in Figure 1.

[0021] Figure 7G Yes means Figure 7F The next step is shown in Figure 1.

[0022] Figure 7H Yes means Figure 7G The next step is shown in Figure 1.

[0023] Fig.7I Yes means Figure 7H The next step is shown in Figure 1.

[0024] Figure 7J Yes means Fig.7I The next step is shown in Figure 1.

[0025] Figure 7K Yes means Figure 7J The next step is shown in Figure 1.

[0026] Figure 7L Yes means Figure 7K The next step is shown in Figure 1.

[0027] Figure 7M Yes means Figure 7L The next step is shown in Figure 1.

[0028] Figure 8 This is a circuit diagram showing the structure of a signal output circuit to which the semiconductor device is applied.

[0029] Fig. 9 is a schematic top view of a semiconductor device according to a second embodiment of the present disclosure, corresponding to Figure 6 . DETAILED DESCRIPTION

[0030] [Details]

[0031] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 It is a schematic plan view of the semiconductor device 1 according to the first embodiment of the present disclosure.

[0033] The semiconductor device 1 includes a semiconductor chip 2 formed into a rectangular parallelepiped shape. The semiconductor chip 2 forms the outer shape of the semiconductor device 1, and is, for example, a structure in which a single crystal semiconductor material is formed into a chip shape (rectangular parallelepiped shape). The semiconductor chip 2 is formed of a semiconductor material such as Si, SiC, etc. The semiconductor chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5 to 8 connecting the first main surface 3 and the second main surface 4. The first to fourth side surfaces 5 to 8 include a first side surface 5, a second side surface 6, a third side surface 7, and a fourth side surface 8. The third side surface 7 and the fourth side surface 8 extend in the first direction X and are opposite to the second direction Y orthogonal to the first direction X. The first side surface 5 and the sixth side surface 6 extend in the second direction Y and are opposite to the first direction X.

[0034] The first principal surface 3 and the second principal surface 4 are formed into a quadrilateral shape when viewed from above (hereinafter referred to as "viewed from above") as viewed from the third direction Z (the normal direction of the first principal surface 3 and the second principal surface 4). The first principal surface 3 can also be referred to as a device surface on which a functional device is formed. The second principal surface 4 can also be referred to as a non-device surface on which no functional device is formed. A plurality of device regions 9 are formed on the first principal surface 3. The number and arrangement of the plurality of device regions 9 are arbitrary. The plurality of device regions 9 can also include functional devices formed using the surface portion of the first principal surface 3. The functional device can include, for example, at least one of a semiconductor switching device, a semiconductor rectifier device, and a passive device. The functional device can also include, for example, a circuit network combining at least two of a semiconductor switching device, a semiconductor rectifier device, and a passive device.

[0035] The semiconductor switching device may include, for example, at least one of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a BJT (Bipolar Junction Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor). The semiconductor rectifying device may include, for example, at least one of a pn junction diode, a pin junction diode, a Zener diode, a Schottky barrier transistor, and a fast recovery diode. The passive device may include, for example, at least one of a resistor, a capacitor, and an inductor.

[0036] Figure 2 1 is a diagram showing an example of a planar layout of the impurity diffusion region in the diode region 11 . Figure 3 It is a diagram showing an example of the planar shape of the field insulating film 18 in the diode region 11 . Figure 4 1 is a diagram showing an example of the planar shape of the gate electrode 19 in the diode region 11 . Figure 5 is along Figure 4 A cross-sectional view taken along line VV is shown. Figure 6 Is Figure 5 This is an enlarged view of the portion surrounded by the dashed line VI. Figure 1 to Figure 6 The structure of the diode region 11 in which the diode 10 as an example of a functional device is formed in the plurality of device regions 9 will be specifically described. The diode 10 has an LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor structure and is a pn junction diode.

[0037] refer to Figure 5 and Figure 6 The diode 10 includes a semiconductor substrate 12 and a semiconductor layer 13. The semiconductor substrate 12 is a p-type (first conductivity type) semiconductor substrate. Specifically, the semiconductor substrate 12 is a silicon substrate. The semiconductor substrate 12 forms the surface layer of the second main surface 4 of the semiconductor chip 2. The p-type impurity concentration of the semiconductor substrate 12 can be 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 The thickness of the semiconductor substrate 12 may be between 100 μm and 500 μm. Since the semiconductor substrate 12 has a relatively low p-type impurity concentration, it may also be referred to as a p-type semiconductor substrate.- Type area.

[0038] refer to Figure 2 , Figure 5 and Figure 6 , a semiconductor layer 13 is formed on the semiconductor substrate 12. The semiconductor layer 13 is formed on the surface of the first main surface 3 of the semiconductor chip 2. The semiconductor layer 13 is formed on the entire surface of the first main surface 3, from the first main surface 3 and the first to fourth side surfaces 5 to 8 (refer to Figure 1 ) is exposed. The thickness of the semiconductor layer 13 may be, for example, smaller than the thickness of the semiconductor substrate 12. The thickness of the semiconductor layer 13 may be 5 μm or more and 20 μm or less.

[0039] refer to Figure 2 , Figure 5 and Figure 6 , the semiconductor layer 13 includes a p-type epitaxial layer 13A. Figure 5 and Figure 6 As shown, a p-type epitaxial layer 13A is selectively formed on the surface layer portion of the first main surface 3 of the semiconductor chip 2. An n-type diffusion region 15 is formed in the p-type epitaxial layer 13A. The n-type diffusion region 15 is formed in a rectangular shape extending long in the first direction X when viewed from above. The p-type epitaxial layer 13A is formed in a rectangular ring shape surrounding the sides of the n-type diffusion region 15.

[0040] The p-type impurity concentration of the p-type epitaxial layer 13A may be 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 The p-type impurity concentration of the p-type epitaxial layer 13A may be the same as the p-type impurity concentration of the semiconductor substrate 12. The p-type epitaxial layer 13A is formed in the surface layer portion of the first main surface 3, except for the region where the n-type diffusion region 15 is formed, from the first main surface 3 and the first to fourth side surfaces 5 to 8 (refer to Figure 1 ) exposed.

[0041] refer to Figure 5 and Figure 6 The semiconductor layer 13 is insulated and separated into a plurality of regions by an element isolation structure (eg, element isolation well, DTI (Deep Trench Isolation), STI (Shallow Trench Isolation), etc.) not shown in the figure. The element isolation structure divides the semiconductor chip 2 into a plurality of device regions 9 . Figure 2 to Figure 6 , a device region 9 in which a diode region 11 is formed among a plurality of separated device regions 9 is shown. Figure 2In the diode region 11 , an n-type diffusion region 15 is formed in the central portion of the first main surface 3 , and a p-type epitaxial layer 13A is formed in the peripheral portion of the first main surface 3 .

[0042] refer to Figure 2 , Figure 5 and Figure 6 The n-type diffusion region 15 is selectively formed on the surface of the first main surface 3 of the semiconductor chip 2. The n-type diffusion region 15 extends in layers along the first main surface 3. The depth of the n-type diffusion region 15 is the same throughout the entire circumferential region. The n-type impurity concentration of the n-type diffusion region 15 can be 1.0×10 12 cm -3 Above 1.0×10 13 cm -3 The thickness of the n-type diffusion region 15 may be 5 μm or more and 20 μm or less. The n-type diffusion region 15 overlaps with the n-type buried layer 14 described below in a plan view. The bottom of the n-type diffusion region 15 is in contact with the n-type buried layer 14 .

[0043] refer to Figure 2 , Figure 5 and Figure 6 The diode 10 further includes an n-type embedded layer (second conductive type embedded layer) 14, a p-type well region (first conductive type well region) 16, a p-type layer (first conductive type region) 17, a field insulating film 18, a gate electrode 19, an anode contact region 20, a first cathode contact region 21, a second cathode contact region 22, a third cathode contact region 23, an interlayer insulating film 24, an anode wiring 25, an anode contact 26, a cathode wiring 27, a first cathode contact 28, a second cathode contact 29, and a third cathode contact 30. Figure 6 As shown, the p-type layer 17 includes an upper p-type layer 31 and a lower p-type layer 32 .

[0044] refer to Figure 5 and Figure 6 The n-type embedded layer 14 is an n-type (second conductivity type) layer (B / L (Buried Layer)) embedded between the semiconductor substrate 12 and the semiconductor layer 13. Specifically, the n-type embedded layer 14 extends in a layered manner along the first main surface 3 in a manner that crosses the boundary between the semiconductor substrate 12 and the n-type diffusion region 15. In other words, the n-type embedded layer 14 is formed to be sandwiched by the semiconductor substrate 12 and the n-type diffusion region 15. Although not shown in the figure, the n-type embedded layer 14 is a quadrilateral when viewed from above. The n-type embedded layer 14 is electrically connected to the semiconductor substrate 12 and the p-type epitaxial layer 13A. The thickness of the n-type embedded layer 14 can be greater than 0.1μm and less than 5μm. The n-type impurity concentration of the n-type embedded layer 14 can be 1.0×10 13 cm -3 Above 1.0×10 14 cm-3 the following.

[0045] The n-type impurity concentration of the n-type buried layer 14 is higher than the n-type impurity concentration of the n-type diffusion region 15. Specifically, as described above, the n-type impurity concentration of the n-type buried layer 14 may be 1.0×10 13 cm -3 Above 1.0×10 14 cm -3 Below, the n-type impurity concentration of the n-type diffusion region 15 is 1.0×10 12 cm -3 Above 1.0×10 13 cm -3 The n-type impurity concentration of the n-type buried layer 14 may be 10 times or more higher than the impurity concentration of the n-type diffused region 15 . The n-type impurity concentration of the n-type buried layer 14 may be 1 time or more higher than the impurity concentration of the n-type diffused region 15 .

[0046] The n-type diffusion region 15 is divided into an inner diffusion region 15A having a rectangular shape in plan view and an outer diffusion region 15B having a rectangular ring shape in plan view by the p-type layer 17. The outer periphery of the inner diffusion region 15A and the inner periphery of the outer diffusion region 15B are separated from each other in the first direction X and the second direction Y. The inner diffusion region 15A includes a lower diffusion region 15C sandwiched between the n-type buried layer 14 and the p-type well region 16.

[0047] refer to Figure 2 , Figure 5 and Figure 6 The p-type well region 16 is a p-type diffusion region formed in the surface portion of the n-type diffusion region 15. The p-type well region 16 is in contact with the inner diffusion region 15A (n-type diffusion region 15) in both the first direction X and the second direction Y. The p-type well region 16 is in contact with the lower diffusion region 15C (inner diffusion region 15A) in the third direction Z. The p-type well region 16 is a region in the diode region 11 to which a voltage is applied from the anode wiring 25.

[0048] refer to Figure 2 and Figure 5 The p-type well region 16 is formed into an elliptical shape extending long in the first direction X when viewed from above. The p-type well region 16 has a first peripheral edge 61 and a second peripheral edge 62 extending linearly with a gap in the first direction X. The p-type well region 16 has a third peripheral edge 63 and a fourth peripheral edge 64 connecting the first peripheral edge 61 and the second peripheral edge 62. The third peripheral edge 63 and the fourth peripheral edge 64 face the first direction X. The third peripheral edge 63 and the fourth peripheral edge 64 are formed into an arc shape bulging outward in the first direction X.

[0049] refer to Figure 2 and Figure 5The p-type layer 17 is a p-type impurity region formed in the surface portion of the first main surface 3. The lower end of the p-type layer 17 reaches the n-type embedded layer 14. The p-type layer 17 is annular in a plan view, and divides the n-type diffusion region 15 in two directions, the first direction X and the second direction Y. The depth of the p-type layer 17 is the same throughout the entire circumferential region. Figure 2 The p-type layer 17 may be formed in a rectangular ring shape extending long in the first direction X in a plan view.

[0050] The p-type layer 17 is adjacent to the inner diffusion region 15A so as to surround the outer periphery of the inner diffusion region 15A in a plan view. The p-type layer 17 is adjacent to the outer diffusion region 15B so as to be surrounded by the inner periphery of the outer diffusion region 15B in a plan view. The p-type layer 17 surrounds the outer periphery of the p-type well region 16 in a plan view. The p-type layer 17 is formed with a gap in both the first direction X and the second direction Y with respect to the p-type well region 16 in a plan view. Although not shown in the figure, the p-type layer 17 may be formed in an elliptical ring shape extending long in the first direction X in a plan view.

[0051] refer to Figure 6 The p-type layer 17 includes an upper p-type layer 31 and a lower p-type layer 32. The upper p-type layer 31 and the lower p-type layer 32 are adjacent to each other vertically. The upper p-type layer 31 and the lower p-type layer 32 form a ring-shaped p-type layer 17.

[0052] The upper p-type layer 31 is a p-type impurity region formed in the surface portion of the first main surface 3. The upper p-type layer 31 is formed of a p-type diffusion layer. The p-type impurity concentration of the upper p-type layer 31 can be, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 The p-type impurity concentration of the upper p-type layer 31 is the same as the p-type impurity concentration of the p-type well region 16. The p-type impurity concentration of the upper p-type layer 31 may be higher than the p-type impurity concentration of the p-type well region 16. The p-type impurity concentration of the upper p-type layer 31 may be lower than the p-type impurity concentration of the p-type well region 16.

[0053] refer to Figure 2 The upper p-type layer 31 is, for example, in a quadrilateral ring shape. The upper p-type layer 31 surrounds the side of the p-type well region 16. The upper p-type layer 31 faces the p-type well region 16 in the first direction X and the second direction Y. The first depth D1 of the bottom of the upper p-type layer 31 is the same as the second depth D2 of the bottom of the p-type well region 16. The first depth D1 may be deeper than the second depth D2. The first depth D1 may be shallower than the second depth D2.

[0054] refer to Figure 5 and Figure 6The lower p-type layer 32 is formed on the second main surface 4 side relative to the upper p-type layer 31. The lower p-type layer 32 is in contact with the upper p-type layer 31. Although not shown in the figure, the lower p-type layer 32 is a quadrilateral ring and overlaps with the upper p-type layer 31 in a plan view. The lower p-type layer 32 does not face the p-type well region 16 in the lateral direction (the first direction X and the second direction Y).

[0055] The lower p-type layer 32 is formed of a p-type epitaxial layer. The p-type impurity concentration of the lower p-type layer 32 may be 1.0×10 13 cm -3 Above 1.0×10 15 cm -3 The p-type impurity concentration of the lower p-type layer 32 may be the same as the p-type impurity concentration of the p-type epitaxial layer 13A. The p-type impurity concentration of the lower p-type layer 32 may also be the same as the p-type impurity concentration of the semiconductor substrate 12. The p-type impurity concentration of the lower p-type layer 32 is lower than the p-type impurity concentration of the upper p-type layer 31. The p-type impurity concentration of the lower p-type layer 32 is lower than the p-type impurity concentration of the p-type well region 16. Since the lower p-type layer 32 has a relatively low p-type impurity concentration, it may also be referred to as a p-type well region 16. - Type area.

[0056] refer to Figure 6 , the inner peripheral end of the upper p-type layer 31 and the inner peripheral end of the lower p-type layer 32 are aligned in the first direction X and the second direction Y. The outer peripheral end of the upper p-type layer 31 and the outer peripheral end of the lower p-type layer 32 are aligned in the first direction X and the second direction Y. Although not shown in the figure, the inner peripheral end of the upper p-type layer 31 may be away from the inner peripheral end of the lower p-type layer 32 toward the outside or toward the inside. In addition, although not shown in the figure, the outer peripheral end of the upper p-type layer 31 may be away from the outer peripheral end of the lower p-type layer 32 toward the outside or toward the inside.

[0057] refer to Figure 2 and Figure 3 The field insulating film 18 is formed on the first main surface 3 of the semiconductor chip 2. The field insulating film 18 covers the first main surface 3. For the sake of clarity, Figure 2 In FIG. 1 , the outer edges of the anode contact region 20, the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 are all indicated by thick solid lines. Figure 3 In FIG. 1 , the field insulating film 18 is indicated by hatching. Figure 3 The unhatched region in FIG. 1 is a region not covered by the field insulating film 18. The field insulating film 18 may be, for example, a LOCOS (Local Oxidation of Silicon) oxide film formed by selectively oxidizing the surface (first main surface 3) of the n-type diffusion region 15.

[0058] refer to Figure 3The field insulating film 18 has a first opening 41, a second opening 42, a third opening 43, and a fourth opening 44. The first opening 41 is formed in a rectangular ring shape extending long in the first direction X in a plan view. The first opening 41 exposes a portion of the inner diffusion region 15A of the n-type diffusion region 15 (the first cathode contact region 21 described below). The second opening 42 is extended long in the first direction X in a plan view, and is formed in a rectangular ring shape surrounding the first opening 41 in a plan view. The second opening 42 exposes a portion of the upper p-type layer 31 (p-type layer 17) (the second cathode contact region 22 described below). The third opening 43 is extended long in the first direction X in a plan view, and is formed in a rectangular ring shape surrounding the first opening 41 in a plan view. The third opening 43 exposes a portion of the outer diffusion region 15B of the n-type diffusion region 15 (the third cathode contact region 23 described below).

[0059] refer to Figure 3 The fourth opening 44 is formed in an elliptical ring shape extending long in the first direction X in a plan view. The fourth opening 44 exposes the inner diffusion region 15A (n-type diffusion region 15) and the p-type well region 16. The opening width (width in the second direction Y) of the fourth opening 44 is wider than the opening widths (widths in the first direction X and the second direction Y) of the first opening 41, the second opening 42, and the third opening 43. Although not shown in the figure, the fourth opening 44 may be formed in a quadrilateral shape extending long in the first direction X in a plan view.

[0060] Although not shown in the figure, the first opening 41 may be formed as a pair so as to sandwich the fourth opening 44 in the second direction Y. Furthermore, although not shown in the figure, the second opening 42 may be formed as a pair so as to sandwich the first opening 41 and the fourth opening 44 in the second direction Y. Furthermore, although not shown in the figure, the third opening 43 may be formed as a pair so as to sandwich the first opening 41, the second opening 42, and the fourth opening 44 in the second direction Y.

[0061] refer to Figure 2 , Figure 5 and Figure 6 The first cathode contact region 21 is formed on the surface of the inner diffusion region 15A. The first cathode contact region 21 may have a higher n-type impurity concentration than the inner diffusion region 15A. The n-type impurity concentration of the first cathode contact region 21 may be, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 the following.

[0062] refer to Figure 3, the first cathode contact region 21 is exposed from the field insulating film 18 in the first opening 41. The first cathode contact region 21 is a quadrilateral ring matching the first opening 41. The first cathode contact region 21 has a first side portion 21a and a second side portion 21b extending at intervals along the first direction X. The first cathode contact region 21 has a third side portion 21c and a fourth side portion 21d connecting the first side portion 21a and the second side portion 21b. The third side portion 21c and the fourth side portion 21d extend at intervals along the second direction Y. Reference Figure 6 The first width W1 of the first cathode contact region 21 is not less than 0.6 μm and not more than 0.8 μm. The first width W1 may be constant over the entire circumferential region of the first cathode contact region 21 .

[0063] refer to Figure 2 , Figure 5 and Figure 6 The second cathode contact region 22 is formed on the surface of the upper p-type layer 31 (p-type layer 17). The second cathode contact region 22 may have a p-type impurity concentration higher than that of the upper p-type layer 31. The p-type impurity concentration of the second cathode contact region 22 may be, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 the following.

[0064] refer to Figure 3 , the second cathode contact region 22 is exposed from the field insulating film 18 in the second opening 42. The second cathode contact region 22 is a quadrilateral ring that matches the second opening 42. The second cathode contact region 22 has a first side portion 22a and a second side portion 22b extending at intervals along the first direction X. The second cathode contact region 22 has a third side portion 22c and a fourth side portion 22d connecting the first side portion 22a and the second side portion 22b. The third side portion 22c and the fourth side portion 22d extend at intervals along the second direction Y. Reference Figure 6 The second width W2 of the second cathode contact region 22 is not less than 0.6 μm and not more than 0.8 μm. The second width W2 may be constant over the entire circumferential region of the second cathode contact region 22 .

[0065] refer to Figure 2 , Figure 5 and Figure 6 The third cathode contact region 23 is formed on the surface of the outer diffusion region 15B. The third cathode contact region 23 may also have a higher n-type impurity concentration than the outer diffusion region 15B. The n-type impurity concentration of the third cathode contact region 23 may be, for example, 1.0×10 16 cm -3 Above 5.0×10 17 cm -3 the following.

[0066] refer to Figure 3 , the third cathode contact region 23 is exposed from the field insulating film 18 in the third opening 43. The third cathode contact region 23 is a quadrilateral ring matching the third opening 43. The third cathode contact region 23 has a first side portion 23a and a second side portion 23b extending at intervals along the first direction X. The third cathode contact region 23 has a third side portion 23c and a fourth side portion 23d connecting the first side portion 23a and the second side portion 23b. The third side portion 23c and the fourth side portion 23d extend at intervals along the second direction Y. Reference Figure 6 The third width W3 of the third cathode contact region 23 is not less than 0.6 μm and not more than 0.8 μm. The third width W3 may be constant over the entire circumferential region of the third cathode contact region 23 .

[0067] refer to Figure 4 , a gate electrode 19 is formed on the first main surface 3 of the semiconductor chip 2. For the sake of clarity, Figure 4 , the gate electrode 19 is indicated by hatching. The gate electrode 19 may include, for example, a conductive material such as polysilicon or aluminum. The gate electrode 19 is formed in a ring shape when viewed from above. The gate electrode 19 may include a pair of first portions 51 facing each other in the second direction Y, and a second portion 52 connecting the pair of first portions 51 to each other. In the above embodiment, the first portion 51 is formed in a straight line extending parallel to each other in the first direction X, and the second portion 52 is formed in an arc shape bulging outward in the first direction X. An opening portion 50 is formed in the central portion of the gate electrode 19 divided by the pair of first portions 51 and the pair of second portions 52. The opening portion 50 is formed in an elliptical shape extending in the first direction X when viewed from above. The opening portion 50 exposes a portion of the p-type well region 16. Specifically, the opening portion 50 exposes the anode contact region 20.

[0068] refer to Figure 4 A channel is formed in a region of the p-type well region 16 that faces the gate electrode 19. The formation of the channel in the region is controlled by the gate electrode 19. The thickness of the gate electrode 19 can be, for example, not less than 0.1 μm and not more than 0.4 μm.

[0069] refer to Figure 6 A gate insulating film 54 is formed between the gate electrode 19 and the first main surface 3. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing the first main surface 3. The thickness of the gate insulating film 54 may be, for example, not less than 0.2 nm and not more than 100 nm.

[0070] refer to Figure 6The gate electrode 19 may integrally include an annular control portion 55 on the side (inside) of the opening 50 and an annular field plate portion 56 outside the control portion 55. The control portion 55 of the gate electrode 19 sequentially covers the p-type well region 16 (region forming a channel) and the p-type layer 17 through the gate insulating film 54 from the inside toward the outside. The field plate portion 56 of the gate electrode 19 is formed on the p-type layer 17 and on the field insulating film 18.

[0071] refer to Figure 6 A side wall structure 57 is formed on the side of the gate electrode 19. The side wall structure 57 is formed on both the inner side (the side of the opening 50) and the outer side of the gate electrode 19.

[0072] refer to Figure 6 The anode contact region 20 is formed in the surface layer portion of the p-type well region 16. The anode contact region 20 is in a strip shape extending in the first direction X. The anode contact region 20 is a p-type impurity region.

[0073] refer to Figure 2 The anode contact region 20 has a first side portion 20a and a second side portion 20b extending at intervals in the first direction X. The anode contact region 20 has a third side portion 20c and a fourth side portion 20d connecting the first side portion 20a and the second side portion 20b. The third side portion 20c and the fourth side portion 20d are formed in an arc shape that bulges outward in the first direction X. The first side portion 20a to the fourth side portion 20d are all separated from the periphery (the first periphery 61 to the fourth periphery 64) of the p-type well region 16 toward the inner side when viewed from above. That is, the anode contact region 20 is formed in the surface layer portion of the p-type well region 16, separated from the periphery (the first periphery 61 to the fourth periphery 64) of the p-type well region 16 toward the inner side.

[0074] refer to Figure 6 , the fourth width W4 of the anode contact region 20 in the second direction Y is not less than 1.5 μm and not more than 2.0 μm. The fourth width W4 is wider than any one of the first width W1, the second width W2, and the third width W3 (W4>W1, W4>W2, W4>W3). The fourth width W4 may be constant throughout the entire region in the first direction X. The anode contact region 20 may be formed in a quadrilateral shape extending long in the first direction X when viewed from above.

[0075] refer to Figure 3 and Figure 6 The anode contact region 20, the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 are electrically separated by the field insulating film 18 in the surface portion of the first main surface 3. In the surface portion of the first main surface 3, the first cathode contact region 21 surrounds the anode contact region 20. Figure 6, a first interval W between the anode contact region 20 and the first cathode contact region 21 in the second direction Y 11 The second cathode contact region 22 surrounds the outer periphery of the first cathode contact region 21. Figure 6 , a second interval W between the first cathode contact region 21 and the second cathode contact region 22 in the second direction Y 12 The third cathode contact region 23 surrounds the outer periphery of the second cathode contact region 22. Figure 6 , a third interval W between the second cathode contact region 22 and the third cathode contact region 23 in the second direction Y 13 It is not less than 1.0 μm and not more than 2.0 μm.

[0076] refer to Figure 6 , the first interval W 11 Can be larger than the second interval W 12 (W 11 >W 12 ). The third interval W 13 Can be connected with the second interval W 12 Same (W 13 =W 12 ). The third interval W 13 Can be larger than the second interval W 12 (W 13 >W 12 ), it can also be smaller than the second interval W 12 (W 13 <W 12 ).

[0077] refer to Figure 5 and Figure 6 The interlayer insulating film 24 is formed on the first main surface 3 of the semiconductor chip 2. The interlayer insulating film 24 covers the gate electrode 19. The interlayer insulating film 24 is formed of, for example, silicon oxide (SiO2) or silicon nitride (SiN2). In the above embodiment, the interlayer insulating film 24 is formed of a single layer of silicon oxide, but may be formed of a plurality of interlayer insulating films 24.

[0078] refer to Figure 6 The anode wiring 25 is formed on the interlayer insulating film 24. The anode wiring 25 is electrically connected to the anode contact region 20 via the anode contact 26. Figure 6 The anode contact 26 is formed so as to penetrate the interlayer insulating film 24 at a position overlapping with the anode contact region 20 in a plan view.

[0079] refer to Figure 6The cathode wiring 27 is formed on the interlayer insulating film 24. The cathode wiring 27 is electrically connected to the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 via the first cathode contact 28, the second cathode contact 29, and the third cathode contact 30, respectively. Figure 4 7 , the first cathode contact 28 is formed at a position overlapping with the first cathode contact region 21 in a plan view, and penetrates the interlayer insulating film 24. The second cathode contact 29 is formed at a position overlapping with the second cathode contact region 22 in a plan view, and penetrates the interlayer insulating film 24. The third cathode contact 30 is formed at a position overlapping with the third cathode contact region 23 in a plan view, and penetrates the interlayer insulating film 24.

[0080] In the above embodiment, the anode wiring 25 and the cathode wiring 27 are formed of aluminum (Al), but they may be formed of other conductive materials (such as copper (Cu)). In the above embodiment, the anode contact 26, the first cathode contact 28, the second cathode contact 29 and the third cathode contact 30 are formed of tungsten (W), but they may be formed of other conductive materials (such as aluminum (Al), copper (Cu)). In this case, of course, a barrier film such as TiN may be used.

[0081] Although not shown in the figure, a gate contact mechanically and electrically connected to the gate electrode 19 is embedded in the interlayer insulating film 24. The gate contact is electrically insulated from the anode contact 26, the first cathode contact 28, the second cathode contact 29, and the third cathode contact 30.

[0082] The p-type well region 16 and the inner diffusion region 15A adjacent to the p-type well region 16 form a pn junction diode Di1 (see Figure 5 ). When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, a positive voltage is applied to the p-type well region 16, and a negative voltage is applied to the inner diffusion region 15A. In this case, the current flows from the anode contact region 20 to the first cathode contact region 21 via the pn junction diode Di1. Thus, a current path is formed on the surface of the first main surface 3, which goes from the anode contact region 20 through the p-type well region 16 and the inner diffusion region 15A to the first cathode contact region 21.

[0083] In the diode 10, a vertical parasitic pnp transistor is formed by the p-type well region 16, the p-type semiconductor substrate 12, and the n-type semiconductor (n-type diffusion region 15 and n-type buried layer 14) therebetween. In addition, in the diode 10, a lateral parasitic pnp transistor is formed by the p-type well region 16, the p-type layer 17, and the inner diffusion region 15A therebetween. Generally, there is a concern that leakage current may be generated by these parasitic pnp transistors.

[0084] According to the embodiment, the impurity concentration of the n-type embedded layer 14 is relatively high (1.0×10 13 Above 5.0×10 13 Therefore, when a forward bias is applied between the anode wiring 25 and the cathode wiring 27, the amount of current flowing from the inner diffusion region 15A to the n-type embedded layer 14 can be suppressed or prevented. Therefore, leakage current caused by the vertical parasitic pnp transistor can be suppressed or prevented.

[0085] Furthermore, in the above-described embodiment, the n-type diffusion region 15 is separated by the p-type layer 17 outside the first cathode contact region 21. Therefore, it is possible to suppress or prevent the current flowing from the anode contact region 20 to the first cathode contact region 21 from leaking to the outside from the outer region of the anode contact region 20. Therefore, it is possible to suppress or prevent the leakage current caused by the lateral parasitic pnp transistor.

[0086] Furthermore, since the n-type buried layer 14 having a higher impurity concentration than the n-type diffusion region 15 is formed below the n-type diffusion region 15 , the current flowing from the anode contact region 20 to the first cathode contact region 21 can be suppressed or prevented from leaking from the bottom of the n-type diffusion region 15 to the bottom.

[0087] In addition, a pnp transistor Tr (refer to Figure 5 ). The pnp transistor Tr is formed by the p-type well region 16, the p-type layer 17, and the inner diffusion region 15A sandwiched therebetween. In addition, the second cathode contact region 22 formed in the p-type layer 17 is connected to the cathode wiring 27. Therefore, the current flowing to the pnp transistor Tr is recovered to the cathode wiring 27 via the second cathode contact region 22. Thus, the leakage current caused by the lateral parasitic pnp transistor is more effectively suppressed or prevented.

[0088] In addition, the pn junction diode Di2 is formed by the p-type layer 17 and the outer diffusion region 15B adjacent to the p-type layer 17 (see Figure 5 ) When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, a negative voltage is applied not only to the inner diffusion region 15A but also to the outer diffusion region 15B.

[0089] When a forward bias is applied between the anode wiring 25 and the cathode wiring 27, as described above, a current path is formed from the anode contact region 20 through the p-type well region 16 and the inner diffusion region 15A to the first cathode contact region 21. In this case, even if current leaks from the p-type layer 17 to the outside, the leaked current can be returned to the cathode wiring 27 via the pn junction diode Di2 and the first cathode contact region 21.

[0090] As described above, according to the above embodiment, it is possible to reduce leakage current by improving pn junction isolation without using a module that physically reduces leakage current (for example, SOI (Silicon On Insulator) or the like).

[0091] Figure 7A to Figure 7M The diagram shows part of the manufacturing steps of the semiconductor device 1 in order of steps. Figure 7A to Figure 7M Corresponds to Figure 6 .

[0092] First, refer to Fig. 7A , prepare semiconductor wafer 101. Semiconductor wafer 101 becomes semiconductor chip 2 (refer to Figure 5 and Figure 6 ) substrate. The semiconductor wafer 101 is a p-type wafer. The semiconductor wafer 101 corresponds to the semiconductor substrate 12 (refer to Figure 5 and Figure 6 ).

[0093] Next, refer to Figure 7B , the configuration has a configuration corresponding to forming an n-type embedded layer 14 (reference Figure 5 and Figure 6 ), and n-type impurities are selectively introduced into the surface of the semiconductor wafer 101 through the hard mask. Thus, an introduction portion 102 is formed in the surface of the semiconductor wafer 101. Examples of n-type impurities include P (phosphorus) and As (arsenic).

[0094] Next, refer to Figure 7C , an epitaxial layer 103 is formed by epitaxially growing silicon of the semiconductor wafer 101. By forming the epitaxial layer 103, a semiconductor wafer structure 111 including a p-type epitaxial layer 13A is formed. The epitaxial layer 103 corresponds to the p-type epitaxial layer 13A. The n-type impurities introduced into the introduction portion 102 of the main surface of the semiconductor wafer 101 diffuse into the p-type epitaxial layer 103, thereby forming an n-type embedded layer 14. The semiconductor wafer structure 111 has a first wafer main surface 112 on one side and a second wafer main surface 113 on the opposite side. The first wafer main surface 112 and the second wafer main surface 113 correspond to the first main surface 3 and the second main surface 4 of the semiconductor chip 2, respectively (refer to Figure 5 and Figure 6 ). Next, a sacrificial insulating film 114 is formed on the first wafer main surface 112. The sacrificial insulating film 114 may be, for example, a silicon oxide (SiO 2 ) film formed by thermally oxidizing the surface layer of the first wafer main surface 112 into a film shape.

[0095] Next, refer to Fig.7D , configured to correspond to the formation of n-type diffusion region 15 (reference Figure 5 and Figure 6 ) is formed by forming a hard mask (not shown) with an opening in the region of the semiconductor wafer 101, and through the hard mask, n-type impurities are selectively introduced into the surface portion of the semiconductor wafer 101. Next, the introduced n-type impurities are diffused by heat treating the semiconductor wafer structure 111. Thus, an n-type diffusion region 15 is formed. The n-type diffusion region 15 includes an inner diffusion region 15A and an outer diffusion region 15B.

[0096] Next, refer to Fig. 7E , configured to have a configuration corresponding to the formation of a p-type well region 16 (reference Figure 5 and Figure 6 ) region and forming the upper p-type layer 31 (reference Figure 5 and Figure 6 ) is formed by forming a hard mask (not shown) with an opening in the region of the semiconductor wafer 101, and p-type impurities are selectively introduced into the surface portion of the semiconductor wafer 101 through the hard mask. Next, the introduced p-type impurities are diffused by heat treating the semiconductor wafer structure 111. Thus, the upper p-type layer 31 and the p-type layer 17 are formed. In addition, in the first direction X and the second direction Y, the region in the p-type epitaxial layer 13A between the inner diffusion region 15A and the outer diffusion region 15B where the upper p-type layer 31 is not formed becomes the lower p-type layer 32.

[0097] The order of forming the n-type diffusion region 15, the p-type well region 16, and the upper p-type layer 31 can be changed as appropriate. For example, the p-type well region 16 and the upper p-type layer 31 may be formed first, and then the n-type diffusion region 15 may be formed. In addition, instead of forming the p-type well region 16 and the upper p-type layer 31 at the same time, one of the p-type well region 16 and the upper p-type layer 31 may be formed first, and then the other of the p-type well region 16 and the upper p-type layer 31 may be formed.

[0098] Next, refer to Figure 7F A hard mask (not shown) is formed on the sacrificial insulating film 114, and the sacrificial insulating film 114 is selectively removed by etching through the hard mask, thereby forming an opening 115. Next, the surface portion of the first wafer main surface 112 exposed from the opening 115 of the sacrificial insulating film 114 is thermally oxidized to form a field insulating film 18. Thereafter, the sacrificial insulating film 114 is removed.

[0099] Next, refer to Figure 7G , a gate insulating film 54 is formed on the first wafer main surface 112. The gate insulating film 54 may be, for example, a silicon oxide (SiO2) film formed by thermally oxidizing the surface portion of the first wafer main surface 112 exposed from the first opening 41, the second opening 42, the third opening 43, and the fourth opening 44 of the field insulating film 18 into a film shape.

[0100] Next, refer to Figure 7H , becoming the gate electrode 19 (reference Figure 5 and Figure 6 ) is formed on the first wafer main surface 112 in a manner covering the gate insulating film 54 and the field insulating film 18. In the above embodiment, the base 116 includes conductive polysilicon. The base 116 can be formed by, for example, CVD (Chemical Vapor Deposition).

[0101] Next, refer to Fig.7I , by etching through a hard mask (not shown) having a predetermined pattern, the useless portion of the base 116 is removed. Thus, the gate electrode 19 is formed. Etching may be, for example, dry etching (e.g., RIE (Reactive Ion Etching) method) or wet etching. Thereafter, by removing the gate insulating film 54 exposed from the gate electrode 19, the p-type well region 16 is exposed from the opening 50, and the inner diffusion region 15A (n-type diffusion region 15) is exposed from the first opening 41 of the field insulating film 18.

[0102] Next, refer to Figure 7J , forming the side wall structure 57 (reference Figure 6 ) is sequentially formed on the first wafer main surface 112. The base insulating film 117 can be formed, for example, by a CVD method. Next, the useless portion of the base insulating film 117 is removed by etching. Thus, the sidewall structure 57 is formed by the base insulating film 117 remaining on the inner side and outer side of the gate electrode 19.

[0103] Next, refer to Figure 7K, the anode contact region 20 and the second cathode contact region 22 are formed on the surface of the p-type well region 16 and the surface of the upper p-type layer 31 (that is, the surface of the p-type layer 17), respectively. In addition, the first cathode contact region 21 and the third cathode contact region 23 are formed on the surface of the inner diffusion region 15A (n-type diffusion region 15) and the surface of the outer diffusion region 15B (n-type diffusion region 15), respectively. In the above embodiment, the anode contact region 20 is formed by implanting p-type impurities into the surface of the p-type well region 16 using an ion implantation method using the sidewall structure 57 as a hard mask. That is, the anode contact region 20 is formed in self-alignment with respect to the periphery of the sidewall structure 57 of the gate electrode 19. The first cathode contact region 21 and the third cathode contact region 23 are formed by implanting n-type impurities into the surface of the inner diffusion region 15A and the outer diffusion region 15B, respectively, using an ion implantation method using the field insulating film 18 as a hard mask. That is, the first cathode contact region 21 and the third cathode contact region 23 are formed in self-alignment with respect to the peripheries of the first opening 41 and the third opening 43 of the field insulating film 18, respectively. The second cathode contact region 22 is formed by implanting p-type impurities into the surface layer of the upper p-type layer 31 using an ion implantation method using the field insulating film 18 as a hard mask. That is, the second cathode contact region 22 is formed in self-alignment with respect to the periphery of the second opening 42 of the field insulating film 18.

[0104] Next, refer to Figure 7L , an interlayer insulating film 24 is formed on the first wafer main surface 112. The interlayer insulating film 24 can be formed by, for example, a CVD method.

[0105] Next, refer to Figure 7M , an anode contact 26, a first cathode contact 28, a second cathode contact 29, and a third cathode contact 30 are formed on the interlayer insulating film 24 by etching through a hard mask (not shown) having a predetermined pattern, forming a metal film by CVD, and etching an unnecessary metal film. Next, a base wiring film serving as a base for a plurality of wirings is formed on the interlayer insulating film 24, and anode wirings 25 and cathode wirings 27 are formed by patterning. Thereafter, the semiconductor wafer structure 111 is cut to cut out a plurality of semiconductor chips 2. Through the above steps, the semiconductor device 1 is manufactured.

[0106] Figure 8 1 is a circuit diagram showing the structure of a signal output circuit 301 using a diode 10 of a semiconductor device 1. The signal output circuit 301 is, for example, a circuit used in a vehicle network, that is, a CAN (Controller Area Network). The signal output circuit 301 includes a high-side output unit 302, a low-side output unit 303, a resistor division circuit 304, a high-side output terminal 305, and a low-side output terminal 306.

[0107] The high-side output section 302 includes a driving transistor 307, a first diode 308, and a protection transistor 309. The first diode 308 is connected in series to the driving transistor 307. The protection transistor 309 is connected in series to the first diode 308. In the above-described embodiment, the driving transistor 307 and the protection transistor 309 include p-type MOS (Metal Oxide Semiconductor) transistors (PMOS). The first diode 308 functions as a reverse current prevention circuit. As the first diode 308, the diode 10 of the semiconductor device 1 is used. The source of the driving transistor 307 is connected to the first power supply VCC1. The drain of the driving transistor 307 is connected to the anode of the first diode 308. The cathode of the first diode 308 is connected to the source of the protection transistor 309. The drain of the protection transistor 309 is connected to the high-side output terminal 305. The gate of the protection transistor 309 is grounded.

[0108] The low-side output section 303 includes a second diode 310, a protection transistor 311, and a driving transistor 312. The second diode 310 is connected in series to the protection transistor 311. The protection transistor 311 is connected in series to the second diode 310. The driving transistor 312 is connected in series to the protection transistor 311. In the above embodiment, the protection transistor 311 and the driving transistor 312 include n-type MOS transistors (NMOS). The anode of the second diode 310 is connected to the low-side output terminal 306. The cathode of the second diode 310 is connected to the drain of the protection transistor 311. The gate of the protection transistor 311 is connected to the first power supply VCC1. The source of the protection transistor 311 is connected to the drain of the driving transistor 312. The source of the driving transistor 312 is grounded.

[0109] The resistor division circuit 304 includes a first resistor 313 and a second resistor 314. One end of the first resistor 313 is connected to the high-side output terminal 305. The other end of the first resistor 313 is connected to one end of the second resistor 314. The other end of the second resistor 314 is grounded. The second power supply VCC2 is connected to the connection point between the first resistor 313 and the second resistor 314.

[0110] The high-side output terminal 305 is connected to the first bus. The low-side output terminal 306 is connected to the second bus. A load resistor is connected between the first bus and the second bus. The load resistor is a high-side load resistor 315A and a low-side load resistor 315B connected in series at a connection node N. The load resistor 315A and the load resistor 315B have the same resistance value.

[0111] For example, the first power supply VCC1 is set to 5V. At this time, the connection node N is set to the midpoint voltage, that is, 2.5V. Since the current flowing through the first resistor 313 and the second resistor 314 is common, the voltage drop generated by each of the first resistor 313 and the second resistor 314 is the same, and the high-side signal CANH generated in the high-side output terminal 305 becomes a voltage higher than the voltage of the connection node N (= midpoint voltage) by the voltage drop amount, and the low-side signal CANL generated in the low-side output terminal 306 becomes a voltage lower than the voltage of the connection node N (= midpoint voltage) by the voltage drop amount. The midpoint voltage can also be called a common voltage.

[0112] A control signal is provided to the gate of the driving transistor 307. An inversion signal of the control signal is provided to the gate of the driving transistor 312. When the control signal is at a low (L) level, both driving transistors 307 and 312 are turned on. Thus, a high-side signal CANH of 3.5V (standard value) is output to the high-side output terminal 305, and a low-side signal CANL of 1.5V (standard value) is output to the low-side output terminal 306 (dominant state). On the other hand, when the control signal is at a high (H) level, both driving transistors 307 and 312 are turned off. Thus, a high-side signal CANH of 2.5V (standard value) is output to the high-side output terminal 305, and a low-side signal CANL of 2.5V (standard value) is output to the low-side output terminal 306 (resessive state).

[0113] In the above-described embodiment, the diode 10 of the semiconductor device 1 is used as the first diode 308 of the high-side output portion 302 and the second diode 310 of the low-side output portion 303 .

[0114] Assuming that other diodes (diodes that do not sufficiently reduce leakage current) are used instead of the diode 10 of the semiconductor device 1 as the first diode 308 and the second diode 310, the following problem will occur in the above case. That is, due to the leakage current in the first diode 308 and the second diode 310, the current I flowing through the low-side output unit 303 a The value is lower than the current I flowing through the high-side output section 302 CANH The value of CANL <I CANH ). In such a case, there is a concern that the voltage of the connection node N (= midpoint voltage) may decrease. When the voltage (= midpoint voltage) decreases, there is a concern that the voltage of the high-side signal CANH and the low-side signal CANL may decrease from the desired voltage. In order to achieve good CAN communication, it is necessary to sufficiently reduce the leakage current of the first diode 308 and the second diode 310. Furthermore, it is preferred that the current I CANL The value is as close as possible to the current I CANH The value of (ICANL =I CANH ).

[0115] In the above embodiment, the diode 10 of the semiconductor device 1 is used as the first diode 308 and the second diode 310. Therefore, the leakage current of the first diode 308 and the second diode 310 can be sufficiently reduced, thereby making the current I CANL The value is as close as possible to the current I CANH The value of .

[0116] Fig. 9 It is a diagram for explaining the effects of the semiconductor device 1 .

[0117] [Table 1]

[0118]

[0119] In Table 1, the leakage current ratio (leakage current value (I CANH -I CANL ) / Current value(I CANH )). The semiconductor device of the reference example is different from the semiconductor device 1 in that the bottom of the p-type layer 17 does not reach the n-type buried layer 14 (that is, the lower p-type layer 32 is not provided). The other points of the semiconductor device of the reference example are the same as those of the semiconductor device 1.

[0120] As can be seen from Table 1, the semiconductor device 1 can achieve a reduction in leakage current compared to the semiconductor device of the reference example.

[0121] Fig. 9 It is a schematic cross-sectional view of a semiconductor device 201 according to the second embodiment of the present disclosure, and corresponds to FIG. 7 . Fig. 9 In the present invention, the same reference symbols are given to the same structures as those described so far, and their description is omitted.

[0122] The semiconductor device 201 is different from the semiconductor device 1 of the first embodiment in that a p-type layer 217 is provided instead of the p-type layer 17. The p-type layer 217 is different from the p-type layer 17 of the first embodiment in that the p-type layer 217 is formed only of a p-type diffusion layer 217a. The bottom of the p-type diffusion layer 217a extends to the n-type embedded layer 14 in the depth direction.

[0123] According to the semiconductor device 201 of the second embodiment of the present disclosure, the same operational effects as those described in connection with the first embodiment are achieved.

[0124] In addition, in the semiconductor device 1 and the semiconductor device 201, the first cathode contact region 21, the second cathode contact region 22, and the third cathode contact region 23 are described as being in the shape of a quadrilateral ring, but the cathode contact regions 21 to 23 may also be in the shape of a strip that is long in the first direction X. In such a case, each cathode contact region 21 to 23 forms a pair in the second direction Y with the anode contact region 20 therebetween.

[0125] In the above embodiments, the first conductivity type is p-type and the second conductivity type is n-type, but the first conductivity type may be n-type and the second conductivity type may be p-type. The specific configuration of the above case is obtained by replacing the p-type region with the n-type region and the n-type region with the p-type region in the above description and drawings.

[0126] In the above-mentioned embodiments, the signal output circuit 301 is described as a circuit used in a vehicle network, namely, CAN, but the diodes 308 and 310 (that is, the diode 10 of the semiconductor device 1) used in the signal output circuit 301 can be applied not only to the signal output circuit used in CAN, but also to the signal output circuit used in other vehicle networks such as LIN (Local Interconnect Network) and FlexRay (vehicle network standard). Of course, the diode 10 of the semiconductor device 1 can also be applied to a diode for a vehicle switch IC (Integrated Circuit), a diode for a DC / DC (Direct Current / Direct Current) converter, etc.

[0127] The embodiments of the present disclosure are illustrative in all points and should not be interpreted restrictively, and are intended to include modifications in all points.

[0128] The following features can be extracted from the description of this specification and the drawings. Hereinafter, the alphanumeric characters in parentheses indicate corresponding components in the above-described embodiment, and do not limit the scope of each clause to the gist of the embodiment.

[0129] [Additional Note 1-1]

[0130] A semiconductor device (1, 201), comprising:

[0131] A first conductive type semiconductor substrate (12);

[0132] A second conductive type diffusion region (15) is selectively formed on the surface of the semiconductor substrate (12);

[0133] a second conductive type embedded layer (14) formed by sandwiching the semiconductor substrate (12) and the second conductive type diffusion region (15), and having an impurity concentration higher than that of the second conductive type diffusion region (15);

[0134] A first conductive type anode contact region (20) formed on the surface of the main surface 3;

[0135] A second conductive type first cathode contact region (21) is formed on the surface of the second conductive type diffusion region (15) and the surface of the main surface (3); and

[0136] The first conductive type layer (17, 217) extends from the main surface 3 of the semiconductor substrate (12) in the depth direction outside the first cathode contact region (21) to reach the second conductive type embedded layer (14) and divides the second conductive type diffusion region (15) in the direction along the main surface.

[0137] According to the above configuration, a current path from the anode contact region (20) to the first cathode contact region (21) is formed in the second conductive type diffusion region (15). Furthermore, the second conductive type diffusion region (15) is separated from the first cathode contact region (21) by the first conductive type layer (17, 217). Therefore, it is possible to suppress or prevent the current flowing from the anode contact region (20) to the first cathode contact region (21) from flowing to the outside from the region outside the first cathode contact region (21).

[0138] In addition, since the second conductive type embedded layer (14) having a higher impurity concentration than the second conductive type diffusion region (15) is formed below the second conductive type diffusion region (15), it is possible to suppress or prevent the current flowing from the anode contact region (20) to the first cathode contact region (21) from flowing from the bottom of the second conductive type diffusion region (15) to the bottom.

[0139] Thus, a semiconductor device (1, 201) including a diode capable of reducing leakage current can be provided.

[0140] [Additional Notes 1-2]

[0141] According to the semiconductor device (1, 201) described in Note 1-1, the first conductive layer (17, 217) is annular when viewed from above, and divides the second conductive diffusion region (15) in two directions: a first direction (X) along the main surface (3) and a second direction (Y) along the main surface (3) and intersecting the first direction (X).

[0142] [Notes 1-3]

[0143] The semiconductor device (1, 201) according to Supplement 1-1 or 1-2, further comprising a second cathode contact region (22) of the first conductivity type formed outside the first cathode contact region (21) in the surface layer portion of the main surface (3), and

[0144] The first conductive type layer (7, 217) is electrically connected to the second cathode contact region (22).

[0145] [Notes 1-4]

[0146] The semiconductor device (1, 201) according to Supplementary Notes 1 to 3, wherein the second cathode contact region (22) is formed on a surface portion of the first conductive type layer (17, 217).

[0147] [Notes 1-5]

[0148] The semiconductor device (1, 201) according to Supplement 1-3 or 1-4, further comprising a third cathode contact region (23) of the second conductivity type formed on the surface layer portion of the main surface (3) outside the second cathode contact region (22), and

[0149] The second conductive type diffusion region (15) includes an outer diffusion region (15B) formed outside the first conductive type layer (17, 217),

[0150] The outer diffusion region (15B) is electrically connected to the third cathode contact region (23).

[0151] [Appendix 1-6]

[0152] The semiconductor device (1, 201) according to Supplementary Notes 1 to 5, wherein the third cathode contact region (23) is formed on the surface layer portion of the outer diffusion region (15B).

[0153] [Appendix 1-7]

[0154] A semiconductor device (1) according to any one of Notes 1-1 to 1-6, wherein the first conductive type layer 17 comprises: an upper first conductive type layer (31); and a lower first conductive type layer (32) formed adjacent to and below the upper first conductive type layer (31) and having an impurity concentration different from that of the upper first conductive type layer (31).

[0155] [Appendix 1-8]

[0156] The semiconductor device (1) according to Supplementary Notes 1 to 7, wherein the impurity concentration of the upper first conductivity type layer (31) is higher than the impurity concentration of the lower first conductivity type layer (32).

[0157] [Appendix 1-9]

[0158] The semiconductor device (1) according to Supplement 1-8, wherein the upper first conductivity type layer (31) includes a first conductivity type diffusion layer including a diffusion layer,

[0159] The lower first conductivity type layer (32) includes a first conductivity type epitaxial layer including an epitaxial layer.

[0160] [Notes 1-10]

[0161] The semiconductor device (1) according to any one of Supplementary Notes 1-7 to 1-9, further comprising a first conductive type well region (16) formed adjacent to the second conductive type diffusion region (15) in the surface layer portion of the main surface (3) and forming the anode contact region (20) in the surface layer portion,

[0162] A first depth D1 of the bottom of the upper first conductivity type layer (31) is the same as a second depth D2 of the bottom of the first conductivity type well region (16).

[0163] [Appendix 1-11]

[0164] The semiconductor device (201) according to any one of Supplementary Notes 1-1 to 1-10, wherein the first conductive type layer (217) includes a first conductive type diffusion layer (217a) including a diffusion layer, and

[0165] The bottom of the first conductive type diffusion layer (217a) extends from the main surface in the depth direction to reach the second conductive type buried layer (14).

[0166] [Appendix 1-12]

[0167] The semiconductor device (1, 201) according to any one of Notes 1-1 to 1-11, wherein the anode contact region (20) and the first cathode contact region (21) are strip-shaped and extend along the first direction (X) along the main surface (3),

[0168] A width W4 of the anode contact region (20) in a second direction (Y) along the main surface (3) and intersecting the first direction (X) is wider than a width W1 of the first cathode contact region (21) in the second direction (Y).

[0169] [Appendix 1-13]

[0170] The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-12, further comprising a first conductive type well region (16) formed in the surface layer portion of the main surface (3) adjacent to the second conductive type diffusion region (15), and

[0171] The second conductive type diffusion region (15) includes a lower diffusion region (15C) sandwiched between the second conductive type embedded layer (14) and the first conductive type well region (16).

[0172] [Appendix 1-14]

[0173] The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-13, wherein the impurity concentration of the second conductivity type embedded layer is higher than the impurity concentration of the second conductivity type diffusion region by more than 10 times.

[0174] [Note 1-15]

[0175] The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-14, wherein the first conductivity type is p-type and the second conductivity type is n-type.

[0176] [Explanation of symbols]

[0177] 1 Semiconductor devices

[0178] 2 Semiconductor Chips

[0179] 3 1st main side (main side)

[0180] 4 2nd main side

[0181] 5 Side 1

[0182] 6 Side 2

[0183] 7 Side 3

[0184] 8 Side 4

[0185] 9 Device Area

[0186] 10 diodes

[0187] 11Diode area

[0188] 12Semiconductor substrate

[0189] 13Semiconductor layer

[0190] 14n-type embedded layer (second conductivity type embedded layer)

[0191] 15n-type diffusion region (second conductivity type diffusion region)

[0192] 15A Inner diffusion area

[0193] 15B Outer diffusion area

[0194] 15C Outer diffusion region

[0195] 16p-type well region (first conductivity type well region)

[0196] 17p-type layer (first conductivity type layer)

[0197] 18 Field insulation film

[0198] 19Gate electrode

[0199] 20 Anode contact area

[0200] 20a1st side

[0201] 20b 2nd side

[0202] 20c 3rd side

[0203] 20d 4th side

[0204] 21 1st cathode contact area

[0205] 21a1st side

[0206] 21b Second side

[0207] 21c 3rd side

[0208] 21d 4th side

[0209] 22 2nd cathode contact area

[0210] 22a1st side

[0211] 22b 2nd side

[0212] 22c 3rd side

[0213] 22d 4th side

[0214] 23 3rd cathode contact area

[0215] 23a1st side

[0216] 23b 2nd side

[0217] 23c 3rd side

[0218] 23d 4th side

[0219] 24 interlayer insulation film

[0220] 25 Anode wiring

[0221] 26 Anode contact

[0222] 27 Cathode wiring

[0223] 28 1st cathode contact

[0224] 29 2nd cathode contact

[0225] 30 3rd cathode contact

[0226] 31 Upper p-type layer (upper first conductivity type layer)

[0227] 32 lower p-type layer (lower first conductivity type layer)

[0228] 41 1st opening

[0229] 42 2nd opening

[0230] 43 3rd opening

[0231] 44 4th opening

[0232] 50 opening

[0233] 51 Part 1

[0234] 52 Part 2

[0235] Channel 53 Area

[0236] 54Gate insulating film

[0237] 55 Control Department

[0238] 56 Field Board

[0239] 57 side wall structure

[0240] 61 1st week

[0241] 62 2nd periphery

[0242] 63 3rd perimeter

[0243] 64 4th week

[0244] 101 Semiconductor Wafer

[0245] 102 Import Department

[0246] 103 Epitaxial layer

[0247] 108 No.1 diode

[0248] 111Semiconductor wafer structure

[0249] 1121st wafer main surface

[0250] 113 Second wafer main surface

[0251] 114 Sacrificial insulation film

[0252] 115 Opening

[0253] 116 Base

[0254] 117 Base insulation film

[0255] 201 Semiconductor devices

[0256] 217p-type layer (first conductivity type layer)

[0257] 217a n-type diffusion layer (first conductivity type diffusion layer)

[0258] 301 signal output circuit

[0259] 302 High-side output

[0260] 303 Low-side output

[0261] 304 Resistor Division Circuit

[0262] 305 High-side output terminal

[0263] 306 Low-side output terminal

[0264] 307 Driver transistor

[0265] 308 No.1 diode

[0266] 309 protection transistor

[0267] 310 No. 2 diode

[0268] 311 Protection Transistor

[0269] 312 Driver transistor

[0270] 313 1st resistor

[0271] 314 2nd resistor

[0272] 315A load resistor

[0273] 315B load resistor

[0274] CANH high side signal

[0275] CANL low side signal

[0276] D1 Depth 1

[0277] D2 Depth 2

[0278] I CANH Current

[0279] I CANL Current

[0280] VCC1 1st power supply

[0281] VCC2 Second power supply

[0282] W1: first width (width of the first cathode contact region in the second direction)

[0283] W2 2nd Width

[0284] W3 3rd Width

[0285] W4: 4th width (width of the anode contact region in the second direction)

[0286] W 11 Interval 1

[0287] W 12 Interval 2

[0288] W 13 Interval 3

[0289] X 1st direction

[0290] Y 2nd direction

[0291] Z 3rd direction.

Claims

1. A semiconductor device comprising: a first conductive type semiconductor substrate; A second conductive type diffusion region is selectively formed on the surface of the semiconductor substrate; a second conductive type embedded layer, formed between the semiconductor substrate and the second conductive type diffusion region, and having an impurity concentration higher than that of the second conductive type diffusion region; A first conductive type anode contact region formed on a surface portion of the main surface; a second conductive type first cathode contact region formed on a surface portion of the second conductive type diffusion region; and The first conductivity type layer extends from the main surface of the semiconductor substrate in the depth direction outside the first cathode contact region to reach the second conductivity type buried layer, thereby dividing the second conductivity type diffusion region in the direction along the main surface.

2. The semiconductor device according to claim 1, wherein the first conductive type layer is ring-shaped in a plan view, dividing the second conductive type diffusion region in two directions: a first direction along the main surface and a second direction along the main surface and intersecting the first direction.

3. The semiconductor device according to claim 1 or 2, further comprising: in the surface portion of the main surface, the second cathode contact region of the first conductivity type is formed outside the first cathode contact region, and the first conductivity type layer is electrically connected to the second cathode contact region. 4 . The semiconductor device according to claim 3 , wherein the second cathode contact region is formed in a surface portion of the first conductive type layer.

5. The semiconductor device according to claim 3 or 4, further comprising: a third cathode contact region of the second conductivity type formed outside the second cathode contact region in the surface layer portion of the main surface, and The second conductivity type diffusion region includes an outer diffusion region formed outside the first conductivity type layer, and the outer diffusion region is electrically connected to the third cathode contact region. 6 . The semiconductor device according to claim 5 , wherein the third cathode contact region is formed in a surface layer portion of the outer diffusion region.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first conductivity type layer comprises: an upper first conductivity type layer; and a lower first conductivity type layer formed adjacent to and below the upper first conductivity type layer and having an impurity concentration different from that of the upper first conductivity type layer. 8 . The semiconductor device according to claim 7 , wherein an impurity concentration of the upper first conductivity type layer is higher than an impurity concentration of the lower first conductivity type layer.

9. The semiconductor device according to claim 8, wherein the upper first conductivity type layer includes a first conductivity type diffusion layer including a diffusion layer, The lower first conductivity type layer includes a first conductivity type epitaxial layer including an epitaxial layer.

10. The semiconductor device according to any one of claims 7 to 9, further comprising: a first conductivity type well region formed adjacent to the second conductivity type diffusion region in a surface portion of the main surface, and the anode contact region is formed in the surface portion; and A first depth of a bottom portion of the upper first conductivity type layer is equal to a second depth of a bottom portion of the first conductivity type well region.

11. The semiconductor device according to any one of claims 1 to 10, wherein the first conductivity type layer includes a first conductivity type diffusion layer including a diffusion layer, The bottom of the first conductivity type diffusion layer extends from the main surface in the depth direction to reach the second conductivity type buried layer.

12. The semiconductor device according to any one of claims 1 to 11, wherein the anode contact region and the first cathode contact region are strip-shaped and extend along a first direction along the main surface, A width of the anode contact region in a second direction that is along the main surface and intersects the first direction is wider than a width of the first cathode contact region in the second direction.

13. The semiconductor device according to any one of claims 1 to 12, further comprising a first conductivity type well region formed adjacent to the second conductivity type diffusion region in a surface layer portion of the main surface, The second conductivity type diffusion region includes a lower diffusion region sandwiched between the second conductivity type embedded layer and the first conductivity type well region.

14. The semiconductor device according to any one of claims 1 to 13, wherein an impurity concentration of the second conductivity type embedded layer is higher than an impurity concentration of the second conductivity type diffusion region by more than 10 times. 15 . The semiconductor device according to claim 1 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

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