Micro-groove type power device with low warping stress

Abstract

The invention relates to a micro-groove type power device with low warping stress, which is characterized in that any micro-groove type cell comprises a first type of groove unit and a second type of groove unit; a first type of conductive polycrystalline silicon and an insulating dielectric layer in the groove are arranged in each first type of groove, the second type of conductive polycrystalline silicon is in ohmic contact with front-side first electrode metal located above the front side of the semiconductor substrate, and the first type of conductive polycrystalline silicon is electrically connected with front-side second electrode metal located above the front side of the semiconductor substrate. And the second type of conductive polycrystalline silicon is insulated and isolated from the first electrode metal on the front surface through the insulating dielectric layer in the groove. According to the invention, the stress in the processing process of the micro-groove type power device can be reduced, the photoetching sleeve deviation of the contact hole caused by warping is avoided, and high-consistency threshold voltage and saturation voltage drop are obtained.

Description

Technical Field

[0001] The invention relates to a power device, in particular to a micro-groove type power device with low warping stress. Background Art

[0002] IGBT (Insulate-Gate Bipolar Transistor) is a representative type of power semiconductor device. Because of its advantages such as high withstand voltage, low on-state voltage drop, easy drive and fast switching speed, it has important applications in many power fields such as switching power supplies, variable frequency speed regulation, inverters, etc.

[0003] Since the invention of IGBT devices, reducing device power loss (i.e. optimizing conduction loss and switch-off loss) has always been one of the development directions of IGBT device technology. With the upgrading of technology, IGBT devices are constantly iterating, among which the front structure has evolved from planar to trench to micro-trench structure.

[0004] As the cell size of IGBT devices continues to shrink, the density of trench gates increases, the channel density increases, and the saturation voltage drop decreases accordingly. However, the increase in trench density will lead to an increase in warpage stress, which is easy to cause contact hole overlay deviation. At this time, the distance from the emitter contact hole to the trench gate decreases, making the photolithography of the emitter contact hole a technical bottleneck, which will eventually lead to poor consistency of the device's threshold voltage and saturation voltage, narrowing the safe operating area, and even causing a short circuit between the gate and the emitter in severe cases, leading to failure of the IGBT device. Summary of the invention

[0005] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a micro-groove power device with low warping stress, which can reduce the stress during the processing of the micro-groove power device, avoid contact hole lithography deviation caused by warping, and obtain highly consistent threshold voltage and saturation voltage drop.

[0006] According to the technical solution provided by the present invention, a micro-groove type power device with low warpage stress comprises: A semiconductor substrate having a first conductivity type; The active region includes a plurality of micro-groove cells distributed in parallel, wherein any micro-groove cell includes a first type of groove unit and a second type of groove unit; The first type trench unit includes at least two first type trenches, the second type trench unit includes at least two second type trenches, and the first type trench is located between the second type trenches; A first type of conductive polysilicon and an insulating dielectric layer in each first type of trench are arranged, wherein the first type of conductive polysilicon is insulated and isolated from the inner wall of the first type of trench, the insulating dielectric layer in the trench is distributed in the notch area of ​​the first type of trench, the first type of conductive polysilicon is located between the insulating dielectric layer in the trench and the bottom of the first type of trench, and the insulating dielectric layer in the trench is in contact with the first type of conductive polysilicon; Disposing a second type of conductive polysilicon in each second type of trench, wherein the second type of conductive polysilicon is insulated and isolated from an inner wall of the second type of trench; The second type of conductive polysilicon is in ohmic contact with the front first electrode metal located above the front side of the semiconductor substrate. The first type of conductive polysilicon is electrically connected to the front second electrode metal located above the front side of the semiconductor substrate, and the second type of conductive polysilicon is insulated and isolated from the front first electrode metal by the insulating dielectric layer in the trench.

[0007] The first type of trench and the second type of trench extend vertically from the front side of the semiconductor substrate to the back side of the semiconductor substrate, and both the first type of trench and the second type of trench penetrate the second conductive type base region distributed in the active region, wherein: The corresponding bottoms of the first type trenches and the second type trenches are both located below the second conductive type base region; The bottom surface of the second conductive type base region is located below the contact interface between the insulating dielectric layer in the trench and the first conductive polysilicon.

[0008] For two adjacent first-type trenches, a plurality of first-conductivity-type emitter regions and a plurality of second-conductivity-type first heavily doped regions are arranged in the second-conductivity-type base region between the first-type trenches, wherein: Along the length direction of the first type trench, the first conductivity type emitter region and the second conductivity type first heavily doped region are alternately distributed, and the first conductivity type emitter region and the second conductivity type first heavily doped region are separated by the second conductivity type base region; The first conductive type emitter region and the second conductive type first heavily doped region are in contact with the outer wall of the corresponding first type trench; The first conductive type emitter region overlaps with the first conductive polysilicon in the first type trench it contacts; The first conductive type emitter region and the second conductive type first heavily doped region are in ohmic contact with the front first electrode metal.

[0009] The distance between the contact interface between the insulating dielectric layer and the first type of conductive polysilicon in the trench and the front surface of the semiconductor substrate is 1μm~1.5μm, and the distance between the bottom of the first conductive type emitter region and the contact interface between the insulating dielectric layer and the first type of conductive polysilicon in the trench is at least 0.2μm.

[0010] A plurality of second conductive type second heavily doped regions and non-ohmic contact regions are arranged alternately between the first type trench and the adjacent second type trench, and the second conductive type second heavily doped region is located in the second conductive type base region between the first type trench and the adjacent second type trench, wherein: The second heavily doped region of the second conductivity type contacts the corresponding outer walls of the first type trench and the second type trench on both sides. The bottom of the second heavily doped region of the second conductivity type is located below the contact interface between the insulating dielectric layer in the trench and the first conductive polysilicon; The second heavily doped region of the second conductivity type is in ohmic contact with the first front electrode metal. The front first electrode metal is in non-ohmic contact with the non-ohmic contact area.

[0011] The junction depth of the second conductive type second heavily doped region is 0.3 μm to 2 μm.

[0012] The second type of conductive polysilicon fills up the second type of trench, and the second type of conductive polysilicon is insulated and isolated from the inner wall of the second type of trench by the second type of trench insulating oxide layer.

[0013] A carrier storage layer is also provided in the active region, wherein: The carrier storage layer traverses the active region and is located below the second conductivity type base region, and the carrier storage layer is adjacent to the second conductivity type base region; The carrier storage layer contacts the corresponding outer walls of the first type trench and the second type trench, and the corresponding groove bottoms of the first type trench and the second type trench are both located below the carrier storage layer.

[0014] The front first electrode metal is in ohmic contact with the second type conductive polysilicon through a first electrode contact hole, wherein the first electrode contact hole is formed by self-alignment.

[0015] The corresponding groove depths of the first and second type grooves are 5 μm to 6 μm; The corresponding groove widths of the first type groove and the second type groove are 0.5μm~1μm.

[0016] The advantages of the present invention are as follows: the micro-groove type cell includes both the first type of groove unit and the second type of groove unit; the first type of conductive polysilicon and the insulating dielectric layer in the groove are arranged in the first type of groove in the first type of groove unit; the contact interface formed by the insulating dielectric layer in the groove and the first type of conductive polysilicon can be used to reduce the warping stress in the processing of the power device; in addition, the first electrode contact hole can be made in the active area by a general opening method, so as to avoid the contact hole lithography deviation caused by warping, obtain a threshold voltage and a saturation voltage drop with high consistency, and prevent the safe working area from narrowing.

[0017] After the first type of conductive polysilicon is arranged in the first type of trench and matched with the insulating dielectric layer in the trench, a short channel can be formed when a conductive channel is formed by overlapping the first conductive type emitter region and the first type of conductive polysilicon. Without improving the thermal process of the second conductive type base region and the carrier storage layer, the saturation voltage drop and turn-on loss can be effectively reduced.

[0018] By arranging alternately distributed first conductivity type emitter regions and second conductivity type first heavily doped regions between two adjacent first type trenches, the saturation current can be effectively adjusted to prevent latch-up.

[0019] An alternatingly distributed second conductive type second heavily doped region and a non-ohmic contact region are arranged between the first type of grooves and the second type of grooves. The second conductive type second heavily doped region is in ohmic contact with the front first electrode metal, and the non-ohmic contact region is in non-ohmic contact with the front first electrode metal. At this time, hole storage during the turn-on process and hole extraction during the turn-off process of the power device can be modulated, thereby achieving the effect of optimizing the compromise between the on-state voltage drop and the turn-off loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A top view of an embodiment of a micro-groove cell of the present invention.

[0021] Figure 2 for Figure 1 AA section view in.

[0022] Figure 3 for Figure 1 BB section view in.

[0023] Explanation of the figure marks: 1-first type of trench, 2-second type of trench, 3-P+ second heavily doped region, 4-first P-type base region between trenches, 5-N+ emitter region, 6-P+ first heavily doped region, 7-front first electrode metal, 8-insulating dielectric layer in the trench, 9-second P-type base region between trenches, 10-gate oxide layer, 11-first type of conductive polysilicon, 12-second type of conductive polysilicon, 13-second type of trench insulating oxide layer, 14-carrier storage layer, 15-N-type drift region, 16-N+ substrate, 17-P+ collector region, 18-collector region metal, 19-non-ohmic contact. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with specific drawings and embodiments.

[0025] In order to reduce the stress during the processing of micro-groove power devices, avoid contact hole lithography offset caused by warping, and obtain a threshold voltage and saturation voltage drop with high consistency, taking the first conductivity type as N type as an example, the present invention provides a micro-groove power device with low warping stress, specifically, the micro-groove power device includes: A semiconductor substrate having an N conductivity type; The active region includes a plurality of micro-groove cells distributed in parallel, wherein any micro-groove cell includes a first type of groove unit and a second type of groove unit; The first type trench unit includes at least two first type trenches 1, the second type trench unit includes at least two second type trenches 2, and the first type trench 1 is located between the second type trenches 2; A first-type conductive polysilicon 11 and an in-groove insulating dielectric layer 8 are provided in each first-type trench 1, wherein the first-type conductive polysilicon 11 is insulated and isolated from the inner wall of the first-type trench 1, the in-groove insulating dielectric layer 8 is distributed in the notch region of the first-type trench 1, the first-type conductive polysilicon 11 is located between the in-groove insulating dielectric layer 8 and the bottom of the first-type trench 1, and the in-groove insulating dielectric layer 8 is in contact with the first-type conductive polysilicon 11; A second type of conductive polysilicon 12 is disposed in each second type of trench 2, wherein the second type of conductive polysilicon 12 is insulated and isolated from the inner wall of the second type of trench 2; The second type of conductive polysilicon 12 is in ohmic contact with the front first electrode metal 7 located above the front surface of the semiconductor substrate. The first type of conductive polysilicon 11 is electrically connected to the front second electrode metal located above the front side of the semiconductor substrate, and the second type of conductive polysilicon 11 is insulated and isolated from the front first electrode metal 7 by the insulating dielectric layer 8 in the trench.

[0026] Specifically, the conductivity type of the semiconductor substrate is N-type, and the semiconductor substrate can be made of existing commonly used materials, such as silicon and other materials. The material of the semiconductor substrate can be selected according to actual needs. Figure 2 and Figure 3 An embodiment of a semiconductor substrate is shown in the figure. As can be seen from the figure, the semiconductor substrate includes an N+ substrate 16 and an N-type drift region 15 located on the N+ substrate 16. Generally, the doping concentration of the N-type drift region 15 is lower than the doping concentration of the N+ substrate 16. The corresponding surface of the N-type drift region 15 can form the front side of the semiconductor substrate, and the corresponding surface of the N+ substrate 16 can form the back side of the semiconductor substrate. It can be understood that the front side of the semiconductor substrate and the back side of the semiconductor substrate are two corresponding surfaces of the semiconductor substrate.

[0027] In order to form a micro-groove power device, an active region should generally be set in the central region of the semiconductor substrate, and the functional region of the micro-groove power device can be formed by using the active region, wherein the active region generally includes a number of micro-groove cells distributed in parallel, and the way in which the micro-groove cells are connected in parallel can be consistent with the existing methods, such as forming a parallel distribution state through the following front first electrode metal 7. The micro-groove cells in the active region generally adopt the same structure. In one embodiment of the present invention, the micro-groove cells may include a first type of groove unit and a second type of groove unit.

[0028] In a specific implementation, the first type trench unit includes at least two first type trenches 1, and the second type trench unit includes at least two second type trenches 2, wherein all the first type trenches 1 should be located between the second type trenches 2. Figure 1 , an embodiment is shown in which the first type trench unit includes two first type trenches 1, and the second type trench unit also includes two second type trenches 2. In this case, the two first type trenches 1 are located between the two second type trenches 2. As can be seen from the figure, the first type trench 1 and the second type trench 2 are both in the shape of long strips, and the first type trench 1 and the second type trench 2 are parallel to each other.

[0029] Specifically, a first type of conductive polysilicon 11 and an insulating dielectric layer 8 in the trench are disposed in the first type of trench 1, wherein the length of the first type of conductive polysilicon 11 is smaller than the depth of the first type of trench 1. Figure 2 and Figure 3 As shown in the figure, the first type of conductive polysilicon 11 is located in the central part of the first type of trench 1, the insulating dielectric layer 8 in the trench fills the notch area of ​​the first type of trench 1, the insulating dielectric layer 8 in the trench is in contact with the first type of conductive polysilicon 11, and the insulating dielectric layer 8 in the trench can be an oxide layer, or a commonly used interlayer dielectric material such as silicon nitride or BPSG.

[0030] It should be noted that the high stress of the trench power device includes the stress contributed by the conductive polysilicon filled in the trench. In one embodiment of the present invention, in the first type of trench 1, the insulating dielectric layer 8 in the trench covers the first type of conductive polysilicon 11. Since the material of the insulating dielectric layer 8 in the trench is different from that of the first type of conductive polysilicon 11, the thermal expansion coefficients are different. At this time, the material properties such as the thermal expansion coefficients of different materials can be used to reduce the stress, thereby reducing the risk of fragmentation in the processing of the micro-groove power device of the present invention.

[0031] Figure 2 and Figure 3In the embodiment, a gate oxide layer 10 is arranged in the first type of trench 1, and the gate oxide layer 10 covers the bottom wall and the side wall of the first type of trench 1. When the first type of conductive polysilicon 11 is filled in the first type of trench 1, the gate oxide layer 10 can be used to achieve insulation isolation from the inner wall of the first type of trench 1. The gate oxide layer 10 can generally be a silicon dioxide layer.

[0032] A second type of conductive polysilicon 12 is arranged in the second type of groove 2, and the second type of conductive polysilicon 12 should also be insulated and isolated from the inner wall of the second type of groove 2. For example, a second type of trench insulating oxide layer 13 can be arranged on the inner wall of the second type of groove 2. The second type of trench insulating oxide layer 13 is generally a silicon dioxide layer. When the second type of conductive polysilicon 12 is filled in the second type of groove 2, the second type of trench insulating oxide layer 13 can be used to achieve insulation isolation from the inner wall of the second type of groove 2.

[0033] In a specific implementation, the distribution state of the second type of conductive polysilicon 12 in the second type of trench 2 may be consistent with the distribution state of the first type of conductive polysilicon 11 in the first type of trench 1, that is, the second type of conductive polysilicon 12 is distributed in the middle and lower part of the second type of trench 2, and an insulating dielectric layer covering the second type of conductive polysilicon 12 is provided in the second type of trench 2. Of course, the distribution state of the second type of conductive polysilicon 12 in the second type of trench 2 may also be different from the distribution state of the first type of conductive polysilicon 11 in the first type of trench 1. Figure 2 and Figure 3 An embodiment with a different distribution state is shown in the figure. Specifically, the second type of conductive polysilicon 12 fills the second type of trench 2, and the second type of conductive polysilicon 12 is insulated and isolated from the inner wall of the second type of trench 2 by the second type of trench insulating oxide layer 13. In the figure, the upper end of the second type of conductive polysilicon 12 can be aligned with the notch of the second type of trench 2.

[0034] A front electrode unit should generally be arranged above the front side of the semiconductor substrate. Specifically, the front first electrode metal 7 is in ohmic contact with the second type of conductive polysilicon 12, and the front second electrode metal is electrically connected to the first type of conductive polysilicon 11. At this time, the front first electrode metal 7 is used to form the front first electrode in the front electrode unit, and the front second electrode metal is used to form the front second electrode in the front electrode unit. The corresponding types of the front first electrode and the front second electrode are related to the type of the power device. For example, when the power device is a MOSFET type device, the front first electrode is the source electrode of the power device, and the front second electrode is the gate electrode of the power device; and when the power device is an IGBT type device, the front first electrode is the emitter of the power device, and the front second electrode is the gate electrode of the power device. The front first electrode metal 7 and the front second electrode metal can be made of existing commonly used metal materials. The specific type of the metal material used can be selected according to needs, which will not be repeated here.

[0035] In one embodiment of the present invention, the front first electrode metal 7 is in ohmic contact with the second type conductive polysilicon 12 through a first electrode contact hole, wherein the first electrode contact hole is formed by self-alignment.

[0036] Figure 2 and Figure 3 FIG. 4 shows an embodiment in which the front first electrode metal 7 makes ohmic contact with the second type conductive polysilicon 12 through the first electrode contact hole. Figure 2 and Figure 3 The distribution of the front second electrode metal on the front side of the semiconductor substrate is not shown in the figure. Since the insulating dielectric layer 8 in the groove covers the first type of conductive polysilicon 11, the insulating dielectric layer 8 in the groove can be used to achieve insulation isolation between the front first electrode metal 7 and the first type of conductive polysilicon 11. At this time, the first electrode contact hole can be formed by opening the contact hole in general. The first electrode contact hole can make the micro-groove cell and the semiconductor substrate surface corresponding to the surface in an exposed state. Since the general opening method is adopted, the step of photolithography alignment can be omitted, and the problem of photolithography offset caused by the reduction of the cell size spacing can be avoided, which reduces the process difficulty. It can be seen that the contact hole photolithography offset caused by warping can be avoided, and a high consistency threshold voltage and saturation voltage drop can be obtained.

[0037] Depend on Figure 2 and Figure 3 It can be seen that after the first electrode contact hole is formed by the general opening method, after the front first electrode metal 7 is prepared, the front first electrode metal 7 can directly contact the second type of conductive polysilicon 12 and form an ohmic contact state. Of course, the front first electrode metal 7 will also contact the insulating dielectric layer 8 in the groove. From the above description, it can be seen that the insulation state between the front first electrode metal 7 and the first type of conductive polysilicon 11 can still be maintained. Generally, when the front second electrode metal is electrically connected to the first type of conductive polysilicon 11, the first type of conductive polysilicon 11 should be led out by a lead-out method. Thereafter, the electrical connection with the first type of conductive polysilicon 11 can be achieved. The method of forming an electrical connection between the front second electrode metal and the first type of conductive polysilicon 11 can be consistent with the existing technology and will not be repeated here.

[0038] In one embodiment of the present invention, the first type trench 1 and the second type trench 2 extend vertically from the front side of the semiconductor substrate to the back side of the semiconductor substrate, and both the first type trench 1 and the second type trench 2 penetrate the P-type base region in the active region, wherein: The corresponding bottoms of the first type trench 1 and the second type trench 2 are both located below the P-type base region; The bottom surface of the P-type base region is located below the contact interface between the insulating dielectric layer 8 and the first type of conductive polysilicon 11 in the trench.

[0039] In a specific implementation, the first type of trenches 1 and the second type of trenches 2 are distributed in the same manner in the semiconductor substrate. Figure 2 and Figure 3 , an embodiment is shown in which the first type trench 1 and the second type trench 2 are both distributed in the N-type drift region 15, that is, the corresponding trench depths of the first type trench 1 and the second type trench 2 are both less than the thickness of the N-type drift region 15. Specifically, the sizes of the first type trench 1 and the second type trench 2 can be selected as needed, such as the corresponding trench depths of the first type trench 1 and the second type trench 2 are 5μm~6μm; the corresponding trench widths of the first type trench 1 and the second type trench 2 are 0.5μm~1μm. In addition, the corresponding sizes of the first type trench 1 and the second type trench 2 can be the same, of course, they can also be different, which can be selected according to specific needs.

[0040] For power devices, a P-type base region should also be set in the active region, wherein the P-type base region traverses the active region, that is, the P-type base region is distributed throughout the active region, but the corresponding bottoms of the first type trench 1 and the second type trench 2 are both located below the P-type base region, that is, the junction depth of the P-type base region is smaller than the corresponding trench depths of the first type trench 1 and the second type trench 2. In addition, the P-type base region should be in contact with the first type trench 1 and the second type trench 2, and the first type trench 1 and the second type trench 2 form a distribution state that runs through the P-type base region.

[0041] The bottom surface of the P-type base region specifically refers to the surface of the P-type base region adjacent to the N+ substrate 16. In order not to affect the formation of the micro-groove type cell, the bottom surface of the P-type substrate should be located below the contact interface between the insulating dielectric layer 8 in the groove and the first type of conductive polysilicon 11. Considering factors such as the process, the distance between the contact interface between the insulating dielectric layer 8 in the groove and the first type of conductive polysilicon 11 and the front surface of the semiconductor substrate can be 1μm~1.5μm.

[0042] In one embodiment of the present invention, for two adjacent first-type trenches 1, a plurality of N+ emitter regions 5 and a plurality of P+ first heavily doped regions 6 are arranged in the P-type base region between the first-type trenches 1, wherein: Along the length direction of the first type trench 1, the N+ emitter region 5 and the P+ first heavily doped region 6 are alternately distributed, and the N+ emitter region 5 and the P+ first heavily doped region 6 are separated by the P-type base region; The N+ emitter region 5 and the P+ first heavily doped region 6 are in contact with the outer wall of the corresponding first type trench 1; The N+ emitter region 5 overlaps with the first type of conductive polysilicon 11 in the first type of trench 1 it contacts; The N+ emitter region 5 and the P+ first heavily doped region 6 are in ohmic contact with the front first electrode metal 7 .

[0043] From the above description, it can be seen that the micro-groove type cell includes a plurality of first-type grooves 1 and a plurality of second-type grooves 2. Therefore, the first-type grooves 1 and the second-type grooves 2 can be used to divide the P-type base region. Figure 2 and Figure 3 In the figure, the corresponding P-type base region can be divided into a second P-type base region 9 between the grooves through two adjacent first-type grooves 1, and the corresponding P-type base region can be divided into a first P-type base region 4 between the grooves through the first-type groove 1 and the adjacent second-type groove 2. It can be understood that the first P-type base region 4 between the grooves and the second P-type base region 9 between the grooves have the same junction depth and doping state.

[0044] In order to form a conductive channel, an N+ emitter region 5 should be set at least in the second P-type base region 9 between the grooves, wherein the N+ emitter region 5 should extend vertically downward from the front side of the semiconductor substrate, and the N+ emitter region 5 contacts the outer side walls of the first type of grooves 1 on both sides, and overlaps with the first type of conductive polysilicon 11 in the first type of grooves 1 on both sides, wherein the N+ emitter region 5 overlaps with the first type of conductive polysilicon 11, specifically when the N+ emitter region 5 is projected in the direction of the first type of conductive polysilicon 11, the projection position of the N+ emitter region 5 should at least intersect with the first type of conductive polysilicon 11, because the N+ emitter region 5 is in ohmic contact with the first electrode metal 7 on the front side, at this time, the N+ emitter region 5 and the first electrode metal 7 on the front side can be used to form a conductive channel on the outer side wall of the first type of groove 1.

[0045] The area of ​​the formed conductive channel is located below the notch of the first type of groove 1. Therefore, compared with the prior art, the length of the conductive channel can be shortened, that is, a short channel is formed. At this time, based on the characteristics of the short channel, the saturation voltage drop and turn-on loss can be effectively reduced.

[0046] In order to effectively adjust the saturation current and prevent latch-up, a P+ first heavily doped region 6 should also be provided in the second P-type base region 9 between the grooves, and the P+ first heavily doped region 6 contacts the outer wall of the corresponding first-type groove 1; generally, along the length direction of the first-type groove 1, the N+ emitter region 5 and the P+ first heavily doped region 6 should be alternately distributed, and the N+ emitter region 5 and the P+ first heavily doped region 6 should be separated by the P-type base region, that is, the N+ emitter region 5 and the P+ first heavily doped region 6 in the second P-type base region 9 between the grooves are not in contact. In addition, the corresponding distribution and spacing distance of the N+ emitter region 5 and the P+ first heavily doped region 6 should be configured, specifically based on the ability to adjust the saturation current, prevent latch-up, and prevent the safe operating area (SOA) from narrowing.

[0047] In specific implementation, the P+ first heavily doped region 6 should be in ohmic contact with the front first electrode metal 7. In addition, the junction depth of the P+ first heavily doped region 6 can be 0.3μm~2μm. In addition, in order to form an effective conductive channel, the distance between the bottom of the N+ emitter region 5 and the contact interface between the insulating dielectric layer 8 in the groove and the first type of conductive polysilicon 11 is at least 0.2μm. After determining the contact interface between the insulating dielectric layer 8 in the groove and the first type of conductive polysilicon 11, the bottom of the N+ emitter region 5 should be at least 0.2μm below the contact cross section, so as to configure the junction depth of the N+ emitter region 5.

[0048] like Figure 2 and Figure 3 In the figure, the corresponding junction depths of the P+ first heavily doped region 6 and the N+ emitter region 5 are smaller than the corresponding junction depths of the second P-type base region 9 between the grooves. Therefore, after the P+ first heavily doped region 6 and the N+ emitter region 5 are prepared in the second P-type base region 9 between the grooves, the N+ emitter region 5 and the P+ first heavily doped region 6 should be in contact with the second P-type base region 9 between the grooves, and the isolation between the N+ emitter region 4 and the P+ first heavily doped region 6 is achieved through the second P-type base region 9 between the grooves.

[0049] In one embodiment of the present invention, a plurality of P+ second heavily doped regions 3 and non-ohmic contact regions 19 are arranged alternately between the first type trench 1 and the adjacent second type trench 2, and the P+ second heavily doped region 3 is located in the P-type base region between the first type trench 1 and the adjacent second type trench 2, wherein: The P+ second heavily doped region 3 contacts the corresponding outer walls of the first type trench 1 and the second type trench 2 on both sides. The bottom of the P+ second heavily doped region 3 is located below the contact interface between the insulating dielectric layer 8 and the first type of conductive polysilicon 11 in the trench; The P+ second heavily doped region 3 is in ohmic contact with the front first electrode metal 7. The front first electrode metal 7 is in non-ohmic contact with the non-ohmic contact region 19 .

[0050] It can be seen from the above description that the P-type base region between the first type of trench 1 and the second type of trench 2 is divided to form the first P-type base region 4 between the grooves. Thereafter, a P+ second heavily doped region 3 can be set in the first P-type base region 4 between the grooves, and an ohmic contact region can be formed by using the P+ second heavily doped region 3, while a non-ohmic contact region 19 can be formed in the region of the first P-type base region 4 between the grooves where the P+ second heavily doped region 3 is not set. It can be understood that the doping concentration of the P+ second heavily doped region 3 is greater than the doping concentration of the first P-type base region 4 between the grooves, and the doping concentration of the non-ohmic contact region 19 is lower than the doping concentration of the P+ second heavily doped region 3, that is, the P+ second heavily doped region 3 and the non-ohmic contact region 19 can be formed by adjusting the doping concentration of the first P-type base region 4 between the grooves.

[0051] In a specific implementation, the junction depth of the P+ second heavily doped region 3 is 0.3μm~2μm, and the P+ second heavily doped region 3 should contact the outer wall of the first type of trench 1 and the outer wall of the second type of trench 2 corresponding to both sides. In addition, along the corresponding length direction of the first type of trench 1 and the second type of trench 2, the P+ second heavily doped region 3 and the non-ohmic contact region 19 are also alternately distributed, but the non-ohmic contact region 19 is in contact with the P+ second heavily doped region 3.

[0052] When the front first electrode metal 7 is filled in the first electrode contact hole, the front first electrode metal 7 is in ohmic contact with the P+ second heavily doped region 3, and non-ohmic contact is formed between the front first electrode metal 7 and the non-ohmic contact region 19. It should be noted that the non-ohmic contact specifically refers to a certain contact potential barrier. It can be seen that the contact between the front first electrode metal 7 and the non-ohmic contact region 19 can form a hole blocking layer. Compared with the ohmic contact area of ​​the P+ second heavily doped region 3, the non-ohmic contact region 19 can prevent the extraction of holes to a certain extent. Therefore, after the ohmic contact and non-ohmic contact states are formed between the first type of groove 1 and the second type of groove 2, the hole storage during the opening process and the hole extraction during the closing process of the power device can be modulated to achieve the effect of optimizing the compromise between the on-state voltage drop (Vce) and the off-state loss (Eoff).

[0053] In one embodiment of the present invention, a carrier storage layer 14 is further provided in the active region, wherein: The carrier storage layer 14 traverses the active region and is located below the P-type base region, and the carrier storage layer 14 is adjacent to the second conductivity type base region; The carrier storage layer 14 contacts the corresponding outer walls of the first type trench 1 and the second type trench 2 , and the corresponding bottoms of the first type trench 1 and the second type trench 2 are both located below the carrier storage layer 14 .

[0054] Specifically, the conductivity type of the carrier storage layer 14 is N-type, and the carrier storage layer 14 generally also traverses the active region. The carrier storage layer 14 should be located below the P-type base region, such as Figure 2 and Figure 3 In the embodiment, the carrier storage layer 14 is located below the second P-type base region 9 between the grooves and the first P-type base region 4 between the grooves, and the carrier storage layer 14 is located adjacent to the second P-type base region 9 between the grooves and the first P-type base region 4 between the grooves. The carrier storage layer 14 can realize the ability of carrier storage, and the principle of realizing carrier storage by using the carrier storage layer 14 can be consistent with the prior art, which will not be repeated here.

[0055] It should be noted that when a carrier storage layer 14 is set in the drift region 15 and a short channel is formed based on the above-mentioned N+ emitter region 5, the saturation voltage drop and turn-on loss can be effectively reduced without improving the thermal process of the P-type base region and the carrier storage layer 14.

[0056] The above introduces the front structure of the power device on the front side of the semiconductor substrate. In order to form the required power device, a back electrode structure should also be set on the back side of the semiconductor substrate, such as setting a back electrode structure on the back side, so as to utilize the back electrode structure to configure the power device as an IGBT type power device or a MOSFET type power device. Figure 2 and Figure 3 An embodiment of the back electrode structure is shown in FIG. Figure 1 In the embodiment, the back electrode structure includes a P+ collector region 17 and a collector region metal 18, wherein the P+ collector region 17 covers the N+ substrate 16, that is, it is arranged on the back side of the semiconductor substrate, and the collector region metal 18 is in ohmic contact with the P+ collector region 17. At this time, the power device formed is an IGBT (Insulated Gate Bipolar Transistor) type power device. The method of forming a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) type power device using the back electrode structure can be consistent with the prior art and will not be repeated here.

Claims

1. A micro-groove power device with low warpage stress, characterized in that: The micro-trench power device comprises: A semiconductor substrate having a first conductivity type; The active region includes a plurality of micro-groove cells distributed in parallel, wherein any micro-groove cell includes a first type of groove unit and a second type of groove unit; The first type trench unit includes at least two first type trenches, the second type trench unit includes at least two second type trenches, and the first type trench is located between the second type trenches; A first type of conductive polysilicon and an insulating dielectric layer in the trench are arranged in each first type of trench, wherein the first type of conductive polysilicon is insulated and isolated from the inner wall of the first type of trench, the insulating dielectric layer in the trench is distributed in the notch area of ​​the first type of trench, the first type of conductive polysilicon is located between the insulating dielectric layer in the trench and the bottom of the first type of trench, and the insulating dielectric layer in the trench is in contact with the first type of conductive polysilicon; Disposing a second type of conductive polysilicon in each second type of trench, wherein the second type of conductive polysilicon is insulated and isolated from an inner wall of the second type of trench; The second type of conductive polysilicon is in ohmic contact with the front first electrode metal located above the front side of the semiconductor substrate. The first type of conductive polysilicon is electrically connected to the front second electrode metal located above the front side of the semiconductor substrate, and the second type of conductive polysilicon is insulated and isolated from the front first electrode metal by the insulating dielectric layer in the trench.

2. The micro-groove power device with low warpage stress according to claim 1, characterized in that: The first type of trench and the second type of trench extend vertically from the front side of the semiconductor substrate to the back side of the semiconductor substrate, and both the first type of trench and the second type of trench penetrate the second conductive type base region distributed in the active region, wherein: The corresponding bottoms of the first type trenches and the second type trenches are both located below the second conductive type base region; The bottom surface of the second conductive type base region is located below the contact interface between the insulating dielectric layer in the trench and the first conductive polysilicon.

3. The micro-groove power device with low warpage stress according to claim 2, characterized in that: For two adjacent first-type trenches, a plurality of first-conductivity-type emitter regions and a plurality of second-conductivity-type first heavily doped regions are arranged in the second-conductivity-type base region between the first-type trenches, wherein: Along the length direction of the first type trench, the first conductivity type emitter region and the second conductivity type first heavily doped region are alternately distributed, and the first conductivity type emitter region and the second conductivity type first heavily doped region are separated by the second conductivity type base region; The first conductive type emitter region and the second conductive type first heavily doped region are in contact with the outer wall of the corresponding first type trench; The first conductive type emitter region overlaps with the first conductive polysilicon in the first type trench it contacts; The first conductive type emitter region and the second conductive type first heavily doped region are in ohmic contact with the front first electrode metal.

4. The micro-groove power device with low warpage stress according to claim 3, characterized in that: The distance between the contact interface between the insulating dielectric layer and the first type of conductive polysilicon in the trench and the front surface of the semiconductor substrate is 1μm~1.5μm, and the distance between the bottom of the first conductive type emitter region and the contact interface between the insulating dielectric layer and the first type of conductive polysilicon in the trench is at least 0.2μm.

5. The micro-groove power device with low warpage stress according to claim 2, characterized in that: A plurality of second conductive type second heavily doped regions and non-ohmic contact regions are arranged alternately between the first type trench and the adjacent second type trench, and the second conductive type second heavily doped region is located in the second conductive type base region between the first type trench and the adjacent second type trench, wherein: The second heavily doped region of the second conductivity type contacts the corresponding outer walls of the first type trench and the second type trench on both sides. The bottom of the second heavily doped region of the second conductivity type is located below the contact interface between the insulating dielectric layer in the trench and the first conductive polysilicon; The second heavily doped region of the second conductivity type is in ohmic contact with the first front electrode metal. The front first electrode metal is in non-ohmic contact with the non-ohmic contact area.

6. The micro-groove power device with low warpage stress according to claim 5, characterized in that: The junction depth of the second conductive type second heavily doped region is 0.3 μm to 2 μm.

7. The micro-groove power device with low warpage stress according to claim 1, characterized in that: The second type of conductive polysilicon fills up the second type of trench, and the second type of conductive polysilicon is insulated and isolated from the inner wall of the second type of trench by the second type of trench insulating oxide layer.

8. The micro-groove type power device with low warpage stress according to claim 2, characterized in that A carrier storage layer is also provided in the active area, wherein: The carrier storage layer traverses the active region and is located below the second conductivity type base region, and the carrier storage layer is adjacent to the second conductivity type base region; The carrier storage layer contacts the corresponding outer walls of the first type trench and the second type trench, and the corresponding groove bottoms of the first type trench and the second type trench are both located below the carrier storage layer.

9. The micro-trench power device with low warpage stress according to any one of claims 1 to 8, characterized in that: The front first electrode metal is in ohmic contact with the second type conductive polysilicon through a first electrode contact hole, wherein the first electrode contact hole is formed by self-alignment.

10. The micro-trench power device with low warpage stress according to any one of claims 1 to 8, characterized in that the first type The corresponding groove depth of the groove and the second type groove is 5μm~6μm; The corresponding groove widths of the first type groove and the second type groove are 0.5μm~1μm.

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