Semiconductor device, chip, and electronic apparatus

Abstract

The invention provides a semiconductor device, a chip and electronic equipment, relates to the technical field of semiconductors, in particular to a gallium nitride power device, and aims to solve the problem that a semiconductor device with a reverse blocking characteristic is high in turn-on voltage. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a grid electrode, a source electrode, a drain electrode and a functional layer, the channel layer and the barrier layer are stacked on the substrate, and the barrier layer is far away from the substrate compared with the channel layer; the gate is located at one side of the barrier layer away from the substrate; the source electrode and the drain electrode are located on the side, away from the substrate, of the barrier layer and located on the two opposite sides of the grid electrode in the first direction, and the first direction is the arrangement direction of the source electrode, the grid electrode and the drain electrode; the functional layer is located on the side, away from the substrate, of the barrier layer, and the functional layer and the drain are located on the same side of the gate; the drain at least covers the side surface of the functional layer close to the gate and the side surface of the functional layer away from the gate, and the drain contacts with the barrier layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, specifically to the field of gallium nitride power device technology, and especially to a semiconductor device, chip and electronic equipment. Background Art

[0002] Gallium nitride (GaN) materials, as third-generation semiconductor materials, are widely used in various fields due to their wide bandgap, high power density, stable chemical properties, etc. Semiconductor devices, namely gallium nitride high-electron-mobility transistors (HEMTs), have the advantages of small chip area, low switching loss, fast operating speed, high conversion efficiency, and high power density. In the field of power electronics, they can further improve the efficiency of power electronic systems, reduce their size, and reduce manufacturing costs.

[0003] First, semiconductor devices with enhanced characteristics are widely used in the switching field. With the optimization of design and process, their forward blocking characteristics are continuously improved. However, in some application scenarios, such as matrix converters or resonant converters, semiconductor devices are also required to have good reverse blocking capabilities to achieve power reverse protection and bidirectional conversion.

[0004] Second, as a natural bidirectional conducting device, semiconductor devices perform poorly in the following application scenarios. For example, when signal oscillation or erroneous signals occur in the system and cause it to be in the reverse direction, the device will conduct in the reverse direction, thus affecting the safety and stability of the system. In systems with high requirements for unidirectional conduction, it may even cause catastrophic effects.

[0005] Therefore, an improved semiconductor device is desired to solve the above problems. Summary of the invention

[0006] Embodiments of the present disclosure provide a semiconductor device, a chip, and an electronic device, which are intended to solve the problem of high turn-on voltage and large on-resistance of a semiconductor device with reverse blocking characteristics.

[0007] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a semiconductor device is provided, comprising a substrate, a channel layer and a barrier layer stacked on the substrate, a gate, a source, a drain and a functional layer. The barrier layer is farther away from the substrate than the channel layer. The gate is located on the side of the barrier layer away from the substrate. The source and the drain are located on the side of the barrier layer away from the substrate, and are respectively located on opposite sides of the gate in a first direction, wherein the first direction is the arrangement direction of the source, the gate and the drain. The functional layer is located on the side of the barrier layer away from the substrate, and the functional layer and the drain are located on the same side of the gate. The drain at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, and the drain is in contact with the barrier layer.

[0008] When a reverse voltage is applied to the semiconductor device, the two-dimensional electron gas under the functional layer is further depleted, pinching off the drain path, thereby achieving reverse blocking of the semiconductor device. If the semiconductor device is in a forward conduction state, the drain at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, the drain can short-circuit the functional layer, reduce the turn-on voltage and on-resistance of the semiconductor device, and thus significantly reduce the on-state power consumption of the semiconductor device.

[0009] In a feasible embodiment, the material of the functional layer includes p-type gallium nitride.

[0010] In a possible embodiment, the functional layer is in contact with the barrier layer.

[0011] Using p-type gallium nitride as the material of the functional layer can deplete the two-dimensional electron gas below the functional layer to form an enhanced structure, thereby achieving reverse blocking of the semiconductor device. At the same time, the drain at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, and the two are electrically connected, which can short-circuit the functional layer when the semiconductor device is forward-conducted, reducing the turn-on voltage of the semiconductor device to approximately 0V.

[0012] In a feasible embodiment, the barrier layer further includes: a first groove, the first groove is located on a side of the barrier layer away from the substrate; at least a portion of the functional layer is located in the first groove.

[0013] Thinning the barrier layer below the functional layer can deplete the two-dimensional electron gas below it to form an enhanced structure, thereby achieving reverse blocking of the semiconductor device. At the same time, the drain at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, and the two are electrically connected, which can short-circuit the functional layer when the semiconductor device is forward-conducted, reducing the turn-on voltage of the semiconductor device to approximately 0V.

[0014] In a feasible embodiment, the method further includes: a first insulating layer, at least a portion of which is located in the first groove and between the functional layer and the barrier layer.

[0015] Adding a first insulating layer between the functional layer and the barrier layer can further reduce the leakage current of the functional layer, thereby reducing the conduction loss of the semiconductor device. At the same time, the drain electrode at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, and the two are electrically connected, which can short-circuit the functional layer when the semiconductor device is forward-conducted, reducing the turn-on voltage of the semiconductor device to approximately 0V.

[0016] In a feasible embodiment, the drain electrode covers the first insulating layer.

[0017] In a feasible embodiment, the barrier layer further includes: a first ion implantation region, wherein the first ion implantation region overlaps with the functional layer in a thickness direction of the substrate.

[0018] By injecting ions, such as fluorine ions, into the barrier layer, the two-dimensional electrons below it can be depleted to form an enhanced structure, thereby achieving reverse blocking of the semiconductor device. At the same time, the drain electrode at least covers the side of the functional layer close to the gate and the side of the functional layer away from the gate, and the two are electrically connected, which can short-circuit the functional layer when the semiconductor device is forward-conducted, reducing the turn-on voltage of the semiconductor device to approximately 0V.

[0019] In a feasible embodiment, the drain includes a first portion covering the side of the functional layer close to the gate; along the first direction, the distance between the surface of the first portion of the drain close to the functional layer and the surface of the first portion of the drain away from the functional layer is 10 nanometers to 500 nanometers.

[0020] Setting the distance to 10 nanometers to 500 nanometers can ensure that when current flows through the drain and barrier layer, the series resistance will not increase due to the drain being too thin, thereby increasing the on-resistance of the semiconductor device. On the other hand, the drain will not be too thick, resulting in the depletion region being smaller than the drain thickness during reverse blocking, and the two-dimensional electron gas under the drain cannot be completely cut off, effectively avoiding the situation where the leakage current is large during reverse blocking and cannot meet actual needs.

[0021] In a feasible embodiment, the drain electrode also covers the surface of the functional layer away from the substrate.

[0022] In a feasible embodiment, the drain electrode covers a portion of the functional layer away from the substrate surface, a portion of the functional layer close to the side of the gate, and a portion of the functional layer away from the side of the gate, which are connected into an integrated structure.

[0023] In a feasible embodiment, the reinforcement structure includes at least two sub-reinforcement structures arranged at intervals.

[0024] In a feasible embodiment, the at least two sub-enhancement structures are arranged along a second direction; the second direction is parallel to the substrate and perpendicular to the first direction.

[0025] In a feasible embodiment, in the orthographic projection onto the substrate, the shape of the sub-enhancement structure is selected from any one of a rectangle, a circle, a triangle, a diamond or a star.

[0026] In a feasible embodiment, the method further includes: a cap layer, wherein the cap layer is located between the barrier layer and the gate, and the material of the cap layer includes p-type gallium nitride.

[0027] In a feasible embodiment, the barrier layer further includes a second groove, and the second groove is located on a side of the barrier layer away from the substrate; a portion of the gate is located in the second groove.

[0028] In a feasible embodiment, the method further includes: a second insulating layer, at least a portion of the second insulating layer is located in the second groove and between the gate and the barrier layer.

[0029] In a feasible embodiment, the barrier layer further includes a second ion implantation region, and the second ion implantation region overlaps with the gate in a thickness direction of the substrate.

[0030] In a feasible embodiment, the method further includes: a nucleation layer, wherein the nucleation layer is located between the substrate and the channel layer; and a buffer layer, wherein the buffer layer is located between the nucleation layer and the channel layer.

[0031] On the other hand, a chip is provided, comprising a packaging substrate and the above-mentioned semiconductor device, wherein the packaging substrate is coupled to the semiconductor device.

[0032] On the other hand, an electronic device is provided, comprising a circuit board and the above chip, wherein the chip is arranged on the circuit board.

[0033] It can be understood that the beneficial effects that can be achieved by the chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0035] Figure 1 A structural diagram of an electronic device provided according to some embodiments; Figure 2 A structural diagram of a semiconductor device provided according to some embodiments; Figure 3 A structural diagram of a semiconductor device provided according to some embodiments; Figure 4 A voltage-current curve diagram of a semiconductor device provided according to some embodiments; Figure 5 A structural diagram of a semiconductor device provided according to some embodiments; Figure 6 for Figure 5 A top view of a semiconductor device; Figure 7 is a top view of a semiconductor device provided according to some embodiments; Figure 8 is a top view of a semiconductor device provided according to some embodiments; Fig. 9 is a top view of a semiconductor device provided according to some embodiments; Fig.10 is a top view of a semiconductor device provided according to some embodiments; Fig.11 A voltage-current curve diagram of a semiconductor device provided according to some embodiments; Fig.12 A structural diagram of a semiconductor device provided according to some embodiments; Fig.13 for Fig.12 A top view of a semiconductor device; Figure 14-16 TCDA simulation diagram of a semiconductor device under different reverse voltages provided according to some embodiments; Fig.17 A voltage-current curve diagram of a semiconductor device provided according to some embodiments; Fig.18 A structural diagram of a semiconductor device provided according to some embodiments; Fig.19 A structural diagram of a semiconductor device provided according to some embodiments; Fig. 20 A structural diagram of a semiconductor device provided according to some embodiments. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0037] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0040] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0041] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0042] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0043] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0044] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0046] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0047] The technical terms in the embodiments of the present application are described as follows: Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or a non-intrinsic semiconductor. Among them, the impurities doped into the impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons, where the impurity semiconductor doped with impurities that provide electrons (such as 5-valent phosphorus elements) is also called an electron-type semiconductor or an N (negative) type semiconductor, and the impurity semiconductor doped with impurities that provide holes (such as 3-valent boron elements) is also called a hole-type semiconductor or a P (positive) type semiconductor), which can improve the conductivity of the intrinsic semiconductor. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of the present application, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material, the impurities doped are nitrogen N, boron B, aluminum Al, etc. In addition, when the impurities doped into the impurity semiconductor can compensate for the impurities of the impurity semiconductor, the donor electrons are just enough to fill the acceptor energy level, but cannot provide electrons and holes to the conduction band and the valence band, so that the semiconductor material with a wider bandgap has a resistivity close to that of an insulator. For example, in the embodiment of the present application, the silicon carbide material is doped with a transition metal to achieve impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating properties.

[0048] Unless otherwise defined, all scientific and technological terms used herein have the same meanings as those known to those of ordinary skill in the art. In this application, the words "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner.

[0049] like Figure 1 As shown, Figure 1It is a structural diagram of an electronic device provided according to some embodiments. The disclosed embodiment provides an electronic device 1, which may be a product or component with a power conversion function, such as a power conversion system of an electric vehicle, a charging device of a mobile phone, a power adapter device of a laptop computer, etc. The electronic device 1 may also be different types of user devices or terminal devices such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and a vehicle-mounted device, or may be a power amplification device used in the above electronic devices. It should be understood that the electronic device 1 may also be a device or component with a signal receiving / transmitting function in an amplifier, a modulator, a base station, a radar, etc., and the embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1.

[0050] In the following, some embodiments of the present disclosure are schematically described by taking the electronic device 1 as an electronic device having a power conversion function as an example, but the implementation of the present disclosure is not limited thereto, and any other display device may also be considered as long as the same technical concept is applied.

[0051] exist Figure 1 In the embodiment, the electronic device 1 includes, for example, a chip 10 and a circuit board 20, the chip 10 is disposed on the circuit board 20, and the circuit board 20 is configured to supply power and transmit signals to the chip 10. Exemplarily, the chip 10 includes a semiconductor device and a packaging substrate, and the semiconductor device is coupled to the packaging substrate.

[0052] In a feasible embodiment, before coupling the semiconductor device to the packaging substrate, the method further includes a step of thinning the substrate of the semiconductor device.

[0053] Figure 2 1 is a structural diagram of a semiconductor device according to some embodiments. The semiconductor device 101 includes a substrate 110 , a source 120 , a gate 131 and a drain 140 .

[0054] The base 110 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114 and a barrier layer 115 which are stacked in sequence. The source 120 and the drain 140 are respectively located on one side of the barrier layer 115 away from the channel layer 114, and the gate 131 is located between the source 120 and the drain 140.

[0055] In some feasible embodiments, the substrate 111 may be selected from at least one of silicon, silicon carbide, gallium nitride, sapphire, and diamond.

[0056] The nucleation layer 112 is located on one side of the substrate 111. For example, the nucleation layer 112 may be selected from at least one of aluminum nitride, gallium nitride and aluminum gallium nitride. For example, the nucleation layer 112 may be a nitride film.

[0057] The buffer layer 113 is located on the side of the nucleation layer 112 away from the substrate 111. For example, the buffer layer 113 may be selected from carbon-doped gallium nitride, wherein the carbon concentration may be 10 -19 Up to 10 -20 The buffer layer 113 may also be a superlattice structure composed of at least one selected from aluminum nitride, gallium nitride and aluminum gallium nitride.

[0058] The channel layer 114 is located on a side of the buffer layer 113 away from the nucleation layer 112 . Exemplarily, the channel layer 114 is selected from a non-intentionally doped gallium nitride layer.

[0059] The barrier layer 115 is located on a side of the channel layer 114 away from the buffer layer 113. Exemplarily, the barrier layer 115 is selected from at least one of aluminum nitride and aluminum gallium nitride. It should be understood that the barrier layer 115 can also be selected from other binary, ternary, or quaternary nitrides.

[0060] The channel layer 114 and the barrier layer 115 are in contact to form a heterojunction interface. Due to the spontaneous polarization effect and the piezoelectric polarization effect of the heterojunction interface, there is a large potential well at the heterojunction interface. In this structure, electrons are confined at the interface between the channel layer 114 and the barrier layer 115, thereby inducing a high-density two-dimensional electron gas 301 (2DEG) on the side of the channel layer 114 close to the barrier layer 115.

[0061] In some feasible embodiments, the semiconductor device 101 further includes an insertion layer, which is located between the channel layer 114 and the barrier layer 115 and whose material may be aluminum nitride. The insertion layer can improve the heterojunction interface quality, reduce scattering, and improve electron mobility, and can also improve conduction band discontinuity, thereby increasing the density of the two-dimensional electron gas 301 and improving the performance of the semiconductor device.

[0062] In some feasible embodiments, the semiconductor device 101 further includes a cap layer 132, the cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111, and the gate 131 is located on a side of the cap layer 132 away from the substrate 111. It can be seen that Figure 2 The two-dimensional electron gas 301 below the middle cap layer 132 is depleted. Exemplarily, the material of the cap layer 132 includes p-type gallium nitride.

[0063] Depend on Figure 2It is easy to know that the semiconductor device 101 is a natural bidirectional conductive device. When the device is in the forward direction, the current flows from the drain 140 of the semiconductor device 101 to the source 120. When the device is in the reverse direction, that is, the difference between the gate 131 voltage and the drain 140 voltage is greater than the threshold voltage, and the source 120 voltage is greater than the drain 140 voltage, the semiconductor device 101 will be reversely conductive, and the current will flow from the source 120 of the semiconductor device 101 to the drain 140. In the system using the semiconductor device 101, reverse conduction will have an adverse effect on the stability and safety of the system. In some systems that require unidirectional conductivity, the reverse conduction of the semiconductor device 101 may even bring irreversible destructive effects to the system.

[0064] Figure 3 The semiconductor device 102 includes a substrate 110 , a source electrode 120 , a gate electrode 131 , a drain electrode 140 , and a functional layer 151 .

[0065] The base 110 includes a substrate 111, a nucleation layer 112, a buffer layer 113, a channel layer 114 and a barrier layer 115 stacked in sequence. The source 120 and the drain 140 are respectively located on the side of the barrier layer 115 away from the substrate 111, and the gate 131 is located between the source 120 and the drain 140.

[0066] The functional layer 151 is located between the gate 131 and the drain 140, and the functional layer 151 is connected to the drain 140 through a connection line 153. Exemplarily, the material of the functional layer 151 includes p-type gallium nitride.

[0067] In some feasible embodiments, the semiconductor device 103 further includes a cap layer 132, the cap layer 132 is located on a side of the barrier layer 115 away from the substrate 111, and the gate 131 is located on a side of the cap layer 132 away from the substrate 111. Exemplarily, the material of the cap layer 132 includes p-type gallium nitride. It should be understood that the cap layer 132 and the functional layer 151 are made of the same material and are disposed in the same layer.

[0068] Depend on Figure 3 It is easy to know that the semiconductor device 102 has a certain reverse blocking performance. When the semiconductor device 102 works in the first quadrant, the functional layer 151 is connected to the drain 140, the voltage is positive, the two-dimensional electron gas 301 below the functional layer 151 accumulates, the channel is turned on, and the current flows from the drain 140 to the source 120. When the semiconductor device 102 works in the third quadrant, the functional layer 151 is connected to the drain 140, the potential of the functional layer 151 is lower than the gate 131, the two-dimensional electrons 301 below the functional layer 151 are exhausted, the channel is closed, and the semiconductor device 102 is in a reverse blocking state.

[0069] Figure 4FIG. 4 is a voltage-current curve diagram of a semiconductor device according to some embodiments. Figure 4 In the figure, the horizontal axis is the drain-source voltage V DS , the unit is V, the vertical axis is the drain-source current I DS , the unit is A, the rectangular dotted line is the voltage-current curve of the semiconductor device with Schottky drain, and the circular dotted line is the pGaN-Ohm mixed drain, that is, Figure 3 The voltage-current curve of the semiconductor device 102 is shown in FIG. It should be understood that the semiconductor device with Schottky drain is also a semiconductor device with reverse blocking characteristics. Figure 4 It can be seen that whether it is a semiconductor device with a Schottky drain or Figure 3 The semiconductor devices 102 shown have a relatively large turn-on voltage, and the turn-on voltages of the two devices are close to 1 V. In addition, in addition to the relatively large turn-on voltage, the two devices also have relatively large on-resistances, and thus cannot be used in application scenarios of high-efficiency power conversion.

[0070] Figure 5 is a structural diagram of a semiconductor device provided according to some embodiments, Figure 6 for Figure 5 A top view of a semiconductor device.

[0071] See also Figure 5 and Figure 6 The semiconductor device 103 includes a substrate 110 , a source 120 , a gate 131 , a drain 140 and an enhancement structure 150 .

[0072] The base 110 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , and a barrier layer 115 which are sequentially stacked.

[0073] The source 120 is located on a side of the barrier layer 115 away from the channel layer 114, the enhancement structure 150 includes a functional layer 151, the functional layer 151 is located on a side of the barrier layer 115 away from the substrate 111, and the drain 140 is located on a side of the barrier layer 115 away from the substrate 111 and covers the enhancement structure 150. The drain 140 covers a portion of the functional layer 151 away from the surface of the substrate 111, a portion of the drain 140 covering the side of the functional layer 151 close to the gate 131, and a portion of the drain 140 covering the side of the functional layer 151 away from the gate 131 are connected into an integrated structure. Exemplarily, the drain 140 is also in contact with the barrier layer 115.

[0074] The enhancement structure 150 includes, for example, a functional layer 151 , and the material of the functional layer 151 may include p-type gallium nitride.

[0075] In some feasible embodiments, the drain electrode 140 covers the side surface of the functional layer 151 close to the gate electrode 131 and the side surface away from the gate electrode 130 , and the two are electrically connected.

[0076] In some feasible embodiments, the drain electrode 140 covers the side surface of the functional layer 151 close to the gate 131 and the side surface away from the gate 130 . The drain electrode 140 also covers the surface of the functional layer 151 away from the substrate 111 .

[0077] In some feasible embodiments, the drain 140 includes a first portion of the covering enhancement structure 150 close to the gate 131, and along the first direction x, the distance between the surface of the first portion of the drain 140 close to the enhancement structure 150 and the surface of the first portion of the drain 140 away from the enhancement structure 150 is 10nm-500nm. The first direction x is the arrangement direction of the source 120, the gate 131 and the drain 140. Exemplarily, the material of the functional layer 151 includes p-type gallium nitride.

[0078] Setting the distance to 10 nm to 500 nm can ensure that when current flows through the drain 140 and the barrier layer 115 , the on-resistance does not increase due to the drain 140 being too thin, thereby increasing the on-state voltage of the semiconductor device 103 .

[0079] In some feasible embodiments, the orthographic projection of the reinforcement structure 150 onto the substrate 111 is in the shape of a continuously distributed strip.

[0080] In some feasible embodiments, the reinforcement structure 150 includes at least two sub-reinforcement structures, such as Figure 6 As shown, in Figure 6 In the embodiment, the reinforcing structure 150 includes four sub-reinforcing structures, which are spaced apart, and the distance between two adjacent sub-reinforcing structures is equal. It should be understood that the present disclosure does not limit the number of sub-reinforcing structures or the distance between adjacent sub-reinforcing structures, and the two can be adjusted according to different application scenarios. For example, the reinforcing structure 150 can include 2 sub-reinforcing structures, 3 sub-reinforcing structures, or 5 sub-reinforcing structures.

[0081] In some feasible embodiments, the sub-enhancement structures are arranged at intervals along the second direction y, wherein the second direction y is parallel to the substrate 111 and perpendicular to the first direction x.

[0082] See also Figures 5 to 10 , Figure 7 is a top view of a semiconductor device provided according to some embodiments, Figure 8 is a top view of a semiconductor device provided according to some embodiments, Fig. 9 is a top view of a semiconductor device provided according to some embodiments, Fig.10 FIG. 1 is a top view of a semiconductor device provided according to some embodiments. Figure 6 In the embodiment, the projection of the sub-enhancement structure on the substrate 111 is a rectangle. In some feasible embodiments, the projection of the sub-enhancement structure on the substrate 111 may be as follows: Figure 7The square shown is Figure 8 The rectangle shown is Fig. 9 as shown, or as Fig.10 The star shape shown. Exemplarily, the projection of the sub-enhancement structure on the substrate 111 can also be selected from a triangle or a diamond.

[0083] When the projection of the sub-enhancement structure on the substrate 111 is a figure with a finite number of symmetry axes, a rectangle is taken as an example. The symmetry axes of the rectangle can be Figure 6 In addition to being parallel or perpendicular to the first direction x as shown, it can also be Figure 8 The first direction x is an angle of a preset degree with the first direction x, wherein the first direction is a connection direction of the source 120, the gate 131 and the drain 140.

[0084] Exemplarily, the source electrode 120 and / or the drain electrode 140 is / are selected from at least one of titanium, aluminum, titanium nitride, silicon and gold.

[0085] The gate 131 is located on a side of the barrier layer 115 away from the substrate 111 and between the source 120 and the drain 140 .

[0086] The gate of the semiconductor device is, for example, selected from any one of a p-type gallium nitride gate structure, a recessed gate structure, a recessed metal insulator semiconductor gate structure or an ion implanted gate structure.

[0087] exist Figure 5 The gate of the semiconductor device 103 is selected from a p-type gallium nitride gate structure. The semiconductor device 103 further includes a cap layer 132 , which is located on a side of the barrier layer 115 away from the substrate 111 , and the gate 131 is located on a side of the cap layer 132 away from the barrier layer 115 .

[0088] Exemplarily, the gate 131 can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, and the gate 131 is, for example, selected from any one of palladium, nickel, aluminum, gold, platinum, titanium, and titanium nitride. The material of the cap layer 132 includes p-type gallium nitride. It should be understood that in the semiconductor device 103, the functional layer 151 and the cap layer 132 are made of the same material and are disposed in the same layer.

[0089] If the semiconductor device 103 is in the forward conduction state, the drain 140 short-circuits the enhancement structure 150, and the enhancement structure 150 does not deplete the two-dimensional electron gas 301 thereunder. Therefore, the forward turn-on voltage of the semiconductor device 103 is Figure 2 The semiconductor device 101 is close to Fig.11 , Fig.11 FIG. 4 is a voltage-current curve diagram of a semiconductor device according to some embodiments.

[0090] exist Fig.11 In the figure, the horizontal axis is the drain-source voltage V DS , the unit is V, the vertical axis is the drain-source current I DS , the unit is A, the solid line is Figure 5 The voltage-current curve diagram of the semiconductor device 103 shown in FIG. Figure 3 The voltage-current curve of the semiconductor device 102 is shown in FIG. 1 . It can be seen that the turn-on voltage V ON is approximately equal to 0V, and the turn-on voltage V ON Approximately equal to 1V.

[0091] Figure 5 The semiconductor device 103 shown has the drain 140 covering the enhancement structure 150 , so that when the semiconductor device 103 is in a forward conduction state, the drain 140 can short-circuit the enhancement structure 150 , thereby reducing the turn-on voltage and on-resistance of the semiconductor device 103 , thereby significantly reducing the on-state power consumption of the semiconductor device 103 .

[0092] Fig.12 is a structural diagram of a semiconductor device provided according to some embodiments, Fig.13 for Fig.12 A top view of a semiconductor device. Fig.12 and Fig.13 As shown, if a reverse voltage is applied to the semiconductor device 103 and it is in a reverse blocking state, the two-dimensional electron gas 301 below the enhancement structure 150 is further depleted to form a depletion region 210. Moreover, as the reverse voltage increases, the depletion region 210 continues to expand until the two-dimensional electron gas 301 path below the drain 140 is pinched off, the channel is closed, and the reverse blocking of the semiconductor device 103 is achieved. The distance is set to 10nm to 500nm. On the one hand, the series resistance will not increase due to the drain 140 being too thin, thereby increasing the on-resistance of the semiconductor device 103. On the other hand, the drain 140 will not be too thick, resulting in the depletion region 210 being smaller than the drain thickness during reverse blocking, and the two-dimensional electron gas below the drain 140 cannot be completely pinched off, effectively avoiding the situation where the leakage current is large during reverse blocking and cannot meet actual needs.

[0093] Figure 14-16 TCDA simulation diagram of a semiconductor device under different reverse voltages according to some embodiments. Fig.14 The reverse voltage Vsd = 20 V, and the concentration of the two-dimensional electron gas 301 below the drain 140 is 2.5e18 cm -3 . Fig.15 The reverse voltage Vsd = 50 V, and the concentration of the two-dimensional electron gas 301 below the drain 140 is 2.2e16 cm -3 . Fig.16At the reverse voltage Vsd=100V, the concentration of the two-dimensional electron gas 301 below the drain 140 is 5.3e13cm -3 .Depend on Figure 5 as well as Figure 14-16 It is easy to obtain that, because the drain 140 in the semiconductor device 103 contacts the barrier layer 115 to form an ohmic channel, the two-dimensional electron gas 301 below the drain 140 will not be completely depleted, but its concentration of the two-dimensional electron gas 301 will be significantly reduced, for example, the concentration of the two-dimensional electron gas 301 can be increased from 2.5e18cm -3 Reduced to 5.3e13cm -3 .

[0094] Fig.17 FIG. 1 is a voltage-current curve diagram of a semiconductor device provided according to some embodiments. Fig.17 In the figure, the horizontal axis is the drain-source voltage V DS , the unit is V, the vertical axis is the drain-source current I DS , the unit is A, the dotted line is Figure 5 The voltage-current curve diagram of the semiconductor device 103 shown in FIG. Figure 3 The voltage-current curve of the semiconductor device 102 shown in FIG. 1 is a dot-dash line indicating the upper limit of acceptable leakage current. It can be seen that when the reverse voltage Vsd is greater than or equal to 50V, the reverse leakage current of the semiconductor device 102 is approximately 10 -13 A, the reverse leakage current of the semiconductor device 103 is 10 -9 A-10 -10 A, in practical applications, the reverse blocking leakage current is less than 10% of the on-state conduction current. -6 times is an acceptable range, and the reverse leakage current of the semiconductor device 103 is within 10 -9 A-10 -10 A, less than 10 -7 A of two to three orders of magnitude can be regarded as reverse blocking, and there is still a large margin.

[0095] Fig.18 FIG. 1 is a structural diagram of a semiconductor device according to some embodiments. The semiconductor device 104 includes a substrate 110 , a source 120 , a gate 131 , a drain 140 , and an enhancement structure 150 .

[0096] The base 110 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , and a barrier layer 115 which are sequentially stacked.

[0097] The reinforcement structure 150 includes a functional layer 151 and a first groove 161, wherein the barrier layer 115 includes the first groove 161, and the first groove 161 is located on a side of the barrier layer 115 away from the substrate 111. At least part of the functional layer 151 is located in the first groove 161.

[0098] The source 120 is located on a side of the barrier layer 115 away from the substrate 111, the functional layer 151 is located on a side of the barrier layer 115 away from the substrate 111, and the drain 140 is located on a side of the barrier layer 115 away from the substrate and covers the functional layer 151. The gate 131 is located on a side of the barrier layer 115 away from the substrate 111 and is located between the source 120 and the drain 140.

[0099] The gate of the semiconductor device 104 is, for example, a groove gate structure, and the barrier layer 115 further includes a second groove 162 , and the second groove 162 is located on a side of the barrier layer 115 away from the substrate 111 . At least part of the gate 131 is located in the second groove 162 .

[0100] In some feasible embodiments, the gate 131 and the functional layer 151 are made of the same material and are disposed in the same layer.

[0101] By thinning the barrier layer 115 below the functional layer 151, the two-dimensional electron gas 301 thereunder can be depleted to form an enhancement structure 150, thereby achieving reverse blocking of the semiconductor device 104. At the same time, the drain 140 covers the functional layer 151, thereby short-circuiting the functional layer 151 when the semiconductor device 104 is forward-conducted, thereby reducing the turn-on voltage of the semiconductor device 104 to approximately 0V.

[0102] Fig.19 A semiconductor device 105 is provided according to some embodiments. The semiconductor device 105 includes a substrate 110 , a source 120 , a gate 131 , a drain 140 and an enhancement structure 150 .

[0103] The base 110 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , and a barrier layer 115 which are sequentially stacked.

[0104] The reinforcement structure 150 includes a functional layer 151, a first groove 161 and a first insulating layer 171, wherein the barrier layer 115 includes the first groove 161, and the first groove 161 is located on a side of the barrier layer 115 away from the substrate 111. At least part of the functional layer 151 is located in the first groove 161, and the first insulating layer 171 is located between the barrier layer 115 and the functional layer 151.

[0105] In some feasible embodiments, the drain 140 covers the end surface of the first insulating layer 171 and the side surface of the first insulating layer 171 which is located higher than the barrier layer 115 on the side away from the substrate 111 .

[0106] The source 120 is located on a side of the barrier layer 115 away from the substrate 111, the functional layer 151 is located on a side of the barrier layer 115 away from the channel layer 114, and the drain 140 is located on a side of the barrier layer 115 away from the substrate 111 and covers the functional layer 151. The gate 131 is located on a side of the barrier layer 115 away from the channel layer 114 and is located between the source 120 and the drain 140.

[0107] The gate of the semiconductor device 105 is, for example, selected from a grooved metal insulator semiconductor gate structure, which is composed of Fig.19 It can be seen that the barrier layer 115 further includes a second groove 162 , and the second groove 162 is located on a side of the barrier layer 115 away from the substrate 111 .

[0108] The semiconductor device 105 further includes a second insulating layer 172 . At least a portion of the second insulating layer 172 is located in the second groove 162 . Furthermore, the second insulating layer 172 is located between the gate 131 and the barrier layer 115 .

[0109] In some feasible embodiments, the gate 131 and the functional layer 151 are made of the same material and are disposed in the same layer.

[0110] In some feasible embodiments, the first insulating layer 171 and the second insulating layer 172 are made of the same material and are disposed in the same layer.

[0111] Adding the first insulating layer 171 between the functional layer 151 and the barrier layer 115 can further reduce the leakage current of the functional layer 151 , thereby reducing the conduction loss of the semiconductor device 105 .

[0112] Fig. 20 The semiconductor device 106 includes a substrate 110 , a source 120 , a gate 131 , a drain 140 and an enhancement structure 150 .

[0113] The base 110 includes a substrate 111 , a nucleation layer 112 , a buffer layer 113 , a channel layer 114 , and a barrier layer 115 which are sequentially stacked.

[0114] The enhancement structure 150 includes a functional layer 151 and a first ion implantation region 181 . The barrier layer 115 includes the first ion implantation region 181 , and the first ion implantation region 181 is located below the functional layer 151 .

[0115] The source 120 is located on a side of the barrier layer 115 away from the channel layer 114, the functional layer 151 is located on a side of the barrier layer 115 away from the substrate 111, and the drain 140 is located on a side of the barrier layer 115 away from the substrate 111 and covers the functional layer 151. The gate 131 is located on a side of the barrier layer 115 away from the channel layer 114 and is located between the source 120 and the drain 140.

[0116] The gate of the semiconductor device 106 is, for example, selected from an ion implantation gate structure, such as Fig. 20 As shown, the barrier layer 115 further includes a second ion implantation region 182, and the second ion implantation region 182 is located below the gate 131, that is, the second ion implantation region 182 overlaps with the gate 131 in the thickness direction of the substrate 111. Exemplarily, the first ion implantation region 181 and the second ion implantation region 182 are implemented using fluorine ion implantation technology.

[0117] By injecting ions, such as fluorine ions, into the barrier layer 115, the two-dimensional electrons 301 thereunder may be depleted to form an enhanced structure, thereby achieving reverse blocking of the semiconductor device 106. At the same time, the drain 140 covers the functional layer 151, and can short-circuit the functional layer 151 when the semiconductor device 106 is forward-conducted, thereby reducing the turn-on voltage of the semiconductor device 106 to approximately 0V.

[0118] It should be understood that the gate and enhancement structure of the semiconductor device can be matched in pairs, and the present disclosure does not limit this.

[0119] In a feasible embodiment, a gate of a power gallium nitride device can be selected from Fig.18 The gate, drain and enhancement structures of the semiconductor device 104 shown may be selected from Fig.19 The drain and enhancement structures of the semiconductor device 105 are shown.

[0120] In a feasible embodiment, a gate of a power gallium nitride device can be selected from Fig.19 The gate, drain and enhancement structures of the semiconductor device 105 shown may be selected from Fig. 20 The drain and enhancement structures of the semiconductor device 106 are shown.

[0121] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A channel layer and a barrier layer stacked on the substrate, wherein the barrier layer is farther away from the substrate than the channel layer; A gate, located at a side of the barrier layer away from the substrate; A source electrode and a drain electrode, located on a side of the barrier layer away from the substrate, and respectively located on two opposite sides of the gate electrode in a first direction, wherein the first direction is an arrangement direction of the source electrode, the gate electrode and the drain electrode; A functional layer is located on a side of the barrier layer away from the substrate, and the functional layer and the drain are located on the same side of the gate; The drain electrode at least covers a side surface of the functional layer close to the gate and a side surface of the functional layer far from the gate, and the drain electrode is in contact with the barrier layer.

2. The semiconductor device according to claim 1, wherein: The material of the functional layer includes p-type gallium nitride.

3. The semiconductor device according to claim 2, characterized in that The functional layer is in contact with the barrier layer.

4. The semiconductor device according to claim 1, wherein: The barrier layer further comprises: a first groove, wherein the first groove is located at a side of the barrier layer away from the substrate; At least a portion of the functional layer is located in the first groove.

5. The semiconductor device according to claim 4, characterized in that Also includes: A first insulating layer, at least a portion of which is located in the first groove and between the functional layer and the barrier layer.

6. The semiconductor device according to claim 5, characterized in that The drain electrode covers the first insulating layer.

7. The semiconductor device according to claim 1, wherein: The barrier layer further comprises: A first ion implantation region overlaps the functional layer in a thickness direction of the substrate.

8. The semiconductor device according to claim 1, wherein: The drain electrode includes a first portion covering a side surface of the functional layer close to the gate; Along the first direction, a distance between a surface of the first portion of the drain electrode close to the functional layer and a surface of the first portion of the drain electrode far from the functional layer is 10 nanometers to 500 nanometers.

9. The semiconductor device according to claim 1, wherein: The drain electrode also covers a surface of the functional layer away from the substrate.

10. The semiconductor device according to claim 9, characterized in that The drain electrode covers a portion of the functional layer away from the substrate surface, a portion of the functional layer close to the gate, and a portion of the functional layer away from the gate are connected into an integrated structure.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: include: a reinforcement structure, the reinforcement structure comprising the functional layer; The reinforcing structure includes at least two sub-reinforcing structures arranged at an interval.

12. The semiconductor device according to claim 11, characterized in that The at least two sub-reinforcement structures are arranged along the second direction; The second direction is parallel to the substrate and perpendicular to the first direction.

13. The semiconductor device according to claim 11, characterized in that In an orthographic projection onto the substrate, the sub-enhancement structure has a shape selected from any one of a rectangle, a circle, a triangle, a diamond or a star.

14. The semiconductor device according to any one of claims 1 to 10, characterized in that: Also includes: A cap layer is located between the barrier layer and the gate, and a material of the cap layer includes p-type gallium nitride.

15. The semiconductor device according to any one of claims 1 to 10, characterized in that: The barrier layer further comprises a second groove, wherein the second groove is located at a side of the barrier layer away from the substrate; Part of the gate is located in the second groove.

16. The semiconductor device according to claim 15, characterized in that Also includes: A second insulating layer, at least a portion of which is located in the second groove and between the gate and the barrier layer.

17. The semiconductor device according to any one of claims 1 to 10, characterized in that: The barrier layer further includes a second ion implantation region, and the second ion implantation region overlaps the gate in a thickness direction of the substrate.

18. The semiconductor device according to claim 1, wherein: Also includes: a nucleation layer, the nucleation layer being located between the substrate and the channel layer; A buffer layer is located between the nucleation layer and the channel layer.

19. A chip, characterized in that: The invention comprises a packaging substrate and the semiconductor device according to any one of claims 1 to 18, wherein the packaging substrate is coupled to the semiconductor device.

20. An electronic device, characterized in that: It comprises a circuit board and the chip as claimed in claim 19, wherein the chip is arranged on the circuit board.

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