Semiconductor device and semiconductor structure thereof

Abstract

A semiconductor device and a semiconductor structure thereof, in which the semiconductor device has a first node and a second node and includes a transistor and a diode. The transistor includes a drain terminal, a gate terminal, a source terminal, and a base terminal. The base end is electrically floating and not connected to other end points, and the drain end is electrically connected to the second node. The diode includes an anode terminal and a cathode terminal. The anode terminal is electrically connected to the first node and the cathode terminal is electrically connected to the source terminal.

Description

Technical Field

[0001] The present invention relates to a bootstrap diode and a semiconductor structure thereof, and more particularly to a bootstrap diode and a semiconductor structure thereof which are integrated in a laterally diffused metal oxide semiconductor and have ultra-high breakdown voltage and ultra-low leakage current. Background Art

[0002] Improving energy efficiency is gaining more and more attention, and offline power converters that can reduce power consumption are becoming increasingly important. In response to market changes, high-voltage integrated circuit (HVIC) chips with higher performance and economic benefits have gradually been adopted, giving designers a flexible solution when implementing high-efficiency power converters. High-voltage integrated circuits are integrated circuits that combine high-voltage components and low-voltage logic circuits or analog circuits. They are widely used in brushless DC motor control system applications, such as air conditioners, fans, air purifiers, etc.

[0003] The function of a high-voltage integrated circuit chip (such as a gate driver) is to drive a power metal oxide semiconductor (MOSFET), in which a bootstrap diode and a capacitor are generally used to form a bootstrap circuit, which uses the floating level of the source voltage of the high-side power metal oxide semiconductor as a reference to provide the driving voltage required by the high-voltage integrated circuit.

[0004] However, when the bootstrap diode is forward-conducting, it often has the disadvantage of leaking electricity to the semiconductor substrate. Furthermore, the general bootstrap diode cannot withstand high voltage. When the reverse bias voltage of the bootstrap diode is too high, the bootstrap diode will be broken down and turned on, and the purpose of unidirectional conduction of the bootstrap diode cannot be achieved. Therefore, it is necessary to optimize the leakage current and withstand voltage of the bootstrap diode, and at the same time increase the conduction current when forward-conducting. Summary of the invention

[0005] The present invention proposes a high-voltage bootstrap diode and a semiconductor structure thereof, wherein the diode is integrated into the semiconductor structure of the lateral diffused metal oxide semiconductor by forming a diode with the base end and the source end of the lateral diffused metal oxide semiconductor. In addition, the present invention utilizes the characteristic that the drain end of the lateral diffused metal oxide semiconductor can withstand high voltage to increase the reverse withstand voltage of the bootstrap diode, and forms a plurality of isolation structure layers around the base end to reduce the leakage current leaking to the substrate when the bootstrap diode is forwardly conducted. Furthermore, the drain end of the lateral diffused metal oxide semiconductor also forms a plurality of layers to reduce the surface electric field, so that under the same withstand voltage, the bootstrap diode proposed by the present invention requires a smaller area.

[0006] In view of this, the present invention provides a semiconductor device having a first node and a second node. The semiconductor device includes a transistor and a diode. The transistor includes a drain terminal, a gate terminal, a source terminal and a base terminal, wherein the base terminal is electrically floating and not connected to other terminals, and the drain terminal is electrically connected to the second node. The diode includes an anode terminal and a cathode terminal, wherein the anode terminal is electrically connected to the first node, and the cathode terminal is electrically connected to the source terminal.

[0007] According to an embodiment of the present invention, when the voltage of the first node is greater than the voltage of the second node, the transistor is turned on, wherein the voltage of the first node is equal to the sum of the voltage of the second node and the forward conduction voltage of the diode.

[0008] According to an embodiment of the present invention, when the voltage of the second node is greater than the voltage of the first node, the transistor is not conducting, wherein the drain terminal is used to withstand the voltage of the second node to prevent the semiconductor device from being damaged.

[0009] According to one embodiment of the present invention, the semiconductor device further includes a substrate, a first well region, a second well region, a third well region, a fourth well region, a gate structure, a first doped region, a second doped region and a third doped region. The substrate has a first conductivity type. The first well region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different. The second well region is formed in the first well region and has the second conductivity type. The third well region is formed in the first well region and has the first conductivity type. The fourth well region is formed in the third well region and has the second conductivity type. The gate structure is formed between the first doped region and the second doped region and covers the first well region and the third well region, wherein the gate structure forms the gate terminal. The first doped region is formed in the second well region and has the second conductivity type, wherein the first doped region forms the drain terminal. The second doped region is formed in the third well region and has the second conductivity type, wherein the second doped region forms the source terminal. The third doped region is formed in the fourth well region and has the first conductivity type, wherein the third well region forms the base terminal.

[0010] According to an embodiment of the present invention, the diode is formed between the second doping region and the third doping region, wherein the second doping region further forms the cathode terminal, and the third doping region further forms the anode terminal. The second doping region is connected to the fourth well region.

[0011] According to an embodiment of the present invention, the doping concentration of the fourth well region is lower than the doping concentration of the second well region, and the doping concentration of the fourth well region is higher than the doping concentration of the first well region.

[0012] According to an embodiment of the present invention, the third doped region, the fourth well region, the third well region, the first well region and the substrate form a plurality of isolation structural layers to reduce leakage current. When the diode is turned on, the plurality of isolation structural layers are used to reduce leakage current from the third doped region to the substrate.

[0013] According to one embodiment of the present invention, the semiconductor device further comprises a field oxide layer, a first top doping region and a second top doping region. The field oxide layer is formed in the first well region and is located between the gate structure and the first doping region. The first top doping region is formed below the field oxide layer and has the first conductivity type. The second top doping region is formed in the first top doping region and has the second conductivity type.

[0014] According to an embodiment of the present invention, the second top doped region, the first top doped region, the first well region and the substrate form multiple layers to reduce the surface electric field to increase the breakdown voltage of the drain terminal. The second top doped region is also used to reduce the channel resistance of the transistor.

[0015] According to an embodiment of the present invention, the doping concentration of the first top doping region is not less than the doping concentration of the third well region, and the doping concentration of the second top doping region is not greater than the doping concentration of the second well region.

[0016] The present invention further proposes a semiconductor structure, comprising a substrate, a first well region, a second well region, a third well region, a fourth well region, a gate structure, a first doped region, a second doped region and a third doped region. The substrate has a first conductivity type. The first well region has a second conductivity type, wherein the first conductivity type and the second conductivity type are different. The second well region is formed in the first well region and has the second conductivity type. The third well region is formed in the first well region and has the first conductivity type. The fourth well region is formed in the third well region and has the second conductivity type. The gate structure is formed between the second well region and the third well region. The first doped region is formed in the second well region and has the second conductivity type. The second doped region is formed in the third well region and has the second conductivity type. The third doped region is formed in the fourth well region and has the first conductivity type. The gate structure, the first doped region, the second doped region and the third doped region form a transistor. The second doping region and the third doping region form a diode.

[0017] According to an embodiment of the present invention, the transistor includes a drain terminal, a gate terminal, a source terminal and a base terminal, and the diode includes an anode terminal and a cathode terminal. The gate structure forms the gate terminal, the first doped region forms the drain terminal, the second doped region forms the source terminal, and the third well region forms the base terminal. The second doped region further forms the cathode terminal, and the third doped region further forms the anode terminal.

[0018] According to one embodiment of the present invention, when the voltage of the third doping region is higher than the voltage of the first doping region, the transistor is turned on according to the voltage of the gate terminal, and the voltage of the third doping region is equal to the sum of the voltage of the first doping region and the forward conduction voltage of the diode.

[0019] According to an embodiment of the present invention, when the voltage of the first doping region is higher than the voltage of the third doping region, the transistor is turned off according to the voltage of the gate terminal, and the semiconductor structure withstands the voltage of the first doping region and is not damaged.

[0020] According to an embodiment of the present invention, the third doped region is formed in the fourth well region, and the second doped region is connected to the fourth well region.

[0021] According to an embodiment of the present invention, the doping concentration of the fourth well region is lower than the doping concentration of the second well region, and the doping concentration of the fourth well region is higher than the doping concentration of the first well region.

[0022] According to an embodiment of the present invention, the third doped region, the fourth well region, the third well region, the first well region and the substrate form a plurality of isolation structural layers for reducing leakage current. When the diode is turned on, the plurality of isolation structural layers are used to reduce leakage current from the third doped region to the substrate.

[0023] According to one embodiment of the present invention, the semiconductor structure further includes a field oxide layer, a first top doping region and a second top doping region. The field oxide layer is formed in the first well region and is located between the gate structure and the first doping region. The first top doping region is formed below the field oxide layer and has the first conductivity type. The second top doping region is formed in the first top doping region and has the second conductivity type.

[0024] According to an embodiment of the present invention, the second top doped region, the first top doped region, the first well region and the substrate form a plurality of layers to reduce the surface electric field so as to increase the breakdown voltage of the first doped region. The second top doped region is also used to reduce the on-resistance of the channel between the first doped region and the second doped region.

[0025] According to an embodiment of the present invention, the doping concentration of the first top doping region is not less than the doping concentration of the third well region, and the doping concentration of the second top doping region is not greater than the doping concentration of the second well region. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A circuit diagram showing a semiconductor device according to an embodiment of the present invention;

[0027] Figure 2 A cross-sectional view showing a semiconductor structure according to an embodiment of the present invention; and

[0028] Figure 3 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown.

[0029] Figure Number:

[0030] 100:Semiconductor device

[0031] 110: Transistor

[0032] 120: diode

[0033] 200:Semiconductor structure

[0034] 211: first doping region

[0035] 212: second doping region

[0036] 213: third doping region

[0037] 214: fourth doping region

[0038] 221: Gate structure

[0039] 231: Drain electrode

[0040] 232: Gate electrode

[0041] 233: diode anode terminal electrode

[0042] 234: Substrate electrode

[0043] T1: First Node

[0044] T2: Second Node

[0045] TD: Drain terminal

[0046] TG: Gate terminal

[0047] TS: Source terminal

[0048] TB: Base terminal

[0049] VG: Gate voltage

[0050] VF: forward conduction voltage

[0051] TA: Anode terminal

[0052] TC: cathode terminal

[0053] SUB:Substrate

[0054] W1: First well region

[0055] W2: Second well region

[0056] W3: The third well region

[0057] W4: Fourth well region

[0058] W5: Fifth well region

[0059] W6: Sixth well region

[0060] ISO1: First isolation structure

[0061] ISO2: Second isolation structure

[0062] ISO3: The third isolation structure

[0063] ISO4: The fourth isolation structure

[0064] FOX: Field Oxide

[0065] WD1: First width

[0066] WD2: Second width

[0067] TOP1: The first top doping region

[0068] TOP2: The second top doping region DETAILED DESCRIPTION

[0069] The following description is an embodiment of the present invention. Its purpose is to illustrate the general principles of the present invention and should not be regarded as limiting the present invention. The scope of the present invention should be based on the claims.

[0070] It is worth noting that the following disclosure may provide multiple embodiments or examples for practicing different features of the present invention. The specific component examples and arrangements described below are only used to briefly and concisely explain the spirit of the present invention and are not used to limit the scope of the present invention. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reusing is only to provide a simplified and clear description, and is not used to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0071] In addition, the description of a feature being connected to, coupled to and / or formed on another feature described in the following specification may actually include multiple different embodiments, including multiple features being in direct contact, or including other additional features formed between multiple features, etc., so that multiple features are not in direct contact.

[0072] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0073] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0074] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0075] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0076] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art of this invention. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0077] In some embodiments of the present invention, terms such as "connection" and "interconnection" may refer to two structures being in direct contact with each other, or two structures not being in direct contact with each other, with another structure disposed between the two structures, unless otherwise specified. Such terms may also include situations where both structures are movable or both structures are fixed.

[0078] In the drawings, similar components and / or features may have the same reference numerals. Various components of the same type may be distinguished by adding letters or numbers after the reference numerals to distinguish similar components and / or similar features.

[0079] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Moreover, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0080] Embodiments of the present invention disclose embodiments of semiconductor devices, and the above embodiments may be included in an integrated circuit (IC) such as a microprocessor, a memory element and / or other elements. The above integrated circuit may also include various passive and active microelectronic components, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused metal oxide semiconductors, high-power MOS transistors or other types of transistors. It will be appreciated by those skilled in the art that the semiconductor device may also be used to include other types of semiconductor elements in an integrated circuit.

[0081] Figure 1 A circuit diagram of a semiconductor device according to an embodiment of the present invention is shown. Figure 1As shown, the semiconductor device 100 has a first node T1 and a second node T2, and includes a transistor 110 and a diode 120. The transistor 110 includes a drain terminal TD, a gate terminal TG, a source terminal TS, and a base terminal TB. The base terminal TB is electrically floating and not connected to other terminals, the drain terminal TD is electrically connected to the second node T2, and the gate terminal TG receives a gate voltage VG. The diode 120 includes an anode terminal TA and a cathode terminal TC, wherein the anode terminal TA is electrically connected to the first node T1, and the cathode terminal TC is electrically connected to the source terminal TS. According to an embodiment of the present invention, the transistor 110 is a laterally diffused metal oxide semiconductor.

[0082] According to an embodiment of the present invention, when the voltage of the first node T1 is greater than the voltage of the second node T2, the gate voltage VG is a positive voltage and the transistor 110 is fully turned on, wherein the voltage of the first node T1 is equal to the sum of the voltage of the second node T2 and the forward conduction voltage VF of the diode 120. In other words, when the semiconductor device 100 is used as a diode, the transistor 110 is fully turned on, so that there is a voltage drop of the forward conduction voltage VF of the diode 120 between the first node T1 and the second node T2.

[0083] According to another embodiment of the present invention, when the voltage of the second node T2 is greater than the voltage of the first node T1, the gate voltage VG is the ground voltage and the transistor 110 is not turned on. In addition, the drain terminal TD of the transistor 110 is used to withstand the high voltage of the second node T2 to prevent the high voltage of the second node T2 from burning the diode 120. According to an embodiment of the present invention, the transistor 110 is a laterally diffused metal oxide semiconductor, and the drain terminal TD can withstand the received high voltage.

[0084] In other words, when the voltage of the first node T1 is greater than the voltage of the second node T2, the semiconductor device 100 acts as a diode, and the transistor 110 is fully turned on, so that there is a voltage drop between the first node T1 and the second node T2 equal to the forward conduction voltage VF of the diode 120. When the voltage of the second node T2 is greater than the voltage of the first node T1, the semiconductor device 100 is not turned on, and the drain terminal TD is used to withstand the high voltage received by the second node T2.

[0085] Figure 2 A cross-sectional view of a semiconductor structure according to an embodiment of the present invention is shown. Figure 2As shown, the semiconductor structure 200 includes a substrate SUB, a first well region W1, a second well region W2, a third well region W3, a fourth well region W4, a fifth well region W5, and a sixth well region W6. The semiconductor substrate SUB has a first conductivity type. According to an embodiment of the present invention, the substrate SUB is a semiconductor substrate. According to an embodiment of the present invention, the substrate SUB is a silicon substrate. According to other embodiments of the present invention, the semiconductor substrate SUB may also be a lightly doped semiconductor substrate having the first conductivity type.

[0086] The first well region W1 is formed in the semiconductor substrate SUB and has a second conductivity type. According to one embodiment of the present invention, the first conductivity type is P type and the second conductivity type is N type. According to one embodiment of the present invention, the first well region W1 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the first well region W1 to form the first well region W1.

[0087] The second well region W2 is formed in the first well region W1 and has a second conductivity type. According to one embodiment of the present invention, the second well region W2 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area where the second well region W2 is to be formed to form the second well region W2. In this embodiment, the doping concentration of the second well region W2 is higher than the doping concentration of the first well region W1.

[0088] The third well region W3 is formed in the first well region W1 and has the first conductivity type. According to one embodiment of the present invention, the third well region W3 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region where the third well region W3 is to be formed to form the third well region W3. In this embodiment, the doping concentration of the third well region W3 is higher than the doping concentration of the semiconductor substrate SUB.

[0089] The fourth well region W4 is formed in the third well region W3 and has the second conductivity type. According to one embodiment of the present invention, the fourth well region W4 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area where the fourth well region W4 is to be formed to form the fourth well region W4. In this embodiment, the doping concentration of the fourth well region W4 is higher than the doping concentration of the first well region W1, and the doping concentration of the fourth well region W4 is lower than the doping concentration of the second well region W2.

[0090] The fifth well region W5 is formed in the first well region W1 and is adjacent to the third well region W3, and has the second conductivity type. According to one embodiment of the present invention, the fifth well region W5 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area where the fifth well region W5 is predetermined to be formed to form the fifth well region W5. In this embodiment, the doping concentration of the fifth well region W5 is higher than the doping concentration of the first well region W1, which can improve the lateral isolation capability and further reduce the occurrence of lateral leakage current. According to other embodiments of the present invention, since the first well region W1 and the fifth well region W5 have the same conductivity type, the fifth well region W5 can also be omitted.

[0091] The sixth well region W6 is formed in the substrate SUB and connected to the first well region W1, and has the first conductivity type. According to one embodiment of the present invention, the sixth well region W6 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the area where the sixth well region W6 is to be formed to form the sixth well region W6. In this embodiment, the doping concentration of the sixth well region W6 is higher than the doping concentration of the semiconductor substrate SUB.

[0092] like Figure 2 As shown, the semiconductor structure 200 further includes a first doping region 211, a second doping region 212, a third doping region 213, a fourth doping region 214 and a gate structure 221. The first doping region 211 is formed in the second well region W2 and has a second conductivity type. According to one embodiment of the present invention, the first doping region 211 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined region of the first doping region 211 to form the first doping region 211. According to one embodiment of the present invention, the first doping region 211 forms the drain terminal TD of the transistor 110. According to one embodiment of the present invention, the doping concentration of the first doping region 211 is higher than the doping concentration of the second well region W2.

[0093] The second doping region 212 is formed in the third well region W3 and connected to the fourth well region W4, wherein the second doping region 212 has a second conductivity type. According to one embodiment of the present invention, the second doping region 212 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in a predetermined area of ​​the second doping region 212 to form the second doping region 212. According to one embodiment of the present invention, the second doping region 212 forms the source terminal TS of the transistor 110. According to one embodiment of the present invention, the doping concentration of the second doping region 212 is higher than the doping concentration of the second well region W2.

[0094] The third doping region 213 is formed in the fourth well region W4 and has the first conductivity type. According to one embodiment of the present invention, the third doping region 213 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region of the predetermined third doping region 213 to form the third doping region 213. According to one embodiment of the present invention, the doping concentration of the third doping region 213 is higher than the doping concentration of the third well region W3.

[0095] The fourth doping region 214 is formed in the sixth well region W6 and has the first conductivity type. According to one embodiment of the present invention, the fourth doping region 214 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in the region of the predetermined fourth doping region 214 to form the fourth doping region 214. According to one embodiment of the present invention, the fourth doping region 214 forms a substrate SUB for electrically connecting the substrate SUB to the ground terminal GND. According to one embodiment of the present invention, the doping concentration of the fourth doping region 214 is higher than the doping concentration of the sixth well region W6.

[0096] The gate structure 221 covers the first well region W1 and the third well region W3, and is located between the first doping region 211 and the second doping region 212. According to an embodiment of the present invention, the gate structure 221 is formed Figure 1 The gate structure 221 controls whether a channel is formed between the first doping region 211 and the second doping region 212 according to the received gate voltage VG. According to an embodiment of the present invention, the first doping region 211, the second doping region 212, and the gate structure 221 form Figure 1 transistor 110.

[0097] According to one embodiment of the present invention, Figure 2 As shown, the third doping region 213, the fourth well region W4 and the second doping region 212 form Figure 1 The diode 120, wherein the third doping region 213 forms the anode terminal TA of the diode 120, and the second doping region 212 forms the cathode terminal TC of the diode 120. According to an embodiment of the present invention, the doping concentration of the fourth well region W4 is used to determine Figure 1 The forward resistance of the diode 120 is .

[0098] The semiconductor structure 200 further includes a first isolation structure ISO1, a field oxide layer FOX, a second isolation structure ISO2, a third isolation structure ISO3 and a fourth isolation structure ISO4. The first isolation structure ISO1 is adjacent to the first doped region 211 and is used to isolate the first doped region 211 from other components. Figure 2As shown, the first isolation structure ISO1 directly contacts the first doped region 211 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the first isolation structure ISO1 does not contact the first doped region 211 .

[0099] The field oxide layer FOX is formed in the first well region W1 and is located between the first doping region 211 and the second doping region 212, wherein at least a portion of the gate structure 221 covers the field oxide layer FOX. Figure 2 As shown, the field oxide layer FOX has a first width WD1. According to an embodiment of the present invention, the first width WD1 is used to determine the breakdown voltage of the first doped region 211 (ie, the drain terminal TD).

[0100] The second isolation structure ISO2 is located between the second doping region 212 and the third doping region 213 and is formed in the fourth well region W4 to isolate the second doping region 212 and the third doping region 213 from each other. Figure 2 As shown, the second isolation structure ISO2 directly contacts the second doping region 212 and the third doping region 213 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the second isolation structure ISO2 does not contact the second doping region 212 and the third doping region 213 .

[0101] The third isolation structure ISO3 is located between the third doping region 213 and the fourth doping region 214 and is formed in the fifth well region W5 to isolate the third doping region 213 and the fourth doping region 214 from each other. Figure 2 As shown, the third isolation structure ISO3 directly contacts the third doping region 213 and the fourth doping region 214 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the third isolation structure ISO3 does not contact the third doping region 213 and the fourth doping region 214 .

[0102] The fourth isolation structure ISO4 is adjacent to the fourth doped region 214 and is used to isolate the fourth doped region 214 from other components. Figure 2 As shown, the fourth isolation structure ISO4 directly contacts the fourth doped region 214 , but this is not intended to limit the present invention. According to other embodiments of the present invention, the fourth isolation structure ISO4 does not contact the fourth doped region 214 .

[0103] like Figure 2 As shown, the semiconductor structure 200 further includes a drain electrode 231, a gate electrode 232, a diode anode terminal electrode 233 and a substrate electrode 234. The first doped region 211 is electrically connected to the drain electrode 231, wherein Figure 1 The second node T2 corresponds to the drain electrode 231. The gate structure 221 is electrically connected to the gate electrode 232 for receiving the gate voltage VG.

[0104] The third doping region 213 is electrically connected to the diode anode terminal electrode 233, wherein Figure 1 The first node T1 corresponds to the diode anode terminal electrode 233. The fourth doped region 214 is electrically connected to the substrate electrode 234, for electrically connecting the substrate SUB to the ground terminal GND. According to an embodiment of the present invention, the semiconductor structure 200 corresponds to Figure 1 The semiconductor device 100 is used as a diode, so the second doped region 212 (ie, the source terminal TS of the transistor 110 and the cathode terminal TC of the diode 120) does not need to be electrically connected to any electrode.

[0105] According to an embodiment of the present invention, the junction between the third doping region 213 and the fourth well region W4 is formed. Figure 1 According to one embodiment of the present invention, the third doped region 213, the fourth well region W4, the third well region W3, the first well region W1 and the substrate SUB form a plurality of isolation structural layers to reduce leakage current, so as to reduce leakage current from the third doped region 213 to the substrate SUB. According to another embodiment of the present invention, the third doped region 213, the fourth well region W4, the third well region W3, the fifth well region W5 and the sixth well region W6 also form a plurality of isolation structural layers to reduce leakage current.

[0106] In other words, when Figure 1 When the voltage of the first node T1 is greater than the voltage of the second node T2, the multiple isolation structure layers formed by the third doping region 213, the fourth well region W4, the third well region W3, the first well region W1 and the substrate SUB (i.e., vertically) or the third doping region 213, the fourth well region W4, the third well region W3, the fifth well region W5 and the sixth well region W6 (i.e., horizontally) help to reduce the leakage current from the first node T1 to the substrate SUB.

[0107] Figure 3 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 3 The semiconductor structure 300 and Figure 2 Compared with the semiconductor structure 200, the semiconductor structure 300 further includes a first top doping region TOP1 and a second top doping region TOP2. According to another embodiment of the present invention, the semiconductor structure 300 corresponds to Figure 1 A semiconductor device 100 is provided.

[0108] The first top doping region TOP1 is formed below the field oxide layer FOX and is located in the first well region W1, and has a first conductivity type. According to one embodiment of the present invention, the first top doping region TOP is connected to the above-mentioned second well region W2. According to one embodiment of the present invention, the first top doping region TOP1 can be formed by an ion implantation step. For example, boron ions or indium ions can be implanted in a predetermined area of ​​the first top doping region TOP1 to form the first top doping region TOP1. According to one embodiment of the present invention, the doping concentration of the first top doping region TOP1 is not less than the doping concentration of the third well region W3. In other words, the doping concentration of the first top doping region TOP1 is greater than or equal to the doping concentration of the third well region W3.

[0109] The second top doping region TOP2 is formed in the first top doping region TOP1 and has a second conductivity type. According to one embodiment of the present invention, the second top doping region TOP2 can be formed by an ion implantation step. For example, phosphorus ions or arsenic ions can be implanted in the area where the second top doping region TOP2 is predetermined to be formed to form the second top doping region TOP2. According to one embodiment of the present invention, the doping concentration of the second top doping region TOP2 is not greater than the doping concentration of the second well region W2. In other words, the doping concentration of the second top doping region TOP2 is less than or equal to the doping concentration of the second well region W2.

[0110] According to an embodiment of the present invention, the second top doping region TOP2, the first top doping region TOP1, the first well region W1 and the substrate SUB form multiple layers to reduce the surface electric field. Figure 1 When the voltage of the second node T2 is greater than the voltage of the first node T1, the multiple layers formed by the second top doping region TOP2, the first top doping region TOP1, the first well region W1 and the substrate SUB are used to reduce the surface electric field to increase the breakdown voltage of the first doping region 211.

[0111] According to an embodiment of the present invention, since the second top doped region TOP2, the first top doped region TOP1, the first well region W1 and the substrate SUB form multiple layers to reduce the surface electric field, the second width WD2 of the field oxide layer FOX of the semiconductor structure 300 may be less than Figure 2 In other words, when the first doped region 211 is subjected to the same voltage, Figure 3 The semiconductor structure 300 is Figure 2 The semiconductor structure 200 occupies a smaller area.

[0112] According to an embodiment of the present invention, when the transistor 110 formed by the first doping region 211, the gate structure 221, the second doping region 212, and the third doping region 213 is turned on according to the gate voltage VG received by the gate electrode 232, the second top doping region TOP2 is beneficial to reducing the on-resistance of the transistor 110. In other words, the second top doping region TOP2 helps to reduce the on-resistance of the semiconductor device 100 when it is forward-conducted (i.e., the voltage of the first node T1 is greater than the voltage of the second node T2).

[0113] The present invention proposes a high-voltage bootstrap diode and a semiconductor structure thereof, wherein the diode is integrated into the semiconductor structure of the lateral diffused metal oxide semiconductor by forming a diode with the base end and the source end of the lateral diffused metal oxide semiconductor. In addition, the present invention utilizes the characteristic that the drain end of the lateral diffused metal oxide semiconductor can withstand high voltage to increase the reverse withstand voltage of the bootstrap diode, and forms a plurality of isolation structure layers around the base end to reduce the leakage current leaking to the substrate when the bootstrap diode is forward-conducted. Furthermore, the drain end of the lateral diffused metal oxide semiconductor also forms a plurality of layers to reduce the surface electric field, so that under the same withstand voltage, the bootstrap diode proposed by the present invention requires a smaller area.

[0114] Although the embodiments of the present invention and its advantages have been described above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present invention. In addition, the scope of protection of the present invention is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art may understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present invention. As long as the same functions can be implemented or the same results can be obtained in the embodiments described herein, they can be used according to some embodiments of the present invention. Therefore, the scope of protection of the present invention includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes a separate embodiment, and the scope of protection of the present invention also includes the combination of each claim and embodiment.

Claims

1. A semiconductor device, characterized in that: The semiconductor device has a first node and a second node, wherein the semiconductor device comprises: a transistor, comprising a drain terminal, a gate terminal, a source terminal and a base terminal, wherein the base terminal is electrically floating and not connected to other terminals, and the drain terminal is electrically connected to the second node; and A diode includes an anode terminal and a cathode terminal, wherein the anode terminal is electrically connected to the first node, and the cathode terminal is electrically connected to the source terminal.

2. The semiconductor device according to claim 1, wherein When the voltage of the first node is greater than the voltage of the second node, the transistor is turned on, wherein the voltage of the first node is equal to the sum of the voltage of the second node and the forward conduction voltage of the diode.

3. The semiconductor device according to claim 1, wherein: When the voltage of the second node is greater than the voltage of the first node, the transistor is not conducting, wherein the drain terminal is used to withstand the voltage of the second node to prevent the semiconductor device from being damaged.

4. The semiconductor device according to claim 1, wherein: Also includes: a substrate having a first conductivity type; a first well region having a second conductivity type, wherein the first conductivity type and the second conductivity type are different; a second well region formed in the first well region and having the second conductivity type; a third well region formed in the first well region and having the first conductivity type; a fourth well region formed in the third well region and having the second conductivity type; A gate structure formed between the first doped region and the second doped region and covering the first well region and the third well region, wherein the gate structure forms the gate terminal; a first doped region formed in the second well region and having the second conductivity type, wherein the first doped region forms the drain terminal; a second doped region formed in the third well region and having the second conductivity type, wherein the second doped region forms the source terminal; and A third doped region is formed in the fourth well region and has the first conductivity type, wherein the third well region forms the base terminal.

5. The semiconductor device according to claim 4, wherein: The diode is formed between the second doping region and the third doping region, wherein the second doping region further forms the cathode terminal, the third doping region further forms the anode terminal, and the second doping region is connected to the fourth well region.

6. The semiconductor device according to claim 5, wherein: The doping concentration of the fourth well region is lower than the doping concentration of the second well region, and the doping concentration of the fourth well region is higher than the doping concentration of the first well region.

7. The semiconductor device according to claim 5, wherein: The third doped region, the fourth well region, the third well region, the first well region and the substrate form a plurality of isolation structure layers to reduce leakage current; When the diode is turned on, the plurality of isolation structure layers are used to reduce leakage current from the third doping region to the substrate.

8. The semiconductor device according to claim 4, wherein: Also includes: A field oxide layer formed in the first well region and located between the gate structure and the first doped region; a first top doped region, formed below the field oxide layer and having the first conductivity type; and A second top doping region is formed in the first top doping region and has the second conductivity type.

9. The semiconductor device according to claim 8, wherein: The second top doped region, the first top doped region, the first well region and the substrate form a plurality of layers for reducing the surface electric field to increase the breakdown voltage of the drain terminal; The second top doped region is used to reduce the channel on-resistance of the transistor.

10. The semiconductor device according to claim 8, wherein The doping concentration of the first top doping region is not less than the doping concentration of the third well region; The doping concentration of the second top doping region is not greater than the doping concentration of the second well region.

11. A semiconductor structure, characterized in that: include: a substrate having a first conductivity type; a first well region having a second conductivity type, wherein the first conductivity type and the second conductivity type are different; a second well region formed in the first well region and having the second conductivity type; a third well region formed in the first well region and having the first conductivity type; a fourth well region formed in the third well region and having the second conductivity type; A gate structure formed between the second well region and the third well region; a first doped region, formed in the second well region and having the second conductivity type; a second doped region formed in the third well region and having the second conductivity type; and a third doped region, formed in the fourth well region and having the first conductivity type; wherein the gate structure, the first doped region, the second doped region and the third doped region form a transistor; The second doping region and the third doping region form a diode.

12. The semiconductor structure according to claim 11, wherein: The transistor comprises a drain terminal, a gate terminal, a source terminal and a base terminal, and the diode comprises an anode terminal and a cathode terminal; The gate structure forms the gate terminal, the first doped region forms the drain terminal, the second doped region forms the source terminal, and the third well region forms the base terminal; The second doped region further forms the cathode terminal, and the third doped region further forms the anode terminal.

13. The semiconductor structure according to claim 12, wherein: When the voltage of the third doping region is higher than the voltage of the first doping region, the transistor is turned on according to the voltage of the gate terminal, and the voltage of the third doping region is equal to the sum of the voltage of the first doping region and the forward conduction voltage of the diode.

14. The semiconductor structure according to claim 12, wherein: When the voltage of the first doping region is higher than the voltage of the third doping region, the transistor is turned off according to the voltage of the gate terminal, and the semiconductor structure withstands the voltage of the first doping region and is not damaged.

15. The semiconductor structure according to claim 11, wherein: The third doping region is formed in the fourth well region, and the second doping region is connected to the fourth well region.

16. The semiconductor structure according to claim 15, wherein: The doping concentration of the fourth well region is lower than the doping concentration of the second well region, and the doping concentration of the fourth well region is higher than the doping concentration of the first well region.

17. The semiconductor structure according to claim 15, wherein: The third doped region, the fourth well region, the third well region, the first well region and the substrate form a plurality of isolation structure layers to reduce leakage current; When the diode is turned on, the plurality of isolation structure layers are used to reduce leakage current from the third doping region to the substrate.

18. The semiconductor structure according to claim 11, wherein: Also includes: A field oxide layer formed in the first well region and located between the gate structure and the first doped region; a first top doped region, formed below the field oxide layer and having the first conductivity type; and A second top doping region is formed in the first top doping region and has the second conductivity type.

19. The semiconductor structure according to claim 18, wherein: The second top doped region, the first top doped region, the first well region and the substrate form a plurality of layers for reducing the surface electric field to increase the breakdown voltage of the first doped region; The second top doped region is also used to reduce the on-resistance of the channel between the first doped region and the second doped region.

20. The semiconductor structure according to claim 18, wherein: The doping concentration of the first top doping region is not less than the doping concentration of the third well region; The doping concentration of the second top doping region is not greater than the doping concentration of the second well region.

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