Semiconductor device with multiple gates and related methods

Abstract

The invention relates to a semiconductor device with multiple gates and a related method. Novel semiconductors and fabrication techniques are provided. In various embodiments, a semiconductor includes a source, a drain, a first gate, a second gate, and a channel. The second gate is electrically coupled to the first gate. The first gate and the second gate are configured to control a current flow between the source and the drain. The channel is in contact with the first gate and the second gate. The channel is configured such that the current flows through the channel. Other aspects, embodiments, and features are also claimed and described.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] Generally, the present disclosure relates to methods, systems, and apparatus for implementing semiconductor technology, and more particularly, to methods, systems, and apparatus for implementing field effect transistors for high voltage applications. Background Art

[0004] Field effect transistors (FETs) have been widely used in various electronic applications due to their ability to effectively control the flow of current. Among FETs, laterally diffused metal oxide semiconductors (LDMOS) can be used in high power applications, such as power amplifiers, RF (radio frequency) amplifiers, and power transistors for radio and wireless communication systems.

[0005] As the demand for high power applications continues to increase, research and development continues to advance LDMOS technology, not only to meet the manufacturing capabilities and capacity of foundries that produce LDMOS, but also to advance and enhance high power applications that use LDMOS transistors. Summary of the invention

[0006] Generally, the technology of the present disclosure relates to tools and techniques for implementing semiconductor technology, and more particularly, to methods, systems, and apparatus for semiconductor devices and / or semiconductor device processing.

[0007] In one aspect, a semiconductor device includes a source, a drain, a first gate, a second gate, and a channel. The second gate is electrically coupled to the first gate. The first gate and the second gate are configured to control a current between the source and the drain. The channel is electrically coupled to the first gate and the second gate. The channel is configured to cause the current to flow through the channel.

[0008] In some embodiments, the semiconductor device further includes a connector positioned directly on the first gate and the second gate to physically connect the first gate to the second gate.

[0009] In some embodiments, a first distance of the first gate along a direction from the source to the drain is longer than a second distance of the second gate along the direction from the source to the drain.

[0010] In some embodiments, the channel is electrically coupled to the second gate by contacting the second gate.

[0011] In some embodiments, the channel includes a first channel and a second channel. The first channel contacts the first gate, and the second channel contacts the second gate. The semiconductor device further includes a fin positioned between the first channel and the second channel.

[0012] According to some embodiments, the first gate is positioned on the first channel, and the second gate is positioned on the second channel.

[0013] According to some embodiments, the fin is positioned between the first gate and the second gate.

[0014] In some embodiments, the channel consists of a single channel in contact with both the first gate and the second gate.

[0015] In some embodiments, the semiconductor device further includes a second channel, the channel and the second channel being positioned parallel with respect to each other in a direction between the source and the drain.

[0016] In some embodiments, the channel comprises: silicon, silicon-germanium, or germanium.

[0017] In some embodiments, the source includes a first fin and the drain includes a second fin.

[0018] According to some embodiments, the first fin and the second fin include in-situ phosphorus or boron doped epitaxy.

[0019] In some embodiments, the semiconductor device further includes a substrate, a first well positioned on the substrate, and a second well positioned on the substrate. The source is positioned on the first well. The drain is positioned on the second well, the channel is positioned on the first well, and the first gate is positioned on the first well.

[0020] According to some embodiments, the second gate is in contact with the channel, and the second gate is positioned over at least one of the first well or the second well.

[0021] In another aspect, a method for processing a semiconductor device includes: forming a first well and a second well on a substrate; forming a channel on the first well and the second well; forming a first gate and a second gate; and forming a source on the first well and a drain on the second well. The first gate is electrically coupled to the second gate, and the channel is in contact with the first gate and the second gate.

[0022] In some embodiments, the method further includes positioning a connector directly on the first gate and the second gate to physically connect the first gate to the second gate.

[0023] In some embodiments, the channel includes a first channel and a second channel. The first channel contacts the first gate, and the second channel contacts the second gate. The method locates a fin between the first channel and the second channel.

[0024] According to some embodiments, the first gate is positioned on the first channel, and the second gate is positioned on the second channel.

[0025] According to some embodiments, the fin is positioned between the first gate and the second gate.

[0026] In yet another aspect, a semiconductor device includes a source, a drain, a first gate, a second gate, a connector, and a channel. The first gate and the second gate are configured to control a current between the source and the drain. The connector is positioned directly on the first gate and the second gate to physically connect the first gate to the second gate. The channel is electrically coupled to the first gate and the second gate. The channel is configured to cause the current to flow through the channel.

[0027] Various modifications and additions may be made to the discussed embodiments without departing from the scope of the invention. For example, although the embodiments described above refer to particular features, the scope of the invention also includes embodiments with different combinations of features and embodiments that do not include all of the features described above.

[0028] The details of one or more aspects of the disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the techniques described in the disclosure will be apparent from the specification and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to designate one of a plurality of similar components. When a reference numeral is made without explanation of an existing sub-label, it is intended to refer to all such plurality of similar components.

[0030] Figure 1 is a schematic diagram illustrating an example laterally diffused metal oxide semiconductor (LDMOS) transistor with a long gate.

[0031] Figure 2Ais a schematic diagram illustrating a side view of an example semiconductor device according to various embodiments, and Figure 2B It is a diagram that illustrates the Figure 2B Schematic diagram of a cross-sectional view of an exemplary semiconductor device according to various embodiments, taken along line AA.

[0032] Figure 3A is a schematic diagram illustrating a side view of another exemplary semiconductor device according to various embodiments, and Figure 3B It is a diagram that illustrates the Figure 3B Schematic diagram of a cross-sectional view of an exemplary semiconductor device according to various embodiments, taken along line AA.

[0033] Figure 4 is a schematic diagram illustrating a side view of an example semiconductor device according to various embodiments.

[0034] Figure 5 is a flow chart illustrating an exemplary process 500 for fabricating a semiconductor device according to various embodiments. DETAILED DESCRIPTION

[0035] As described above, laterally diffused metal oxide semiconductor (LDMOS) can be used in high power applications, such as power amplifiers, RF (radio frequency) amplifiers, and power transistors for radio and wireless communication systems. Some LDMOS (i.e., FinFET LDMOS) can incorporate fin structures in the LDMOS design. Adding the fin structure can improve the performance and power handling capabilities of the LDMOS transistor. Some FinFET LDMOS are designed to use a foundry process that allows long gate lengths (e.g., equal to or longer than 360 nm) for high voltage LDMOS. For example, Figure 1 1 is a schematic diagram illustrating an exemplary laterally diffused metal oxide semiconductor (LDMOS) transistor 100 with a long gate 102. In the LDMOS transistor 100, the gate distance 104 is equal to or longer than 360 nm in the direction from the source 106 to the drain 108. However, some foundries cannot use a long gate for FIN LDMOS. For example, some foundries use a self-aligned contact (SAC) process in the gate module. Therefore, in the foundry, the maximum gate length is shorter than the long gate length (e.g., about 200 nm) due to the W (tungsten) recess process included in the SAC RMG (replacement metal gate) module. The uniform recess depth of the W recess process limits the longest possible gate length.

[0036] Some embodiments described herein provide solutions to these problems by providing improved semiconductors and methods for two gates and channels in contact with the two gates. For example, the described semiconductor devices include multiple shorter gates (e.g., equal to or shorter than 300 nm) to essentially form long gates to enable high voltage applications. Therefore, some foundries that do not have the foundry capacity to produce long gates (e.g., due to the SAC process) can produce transistors for high voltage applications. The improved semiconductor devices can be manufactured by any suitable foundry, using the SAC process or not. In addition, the improved semiconductor devices also provide various other aspects (e.g., no additional masks or process steps, or any other suitable features).

[0037] Figure 2A is a schematic diagram illustrating a side view of an exemplary semiconductor device 200, and Figure 2B It is a diagram that illustrates the Figure 2B 2 is a schematic diagram of a cross-sectional view of an exemplary semiconductor device taken along line AA of FIG. In some examples, semiconductor device 200 may include a transistor, a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a laterally diffused metal oxide semiconductor (LDMOS) transistor, a FinFET LDMOS transistor, and / or any other suitable semiconductor 200. For example, exemplary semiconductor device 200 may include multiple gates 202, 204, a source 206, a drain 208, and / or a channel 210. In some examples, semiconductor device 200 may control current flow by applying voltage to the multiple gates, which causes a change in conductivity between source 206 and drain 208. Thus, current may flow from source 206 through channel 210, be modified by the gate, and reach drain 208.

[0038] In some examples, the semiconductor device 200 may include multiple gates to form a long gate. In some examples, the first gate 202 may be electrically coupled to the second gate 204. The multiple gates in the semiconductor device 200 may include a first gate 202 and a second gate 204, which are configured to control the current between the source 208 and the drain 206 and are positioned between the source 208 and the drain 206. In some examples, the first gate 202 and the second gate 204 may control the current together. In other examples, the first gate 202 or the second gate 204 may control the current. In some examples, the first distance 212 of the first gate 202 along the direction from the source 206 to the drain 208 may be longer than the second distance 214 of the second gate 204 along the direction from the source 206 to the drain 208. In some scenarios, the first distance 212 of the first gate 202 may have the longest length allowed by the foundry. The second distance 214 of the second gate 204 may be added to form the first gate 202 and the second gate 204 into a long gate. For example, the first distance 212 of the first gate 202 may be between 160nm and 300nm, and the second distance 214 of the second gate 204 may be between 70nm and 300nm. In some examples, the second distance 214 of the second gate 204 may be equal to or less than 200nm. In other scenarios, the first gate 202 and the second gate 204 may have the same distance or any suitable distance. In some examples, the first gate 202 and the second gate 204 may extend in parallel in a second direction at right angles to the direction from the source 206 to the drain 208. In some further examples, the first gate 202 and the second gate 204 may extend in parallel in the second direction to control the flow of current through the plurality of channels 210. In other examples, the semiconductor device 200 may include more than two gates to form a long gate.

[0039] In such Figure 2B, the semiconductor device 200 may further include a connector 213 positioned on the first gate 202 and the second gate 204 to connect the first gate to the second gate. In some examples, the connector 213 may be a material that provides electrical contact. For example, the connector 213 may be made of tungsten or any other suitable material to electrically couple the first gate 202 to the second gate 204. For example, the connector is positioned on a first side of the first gate and the second gate 202, and the substrate (e.g., a p-well, an n-well, a p-type substrate, or an n-type substrate) is positioned on a second side of the first gate and the second gate 202. In some examples, the first side is a side opposite to the second side. In some examples, the connector 213 may have an inverted U-shape so that the connector 213 is connected to the first side of the first gate 202 and the second gate 204. In other examples, the connector 213 may have any other suitable shape to connect the first gate 202 and the second gate 204. Therefore, in this example, the first gate 202 and the second gate 204 can be electrically coupled via a physical medium (i.e., connector 213) to form a long gate. In other examples, the connector can be made of copper or any other suitable material to connect between the first gate 202 and the second gate 204.

[0040] In some examples, the semiconductor device 200 may include a channel 210 that contacts the first gate 202 and the second gate 204. In some examples, the first gate 202 may be positioned on the channel 210. For example, the channel 210 is electrically coupled to the source 206 and the drain 208 to carry current from the source 206 to the drain 208, wherein the channel 210 is configured to flow current through the channel 210. In some examples, the channel 210 may include: silicon, silicon-germanium, or germanium. In some examples, the channel 210 may be one channel that contacts the first gate 202 and the second gate 204. For example, again referring to Figure 2B , the channel 210 may pass through the first gate 202. In some examples, the channel 210 may pass through the second gate 204 or may not pass through the second gate. Both the first gate 202 and the second gate 204 may be in contact with the channel 210. In yet other examples, the semiconductor device 200 may include a second channel that is a channel separate from the channel 210. In some examples, the second channel and the channel 210 may be positioned parallel to each other in a direction between the source 206 and the drain 208. In such an example, another channel may be in contact with both the first gate 202 and the second gate 204.

[0041] In some examples, the semiconductor device 200 may include a source 206 and a drain 208. For example, the source 206 may include a first fin, and the drain 208 may include a second fin. In some examples, the fin (e.g., the first fin, the second fin) may be a vertical and / or protruding structure in a semiconductor device (e.g., a transistor) to improve performance and power efficiency. In some examples, each of the first fin and the second fin may include in-situ phosphorus or boron doped epitaxy. However, it should be understood that each of the first fin and the second fin may be any other suitable material. In some other examples, the first fin as the source 206 may be formed in the channel 210. Therefore, the first fin may be positioned in the channel 210 in the direction between the source 206 and the drain 208. In some examples, the first fin may include a region protruding from the channel 210. In some examples, the first fin may contact the first gate. In other examples, the first fin may be away from the first gate 202. In some examples, the second fin as the drain 208 may be formed in the channel 210. Therefore, the second fin may be positioned in the channel 210 in a direction between the source 206 and the drain 208. In some examples, the second fin may include a region protruding from the channel 210. In other examples, the source 206 and the drain 208 may be a p-type or n-type substrate without a fin.

[0042] In some examples, the semiconductor device 200 may further include a substrate 216, a first well 218 positioned on the substrate 216, and / or a second well 220 positioned on the substrate 216. For example, the substrate 216 may include a silicon substrate. Specifically, the substrate 216 may be a lightly boron-doped P-type substrate. In other examples, the substrate 216 may be an N-type substrate or any other suitable silicon substrate.

[0043] In some examples, the first well 218 may include a P-well, and the second well 220 may include an N-well. In yet other examples, the source 206 may be positioned on the first well 218, and the drain 208 may be positioned on the second well 220. In yet other examples, the channel 210 may be positioned on the first well 218. In addition, the first gate 202 may be positioned above the first well 218. For example, the first gate 202 may not be in direct contact with the first well 218, and the channel 210 may be positioned between the first gate 202 and the first well 218. Therefore, the first gate 202 may be positioned above the first well 218 in a direction that is at right angles to the direction from the source 206 to the drain 208. In some examples, the channel 210 may be positioned on the second well 220. For example, the channel 210 may be partially positioned on the second well 220. In other examples, the channel 210 may not be positioned on the second well 220. Thus, the channel 210 may not be in contact with the second well 220. In some examples, the second gate may be in contact with the channel 210 and may be positioned over at least one of the first well 218 or the second well 220. For example, the second gate 204 may be partially positioned over the first well 218 such that the channel 210 may be positioned between the second gate 204 and the first well 218 in a direction at right angles to the direction from the source 206 to the drain 208. In yet other examples, the second gate 204 may be partially positioned over the second well 220 such that the channel 210 may be positioned between the second gate 204 and the second well 220 in a direction at right angles to the direction from the source 206 to the drain 208. In yet other examples, the second gate 204 may be partially positioned on the second well 220 such that the second gate 204 is in contact with the second well 220.

[0044] In yet other examples, the first well 218 may include a first shallow trench isolation 222. In yet other examples, the second well 220 may include a second shallow trench isolation 224 and a third shallow trench isolation 226. In some examples, the second shallow trench isolation 224 may be in contact with the second gate 204 or may not be in contact with the second gate. The number of shallow trench isolations 222, 224, 226 is not limited to three, but may be any suitable number to prevent current leakage.

[0045] Figure 3A is a schematic diagram illustrating a side view of another exemplary semiconductor device, and Figure 3B It is a diagram that illustrates the Figure 3B Schematic diagram of a cross-sectional view of an exemplary semiconductor taken along line AA. Figure 3A and 3BThe semiconductor device 300 in the embodiment may include a plurality of gates, a source 306, a drain 308, and / or a channel. In some examples, the plurality of gates may include a first gate 302 and a second gate 304. In addition, the semiconductor device 300 may further include a connector 312 for electrically coupling the first gate 302 to the second gate 304. In some examples, the first gate 302 and the second gate 304 and the connector 312 may be substantially similar to Figure 2A and 2B The first gate 202 and the second gate 204 and the connector 213 in FIG. In addition, the source 306 and the drain 308 may be substantially similar to Figure 2A and 2B The source 206 and the drain 208 in.

[0046] In some examples, the channel in the semiconductor device 300 may include a first channel 310A and a second channel 310B. In yet other examples, the semiconductor device 300 may further include a fin positioned between the first channel 310A and the second channel 310B. In some examples, the channel may include two separate channels and a fin between the two separate channels. In some examples, the fin 310C may be inserted between the first channel 310A and the second channel 310B. Figure 2B In some other examples, the fin 310C may be inserted with other fins (i.e., source 306 and drain 308). The fin 310C may be substantially similar to the other fins (i.e., source 306 and drain 308). For example, the fin 310C may be made by in-situ phosphorus or boron doped epitaxy. However, it should be understood that the fin 310C may be made of any other suitable material. In some examples, the first channel 310A may contact the first gate 302, and the second channel 310B may contact the second gate 304. Therefore, the first gate 302 may be positioned on the first channel 310A, and the second gate 304 may be positioned on the second channel 310B. Here, the first gate 302 positioned on the first channel 310A may include a first gate 302 positioned entirely on the first channel 310A or partially on the first channel 310A. Similarly, the second gate 304 positioned on the second channel 310B may include the second gate 304 positioned entirely on the second channel 310B or partially on the second channel 310B. Furthermore, the fin 310C may be positioned between the first gate 302 and the second gate 304.

[0047] In some examples, the semiconductor device 300 may further include a substrate 316, a first well 318 positioned on the substrate 316, and / or a second well 320 positioned on the substrate 316. In some examples, the substrate 316, the first well 318, and the second well 320 are substantially similar to Figure 2B The substrate 216, the first well 218 and the second well 220 in the embodiment of the present invention.

[0048] In some instances, Figure 2A and 2B The semiconductor device 200 and Figure 3A and 3B Both semiconductor devices 200 and 300 can realize FinFET LDMOS without having a long gate length that is not available in some foundries. For example, both semiconductor devices 200 and 300 use two gates in contact with the channel and a connector to form a long gate. In some aspects, Figure 2A and 2B The total channel resistance and current of the semiconductor device 200 can be respectively Figure 3A and 3B The transistor 300 in is higher and lower. In another aspect, Figure 2A and 2B The leakage of the semiconductor 200 can be less than Figure 3A and 3B A semiconductor device 300 is provided in FIG.

[0049] Figure 4 4 is a schematic diagram illustrating a side view of an example semiconductor device 400 according to various embodiments. In some examples, the semiconductor device 400 may include a first gate 402, a second gate 404, a source 406, and a drain 408. The semiconductor device 400 may be substantially similar to Figure 2A and 2B The semiconductor device 200 or Figure 3A and 3B A semiconductor device 300 is provided.

[0050] Figure 5 5 is a flow chart illustrating an example process 500 for processing a semiconductor device according to some aspects of the present disclosure. As described below, certain implementations may omit some or all of the illustrated features, and some of the illustrated features may not be required to implement all embodiments. In some examples, a controller having a processor and a memory may be configured to perform the process 500. In some examples, any suitable device or means for performing the functions or algorithms described below may perform the process 500.

[0051] At block 510, the controller may form a first well and a second well on a substrate. In some examples, the substrate, the first well, and the second well are substantially similar to Figure 2B The substrate 216, the first well 218 and the second well 220 in the embodiment of the present invention.

[0052] At block 520, the controller may form a channel on the first well and the second well. In some examples, the channel is substantially similar to Figure 2B Channel 210 in Figure 3BIn some other examples, the controller may further form a fin portion positioned between the first channel and the second channel. In some examples, the fin portion is substantially similar to Figure 3B The fin portion 310C in the embodiment of the present invention.

[0053] At block 530, the controller may form a first gate and a second gate. In some examples, the first gate may be electrically coupled to the second gate, and the channel may be in contact with the first gate and the second gate. In some examples, the first gate and the second gate are substantially similar to Figure 2B In some examples, a first distance of the first gate along the direction from the source to the drain is longer than a second distance of the second gate along the direction from the source to the drain. In some examples, the channel can be formed by Figure 2B The first gate 202 and the second gate 204 described above may be composed of or include a single channel that contacts both the first gate 202 and the second gate 204. Therefore, the single channel may contact both the first gate 202 and the second gate 204. In other examples, the channel may include the first channel and the second channel. In some examples, the first gate may be positioned on the first channel and the second gate is positioned on the second channel. In some other examples, the fin is positioned between the first gate and the second gate. In some other examples, the controller may further position a connector on the first gate and the second gate to connect the first gate to the second gate. In some examples, the connector is substantially similar to Figure 2B Connector 213 in.

[0054] At block 540, the controller may form a source on the first well and a drain on the second well. In some examples, the source and drain are substantially similar to Figure 2A and 2B 206 and drain 208 in the controller. In some examples, the source may include a first fin and the drain may include a second fin. Therefore, the controller may form the source and the drain by forming the first fin and the second fin, respectively. In some other examples, when the channel includes a first channel and a second channel, the fin between the first channel and the second channel may be inserted together with the first fin as the source and the second fin as the drain. In other examples, when the channel includes one channel, the controller may prevent the fin from being inserted between the first channel and the second channel.

[0055] In some examples, "electrically coupled" includes a physical coupling that is configured to form an electrical coupling when an electric current is applied. When an element is referred to herein as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected to the other element, or have an intermediate element present between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it will be understood that there are no intermediate elements in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which intermediate elements may be present.

[0056] When an element is referred to herein as being "placed" in a certain manner relative to another element (e.g., placed on, placed between, placed below, placed adjacent to, or placed in some other relative manner), it will be understood that the element can be placed directly relative to the other element (e.g., placed directly on the other element) or have intervening elements present between the elements. Conversely, when an element is referred to as being "directly placed" relative to another element, it will be understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which intervening elements may be present.

[0057] When an element is described as being "above" or "placed "above" another element, it will be understood that the element may be referred to as being directly above (or placed on) another element, or having an intervening element present between the element and the other element. In some instances, when an element is described as being "above" or "placed "above" another element, at least a portion of the element has an overlap with at least a portion of the other element in at least one axis. Conversely, when an element is referred to as being "directly above" or "placed "directly above" another element, it will be understood that the entire element has an overlap with at least a portion of the other element in at least one axis, or at least a portion of the element has an overlap with the entire other element in at least one axis.

[0058] In still other examples, the phrase "at least one of" preceding a series of items (using the terms "and" or "or" to separate any of the items) modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended to be selected, it is explicitly described as such.

[0059] Although specific features and aspects have been described with respect to some embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, software components, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for illustrative purposes, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may instead be implemented on any suitable hardware, firmware, and / or software configuration. Similarly, although specific functionality is attributed to a specific system component, unless the context otherwise dictates, this functionality need not be limited thereto and may be distributed among various other system components according to several embodiments.

[0060] In addition, although the procedures of the methods and processes described herein are described in a particular order for the sake of illustration, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise dictates. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular structural architecture and / or with respect to a system may be organized and / or incorporated into other described systems in an alternative structural architecture. Therefore, although various embodiments with or without specific features are described for the sake of illustration and some aspects of those embodiments are illustrated, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or deleted from other described embodiments unless the context otherwise dictates. Therefore, although several embodiments are described above, it will be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A semiconductor device comprising: source; Drain; a first gate; a second gate electrically coupled to the first gate, the first gate and the second gate being positioned between the drain and the source; a connector positioned directly on the first grid and the second grid; and A channel is electrically coupled to the first gate and the second gate. 2 . The semiconductor device according to claim 1 , wherein a first distance of the first gate along a direction from the source to the drain is longer than a second distance of the second gate along the direction from the source to the drain. 3 . The semiconductor device according to claim 1 , wherein the channel is electrically coupled to the second gate by being in contact with the second gate.

4. The semiconductor device according to claim 1, wherein the channel comprises a first channel and a second channel, wherein the first channel is in contact with the first gate, wherein the second channel is in contact with the second gate, and The semiconductor device further includes a fin positioned between the first channel and the second channel.

5. The semiconductor device according to claim 4, wherein the first gate is positioned on the first channel, and The second gate is positioned on the second channel. The semiconductor device according to claim 4 , wherein the fin is positioned between the first gate and the second gate. 7 . The semiconductor device according to claim 1 , wherein the channel consists of a single channel in contact with both the first gate and the second gate.

8. The semiconductor device according to claim 1, further comprising: A second channel is positioned parallel to each other in a direction between the source and the drain.

9. The semiconductor device according to claim 1, wherein the channel comprises: Silicon, silicon-germanium or germanium.

10. The semiconductor device according to claim 1, wherein the source comprises a first fin, and The drain includes a second fin. The semiconductor device of claim 10 , wherein the first fin and the second fin comprise in-situ phosphorus or boron doped epitaxy.

12. The semiconductor device according to claim 1, further comprising: substrate; a first well positioned on the substrate; and a second well positioned on the substrate, wherein the source is positioned on the first well, wherein the drain is positioned on the second well, wherein the channel is positioned on the first well, and The first gate is positioned on the first well.

13. The semiconductor device according to claim 12, wherein the second gate is in contact with the channel, and Wherein the second gate is positioned over at least one of the first well or the second well.

14. A method for processing a semiconductor device, comprising: forming a first well and a second well on a substrate; forming a channel on the first well and the second well; forming a first gate and a second gate, wherein the first gate is electrically coupled to the second gate, and the channel is electrically coupled to the first gate and the second gate; positioning a connector directly on the first gate and the second gate to physically connect the first gate to the second gate; and A source is formed on the first well and a drain is formed on the second well.

15. The method according to claim 14, wherein the channel comprises a first channel and a second channel, wherein the first channel is in contact with the first gate, wherein the second channel is in contact with the second gate, and Wherein the method further comprises: A fin is formed that is positioned between the first channel and the second channel.

16. The method of claim 15, wherein the first gate is positioned on the first channel, and The second gate is positioned on the second channel. The method of claim 15 , wherein the fin is positioned between the first gate and the second gate.

18. A semiconductor device comprising: source; Drain; a first gate; a second gate, the first gate and the second gate being positioned between the drain and the source; a connector positioned directly on the first gate and the second gate to physically connect the first gate to the second gate; as well as A channel is electrically coupled to the first gate and the second gate, the channel being in contact with the second gate.

19. The semiconductor device according to claim 18, wherein the channel comprises a first channel and a second channel, wherein the first channel is in contact with the first gate, wherein the second channel is in contact with the second gate, and The semiconductor device further includes a fin positioned between the first channel and the second channel. 20 . The semiconductor device of claim 19 , wherein the fin is positioned between the first gate and the second gate.

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