Optimal high voltage trench design with floating polysilicon trenches

Abstract

A method and apparatus are disclosed for an integrated circuit having a high voltage slot including: a buried layer of a first conductivity type formed in a substrate of a second conductivity type; the central region of the first conductive type is formed in the substrate and is in contact with the buried layer; a first floating isolation trench formed in the substrate so as to surround the central region and extend downward to the buried layer and surround the buried layer; a second floating isolation trench formed in the substrate around the first isolation trench; the shallow ring region of the first conductive type is formed between the first floating isolation groove and the second floating isolation groove in the substrate; the first conductive interconnection structure is used for electrically short-circuiting the central region to the shallow ring region; and a second conductive interconnect structure for electrically shorting the first floating isolation trench to the second floating isolation trench.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices. In one aspect, the present disclosure relates to integrated circuit devices and processes for integrating analog components, digital components, and high voltage devices into a single chip or integrated circuit. Summary of the invention

[0002] An integrated circuit with a high voltage groove and an associated manufacturing method are provided. As disclosed, the method includes forming a buried layer of a first conductivity type (e.g., n-type) in a substrate of a second conductivity type (e.g., p-type). In selected embodiments, the buried layer extends only below a central region and does not extend laterally beyond a first floating isolation trench. As disclosed herein, the term "laterally" generally refers to a lateral position in a plane parallel to a substantially flat main surface of the substrate or positioned in a direction away from a centerline. The method also includes forming a central region of the first conductivity type in contact with the buried layer in the substrate. In addition, the method includes forming a first floating isolation trench on the substrate to surround the central region and extend downward to the buried layer and surround the buried layer. The method also includes forming a second floating isolation trench in the substrate around the first floating isolation trench. In selected embodiments, the first and second floating isolation trenches are each formed with a polysilicon structure formed in an insulating liner layer. In other embodiments, the first and second floating isolation trenches are formed as a first inner polysilicon ring structure disposed around the central region, and a second outer polysilicon ring structure disposed concentrically around the first inner polysilicon ring structure. In addition, the method includes forming a shallow ring region of a first conductivity type in the substrate between at least a portion of the first floating isolation trench and a portion of the second floating isolation trench. In selected embodiments, the shallow ring region extends at least partially downward to the buried layer, and both the first and second floating isolation trenches extend beyond the buried layer into the substrate. The method also includes forming a first conductive interconnect structure for electrically shorting the center region to the shallow ring region. In addition, the method includes forming a second conductive interconnect structure for electrically shorting the first floating isolation trench to the second floating isolation trench. In selected embodiments, the center region is electrically shorted to the shallow ring region by forming a first conductive interconnect structure having a metal interconnect structure formed above the substrate to electrically connect the center region to the shallow ring region. In other embodiments, the first and second floating isolation trenches are electrically shorted by forming a second conductive interconnect structure having a metal interconnect structure formed above the substrate to electrically connect the first floating isolation trench to the second floating isolation trench. In other embodiments, the first and second floating isolation trenches are electrically shorted by forming a second conductive interconnect structure having an insulating polysilicon interconnect structure formed in the substrate to electrically connect the first floating isolation trench to the second floating isolation trench.

[0003] In another form, an integrated circuit device having a high voltage groove and an associated manufacturing method are provided. As disclosed, the integrated circuit device includes a substrate of a first conductivity type and a buried layer of a second conductivity type located above the substrate. In addition, the integrated circuit device includes a central isolation region of the second conductivity type located above the buried layer. In selected embodiments, bipolar transistor devices, CMOS transistor devices, and DMOS transistor devices are at least partially located within the central isolation region. The integrated circuit device also includes a first floating polysilicon isolation structure located in the substrate to surround the central isolation region and extend downward to the buried layer and surround the buried layer. In selected embodiments, the buried layer extends laterally only below the central isolation region and does not extend laterally beyond the first floating polysilicon isolation structure. In addition, the integrated circuit device includes a second floating polysilicon isolation structure, which is located in the substrate around the first floating polysilicon isolation structure. In selected embodiments, the first and second floating polysilicon isolation structures each include a polysilicon structure formed in an insulating liner layer. The integrated circuit device also includes a shallow ring region of the second conductivity type, which is located in the substrate between at least a portion of the first floating polysilicon isolation structure and a portion of the second floating polysilicon isolation structure. In addition, the integrated circuit device includes a first conductive interconnect structure for electrically shorting the central isolation region to the shallow ring region. In selected embodiments, the central isolation region is electrically shorted to the shallow ring region by a first conductive interconnect structure formed with a metal interconnect structure formed above the substrate to electrically connect the central isolation region to the shallow ring region. The integrated circuit device also includes a second conductive interconnect structure for electrically shorting the first floating polysilicon isolation structure to the second floating polysilicon isolation structure. In selected embodiments, the first and second floating polysilicon isolation structures are electrically shorted by a second conductive interconnect structure formed with a metal interconnect structure formed above the substrate to electrically connect the first floating polysilicon isolation structure to the second floating polysilicon isolation structure. In other selected embodiments, the first and second floating polysilicon isolation structures are electrically shorted by a second conductive interconnect structure formed with an adiabatic polysilicon interconnect structure formed in the substrate to electrically connect the first floating polysilicon isolation structure to the second floating polysilicon isolation structure. In selected embodiments, the shallow ring region at least partially extends down to the buried layer, and both the first and second floating polysilicon isolation structures extend beyond the buried layer into the substrate. In other embodiments, when the central isolation region is set to a potential greater than zero relative to the substrate, the voltage across the peripheral end of the buried layer to the substrate is less than the voltage across the central portion of the buried layer to the substrate. In other embodiments, the shallow ring region of the second conductivity type and the underlying portion of the substrate of the first conductivity type form a through structure configured to pull up the potential of the first floating polysilicon isolation structure when the central isolation region is set to a potential greater than zero relative to the substrate. One of ordinary skill in the art will appreciate that the through structure will consist of a first conductivity region in the middle of the ring region of the second conductivity type.

[0004] In yet another form, an integrated circuit device having a high voltage trench and an associated method of manufacturing are provided. As disclosed, the integrated circuit device includes a p-type substrate, an n-type buried layer located above the p-type substrate, and an isolated n-type region located above the n-type buried layer, wherein the isolated n-type region and the n-type buried layer are vertically aligned. The integrated circuit device also includes a first floating polysilicon isolation trench, which is concentrically disposed in the p-type substrate to surround the isolated n-type region. In addition, the integrated circuit device includes a shallow n-type well region, which is concentrically disposed in the p-type substrate to surround the first floating polysilicon isolation trench. The integrated circuit device also includes a second floating polysilicon isolation trench, which is concentrically disposed in the p-type substrate to surround the shallow n-type well region. In addition, the integrated circuit device includes a first conductive interconnect structure, which is connected to electrically short the isolated n-type region to the shallow n-type well region. The integrated circuit device also includes a second conductive interconnect structure connected to electrically short the first floating polysilicon isolation trench to the second floating polysilicon isolation trench. In selected embodiments, the integrated circuit device also includes a bipolar transistor device, a CMOS transistor device, and a DMOS transistor device at least partially located within the isolation n-type region. Background Art

[0005] Electronic devices, especially semiconductor devices and integrated circuits, usually include multiple separate semiconductor-based components manufactured on the same semiconductor substrate or die. These components are usually designed to operate independently of each other so that they do not interfere with adjacent components or latch adjacent components. In order to provide electrical isolation between different components, deep trench isolation (DTI) structures and / or high voltage regions can be used in semiconductor devices to electrically isolate adjacent regions of the substrate laterally and vertically. In addition, trench-based isolation technology is used with silicon-on-insulator wafers to eliminate the risk of latching. However, as the operating voltage and component density (components per unit area) on the substrate increase, it becomes increasingly difficult to maintain the desired isolation breakdown voltage. In addition, as the size of the device decreases, junction-based isolation technology requires too much silicon area, and trench-based isolation technology on SOI wafers is too expensive. As the packing density of semiconductor components increases, there is a greater variation in the breakdown voltage distribution observed across the die or wafer, which may result in lower manufacturing yields. As can be seen from the foregoing, existing solutions for providing isolation between different or adjacent devices formed on a shared substrate are extremely difficult at a practical level because it is challenging to provide effective isolation structures while meeting the performance requirements and cost constraints of mass production of semiconductor devices and avoiding performance and reliability-related issues associated with traditional isolation structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure and its numerous objects, features and advantages achieved will be understood when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0007] Figure 1 Depicting a simplified cross-sectional view of an integrated circuit employing a prior art isolation structure in which a single conductive buried layer intersects a polysilicon-filled deep trench.

[0008] Figure 2 Depicting a simplified cross-sectional view of an integrated circuit employing a prior art isolation structure in which a single conductive buried layer intersects concentric polysilicon-filled deep trench rings.

[0009] Figure 3A Depicted is a simplified cross-sectional view of an integrated circuit employing a first high voltage trench structure having a pair of electrically shorted concentric polysilicon-filled trenches separating and defining an outer conductive well ring shorted to an inner conductive well region in accordance with selected embodiments of the present disclosure.

[0010] Figure 3B A first exemplary embodiment of a conductive interconnect structure for shorting concentric polysilicon-filled trenches and for individually shorting outer conductive well rings and inner conductive well regions according to selected embodiments of the present disclosure is depicted. Figure 3A A simplified plan view of the integrated circuit shown in FIG.

[0011] Figure 3C A second exemplary embodiment of a conductive interconnect structure for shorting concentric polysilicon-filled trenches and for individually shorting outer conductive well rings and inner conductive well regions according to selected embodiments of the present disclosure is depicted. Figure 3A A simplified plan view of the integrated circuit shown in FIG.

[0012] Figure 4 Nanoprobe measurement graph depicting the normalized breakdown voltage for evaluating different isolation structures as a function of the ratio of floating poly voltage to conductive well voltage.

[0013] Figure 5 Depicted is a simplified flow chart showing a process flow for fabricating a high voltage trench with deep trench isolation provided by shorting concentric polysilicon trenches and an outer N-well ring shorted to an inner N-well region, in accordance with selected embodiments of the present disclosure. DETAILED DESCRIPTION

[0014] A method and apparatus for manufacturing an integrated semiconductor device is described, the integrated semiconductor device having a high voltage groove or region surrounded and protected by electrically shorted concentric deep trench isolation rings, the concentric deep trench isolation rings separating and defining an outer conductive well ring shorted to an inner conductive well region, thereby providing an optimized breakdown voltage. As disclosed, the integrated semiconductor device includes: a substrate of a first conductive type; a buried layer of a second conductive type located above the substrate; an isolated conductive well region of the second conductive type located above the buried layer; a first floating polysilicon isolation trench ring located around the isolated conductive well region; a first conductive well ring region of the second conductive type located around the first floating polysilicon isolation trench ring; a second floating polysilicon isolation trench ring concentrically located around the first conductive well ring region, wherein the first and second floating polysilicon isolation trench rings are electrically shorted together, and wherein the isolated conductive well region and the first conductive well ring region are electrically shorted together.

[0015] Various illustrative embodiments will now be described in detail with reference to the accompanying drawings. As described below, the disclosed embodiments can be arranged and designed in a variety of different configurations. Therefore, the detailed description of the various embodiments shown below is not intended to limit the scope of the present disclosure, but merely represents various embodiments. Although various details are set forth in the following description, it should be understood that the present invention can be practiced without these specific details, and many implementation-specific decisions can be made for the present invention described herein to achieve the specific goals of the device designer, such as compliance with process technology or related design constraints, which vary from implementation to implementation. Although such research and development work may be complex and time-consuming, it is nothing more than a routine task routine for ordinary technicians in the field who benefit from the present disclosure. In addition, various aspects of the embodiments are presented in the illustrations, and unless specifically indicated, the drawings may not be drawn to scale. In addition, the described features, advantages and characteristics of the present invention can be combined in one or more embodiments in any suitable manner. In view of the description herein, it should be recognized by those skilled in the relevant art that embodiments can be practiced without one or more specific features or advantages of a specific embodiment. In other cases, additional features and advantages that may not be present in all embodiments can be identified in certain embodiments. For example, selected aspects are depicted with reference to simplified cross-sectional views of semiconductor devices, but not including every device feature or geometry, so as not to limit or confuse the present invention. It should also be noted that throughout this detailed description, certain materials will be formed and removed to make semiconductor structures. Where specific processes for forming or removing such materials are not described in detail below, it is contemplated that such layers will be grown, deposited, removed or otherwise formed with appropriate thicknesses using techniques conventional to those skilled in the art. Such details are well known and are not considered necessary to teach those skilled in the art how to make or use the present invention.

[0016] As will be appreciated by those skilled in the art, semiconductor-based electronic devices are typically formed from a single substrate in which a plurality of independent semiconductor components, such as bipolar devices, complementary MOS (CMOS) devices, and / or double-diffused (DMOS) devices (collectively referred to as BCD devices) are formed. In order to ensure that each semiconductor component operates correctly, one or more isolation structures are used to electrically isolate the semiconductor components from each other and from the substrate so that each component type can be formed within an isolation region of the isolation structure. For each isolation structure, lateral isolation of the isolation region is typically achieved by surrounding the isolation region with an insulating trench structure, which is configured to inhibit lateral current flow from one component on the substrate to the next component. Vertical isolation is achieved using junction isolation between the isolation region and the substrate. The degree to which each component is electrically isolated from the surrounding components and the substrate affects the maximum voltage at which the semiconductor device can operate.

[0017] The isolation voltage capability (also called breakdown voltage) of a particular isolation structure refers to the maximum voltage to which the isolation region of the isolation structure can be exposed without adversely affecting the operation of other semiconductor components formed on the same substrate. If the voltage of the isolation region is too large, a certain amount of current that significantly exceeds the normal leakage current begins to flow from the isolation region to other isolation regions or the substrate, and this may cause components in other isolation regions to malfunction and / or may cause significant power consumption, or even burn the entire device. This current limiting device, sometimes referred to as crosstalk, can utilize the maximum voltage, thereby limiting the capabilities of individual semiconductor components.

[0018] In a particular semiconductor device, many factors can be used to reduce the isolation breakdown voltage of a particular isolation structure. First, as the number of components formed on a single substrate increases, the density of the individual semiconductor components on the substrate also increases, and this in turn increases the density of the isolation trenches formed around the components. In the case where the isolation trenches are typically formed by an oxide or insulator liner layer deposited by chemical vapor deposition (CVD) or thermal oxidation, the increase in the density of the isolation trenches requires that a large surface area be uniformly coated with an oxide / insulator material to provide the desired isolation, but the process restrictions on the material for depositing the oxide / insulator may result in an uneven oxide / insulator liner thickness, which may reduce the isolation breakdown voltage of the device. Therefore, increasing the density of components can reduce the isolation breakdown voltage capability of the semiconductor device. Another factor that adversely affects the isolation breakdown voltage of a particular isolation structure is the temperature stress within the operating life of the component. For example, during high temperature operating conditions, the isolation breakdown voltage of a relatively densely structured device can be reduced due to charge injection and capture occurring in the polysilicon-oxide-silicon structure of the isolation trench, resulting in device failure.

[0019] In order to provide additional details to improve the contextual understanding of the present disclosure, reference is now made to Figure 1 , Figure 1 A simplified cross-sectional view of an integrated circuit device 1 employing a first prior art isolation structure is depicted, wherein an n-well region 16 is electrically isolated by a single conductive buried layer 12 that intersects polysilicon-filled deep trenches 14-15 formed in a substrate 10-11. In the isolated n-well region 16, a plurality of semiconductor devices, wells, or other structures may be formed. In addition, one or more metal interconnect layers are used to form an isolation connector 18 that makes direct electrical contact with the isolated n-well region 16 through a patterned insulator layer, such as a patterned shallow trench isolation (STI) layer 17A and / or a patterned insulator layer 17B. It will be appreciated that details of the devices located in the isolated n-well region 16 have been omitted from the drawings as such details are not important to the present disclosure. In general, one or more of transistors, resistors, diodes, capacitors, and the like, and combinations thereof, may be formed within the isolated n-well region 16.

[0020] As depicted, the substrate 10-11 may include a first P+ substrate layer 10 and a first P-EPI region 11 formed on the first P+ substrate layer 10, wherein the first P-EPI region 11 includes an outer region outside the floating polysilicon trenches 14A / 15A, 14B / 15B and a central region located below the isolated n-well region 16. In addition, an N-type buried layer (NBL) 12 is formed in the substrate 10-11 over the central region of the first P-EPI layer 11. In addition, an isolated n-well region 16 is formed over the NBL 12 alone or in combination with a peripheral N-type region (not shown) that may be electrically interconnected. In order to electrically isolate the n-well region 16, polysilicon structures 15A, 15B are disposed in trenches that have been lined with oxide or insulator liner layers 14A, 14B, respectively. In addition to providing structural support to the isolation structures, polysilicon structures 15A, 15B also provide protection from environmental shocks caused, for example, by thermal expansion of the isolation structures during operation of one or more semiconductor devices formed over substrate layers 10 - 11 .

[0021] Before or after forming the NBL 12 and the polysilicon-filled deep trenches 14-15 in the substrate 10-11, a selective implantation process may be used to form an isolated n-well region 16, which may be used to construct components and / or circuit systems. Thus, after forming the desired components and / or circuit systems, a plurality of N-type and / or P-type regions may be formed within the isolated n-well region 16. Since the n-well region 16 is laterally and vertically isolated by the polysilicon-filled deep trenches 14-15 and the NBL 12, the semiconductor components formed on the isolated n-well region 16 may operate without interfering with the operation of other nearby components or without being interfered with by the operation of other nearby components. Specifically, the isolated n-well region 16 is typically provided with lateral isolation (i.e., electrical isolation from other components formed on the substrate 10-11) by the polysilicon-filled deep trenches 14-15 formed around the semiconductor components. In addition, vertical isolation (i.e., electrical isolation from the substrate 10-11) is generally provided to the isolated n-well region 16 by the NBL 12, and in particular the junction between the NBL 12 and the first P-EPI layer 11. The junction between the NBL 12 and the first P-EPI layer 11 forms a PN junction that is generally reverse biased, thereby providing electrical isolation to the isolated n-well region 16, up to the isolation breakdown voltage of the assembly. In this configuration, the lateral isolation provided by the polysilicon filled deep trenches 14-15 provides more effective isolation than the vertical isolation provided by the junction between the NBL 12 and the first P-EPI layer 11. Therefore, the vertical isolation provided by the PN junction between the NBL 12 and the first P-EPI layer 11 becomes the limiting factor for the isolation breakdown voltage of the structure. The weakest isolation point is generally found at the hot spot region 19. Therefore, this breakdown voltage of the entire isolation structure can be referred to as the substrate breakdown voltage or BV SUB Given the specific BV used for the isolation structure SUB , and then gives the structure a rated isolation voltage (V ISO-RATED ), when the isolation structure is V ISO-RATED The rated isolation voltage provides sufficient margin for safe operation of the isolation structure during operation. Figure 1 In the example assembly of the structure shown, the breakdown voltage BV SUB Can be compared with the rated voltage (V ISO-RATED ) is approximately 30V higher, or allows this technology to have a higher voltage rating than BV SUB Therefore, during normal device operation, the voltage within the isolation n-well region 16 can be from 0V to V ISO-RATED V changes. It should be noted that higher BV SUB value produces a higher rated voltage V ISO-RATED value, which is desirable for realizing new circuit applications.

[0022] In operation, both the isolated n-well region 16 and the NBL 12 operate at a first potential (e.g., V1) provided by the isolation connector 18, while the substrates 10-11 are set to a second potential (e.g., V2 or ground). FLOATING_POLY In the case of , the potential of polysilicon structure 15A / 15B is free floating and becomes coupled to the potential affected by V1 and V2, where the coupling is similar to the coupling capacitance C1 between floating polysilicon structure 15 and isolated n-well region 16. For example, if V1 is equal to V for conventional devices ISO-RATED And V2 is equal to 0V, then the voltage V FLOATING_POLY can float to about 30% of V1. Therefore, the entire voltage V ISO-RATED The weakest part of the isolation structure at the hot spot location 19 is lowered. Figure 1 In the trench-based isolation structure depicted in FIG. 1 , the hotspot location 19 is limited by the polysilicon potential value, which is affected by the relatively small capacitive coupling C1 between the polysilicon structure 15 and the isolation n-well region 16 .

[0023] In order to provide additional details to improve the contextual understanding of the present disclosure, reference is now made to Figure 2 , Figure 2 A simplified cross-sectional view of an integrated circuit device 2 employing a second prior art isolation structure is depicted, wherein an n-well region 26 is electrically isolated by a single conductive buried layer 22A-C that intersects a plurality of concentric polysilicon-filled deep trench rings 24A / 25A, 24B / 25B formed in the substrate 20-21 to surround the isolated n-well region 26. In the isolated n-well region 26, a plurality of semiconductor devices, wells, or other structures may be formed. Again, details of the devices located in the isolated n-well region 26 have been omitted from the drawings as such details are not important to the present disclosure. Additionally, one or more metal interconnect layers are used to form an isolation connector 28 that makes direct electrical contact with the isolated n-well region 26 through a patterned insulator layer, such as a patterned STI layer 27A and / or a patterned insulator layer 27B.

[0024] As depicted, the substrate 20-21 may include a first P+ substrate layer 20 and a first P-EPI region 21 formed on the first P+ substrate layer 20, wherein the first P-EPI region 21 includes an outer region outside the concentric floating polysilicon trenches 24A / 25A, 25B / 25B and a central region located below the isolated n-well region 26. In addition, an N-type buried layer (NBL) 22A-C is formed in the substrate 20-21 over the central region of the first P-EPI layer 21 to extend across a plurality of concentric polysilicon-filled deep trench rings 24A / 25A, 24B / 25B formed in the substrate 20-21. In addition, the isolated n-well region 26 is formed over a central portion of the NBL 22B, the central portion also including peripheral NBL regions 22A, 22C extending beyond the peripheral sides of the isolated n-well region 26. To electrically isolate the n-well region 26, a first inner polysilicon ring structure 25B is disposed in a first inner trench that has been lined with an oxide or insulator liner 24B. Additionally, a second outer polysilicon ring structure 25A is concentrically disposed in a second outer trench that has been lined with an oxide or insulator liner 24A. Each additional or outer polysilicon filled deep trench ring (e.g., 24A / 25A) is paired with a through structure formed with a shallow implant region 26A, 26B of a second conductivity type formed above a region of the first P-EPI region 21A, 21B of the first conductivity type, wherein the resulting through structure is configured to reduce the potential for a weak point subject to the isolation structure. In addition to providing structural support to the isolation structure, the polysilicon structures 25A, 25B also provide protection from environmental shocks caused by thermal expansion of the isolation structure, such as during operation of one or more semiconductor devices formed above the substrate layer 20-21.

[0025] Before or after forming the NBL 22A-C and the concentric polysilicon-filled deep trench rings 24A / 25A, 24B / 25B in the substrate 20-21, one or more selective implant processes may be used to form an isolated n-well region 26, which may be used to build components and / or circuitry. In addition, the shallow implant regions 26A, 26B may also be selectively implanted to define a punch-through structure resulting from the junction between the regions 26A / 26B and the underlying regions of the first P-EPI regions 21A / 21B. Since the n-well region 26 is laterally and vertically isolated by the concentric polysilicon-filled deep trench rings 24A / 25A, 24B / 25B and the NBL 22B, respectively, the semiconductor components formed on the isolated n-well region 26 may operate without interfering with or being interfered with by the operation of other nearby components. In addition, the through-structure created by the junction between regions 26A / 26B and 21A / 26B serves to more evenly distribute the potential across the entire isolation structure. Thus, the electric field formed within the isolation structure spreads across the main isolation junction below the isolation n-well region 26 and the isolation junctions of the additional isolation trench ring and through-structure.

[0026] In operation, the isolated n-well region 26 and the shallow implant regions 26A, 26B operate at a first potential (e.g., V1) provided by the isolation connector 28, while the substrate 20-21 is set to a second potential (e.g., V2 or ground). In this case, the central NBL portion 22B below the isolated n-well region 26, the isolated n-well region 26, and the shallow implant regions 26A, 26B each share the same potential V1. However, due to the PN junction formed by the interaction of the shallow implant regions 26A, 26B and the underlying regions of the first P-EPI region 21A / 21B, respectively, the potential of the peripheral NBL portions 22A, 22C is reduced by a certain amount below V1 to a lower potential V3.

[0027] In the case where the floating polysilicon structures 25A, 25B are surrounded by oxide or insulator layers 24A, 24B, each floating polysilicon structure has a floating potential V FLOATING POLY , the floating potential is free-floating and can become coupled to a potential that falls somewhere between V1 and V3 (the coupling is similar to capacitive coupling). In this example, V FLOATING_POLY is approximately 70% of V1. This causes the hot spot to move to the bottom of the trench, where V FLOATING_POLY The potential difference with V2 generates a high electric field.

[0028] In order to provide additional details to improve the understanding of selected embodiments of the present disclosure, reference is now made to Figure 3A , Figure 3AA first simplified cross-sectional view of an integrated circuit employing a first high voltage tank structure 3A is depicted, wherein an n-well region 36 is electrically isolated by a single conductive buried layer 32 and a pair of electrically shorted concentric polysilicon-filled trenches 34A / 35A, 34B / 35B that separate and define an outer conductive well ring 37 that is shorted to the inner conductive n-well region 36. As depicted, the first high voltage tank structure 3A is formed in a substrate 30-31, 33 that includes a first P+ substrate layer 30, a first P-EPI region 31 formed on the first P+ substrate layer 30, and a second P-EPI region 33 formed on the first P-EPI region 31 after forming the NBL 32. The first P-EPI region 31 includes an outer region outside the concentric floating polysilicon trenches 34A / 35A, 34B / 35B and a center region located below the isolated n-well region 36. In addition, an N-type buried layer (NBL) 32 is formed in the substrate 30-31 over the central region of the first P-EPI layer 31 to extend only between the inner polysilicon-filled deep trench rings 34B / 35B. Over the NBL 32, an isolation n-well region 36 is formed between the inner polysilicon-filled trench rings 34B / 35B. In the isolation n-well region 36, a plurality of semiconductor devices, wells, or other structures (e.g., BJT, MOSFET, diode, CMOS, DMOS, etc.) may be formed, but the details of the devices are not shown because they are not important to the present disclosure.

[0029] In this configuration, the electrically shorted concentric polysilicon-filled trenches 34A / 35A, 34B / 35B provide lateral electrical isolation for the inner conductive n-well region 36. And between the concentric floating polysilicon trenches 34A / 35A, 34B / 35B, shallow implant regions 37A, 37B may be selectively formed as second n-well ring regions above the regions of the first P-EPI regions 33A, 33B to form a through structure configured to reduce the potential of being subjected to a weak point of the isolation structure. In addition, vertical electrical isolation is provided by a single conductive n-type buried layer (NBL) 32 formed in the substrate 30-31, 33 to extend only between the inner polysilicon-filled trench rings 34B / 35B, and not to the outer polysilicon-filled trench rings 34A / 35A. In addition, one or more metal interconnect layers may be used to form isolation connectors 39 that make direct shorting electrical contact with the isolation n-well region 36 and the outer conductive well ring 37A / B through a patterned insulator layer such as patterned STI layer 38A and / or patterned insulator layer 38B. And although shown in simplified schematic form, one or more conductive polysilicon and / or metal interconnect layers may be used to form one or more floating polysilicon shorting connectors 40A, 40B that make direct shorting electrical contact with the polysilicon structures 35A, 35B in the concentric polysilicon-filled trenches through patterned insulator layers 38A, 38B.

[0030] To provide a first exemplary embodiment for shorting the outer conductive well ring 37 to the inner conductive n-well region 36 and for individually shorting the concentric floating polysilicon filled trenches 34A / 35A, 34B / 35B together, reference will now be made to Figure 3B , Figure 3B Depiction Figure 3A A simplified plan view of the first high pressure tank structure is shown Figure 3B , wherein conductive interconnect structures 39, 40 are formed. Although the plan view shows the concentric floating polysilicon filled trenches 34A / 35A, 34B / 35B as having square or sharp corners in simplified form, it should be understood that in practice curved geometries will be used to reduce electric field effects that would otherwise result from having sharp corner features in the floating polysilicon filled trenches. For example, each of the described corner features will be formed with a defined curvature characteristic (e.g., a corner radius of 0-10 microns).

[0031] As shown, the conductive interconnect structure 39 may be formed with one or more metal interconnect layers to short the isolated n-well region 36 with the outer conductive well ring 37A / B by using any suitable metal damascene process to form one or more patterned conductive interconnect layers to extend through the patterned openings in the insulator layer 38 to make direct shorting electrical contact between the well regions 36, 37. Although the specific arrangement, construction, and connection of the different conductive interconnect layers are not important, the conductive interconnect structure 39 may be constructed using a metal damascene process that deposits a conductive layer in an opening formed in a constituent interlayer dielectric (ILD) layer and then polishes or etches back the conductive layer to be coplanar with the constituent ILD layer, as known to those skilled in the art. Of course, other interconnect fabrication techniques may be used to construct the different conductive interconnect layers, such as photoresist masking and plasma etching. Although the conductive interconnect structure 39 is shown as a single continuous metal interconnect positioned to extend over the first high voltage trench structure 3B to make a direct short connection with the isolated n-well region 36 and the outer conductive well ring 37A / B, it should be understood that two or more metal interconnect structures may also be formed at appropriate locations to short the isolated n-well region 36 and the outer conductive well ring 37A / B.

[0032] Figure 3B Also shown is an example embodiment in which the conductive interconnect structure 40 may be formed with one or more metal interconnect layers to define a pair of floating polysilicon shorting connectors 40A, 40B for shorting the concentric polysilicon-filled trenches 34A / 35A, 34B / 35B together. As disclosed, each floating polysilicon shorting connector 40A, 40B may be formed using any suitable damascene or other interconnect fabrication process to form one or more patterned conductive interconnect layers to extend through the patterned openings in the insulator layer 38 to make direct shorting electrical contact between the concentric polysilicon-filled trenches 34A / 35A, 34B / 35B. Although the floating polysilicon shorting connectors 40A, 40B are shown aligned to form separate metal interconnects, each of which is positioned to make a direct shorting connection between an inner polysilicon-filled trench ring 34B / 35B and an outer polysilicon-filled trench ring 34A / 35A, it should be understood that a single continuous metal interconnect structure can also be formed in an appropriate position to short the concentric polysilicon-filled trenches 34A / 35A, 34B / 35B.

[0033] To provide a second exemplary embodiment for shorting the outer conductive well ring 37 to the inner conductive n-well region 36 and for individually shorting the concentric polysilicon filled trenches 34A / 35A, 34B / 35B together, reference will now be made to Figure 3C , Figure 3C Depiction Figure 3A A simplified plan view of the first high pressure tank structure is shown Figure 3C, wherein conductive interconnect structures 39, 41 are formed. In an embodiment, the conductive interconnect structure 39 may be formed with one or more metal interconnect layers to short the isolation n-well region 36 with the external conductive well ring NW2 37, as shown in FIG. Figure 3B As described. However, instead of using a metal interconnect layer to short the concentric polysilicon-filled trenches 34A / 35A, 34B / 35B, a shorted electrical connection is instead provided during the formation of the concentric polysilicon-filled trenches 34A / 35A, 34B / 35B, so that one or more polysilicon shorting layers 41 are formed to electrically connect the concentric polysilicon structures 35A, 35B. In selected embodiments, the connecting polysilicon shorting layer 41 can be formed by defining the deep trench opening as including an "H"-shaped opening or layout feature connecting the inner trench opening and the outer trench opening. Therefore, when the deep trench opening is filled with the conformal insulating layer 34A, 34B and the floating polysilicon structure 35A, 35B, the "H"-shaped opening or layout feature is also filled to form the floating polysilicon shorting layer 41 connecting the concentric polysilicon structures 35A, 35B. Although the floating polysilicon shorting layer 41 shown is shown as being formed on one side of a polysilicon interconnect positioned to make a direct shorting connection between the concentric polysilicon structures 35A, 35B, it will be appreciated that two or more floating polysilicon shorting layers may be used to short the concentric polysilicon filled trenches 35A, 35B. It will be appreciated that the geographic configuration of the "H" type floating polysilicon shorting layer 41 includes sharp corners that may reduce breakdown voltage performance. Depending on process and manufacturing parameters, the sharp corners may result in a hot spot location 42 between the inner floating polysilicon structure 35A and the outer floating polysilicon structure 35B just below the shallow implant regions 37A, 37B.

[0034] However, a short connection is made, the isolation n-well region 36, the shallow implant regions 37A, 37B and the NBL 32 operate at a first potential (e.g., V1) provided by the isolation connector 39, while the substrates 30-31, 33 are set to a second potential (e.g., V2 or ground). In addition, the electrically shorted concentric polysilicon-filled trenches 34A / 35A, 34B / 35B are at a shared floating polysilicon voltage V of approximately 50% of V1. FLOATING_POLY As the optimization of V1 and V FLOATING_POLY and V FLOATING_POLY As a result of the potential difference with V2 , the hot spot moves between V1 and V2 , as depicted by position 41 .

[0035] In order to improve the understanding of selected embodiments of the present disclosure, reference is now made to Figure 4 , Figure 4 The normalized breakdown voltage used to evaluate different isolation structures is plotted as a function of the floating polysilicon voltage (V FLOATING_POLY ) and the isolation n-well voltage (V N-WELL) is a function of the ratio of the nanoprobe measurement curve Figure 4 In this example, voltage measurements of breakdown voltage are made by nanoprobing the floating polysilicon and n-well regions. Based on the measurement data, the y-axis shows the normalized breakdown voltage BV of the isolated n-well. The x-axis shows the ratio of the polysilicon voltage to the n-well voltage. For example, when the HV trench (e.g., NBL 32) = 100V, V FLOATING_POLY / V N-WELL =0.4 means V FLOATING_POLY =40V.

[0036] In the depicted graph, there is a first breakdown voltage region BV1 where the calculated ratio is relatively low (e.g., V FLOATING_POLY / V N-WELL <0.4). In this first breakdown voltage region BVV1, the first voltage difference (V N-WELL -V FLOATING_POLY ) is high, which makes the hot spots located next to the corners of the NBL and deep trenches (such as Figure 1 19 in the NBL). Therefore, the breakdown voltage in the first breakdown voltage region BV1 is limited by the location of the hotspot 19 at the corner or interface of the NBL and the floating polysilicon trench, where it can contribute to polysilicon implantation and trench oxide charging. Based on the high voltage trench breakdown voltage value, it can be determined Figure 1 The first prior art isolation structure shown has a breakdown voltage shown as normalized to 1, as indicated at graph point 43, where the floating poly is coupled to the HV trench at a calculated ratio of approximately 30% to 35%.

[0037] The depicted graph also shows that when the calculated ratio is relatively high (e.g., V FLOATING_POLY / V N-WELL >0.6). In this second breakdown voltage region BV2, the second voltage difference (V FLOATING_POLY -V SUBSTRATE ) is high, which makes the hot spot near the bottom of the trench (such as Figure 2 29 in the figure). Therefore, the breakdown voltage in the second breakdown voltage region BVV2 is limited by the location of the hot spot 29 at the bottom of the floating polysilicon trench at the interface with the underlying substrate (e.g., P-EPI layer 21), where the breakdown voltage can contribute to polysilicon implantation and trench oxide charging. Based on the high voltage trench breakdown voltage value, it can be determined Figure 2 The second prior art isolation structure shown has a Figure 1The first prior art isolation structure is shown to have a breakdown voltage that is approximately 10% higher, as indicated at graph point 44, where the floating poly is coupled to the HV trench at a calculated ratio of approximately 65% ​​to 70%.

[0038] As can be seen from the depicted graph, neither the first breakdown voltage region BV1 nor the second breakdown voltage region BV2 achieves the best or highest breakdown voltage. Instead, there is a third breakdown voltage region BV3, which is actually FLOATING_POLY / V N-WELL The third breakdown voltage region BV3 is achieved when the ratio of is between 0.4 and 0.6. In this third or optimal breakdown voltage region BV3, the first and second voltage differentials converge to a common value, which causes a hot spot to be located near the bottom of the NBL (as shown by hot spot 41 in FIG. 3 ), where hot carriers are less likely to promote polysilicon implantation and trench oxide charging. Therefore, the breakdown voltage in the third breakdown voltage region BV3 is limited by the voltage difference between the NBL and the substrate, where the floating polysilicon is coupled to the HV groove at a calculated ratio of approximately 50% to 60%.

[0039] According to the present disclosure, the arrangement and depth of the shallow implanted regions 37A, 37B relative to the shorted concentric floating polysilicon trenches 34A / 35A, 34B / 35B can be designed so that 0.5<V FLOATING_POLY / V N-WELL <0.6 to achieve optimized breakdown voltage performance. Therefore, a 50V voltage applied to the isolation n-well region 36 will result in a potential of approximately 25V being applied to the floating polysilicon structures 35A, 34B / 35B.

[0040] In order to provide additional details to improve the understanding of selected embodiments of the present disclosure, reference is now made to Figure 5 , Figure 5 A simplified flow chart is depicted, which illustrates a process flow 5 for manufacturing a high voltage trench with deep trench isolation, which is provided by shorting concentric polysilicon trenches and an outer n-well ring shorted to an inner n-well region. In describing the manufacturing process flow 5, various reference numerals, doping types and concentrations are provided with the aid of examples of different regions that can be formed, but this is merely to facilitate understanding of the various exemplary embodiments and not as a limitation. After the process begins at step 51, a series of manufacturing steps 52-58 sequences are performed to manufacture a wafer containing multiple tube cores, each tube core includes a single substrate with one or more high voltage trench isolation structures, and multiple independent semiconductor components, such as bipolar devices, CMOS devices and / or DMOS devices, are formed in the one or more high voltage trench isolation structures. It will be understood that the specific sequence of steps can be modified or changed. In addition, certain steps can be implemented with multiple separate processing steps, can be omitted and / or performed separately.

[0041] In step 52, a substrate is provided or manufactured, the substrate having a lower p-type epitaxial layer, a buried n-type layer, and an upper p-type epitaxial layer formed above the substrate. With respect to manufacturing step 52, a plurality of steps may be used, which are from preparing a substrate having a first conductivity type (e.g., p-type) and a doping concentration (e.g., in the range of 1e15 cm -3 to 1e19 cm -3 On the substrate, a first epitaxial semiconductor layer (e.g., 31) of a first conductivity type is formed, for example, by epitaxially growing and planarizing a first lightly doped p-type layer above the substrate to a predetermined thickness (e.g., about 3um to 30um) and a doping concentration (e.g., about 1e15 cm -3 to 1e18cm -3 ). On the first epitaxial semiconductor layer, a patterned buried layer (e.g., 32) can be formed to be located in the area of ​​the expected high voltage slot region. As formed, the patterned buried layer has a second conductivity type (e.g., n-type) and a predetermined doping concentration (e.g., 1e17 cm -3 to 1e20 cm -3 ) and / or thickness. When forming the patterned buried layer, a selective mask and implantation or diffusion technique may be used, or alternatively, a patterned buried layer may be formed using selective epitaxial growth under controlled doping conditions. Subsequently, a second epitaxial semiconductor layer (e.g., 33) of the first conductivity type is formed over the first epitaxial semiconductor layer to cover the patterned buried layer, for example, by epitaxially growing and planarizing a second lightly doped p-type layer to a predetermined thickness (e.g., about 3um to 30um) and a doping concentration (e.g., about 1e15 cm -3 to 1e18cm -3 ). Alternatively, a single p-type epitaxial semiconductor layer may be formed over the substrate, and then n-type impurities may be implanted and subsequently annealed to form an n-type buried layer.

[0042] In step 53, the substrate is selectively etched to form concentric inner and outer trench openings formed in at least the upper p-type epitaxial layer to surround and extend beyond the buried n-type buried layer. With respect to fabrication step 53, multiple steps may be used, such as by forming a patterned mask (not shown) on the substrate to define etch openings in which the concentric inner and outer trenches will be formed and positioned relative to the subsequently formed isolation n-well and surrounding n-well ring region. Subsequently, the selective etching process may include performing one or more deep reactive ion etching (RIE) steps with a suitable etching chemistry using the patterned photoresist mask to remove at least the exposed portion of the upper p-type epitaxial layer to a sufficient depth such that the concentric inner and outer trench openings extend beyond the buried n-type buried layer. In selected embodiments, the etching process may be controlled to form trench openings extending 2um to 10um below the bottom junction depth of the buried n-type layer.

[0043] In step 54, a concentric floating polysilicon structure is formed in the concentric inner trench and outer trench opening to define at least a portion of the isolation region of the isolation structure. With respect to manufacturing step 54, a plurality of steps may be used to form the floating polysilicon structure, such as by depositing a conformal thick isolation layer on the sidewalls of the concentric inner trench and outer trench opening. In a selected embodiment, the thick isolation layer may be formed to a controlled thickness with an oxide, a nitride, or a combination of both. Subsequently, the remainder of the concentric inner trench and outer trench opening is filled with a conductive fill material, such as by depositing a highly doped polysilicon plug to fill the trench opening. If desired, one or more processing steps may be applied to planarize the concentric floating polysilicon structure with the remainder of the substrate, such as by applying a polishing step to the surface of the substrate. It will be appreciated that the concentric floating polysilicon structure may be formed and positioned to surround and protect a first isolation n-well region, where a BCD device will subsequently be formed. In addition, one or more shallow trench isolation structures can be formed above the substrate and the concentric floating polysilicon structure by patterning and etching shallow trench openings in the upper surface of the substrate, filling the openings with one or more insulating dielectric layers, and then polishing or planarizing the filling layers down to the surface of the substrate to form a shallow trench isolation (STI) structure above the concentric floating polysilicon structure.

[0044] In step 55, before or after forming the concentric floating polysilicon structure, a central n-well is formed in the upper p-type epitaxial layer and the buried n-type layer to be surrounded by the floating polysilicon structure in the inner trench. With respect to manufacturing step 55, a plurality of steps may be used to form the central n-well in the upper p-type epitaxial layer, such as by using any suitable pattern, mask, and implantation steps. For example, a first implantation mask may be formed above a substrate having a defined opening, the defined opening exposing a region of the upper p-type epitaxial layer surrounded by the inner trench where the inner floating polysilicon structure is located. Subsequently, a selective implantation process may be applied to form a high voltage n-well region 36 in the p-epi layer 33 so as to be completely contained within the inner trench where the inner floating polysilicon structure is located. For example, the selective implantation process may implant n-type impurities at a predetermined density and energy to define the HV n-well 36 to extend down to a depth of the n-type buried layer 32.

[0045] In step 56, before or after forming the central n-well, an n-well ring is formed in the upper p-type epitaxial layer to be located between the inner trench and the outer trench and surrounding the central n-well. With respect to manufacturing step 56, a plurality of steps may be used to form the n-well ring in the upper p-type epitaxial layer, such as by using any suitable pattern, mask, and implantation steps. For example, a second implantation mask may be formed above a substrate having a defined opening, the defined opening exposing a region in the upper p-type epitaxial layer between the inner trench and the outer trench where the floating polysilicon structure is formed. Subsequently, a selective implantation process may be applied to form an n-well ring 37 in the p-epi layer 33 so as to be located between the inner trench and the outer trench where the floating polysilicon structure is located. For example, the selective implantation process may implant n-type impurities at a predetermined density and energy to limit the shallow implantation regions 37A, 37B to a depth that partially, but not completely, extends downward to the n-type buried layer 32. In other embodiments, the selective implant process may implant the shallow implant regions 37A, 37B to a depth of 20% to 80% of the inner and outer trench depths.

[0046] In step 57, one or more active devices are formed at least in the central n-well region. With respect to manufacturing step 57, multiple steps may be used to form active devices, such as additional well regions, gate electrodes, and associated source / drain regions, on the surface of the central n-well. For example, the well region may be formed by doping the upper p-type epitaxial layer using any suitable dopant implantation process to define an n-type or p-type well region. Additionally, the gate electrode may be selectively formed by depositing, patterning, and etching a conductive polysilicon layer formed above one or more gate dielectric layers, and then used with one or more selective masks to implant source and / or drain regions. It will be appreciated that other device regions, such as shallow trench insulators or resistors, may also be formed at this time.

[0047] In step 58, one or more metal interconnect structures are formed over the upper p-type epitaxial layer to electrically connect and short the central n-well and surrounding n-well rings together, and to electrically connect and short the concentric floating polysilicon structures formed in the concentric inner and outer trenches together. With respect to fabrication step 58, the metal interconnect structures may be formed using multiple steps, such as by using a damascene process to form one or more patterned conductive interconnect layers 39, 40 to extend through patterned openings in the insulator layer 38 to make direct shorting electrical contacts between the well regions 36, 37 or between the floating polysilicon structures 35A, 35B. The processing at step 58 may also form interconnect paths having defined silicide layers and connecting metallization conductors (MC) formed in the stack of dielectric layers to form direct shorting electrical contacts between the well regions 36, 37 or between the floating polysilicon structures 35A, 35B.

[0048] At step 59, the manufacturing method 5 ends. At this point, the manufacture of the semiconductor device can continue with singulation into individual integrated circuit dies and additional packaging steps. Of course, the order of the actions described above can be changed to form specific device regions and features required for any specific integrated circuit application. It should be understood that additional processing steps will be used to manufacture the semiconductor devices described herein, such as nitride strip processing, preparation and formation of one or more sacrificial oxide layers, shallow trench isolation regions, and the formation of various buried wells or regions. In addition, other circuit features, such as capacitors, diodes, etc., can be formed on the wafer structure. For example, one or more sacrificial oxide formation, stripping, isolation region formation, well region formation, gate dielectric and electrode formation, extension implantation, halogen implantation, spacer layer formation, source / drain implantation, thermal drive or annealing steps and polishing steps, as well as conventional back-end processing (not depicted), typically including the formation of multiple levels of interconnects for connecting transistors in a desired manner to achieve the desired functionality, can be performed. Therefore, depending on the process and / or design requirements, the specific sequence of steps used to complete the manufacture of the semiconductor structure can be changed.

[0049] Although the described exemplary embodiments disclosed herein relate to various manufacturing processes and integrated circuit designs with isolation structures that employ high-voltage trough designs having electrically shorted concentric floating polysilicon structures, electrically shorted isolated n-wells, and surrounding shallowly implanted n-well rings, the present invention need not be limited to exemplary embodiments that illustrate inventive aspects of the present invention applicable to various transistor manufacturing processes and / or structures. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the present invention, because the present invention may be modified and practiced in different but equivalent ways that are obvious to those skilled in the art who benefit from the teachings herein. For example, although various devices shown herein are used to form high-voltage troughs with isolated n-well regions, etc., this is only for convenience of explanation and is not intended to be limiting, and those skilled in the art should understand that the principles taught herein are applicable to devices of any conductivity type. In addition, the well region is described as being formed by injecting n-type dopants into the p-type upper semiconductor layer, but the opposite method may be used instead by injecting p-type dopants into the n-type upper semiconductor layer. Therefore, the identification of a particular region as N-type or P-type is by way of illustration only and not limitation, and regions of opposite conductivity types may be substituted to form devices of opposite conductivity types. In addition, the thickness and doping concentration of the described layers may be adjusted as required for the desired application. Accordingly, the above description is not intended to limit the invention to the specific form set forth, but rather is intended to cover such alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art should understand that they may make various changes, substitutions and modifications in their broadest form without departing from the spirit and scope of the invention.

[0050] The terms "first", "second", "third", "fourth", etc. (if any) in the embodiments and claims may be used to distinguish similar elements and are not necessarily used to describe a specific sequence or time order. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the invention described herein are, for example, capable of operating in a sequence other than that shown or otherwise described herein. In addition, the terms "including", "having", and any variants thereof are intended to cover non-exclusive inclusions, such that a process, method, article, or device comprising a series of elements need not be limited to those elements, but may also include other elements that are not explicitly listed or that are not inherent to such processes, methods, articles, or devices. The term "coupled" as used herein is defined as being connected directly or indirectly in an electrical or non-electrical manner.

[0051] As used herein, the term "semiconductor" is intended to include any semiconductor in single crystal, polycrystalline or amorphous form, and includes type IV semiconductors, non-type IV semiconductors, compound semiconductors, and organic and inorganic semiconductors. In addition, the terms "substrate" and "semiconductor substrate" are intended to include single crystal structures, polycrystalline structures, amorphous structures, thin film structures, layered structures (e.g., semiconductor on insulator (SOI) structures), and combinations thereof. For ease of explanation and not intended to be limiting, semiconductor components and manufacturing methods for silicon semiconductors are described herein, but those skilled in the art will understand that other semiconductor materials may also be used.

[0052] As used herein, the term "floating" refers to an electrical condition in which an integrated circuit structure (eg, a polysilicon structure) is not connected to a voltage source or fixed reference such as a ground voltage, and / or is not electrically connected to another non-floating (grounded) conductor.

[0053] The benefits, other advantages, and solutions to problems are described above with respect to specific embodiments. However, those benefits, advantages, solutions to problems, and any elements that may cause any benefit, advantage, or solution to occur, or become more significant, shall not be construed as key, required, or essential features or elements of any or all claims. As used herein, the term "comprises" or any other variation thereof is intended to encompass non-exclusive inclusions, such that a process, method, article, or device that includes a list of elements may include not only those elements, but may include other elements that are not explicitly listed or inherent to such process, method, article, or device.

Claims

1. An integrated circuit device, characterized in that: include: a substrate of a first conductivity type; A buried layer of a second conductivity type located in the substrate; a central isolation region of the second conductivity type, which is located above the buried layer; a first floating polysilicon isolation structure located in the substrate to surround the central isolation region and extend down to and surround the buried layer; a second floating polysilicon isolation structure disposed in the substrate to surround the first floating polysilicon isolation structure; the shallow ring region of the second conductivity type located in the substrate between at least a portion of the first floating polysilicon isolation structure and a portion of the second floating polysilicon isolation structure; and a first conductive interconnect structure for electrically shorting the central isolation region to the shallow ring region, The first floating polysilicon isolation structure is short-connected to the second floating polysilicon isolation structure.

2. The integrated circuit device according to claim 1, wherein: The buried layer extends laterally only below the central isolation region and does not extend laterally beyond the first floating polysilicon isolation structure.

3. The integrated circuit device according to claim 1, wherein: The first and second floating polysilicon isolation structures each include a polysilicon structure formed in an insulating liner layer.

4. The integrated circuit device according to claim 1, wherein: The central isolation region is electrically shorted to the shallow ring region through the first conductive interconnect structure formed with a metal interconnect structure formed above the substrate to electrically connect the central isolation region to the shallow ring region.

5. The integrated circuit device according to claim 1, wherein: The first and second floating polysilicon isolation structures are electrically shorted by a second conductive interconnect structure having a metal interconnect structure formed above the substrate to electrically connect the first floating polysilicon isolation structure to the second floating polysilicon isolation structure; or the first and second floating polysilicon isolation structures are electrically shorted by a second conductive interconnect structure having an insulating polysilicon interconnect structure formed in the substrate to electrically connect the first floating polysilicon isolation structure to the second floating polysilicon isolation structure.

6. The integrated circuit device according to claim 1, wherein: The shallow ring region extends at least partially down to the buried layer, and wherein both the first and second floating polysilicon isolation structures extend beyond the buried layer into the substrate.

7. The integrated circuit device according to claim 1, wherein: When the central isolation region is set to a potential greater than zero relative to the substrate, a voltage across the peripheral end of the buried layer to the substrate is less than a voltage across the central portion of the buried layer to the substrate.

8. The integrated circuit device according to claim 1, wherein: The shallow ring region of the second conductivity type and an underlying portion of the substrate of the first conductivity type form a through structure configured to pull up the potential of the first floating polysilicon isolation structure when the central isolation region is set to a potential greater than zero relative to the substrate.

9. An integrated circuit device, characterized in that: include: substrate; An n-type buried layer is located in the substrate; an isolated n-type region located above the n-type buried layer, the isolated n-type region and the n-type buried layer being vertically aligned; a first floating polysilicon isolation trench concentrically disposed in the substrate to surround the isolation n-type region; a shallow n-type well region at least partially disposed in the substrate to surround the first floating polysilicon isolation trench; a second floating polysilicon isolation trench concentrically disposed in the substrate to surround the shallow n-type well region; as well as a first conductive interconnect structure connected to electrically short the isolated n-type region to the shallow n-type well region; and The first floating polysilicon isolation trench is electrically connected to the second floating polysilicon isolation trench.

10. A method, characterized in that include: forming a buried layer of a first conductivity type in a substrate of a second conductivity type; forming a central region of the first conductivity type in the substrate in contact with the buried layer; forming a first floating isolation trench in the substrate to surround the central region and extend down to and surround the buried layer; forming a second floating isolation trench in the substrate around the first isolation trench; forming a shallow ring region of the first conductivity type in the substrate between at least a portion of the first floating isolation trench and a portion of the second floating isolation trench; as well as forming a first conductive interconnect structure for electrically shorting the central region to the shallow ring region, The first floating isolation trench is short-connected to the second floating isolation trench.

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