Semiconductor device terminal structure and manufacturing process thereof

Abstract

The invention discloses a semiconductor device terminal structure and a manufacturing process thereof. The semiconductor device terminal structure is arranged in an N-P-N type doped wide bandgap semiconductor epitaxial wafer. According to the structure, an N-type doped electric field cut-off region and an N-type doped charge compensation region are arranged in a P-type doped buried layer through ion implantation or epitaxy and ion implantation, and the deepest position of the N-type doped electric field cut-off region exceeds the P-type doped buried layer and goes deep into an N-type doped drift region. According to the structure, the effect that the equivalent acceptor impurity atomic weight of the P-type doped buried layer is gradually reduced in the direction from the main junction region to the terminal region and in the direction from the cutting channel region to the terminal region can be achieved by adjusting the interval, the size and the doping of at least one N-type doped charge compensation region, and finally the curvature effect of the main junction region is reduced, and the performance of the device is improved. The problem of electric field concentration near the main junction is relieved, and the problem that the main junction of the power device breaks down in advance is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device terminal structure and a manufacturing process thereof. Background Art

[0002] Traditional silicon devices are limited by their own material properties, and further performance improvements are hoped to rely on higher performance semiconductor materials.

[0003] SiC and Ga 2 O 3 The third and fourth generation wide bandgap semiconductor materials represented by Si came into being. Wide bandgap semiconductor materials have more advantages than Si in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity.

[0004] In power switch applications, SiC, Ga 2 O 3 The prepared power devices such as diodes, transistors and power integrated circuits have smaller areas and better electrical characteristics. In today's power electronics applications with higher power density and lower power consumption requirements, SiC and Ga 2 O 3 The material has greater research significance and broader market application prospects.

[0005] In the blocking state, the device mainly bears voltage through the depletion region formed by the PN junction under reverse bias. According to Poisson's equation, the peak value of the electric field strength in the depletion region is located near the PN junction. When the peak value of the electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will be broken down.

[0006] In the actual preparation process, cylindrical junctions and spherical junctions are formed at the edges and corners of the PN junction. Under the effect of curvature, the electric field near the cylindrical junction and spherical junction is more concentrated, and the electric field strength is much greater than the electric field strength of the parallel plane junction in the middle area. The edges and corners will break down before the parallel plane junction, resulting in the breakdown voltage of the device being much lower than the ideal case. Figure 1 shown.

[0007] In order to alleviate the problem of premature breakdown of the edges and corners of the PN junction (main junction of the device) due to the curvature effect, resulting in reduced device blocking ability, the industry often adds a junction terminal structure around the PN junction (main junction). The introduced junction terminal structure can disperse the electric field originally concentrated at the edge of the main junction, thereby reducing the electric field strength at the edge of the main junction and making the device breakdown voltage closer to the ideal value of a parallel plane junction.

[0008] Commonly used junction terminal structures include field plates, tables, junction terminal extensions and field limiting rings, such as Figure 2 shown.

[0009] The principle of the field plate (FP) structure is to expand the depletion layer on the junction terminal surface by applying an external voltage on the field plate, thereby alleviating the electric field concentration phenomenon at the edge of the PN junction. The principle of the mesa (MESA) structure is to widen the depletion region width at the PN junction by etching the slope, thereby reducing the electric field concentration phenomenon.

[0010] The Junction Termination Extension (JTE) structure expands the depletion region of the P+ main junction through its own depletion, thereby reducing the electric field concentration phenomenon at the main junction. The existence of the Field Limiting Ring (FLR) structure is equivalent to adding a voltage divider to the edge of the main junction of a planar power device. By reasonably optimizing the amount, ring width, doping concentration and ring spacing of the FLR, the width of the main junction depletion region can be effectively widened, the electric field concentration phenomenon of the main junction and the ring can be reduced, and the breakdown voltage can be increased.

[0011] However, the existing junction termination technology still has some problems. Taking SiC material as an example, the main technical defects are as follows: Technical defect 1: Although the junction termination technology is relatively mature for Si materials, due to the extremely low diffusion coefficient of impurities in SiC materials, the doping of SiC materials is often done through high-temperature ion implantation to form a shallow PN junction, which results in a smaller radius of curvature of the PN junction of SiC power devices, easier concentration of the electric field, and further reduction of the device's blocking capability and the protection capability of the junction termination. In addition, with the development of device structure design capabilities, NPN epitaxial layers have emerged, but due to the limitation of injection capabilities, the existing terminals cannot well protect the main junction of NPN epitaxial layer devices.

[0012] Technical defect 2: In a high-voltage, high-temperature, and high-humidity environment, charge accumulation, moisture corrosion, ion migration, and other phenomena will occur at the terminal, and the electrode on the front of the device and the cutting path may be short-circuited. At this time, the cutting path and the back electrode, and the main junction and the back electrode need to withstand the blocking voltage of the device. The traditional terminal structure only protects the main junction, but ignores the protection of the cutting path area, resulting in increased leakage current in the cutting path area or premature breakdown in the cutting path area, and the breakdown voltage of the device is lower than the ideal value.

[0013] Technical defect 3: On the outside of the junction terminal and at the edge of the device, that is, the cutting path area of ​​the device. When the device is in the blocking state, the potential of the cutting path area is equal to the bus voltage, while the potential of the electrode in the middle of the front of the device is 0V, which means that there is a huge potential difference between the electrode and the cutting path, and air breakdown may occur between the front electrode and the cutting path, causing the device to burn out.

[0014] Technical defect 4: The semiconductor surface and the outer side of the device may have unknown charges due to crystal defects and working environment factors. This part of the charge will affect the electric field distribution at the device terminal, making the actual electric field distribution different from the design value, causing the device to break down prematurely. Summary of the invention

[0015] In view of the problem that the existing junction terminal structure is unable to well protect the main junction of the power device due to the limitations of the material thermal diffusion coefficient, ion implantation depth and the like, especially the problem that air breakdown occurs between the surface electrode and the cutting path of the NPN power device and the existing terminal structure cannot protect the cutting path area, which ultimately leads to a serious reduction in the breakdown voltage of the device, the present invention provides a new junction terminal structure and its manufacturing process.

[0016] The technical solution of the present invention to solve the above technical problems is as follows: The present invention provides a new junction terminal structure, wherein the semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer; This structure sets an N-type doped electric field cutoff region and an N-type doped charge compensation region in a P-type doped buried layer by ion implantation, or epitaxy + ion implantation. The deepest part of the N-type doped electric field cutoff region needs to exceed the P-type doped buried layer and go deep into the N-type doped drift region, that is, the N-type doped electric field cutoff region needs to penetrate the P-type doped buried layer; at least one of the N-type doped charge compensation regions and the N-type doped electric field cutoff region can be formed by gradually reducing the distance between the charge compensation regions in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region, or gradually increasing the volume of the charge compensation regions, or gradually increasing the doping concentration of the charge compensation regions, or by other means so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region is gradually reduced.

[0017] This structure can achieve the effect of gradually reducing the equivalent acceptor impurity atomic mass of the P-type doped buried layer from the main junction area to the terminal area and from the cutting road area to the terminal area by adjusting the interval, volume, and doping concentration of at least one N-type doped charge compensation area, and ultimately play a role in reducing the curvature effect of the main junction area, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device. Adjusting the volume of the N-type doped charge compensation area includes adjusting the width, and / or depth, and / or thickness.

[0018] More specifically, A semiconductor device terminal structure, the semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, the wide bandgap semiconductor epitaxial wafer comprises a main junction region, a terminal region and a cutting path which are sequentially connected and include a P-type doped buried layer; In this structure, an N-type doped electric field cutoff region and an N-type doped charge compensation region are arranged in a P-type doped buried layer by means of ion implantation or epitaxy + ion implantation. The deepest part of the N-type doped electric field cutoff region exceeds the P-type doped buried layer and penetrates into the N-type doped drift region. By changing the spacing, and / or volume, and / or doping concentration of the N-type doped charge compensation region, the closer the P-type doped buried layer is to the N-type doped electric field cutoff region in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region, the lower the equivalent acceptor impurity atomic weight of the P-type doped buried layer; Changing the volume includes changing the depth, and / or width, and / or thickness.

[0019] Furthermore, in the above-mentioned semiconductor device terminal structure, the wide bandgap semiconductor epitaxial wafer comprises an N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, an N-type doped current diffusion layer, and a P-type doped main junction region connected in sequence from bottom to top, the side of the N-type doped substrate away from the P-type doped buried layer is connected to a cathode, the side of the P-type doped main junction region away from the P-type doped buried layer is connected to an anode, the end close to the anode forms a main junction region, the end away from the anode forms a cutting path, and the middle is a terminal region; A first insulating dielectric layer for isolating metal ions, a second insulating dielectric layer for isolating water vapor, and a third insulating dielectric layer for isolating an external electric field are sequentially connected above the P-type doped main junction region, and one end of the three insulating dielectric layers close to the anode is connected to the anode; The N-type doped electric field cutoff region is connected to the middle of the terminal region, the N-type doped charge compensation region is connected to the terminal region and is distributed on the left and right sides of the N-type doped electric field cutoff region, and the number of the N-type doped charge compensation regions on each side is not less than one.

[0020] Furthermore, in the above-mentioned semiconductor device terminal structure, the N-type doped electric field stop region, at least one N-type doped charge compensation region on the left side, and at least one N-type doped charge compensation region on the right side are connected, so that both sides of the N-type doped electric field stop region form a step-shaped structure inclined toward it.

[0021] Furthermore, in the above-mentioned semiconductor device terminal structure, the closer to the N-type doped electric field cut-off region, the smaller the spacing between the N-type doped charge compensation regions, and / or the larger the volume, and / or the higher the doping concentration, and the larger the volume includes the deeper the depth, and / or the wider the width, and / or the thicker the thickness.

[0022] Furthermore, in the above-mentioned semiconductor device terminal structure, the N-type doped charge compensation regions have the same area, but the closer to the N-type doped electric field cut-off region, the smaller the interval between adjacent N-type doped charge compensation regions; or The N-type doped charge compensation regions have the same spacing and width, but the closer they are to the N-type doped electric field cut-off region, the deeper the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing and depth, but the closer they are to the N-type doped electric field cut-off region, the wider the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing, depth and interval, but the closer they are to the N-type doped electric field cut-off region, the higher the doping concentration of the N-type doped charge compensation region; or Increase the depth of the P-type doped main junction region so that the P-type doped main junction region and the P-type doped buried layer are connected and the N-type doped current diffusion layer is completely swallowed up; or The terminal structures on the left and right sides of the terminal area are different.

[0023] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the first insulating dielectric layer is silicon oxide; and / or The material of the second insulating dielectric layer is silicon nitride; and / or The third insulating medium layer is made of silicon oxide.

[0024] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

[0025] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the N-type doped substrate is SiC, GaN, Ga 2 O 3 , C or AlN.

[0026] Furthermore, the above-mentioned semiconductor device terminal structure is subjected to opposite type of doping, that is, N-type doping is changed to P-type doping, and P-type doping is changed to N-type doping.

[0027] A process for manufacturing a semiconductor device terminal structure as described in any one of the above, comprising the following steps: Growing an N-type doped drift region on a wide bandgap semiconductor material substrate; Forming a P-type doped buried layer by ion implantation, epitaxy or growing a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; Forming an N-type doped electric field cutoff region and an N-type doped charge compensation region by ion implantation or epitaxy + ion implantation; forming a P-type doped main junction region by ion implantation or the like; The first insulating dielectric layer, the second insulating dielectric layer and the third insulating dielectric layer are deposited and etched, and metal is deposited and etched on the front and back sides to form anode and cathode electrodes.

[0028] In the above-mentioned manufacturing process of the terminal structure of a semiconductor device, after forming a P-type doped buried layer, an N-type doped electric field cutoff region and an N-type doped charge compensation region are first formed, and then an N-type doped current diffusion layer is formed.

[0029] Compared with the prior art, the present invention has the following beneficial effects: In this structure, there is at least one N-type doped charge compensation region and an N-type doped electric field cutoff region on the left side near the anode (i.e., the main junction region), formed by a P-type doped buried layer in which the equivalent acceptor impurity atomic mass gradually decreases in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0030] The P-type doped buried layer formed by at least one N-type doped charge compensation region and an N-type doped electric field cut-off region near the cutting path area on the right side of the structure, in which the equivalent acceptor impurity atomic mass gradually decreases in the direction away from the cutting path area, can reduce the curvature effect of the cutting path area, alleviate the problem of electric field concentration near the cutting path, prevent the cutting path area from breaking down prematurely after the cutting path surface is short-circuited with the anode metal (front electrode of the device), and solve technical defect 2.

[0031] In the blocking state of the device, the P-type doped buried layer can play a role in isolating the cathode (the electrode on the back of the device) potential and leakage current, solving technical defects 2 and 3.

[0032] Because the electric field and potential from the cathode are shielded by the P-type doped buried layer, the P-type doped main junction region located on the device surface can ignore the electric field concentration effect, and a highly doped P-type doped main junction region can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure in which the curvature effect of the PN junction edge leads to electric field concentration in the background technology of the present invention; Figure 2 Schematic diagram of a common terminal structure in the background technology of the present invention, (a) field plate; (b) table; (c) junction terminal extension; (d) field limiting ring; Figure 3 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 1 of the present invention; Figure 4 It is a schematic diagram of doping concentration distribution structure of a simulated structure of a portion of the terminal structure near the main junction region on the left side of the embodiment 1 of the present invention; Figure 5 is a breakdown characteristic curve diagram of the terminal structure of Example 1 of the present invention; Figure 6 for Figure 4 Potential distribution diagram on AA' tangent line; Figure 7 for Figure 4 The electric field intensity distribution diagram on the AA' tangent line; Figure 8 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 2 of the present invention; Fig. 9 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 3 of the present invention; Fig.10 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 4 of the present invention; Fig.11 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 5 of the present invention; Fig.12 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 6 of the present invention; Fig.13 This is a schematic structural diagram of a semiconductor device terminal structure according to Embodiment 7 of the present invention; Fig.14 In the process for manufacturing the terminal structure of Embodiment 12 of the present invention, an N-type doped drift region is grown on a wide bandgap semiconductor material substrate; Fig.15 The P-type doped buried layer is formed by ion implantation, epitaxy, growth of P-type oxide, etc. in the terminal structure manufacturing process of embodiment 12 of the present invention; Fig.16 The N-type doped current diffusion layer is formed by epitaxy in the terminal structure manufacturing process of embodiment 12 of the present invention; Fig.17 The N-type doped electric field cut-off region and the N-type doped charge compensation region are formed by ion implantation or the like in the terminal structure manufacturing process of embodiment 12 of the present invention; Fig.18 The P-type doped main junction region is formed by ion implantation or the like in the terminal structure manufacturing process of embodiment 12 of the present invention; Fig.19 Forming an N-type doped charge compensation region and an N-type doped electric field cutoff region in the terminal structure manufacturing process of embodiment 13 of the present invention; Fig. 20 This is the process for forming an N-type doped current diffusion layer in the terminal structure manufacturing process of embodiment 13 of the present invention.

[0034] In the accompanying drawings, the components represented by the reference numerals are listed as follows: 1. Main junction region; 2. Terminal region; 3. Cutting road; 4. Cathode; 5. N-type doped substrate; 6. N-type doped drift region; 7. P-type doped buried layer; 8. N-type doped current diffusion layer; 9. P-type doped main junction region; 10. Anode; 11. N-type doped electric field cutoff region; 12. N-type doped charge compensation region; 13. First insulating dielectric layer; 14. Second insulating dielectric layer; 15. Third insulating dielectric layer. DETAILED DESCRIPTION

[0035] In order to facilitate understanding of the present application, the present application will be described more comprehensively below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0037] It will be appreciated that spatial relationship terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be appreciated that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0038] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. The "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0039] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0040] The existing junction terminal structure is limited by the thermal diffusion coefficient of semiconductor materials, the depth of ion implantation, etc., and cannot well protect the main junction of power devices, especially the main junction of NPN epitaxial wafer structure (technical defect 1); the short circuit may occur between the surface electrode of the power device and the cutting path 3, and the existing terminal structure cannot protect the cutting path 3 area, which eventually leads to a serious reduction in the breakdown voltage of the device (technical defect 2); the problem that air breakdown is prone to occur in the cutting path 3 area (technical defect 3); the semiconductor surface and the outside of the device may have charges of unknown charge due to crystal defects and working environment factors. This part of the charge will affect the electric field distribution of the device terminal, making the actual electric field distribution different from the design value, resulting in premature breakdown of the device (technical defect 4). The present invention provides a new junction terminal structure and its manufacturing process.

[0041] The semiconductor material used in this solution takes SiC as an example. By replacing the semiconductor material in this solution with other semiconductor materials, such as Si, GaN, Ga 2 O 3 , AlN, diamond (C), etc.; by applying opposite type of doping to the semiconductor material in this scheme, such as changing N-type doping to P-type doping, and changing P-type doping to N-type doping, the same is applicable and is within the scope of protection of the present invention.

[0042] The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, wherein the wide bandgap refers to a semiconductor with a bandgap width greater than 2.2 eV; In this structure, an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 are arranged in the P-type doped buried layer 7 by means of ion implantation, or epitaxy + ion implantation. The deepest part of the N-type doped electric field stop region 11 needs to exceed the P-type doped buried layer 7 and go deep into the N-type doped drift region 6, that is, the N-type doped electric field stop region 11 needs to penetrate the P-type doped buried layer 7; at least one of the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 can be achieved by gradually reducing the distance between the charge compensation regions in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2, and / or gradually increasing the volume of the charge compensation region and / or gradually increasing the doping concentration of the charge compensation region, and / or other forms so that the equivalent acceptor impurity atomic amount of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 presents a trend of gradually decreasing. The gradual increase in the volume of the charge compensation region includes a gradual increase in the thickness of the charge compensation region, and / or a gradual increase in the depth of the charge compensation region, and / or a gradual increase in the width of the charge compensation region. The gradual decrease here can be formed by the N-type doped charge compensation region 12 and the N-type doped electric field cut-off region 11, or can be formed by adjacent N-type doped charge compensation regions.

[0043] This structure can achieve the effect of gradually reducing the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2 by adjusting the spacing, volume, doping concentration, etc. of at least one N-type doped charge compensation region 12, and ultimately play a role in reducing the curvature effect of the main junction region 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device. The volume adjustment includes adjusting the thickness, and / or width, and / or depth.

[0044] In this structure, a P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1, formed by at least one N-type doped charge compensation region 12 on the left side near the anode 10 (i.e., the main junction region 1), can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0045] The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting path 3 region, formed by at least one N-type doped charge compensation region 12 near the cutting path 3 region on the right side of the present structure, can reduce the curvature effect of the cutting path 3 region, alleviate the problem of electric field concentration near the cutting path 3, and prevent the cutting path 3 region from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 10 metal (the front electrode of the device), thereby solving technical defect 2.

[0046] In the blocking state of the device, the P-type doped buried layer 7 can block the cathode 4 (device back electrode) potential and leakage current, solving technical defects 2 and 3.

[0047] Because the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4.

[0048] In view of technical defect 1: the present structure arranges an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 in the P-type doped buried layer 7 by means of ion implantation, or epitaxy + ion implantation. The deepest part of the N-type doped electric field stop region 11 needs to exceed the P-type doped buried layer 7 and penetrate into the P-type doped buried layer 7, that is, the N-type doped electric field stop region 11 needs to penetrate the P-type doped buried layer 7; at least one of the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 can be achieved by gradually reducing the distance between the charge compensation regions in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 and / or gradually increasing the volume of the charge compensation region and / or gradually increasing the doping concentration of the charge compensation region, and / or other forms to gradually reduce the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2. The gradual increase in the volume of the charge compensation region includes a gradual increase in the width of the charge compensation region and / or a gradual increase in the thickness of the charge compensation region and / or a gradual increase in the depth of the charge compensation region.

[0049] In this structure, a P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1, formed by at least one N-type doped charge compensation region 12 and an N-type doped electric field cut-off region 11 on the left side near the anode 10 (main junction region 1), can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0050] Regarding technical defect 2: The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting path 3 region, formed by at least one N-type doped charge compensation region 12 near the cutting path 3 region on the right side of the structure, can reduce the curvature effect of the cutting path 3 region, alleviate the problem of electric field concentration near the cutting path 3, and prevent the cutting path 3 region from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 10 metal (the front electrode of the device).

[0051] Regarding technical defect 3: in the blocking state of the device, the P-type doped buried layer 7 can play a role in isolating the cathode 4 (the back electrode of the device) potential and leakage current.

[0052] Regarding technical defect 4: the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, so the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device.

[0053] Example 1 A semiconductor device terminal structure, wherein the semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, such as Figure 3 shown.

[0054] The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer; The wide bandgap semiconductor epitaxial wafer comprises an N-type doped substrate 5, an N-type doped drift region 6, a P-type doped buried layer 7, an N-type doped current diffusion layer 8, and a P-type doped main junction region 91 which are sequentially connected from bottom to top, wherein the side of the N-type doped substrate 5 away from the P-type doped buried layer 7 is connected to a cathode 4, and the side of the P-type doped main junction region 91 away from the P-type doped buried layer 7 is connected to an anode 10, an end close to the anode 10 forms a main junction region 1, and an end away from the anode 10 forms a cutting path 3, and the middle is a terminal region 2; In this structure, an N-type doped electric field stop region 11 and an N-type doped charge compensation region 12 are arranged in a P-type doped buried layer 7 by means of ion implantation or epitaxy + ion implantation. The N-type doped electric field stop region 11 is at its deepest point beyond the P-type doped buried layer 7 and penetrates into the N-type doped drift region 6. By changing the spacing, and / or volume, and / or doping concentration of the N-type doped charge compensation region 12, the P-type doped buried layer 7 is closer to the N-type doped electric field stop region 11 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2, the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 is lower. Changing the volume of the N-type doped charge compensation region 12 includes changing the width, and / or depth, and / or thickness.

[0055] The P-type doped main junction region 91 is sequentially connected with a first insulating dielectric layer 13 for isolating metal ions, a second insulating dielectric layer 14 for isolating water vapor, and a third insulating dielectric layer 15 for isolating an external electric field, and one end close to the anode 10 is connected to the anode 10; The N-type doped electric field stop region 11 is connected to the middle of the terminal region 2, and the N-type doped charge compensation region 12 is connected to the terminal region 2 and distributed on the left and right sides of the N-type doped electric field stop region 11, and the number of the N-type doped charge compensation regions 12 on each side is not less than one.

[0056] The material of the first insulating dielectric layer 13 is silicon oxide; the material of the second insulating dielectric layer 14 is silicon nitride; and the material of the third insulating dielectric layer 15 is silicon oxide.

[0057] The doping element of the N-type doped drift region 6 is nitrogen; the doping element of the P-type doped buried layer 7 is aluminum or boron; the doping element of the N-type doped current diffusion layer 8 is nitrogen; and the doping element of the P-type doped main junction region 9 is aluminum or boron.

[0058] In order to more intuitively demonstrate the effect of this structure, the protection effect of the terminal left side structure on the main junction is demonstrated by simulation software, such as Figure 4~Figure 7 shown.

[0059] It can be seen from the breakdown characteristic curve that the terminal structure of the present invention achieves a withstand voltage of more than 1600V on an 11μm SiC epitaxial layer, and at least one N-type doped charge compensation region plays a role in dispersing the potential and electric field strength distribution, avoiding the problem of premature breakdown caused by excessive concentration of the electric field at the edge of the main junction.

[0060] Example 2 Example 2 is substantially the same as Example 1, except that Figure 8 As shown, in addition to the solution of injecting at least one N-type doped charge compensation region 12 in Embodiment 1, a single multi-level N-type doped charge compensation region 12 can also be formed to achieve the effect of gradually reducing the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 from the main junction region 1 to the terminal region 2 and from the cutting road 3 region to the terminal region 2, thereby ultimately reducing the curvature effect of the main junction region 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device. That is, unlike the N-type doped electric field stop region 11, at least one N-type doped charge compensation region 12 on the left, and at least one N-type doped charge compensation region 12 on the right in Embodiment 1, which are independent of each other, the N-type doped electric field stop region 11, at least one N-type doped charge compensation region 12 on the left, and at least one N-type doped charge compensation region 12 on the right in this embodiment are connected, so that both sides of the N-type doped electric field stop region 11 form a step-shaped structure inclined toward it.

[0061] Example 3 Example 3 is substantially the same as Example 1, except that Fig. 9As shown, unlike Example 1, the area of ​​the N-type doped charge compensation region 12 becomes larger as it is closer to the N-type doped electric field stop region 11, the area of ​​the N-type doped charge compensation region 12 in this embodiment is the same, but the closer to the N-type doped electric field stop region 11, the smaller the interval between adjacent N-type doped charge compensation regions 12, so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 gradually decreases.

[0062] Example 4 Example 4 is substantially the same as Example 1, except that Fig.10 As shown, the N-type doped charge compensation regions 12 of this embodiment have the same spacing and width, but the closer to the N-type doped electric field cut-off region 11, the deeper the N-type doped charge compensation region 12 is, so that the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 gradually decreases.

[0063] Example 5 Example 5 is substantially the same as Example 1, except that Fig.11 As shown, the N-type doped charge compensation regions 12 of this embodiment have the same spacing and depth, but the closer to the N-type doped electric field cut-off region 11, the wider the N-type doped charge compensation region 12 is, so that the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 gradually decreases.

[0064] Example 6 Example 6 is substantially the same as Example 1, except that Fig.12 As shown, the N-type doped charge compensation regions 12 of the present embodiment have the same pitch, depth and spacing, but the closer to the N-type doped electric field cut-off region 11, the higher the doping concentration of the N-type doped charge compensation region 12, so that the equivalent acceptor impurity atomic mass of the P-type doped buried layer 7 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 gradually decreases.

[0065] Example 7 Example 7 is substantially the same as Example 1, except that Fig.13 As shown, the depth of the P-type doped main junction region 9 is increased so that the P-type doped main junction region 9 and the P-type doped buried layer 7 are connected, that is, the P-type doped main junction region 9 swallows up the N-type doped current diffusion layer 8.

[0066] Example 8 Example 8 is basically the same as Example 1, except that the terminal structures on the left and right sides of the terminal area 2 may be different, that is, the terminal protection structure for the main junction and the terminal protection structure for the cutting path 3 may be freely combined. For example, the terminal structure on the left side is achieved by changing the spacing of the N-type doped charge compensation area 12, and the terminal structure on the right side is achieved by changing the doping concentration of the N-type doped charge compensation area 12.

[0067] Example 9 The semiconductor material used in the above embodiment is SiC. In this embodiment, the semiconductor material in the present invention can be replaced by other semiconductor materials, such as Si, GaN, Ga 2 O 3 , AlN, diamond (C), etc.

[0068] Example 10 Example 10 is basically the same as Example 1, except that the situation where the semiconductor material in this scheme is doped with the opposite type, such as changing N-type doping to P-type doping and P-type doping to N-type doping, is also applicable and is within the scope of protection of the present invention.

[0069] Embodiment 11 The difference between Example 11 and Example 1 is that the width of the charge compensation region is gradually increased, the thickness of the charge compensation region is gradually increased, and the depth of the charge compensation region is gradually increased, so as to achieve the effect of gradually increasing the volume of the charge compensation region, and the distance between the charge compensation regions is gradually reduced, and the doping concentration of the charge compensation region is gradually increased, so that the volume of the P-type doped buried layer 7 compensated in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting road 3 area to the terminal area 2 shows an increasing trend, that is, in this direction, the equivalent acceptor impurity atomic weight of the P-type doped buried layer 7 is gradually reduced.

[0070] Example 12 The specific manufacturing process of a semiconductor device terminal structure according to Embodiment 1 of the present invention is as follows: 1) In wide bandgap semiconductor materials (SiC / GaN / Ga 2 O 3 / C / AlN, etc.) substrate to grow an N-type doped drift region 6, such as Fig.14 As shown; 2) Forming a P-type doped buried layer 7 by ion implantation, epitaxy, growing a P-type oxide, etc. Fig.15 As shown; 3) Forming an N-type doped current diffusion layer 8 by epitaxy, such as Fig.16 As shown; 4) Forming an N-type doped electric field cutoff region 11 and an N-type doped charge compensation region 12 by ion implantation or the like, such as Fig.17 As shown; 5) Forming a P-type doped main junction region 9 by ion implantation or the like, such as Fig.18 As shown; 6) Deposit and etch the first insulating dielectric layer 13, the second insulating dielectric layer 14 and the third insulating dielectric layer 15, deposit and etch metal on the front and back sides to form the anode 10 and the cathode 4 electrodes, and form the following Figure 3 A terminal structure of a semiconductor device is shown.

[0071] Example 13 Embodiment 13 is substantially the same as Embodiment 12, except that some process steps are changed to realize the present structure. For example, an N-type doped charge compensation region 12 and an N-type doped electric field stop region 11 may be formed before the N-type doped current diffusion layer 8 is formed by epitaxial growth. Fig.19 shown.

[0072] Specifically, after forming the P-type doped buried layer 7, the N-type doped charge compensation region 12 and the N-type doped electric field stop region 11 are first formed by ion implantation or the like, as shown in FIG. Fig.19 As shown, an N-type doped current diffusion layer 8 is formed by epitaxy. Fig. 20 shown.

[0073] In this structure, a P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the main junction region 1, formed by at least one N-type doped charge compensation region 12 on the left side near the anode 10 (main junction region 1), can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, avoid the problem of premature breakdown of the main junction of the power device, and solve technical defect 1.

[0074] The P-type doped buried layer 7 with an equivalent amount of acceptor impurity atoms in the direction away from the cutting path 3 region, formed by at least one N-type doped charge compensation region 12 near the cutting path 3 region on the right side of the present structure, can reduce the curvature effect of the cutting path 3 region, alleviate the problem of electric field concentration near the cutting path 3, and prevent the cutting path 3 region from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 10 metal (the front electrode of the device), thereby solving technical defect 2.

[0075] In the blocking state of the device, the P-type doped buried layer 7 can block the cathode 4 (device back electrode) potential and leakage current, solving technical defects 2 and 3.

[0076] Because the electric field and potential from the cathode 4 are shielded by the P-type doped buried layer 7, the P-type doped main junction region 9 located on the surface of the device can ignore the electric field concentration effect, and a highly doped P-type doped main junction region 9 can be formed on the entire surface of the device. The advantage of this is that it shields the influence of charges on the device surface and the working environment on the electric field distribution inside the device, thereby solving technical defect 4.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device terminal structure, characterized in that: The semiconductor device terminal structure is arranged in an NPN-type doped wide bandgap semiconductor epitaxial wafer, wherein the wide bandgap semiconductor epitaxial wafer comprises a main junction region, a terminal region and a cutting path which are sequentially connected and include a P-type doped buried layer; In this structure, an N-type doped electric field cutoff region and an N-type doped charge compensation region are arranged in a P-type doped buried layer by means of ion implantation or epitaxy + ion implantation. The deepest part of the N-type doped electric field cutoff region exceeds the P-type doped buried layer and penetrates into the N-type doped drift region. By changing the spacing, and / or volume, and / or doping concentration of the N-type doped charge compensation region, the closer the P-type doped buried layer is to the N-type doped electric field cutoff region in the direction from the main junction region to the terminal region and in the direction from the cutting path region to the terminal region, the lower the equivalent acceptor impurity atomic weight of the P-type doped buried layer; Changing the volume includes changing the depth, and / or width, and / or thickness.

2. A semiconductor device terminal structure according to claim 1, characterized in that: The wide bandgap semiconductor epitaxial wafer comprises an N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, an N-type doped current diffusion layer, and a P-type doped main junction region which are sequentially connected from bottom to top, wherein the side of the N-type doped substrate away from the P-type doped buried layer is connected to a cathode, and one end of the P-type doped main junction region away from the P-type doped buried layer is connected to an anode, an end close to the anode forms a main junction region, and an end away from the anode forms a cutting path, with a terminal region in the middle; A first insulating dielectric layer for isolating metal ions, a second insulating dielectric layer for isolating water vapor, and a third insulating dielectric layer for isolating an external electric field are sequentially connected above the P-type doped main junction region, and one end of the three insulating dielectric layers close to the anode is connected to the anode; The N-type doped electric field cutoff region is connected to the middle of the terminal region, the N-type doped charge compensation region is connected to the terminal region and is distributed on the left and right sides of the N-type doped electric field cutoff region, and the number of the N-type doped charge compensation regions on each side is not less than one.

3. A semiconductor device terminal structure according to claim 1, characterized in that: The N-type doped electric field stop region, at least one N-type doped charge compensation region on the left, and at least one N-type doped charge compensation region on the right are connected, so that both sides of the N-type doped electric field stop region form a step-shaped structure inclined toward it.

4. A semiconductor device terminal structure according to claim 1, characterized in that: The closer to the N-type doped electric field cut-off region, the smaller the spacing between the N-type doped charge compensation regions, and / or the larger the volume, and / or the higher the doping concentration, and the larger the volume includes the deeper the depth, and / or the wider the width, and / or the thicker the thickness.

5. A semiconductor device terminal structure according to claim 1, characterized in that: The areas of the N-type doped charge compensation regions are the same, but the closer they are to the N-type doped electric field cut-off region, the smaller the interval between adjacent N-type doped charge compensation regions; or The N-type doped charge compensation regions have the same spacing and width, but the closer they are to the N-type doped electric field cut-off region, the deeper the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing and depth, but the closer they are to the N-type doped electric field cut-off region, the wider the N-type doped charge compensation regions are; or The N-type doped charge compensation regions have the same spacing, depth and interval, but the closer they are to the N-type doped electric field cutoff region, the higher the doping concentration of the N-type doped charge compensation region; or Increase the depth of the P-type doped main junction region so that the P-type doped main junction region and the P-type doped buried layer are connected and the N-type doped current diffusion layer is completely swallowed up; or The terminal structures on the left and right sides of the terminal area are different.

6. A semiconductor device terminal structure according to claim 2, characterized in that: The material of the first insulating dielectric layer is silicon oxide; and / or The material of the second insulating dielectric layer is silicon nitride; and / or The third insulating medium layer is made of silicon oxide.

7. A semiconductor device terminal structure according to claim 2, characterized in that: The doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; the doping element of the P-type doped main junction region is aluminum or boron; the material of the N-type doped substrate is SiC, GaN, Ga2O3, diamond or AlN.

8. A semiconductor device terminal structure according to claim 1, characterized in that: The opposite type of doping is applied, N-type doping is changed to P-type doping, and P-type doping is changed to N-type doping.

9. A process for manufacturing a semiconductor device terminal structure according to any one of claims 2 to 7, characterized in that: The following steps are involved: Growing an N-type doped drift region on a wide bandgap semiconductor material substrate; Forming a P-type doped buried layer by ion implantation, epitaxy or growing a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; Forming an N-type doped electric field cutoff region and an N-type doped charge compensation region by ion implantation or epitaxy + ion implantation; Forming a P-type doped main junction region by ion implantation; The first insulating dielectric layer, the second insulating dielectric layer and the third insulating dielectric layer are deposited and etched, and metal is deposited and etched on the front and back sides to form anode and cathode electrodes.

10. A process for manufacturing a semiconductor device terminal structure according to claim 9, characterized in that: After forming the P-type doped buried layer, an N-type doped electric field cutoff region and an N-type doped charge compensation region are formed first, and then an N-type doped current diffusion layer is formed.

Images