Complementary field effect transistor and preparation method thereof

Abstract

The invention provides a complementary field effect transistor and a preparation method thereof. The complementary field effect transistor comprises a substrate; a first field effect transistor of a vertical structure disposed on the substrate; and a second field effect transistor of a vertical structure disposed on the first field effect transistor, wherein the first field effect transistor comprises a first channel, the second field effect transistor comprises a second channel, one of the first channel and the second channel is an N-type channel, the other one of the first channel and the second channel is a P-type channel, the N-type channel is made of a silicon material, the P-type channel is made of a silicon-germanium material, and the N-type channel is made of a silicon-germanium material. And enabling the source-drain current of the first field effect transistor to be close to the source-drain current of the second field effect transistor, wherein the first field effect transistor and the second field effect transistor share the drain electrode and the gate electrode.

Description

Technical Field

[0001] The present disclosure relates to the technical field of vertical channel transistors, and in particular to a complementary field effect transistor and a method for preparing the same. Background Art

[0002] Vertical channel transistor (VCT) technology is considered to be a key technology for improving integration density and continuing Moore's Law in the future.

[0003] Vertical devices are three-dimensional devices, and compared with horizontal devices, which are two-dimensional, the manufacturing logic is different. In particular, many new technical challenges will arise during the manufacturing process of vertical device stacking.

[0004] In the related art, since the electron mobility is nearly twice that of the hole mobility, when a complementary field effect transistor (CFET) is formed under the same gate width, the difference in electron and hole mobility will cause current mismatch, resulting in a decline in device function. In the case of current matching, the device unit area is often determined by the size of the P-type field effect transistor (PMOS), which is not conducive to further miniaturization of the device. Summary of the invention

[0005] In view of this, the present disclosure provides a complementary field effect transistor and a method for manufacturing the same, which can make the source-drain current of a P-type field effect transistor close to the source-drain current of an N-type field effect transistor.

[0006] As a method of an embodiment of the present disclosure, a complementary field effect transistor is provided, comprising a substrate, a first field effect transistor of a vertical structure, and a second field effect transistor of a vertical structure. The first field effect transistor is arranged on the substrate, and the second field effect transistor is arranged on the first field effect transistor. The first field effect transistor comprises a first channel, the second field effect transistor comprises a second channel, one of the first channel and the second channel is an N-type channel, the other of the first channel and the second channel is a P-type channel, the N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material, so that the source-drain current of the first field effect transistor is close to the source-drain current of the second field effect transistor, wherein the first field effect transistor and the second field effect transistor share a drain and a gate.

[0007] As another aspect of the embodiments of the present disclosure, a method for preparing any one of the above complementary field effect transistors is provided, comprising:

[0008] epitaxially growing a first growth layer and a second growth layer on the substrate in sequence, wherein the first growth layer comprises two stacked first doped layers and a first silicon germanium layer located between the two first doped layers, and the second growth layer comprises two stacked second doped layers and a second silicon germanium layer located between the two second doped layers;

[0009] A silicon layer is etched inwardly along a first direction parallel to the substrate and deposited as an N-type channel in one of the first silicon germanium layer and the second silicon germanium layer;

[0010] Etching downward from the second doped layer located at the upper portion along a second direction perpendicular to the substrate to the first doped layer close to the substrate, forming a cavity on the substrate, and etching the first silicon germanium layer and the second silicon germanium layer outward from the cavity along the first direction, respectively, to remove the silicon germanium material adjacent to the N-type channel, and retaining a portion of the silicon germanium material in the other of the first silicon germanium layer and the second silicon germanium layer as a P-type channel;

[0011] A gate dielectric layer and a gate are formed on the periphery of the N-type channel and the P-type channel respectively.

[0012] According to the complementary field effect transistor of the embodiment of the present disclosure, by using silicon germanium (SiGe) material to manufacture a P-type channel, the hole mobility of the P-type channel can be enhanced, so as to achieve a source-drain current close to that of a pure silicon channel of an N-type field effect transistor (NMOS) under the condition of equal gate width, and not only can the current of the P-type field effect transistor (PMOS) be flexibly regulated by adjusting the SiGe component, so that the source-drain current of the PMOS can be improved, and the source-drain current of the P-type field effect transistor (PMOS) is closer to that of the NMOS; the overall performance of the complementary field effect transistor can also be improved by matching the mobility of electrons and holes. Due to the improvement of the matching of the source-drain current of the PMOS and the source-drain current of the NMOS, the device unit area can be more effectively controlled, which helps to further shrink the device size, thereby improving the integration density of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0014] Figure 1 Schematically shows a cross-sectional view of a complementary field effect transistor according to an embodiment of the present disclosure;

[0015] Figure 2 schematically shows a cross-sectional view of a complementary field effect transistor according to another embodiment of the present disclosure;

[0016] Figure 3 Schematically shows an equivalent circuit diagram of a complementary field effect transistor according to an embodiment of the present disclosure;

[0017] Figure 4 A flow chart schematically shows a method for preparing a complementary field effect transistor according to an embodiment of the present disclosure;

[0018] Figures 5 to 28 A schematic diagram showing a change in the preparation process of a complementary field effect transistor according to an embodiment of the present disclosure; and

[0019] Figure 29 to Figure 42 A schematic diagram shows a change in the preparation process of a complementary field effect transistor according to another embodiment of the present disclosure.

[0020] The following are the descriptions of the reference numerals:

[0021] 1-substrate; 11-well layer;

[0022] 2- a first field effect transistor;

[0023] 21 - first channel; 22 - first doping layer; 23 - first gate; 24 - first gate dielectric layer; 25 - first side wall;

[0024] 3- a second field effect transistor;

[0025] 31 - second channel; 32 - second doping layer; 33 - second gate; 34 - second gate dielectric layer;

[0026] 4-first growth layer; 41-first silicon germanium layer;

[0027] 5-second growth layer; 51-second silicon germanium layer;

[0028] 6-barrier layer; 7-core mold layer; 8-sacrificial layer; 9-first boss; 10-covering layer; 101-third boss; 102-fourth boss; 103-first annular space; 104-silicon layer; 105-first annular groove; 106-protective layer; 107-second annular space; 108-first filling layer; 109-cavity; 110-third annular space; 111-fourth annular space; 112-second filling layer; 113-etching layer; 114-gate dielectric layer; 115-first source; 116-second source; 117-drain; 118-gate electrode; 120-third filling layer; 121-second annular groove. DETAILED DESCRIPTION

[0029] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0030] Figure 1 Schematically shows a cross-sectional view of a complementary field effect transistor according to an embodiment of the present disclosure, Figure 2 A cross-sectional view of a complementary field effect transistor according to another embodiment of the present disclosure is schematically shown.

[0031] As one aspect of the embodiments of the present disclosure, a complementary field effect transistor is provided, such as Figure 1 and Figure 2 As shown, the complementary field effect transistor includes a substrate 1, a first field effect transistor 2 of a vertical structure, and a second field effect transistor 3 of a vertical structure. The first field effect transistor 2 is arranged on the substrate 1, and the second field effect transistor 3 is arranged on the first field effect transistor 2. The first field effect transistor 2 includes a first channel 21, and the second field effect transistor 3 includes a second channel 22. One of the first channel 21 and the second channel 22 is an N-type channel, and the other of the first channel 21 and the second channel 22 is a P-type channel. The N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material, so that the source-drain current of the first field effect transistor 2 is similar to the source-drain current of the second field effect transistor 3, wherein the first field effect transistor 2 and the second field effect transistor 3 share a drain 117 and a common gate.

[0032] According to the complementary field effect transistor of the embodiment of the present disclosure, by using silicon germanium (SiGe) material to manufacture a P-type channel, the hole mobility of the P-type channel can be enhanced, so as to achieve a source-drain current close to that of a pure silicon channel of an N-type field effect transistor (NMOS) under the condition of equal gate width, and not only can the current of the P-type field effect transistor (PMOS) be flexibly regulated by adjusting the SiGe component, so that the source-drain current of the PMOS can be improved, and the source-drain current of the P-type field effect transistor (PMOS) is closer to that of the NMOS; the overall performance of the complementary field effect transistor can also be improved by matching the mobility of electrons and holes. Due to the improvement of the matching of the source-drain current of the PMOS and the source-drain current of the NMOS, the device unit area can be more effectively controlled, which helps to further shrink the device size, thereby improving the integration density of the integrated circuit.

[0033] According to the embodiments of the present disclosure, by using a P-type channel made of silicon germanium material and an N-type channel made of silicon material, the difference between the source-drain current of the N-type field effect transistor and the source-drain current of the P-type field effect transistor can be made within one times of the source-drain current of the P-type field effect transistor.

[0034] In an illustrative embodiment, the SiGe composition can be adjusted so that the difference between the source-drain current of the N-type field effect transistor and the source-drain current of the P-type field effect transistor is 0.9 times, 0.5 times, 0.3 times or 0 times the source-drain current of the P-type field effect transistor.

[0035] In an illustrative embodiment, Figure 1As shown, the first field effect transistor 2 is a P-type field effect transistor having a P-type channel; the second field effect transistor 3 is an N-type field effect transistor having an N-type channel.

[0036] In another exemplary embodiment, Figure 2 As shown, the first field effect transistor 2 is an N-type field effect transistor having an N-type channel; the second field effect transistor 3 is a P-type field effect transistor having a P-type channel.

[0037] Figure 3 The figure schematically shows an equivalent circuit diagram of a complementary field effect transistor according to an embodiment of the present disclosure.

[0038] like Figure 3 As shown, T1 represents a PMOS transistor, and T2 represents an NMOS transistor. The PMOS transistor and the NMOS transistor are of a common gate structure, and v1 represents the gate voltage Vin input; the PMOS transistor and the NMOS transistor are of a common drain structure, and Vo represents the drain voltage Vout output; VDD represents the power supply, which is connected to the source of the PMOS transistor; Vss represents the ground, which is connected to the source of the NMOS transistor. The PMOS transistor and the NMOS transistor form an inverter structure.

[0039] According to an embodiment of the present disclosure, an N-type channel is formed by doping a semiconductor region with donor impurities (such as phosphorus or arsenic), wherein the main carriers are electrons. A P-type channel is formed by doping a semiconductor region with acceptor impurities (such as boron or gallium), wherein the main carriers are holes.

[0040] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the first field effect transistor 2 further includes two first doped layers 22, two electrically connected first gate electrodes 23 and a first gate dielectric layer 24. The two first doped layers 22 are stacked on the substrate 1, wherein the first channel 21 is arranged between the two first doped layers 22, and the first doped layer 22 at the bottom is led out through the first source electrode 115. The two electrically connected first gate electrodes 23 are arranged between the two first doped layers 22, and are respectively located on both sides of the first channel 21 in a first direction parallel to the substrate 1. The first gate dielectric layer 24 is arranged between the first channel 21 and the first gate electrode 23, and is suitable for electrically isolating the first channel 21 from the first gate electrode 23.

[0041] like Figure 1 and Figure 2As shown, the second field effect transistor 3 further includes two second doped layers 32, two electrically connected second gate electrodes 33 and a second gate dielectric layer 34. The two second doped layers 32 are stacked on the first field effect transistor 2, wherein the second channel 22 is arranged between the two second doped layers 32, wherein the adjacent first doped layers 22 and second doped layers 32 are led out through a common drain 117, and the second doped layer 32 located at the top is led out through a second source 116. Two electrically connected second gate electrodes 33 are arranged between the two second doped layers 32, and are respectively located on both sides of the first direction of the second channel 22, wherein the two second gate electrodes 33 are electrically connected to the two first gate electrodes 23. The second gate dielectric layer 34 is arranged between the second channel 22 and the second gate electrode 33, and the second gate dielectric layer 34 is suitable for electrically isolating the second channel 22 and the second gate electrode 33.

[0042] According to an embodiment of the present disclosure, the first doping layer 22 forms the source and drain 117 regions of the first field effect transistor 2 by doping different types of impurities (eg, N-type or P-type).

[0043] According to an embodiment of the present disclosure, the second doping layer 32 forms the source and drain 117 regions of the first field effect transistor 2 by doping different types of impurities (eg, N-type or P-type).

[0044] According to an embodiment of the present disclosure, the doping type of the first doping layer 22 is the same as that of the first channel 21, and the doping type of the second doping layer 32 is the same as that of the second channel 22. For example, when the first channel 21 is N-type, the doping type of the first doping layer 22 is also N-type.

[0045] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the first distance between the N-type channel and the first side wall 25 of the first doping layer 22 is greater than the second distance between the P-type channel and the first side wall 25. Fig.15 and Fig.34 Detailed description.

[0046] According to the embodiments of the present disclosure, Figure 1 and Figure 2 As shown, the base 1 includes a substrate (not shown in the figure) and a well layer 11. The well layer 11 is located between the substrate and the first field effect transistor 2. Wherein, when the first channel 21 is N-type, the well layer is P-type; when the first channel 21 is P-type, the well layer is N-type. In this way, the substrate and the first field effect transistor 2 can be electrically isolated by the well layer 11.

[0047] According to the embodiments of the present disclosure, Figure 1 and Figure 2As shown, the complementary field effect transistor further includes a third filling layer 120, which is filled around the first field effect transistor 2 and the second field effect transistor 3, for protecting the first field effect transistor 2 and the second field effect transistor 3 and isolating the first field effect transistor 2 and the second field effect transistor 3 from the outside.

[0048] In an exemplary embodiment, the third filling layer 120 is made of insulating material.

[0049] Figure 4 The flowchart of the method for preparing a complementary field effect transistor according to an embodiment of the present disclosure is schematically shown.

[0050] As another aspect of the embodiments of the present disclosure, a method for preparing a complementary field effect transistor is provided, such as Figure 4 As shown, the preparation method includes operations S410 to S440.

[0051] In operation S410, a first growth layer and a second growth layer are sequentially epitaxially grown on a substrate, wherein the first growth layer includes two stacked first doped layers and a first silicon germanium layer located between the two first doped layers, and the second growth layer includes two stacked second doped layers and a second silicon germanium layer located between the two second doped layers.

[0052] In operation S420, one of the first silicon germanium layer and the second silicon germanium layer is etched inwardly along a first direction parallel to the substrate and a silicon layer is deposited as an N-type channel.

[0053] In operation S430, the second doped layer located at the top is etched downward along a second direction perpendicular to the substrate to the first doped layer close to the substrate to form a cavity on the substrate, and the first silicon germanium layer and the second silicon germanium layer are etched outward along the first direction from the cavity to remove the silicon germanium material adjacent to the N-type channel and retain a portion of the silicon germanium material in the other of the first silicon germanium layer and the second silicon germanium layer as a P-type channel.

[0054] In operation S440 , a gate dielectric layer and a gate are formed at peripheries of the N-type channel and the P-type channel, respectively.

[0055] According to the preparation method of the complementary field effect transistor of the embodiment of the present disclosure, by using the retained silicon germanium layer as a P-type channel, the material properties of silicon germanium can be used to optimize the performance of the P-type transistor, such as improving the hole mobility, so as to achieve a source-drain current close to that of the pure silicon channel of the N-type field effect transistor (NMOS) under the condition of equal gate width, and not only can the P-type field effect transistor (PMOS) current be flexibly regulated by adjusting the SiGe component, so that the source-drain current of the PMOS can be improved, so that the source-drain current of the P-type field effect transistor (PMOS) is closer to the source-drain current of the NMOS; the overall performance of the complementary field effect transistor can also be improved by matching the electron and hole mobility. Due to the improvement of the matching of the source-drain current of the PMOS and the source-drain current of the NMOS, the device unit area can be more effectively controlled, which helps to further shrink the device size, thereby improving the integration density of the integrated circuit. The preparation method provided by the present disclosure is compatible with the process and the existing semiconductor manufacturing technology, and is easy to be integrated into the existing production process.

[0056] Before operation S410 , the method further includes: performing well layer implantation on the substrate.

[0057] Furthermore, the injection type of the well layer is opposite to that of the first field effect transistor 2. Specifically, when the first field effect transistor 2 is of N type, the well layer is of P type; when the first field effect transistor 2 is of P type, the well layer is of N type.

[0058] Figures 5 to 28 The following schematically shows a change diagram of the preparation process of a complementary field effect transistor according to an embodiment of the present disclosure. Figure 29 to Figure 42 A schematic diagram shows a change in the preparation process of a complementary field effect transistor according to another embodiment of the present disclosure.

[0059] like Figure 5 As shown, epitaxial stacking is performed from bottom to top on the well layer to form a first growth layer 4 and a second growth layer 5. Specifically, a first doping layer 22, a first silicon germanium layer 41, a first doping layer 22, a second doping layer 32, a second silicon germanium layer 51 and a second doping layer 32 are sequentially deposited on the well layer.

[0060] In an exemplary embodiment, heavily doped P-type silicon, intrinsic germanium silicon, heavily doped P-type silicon, heavily doped N-type silicon, intrinsic germanium silicon, and heavily doped N-type silicon are sequentially epitaxially grown on the well layer. The thickness of each layer can be adjusted according to actual conditions. The heavily doped layer is about 1e 19 ~1e 20 cm -3 , which can be adjusted according to the specific device performance requirements.

[0061] According to an embodiment of the present disclosure, etching inwardly along a first direction in the second silicon germanium layer 51 and depositing a silicon layer 104 as an N-type channel includes:

[0062] like Figure 6-Figure 10 As shown, a fourth protrusion 102 is formed on the substrate 1, and a first annular space 103 is formed between the two second doping layers 32;

[0063] like Fig.11 As shown, a silicon layer 104 is deposited in the first annular space 103, and the silicon layer 104 in the first annular space 103 forms a first annular groove 105;

[0064] like Fig.13 As shown, a protective layer 106 is filled in the first annular groove 105 to protect the first annular groove 105;

[0065] like Fig.14 As shown, the fourth boss 102 is used as a mask to remove the silicon layer 104 on the sidewall of the fourth boss 102, and is etched downward along the second direction to the first doped layer 22 adjacent to the substrate 1, leaving the silicon layer 104 in the first annular space 103 as an N-type channel.

[0066] In such an embodiment, the first annular space 103 and the surrounding epitaxial silicon layer 104 act as a self-aligned vertical channel.

[0067] According to an embodiment of the present disclosure, a fourth boss 102 is formed on the substrate 1, and a first annular space 103 is formed between two second doping layers 32, including:

[0068] like Figure 6 As shown, a barrier layer 6, a core mode layer 7 and a sacrificial layer 8 are sequentially deposited on the second growth layer 5;

[0069] like Figure 7 As shown, the sacrificial layer 8 and the core mold layer 7 are etched in sequence to form a patterned sacrificial layer 8 and a core mold layer 7, and the patterned sacrificial layer 8 and the core mold layer 7 form a first boss 9 on the barrier layer 6;

[0070] Depositing a cover layer 10 on the surface and sidewall of the first boss 9 to form a second boss;

[0071] like Figure 8 As shown, the barrier layer 6 is etched using the second boss as a mask to form a third boss 101;

[0072] like Fig. 9 As shown, the third protrusion 101 is used as a mask to etch from the second growth layer 5 to between the second doping layer 32 adjacent to the first growth layer 4 and the first doping layer 22 adjacent to the second growth layer 5, that is, Fig. 9 Between t1 and t2, a fourth boss 102 is formed;

[0073] like Fig.10As shown, the second silicon germanium layer 51 is etched along a first direction to a first etching depth, so that a first annular space 103 is formed between the two second doping layers 32 .

[0074] According to an embodiment of the present disclosure, filling the protective layer 106 in the first annular groove 105 includes:

[0075] like Fig.12 As shown, a material layer is covered on the surface of the substrate 1 where the first annular groove 105 is formed.

[0076] like Fig.13 As shown, the material layer outside the first annular groove 105 is removed, and the material layer inside the first annular groove 105 is used as the protective layer 106 .

[0077] In an exemplary embodiment, the material of the protection layer 106 may be silicon nitride.

[0078] In an illustrative embodiment, the material of the barrier layer 6 has a certain selection ratio with the silicon material, for example, it may be silicon nitride or silicon oxide.

[0079] In an illustrative embodiment, the material of the sacrificial layer 8 has a certain selection ratio with the silicon material, for example, it may be silicon nitride or silicon oxide.

[0080] In an illustrative embodiment, the material of the barrier layer 6 includes silicon oxide, the material of the core mold layer 7 includes amorphous silicon (a-Si), and the material of the sacrificial layer 8 may include silicon oxide.

[0081] In an illustrative embodiment, the sacrificial layer 8 and the core mold layer 7 are etched in sequence to form a patterned sacrificial layer 8 and a core mold layer 7, and the patterned sacrificial layer 8 and the core mold layer 7 form a first boss 9 on the barrier layer 6, including: defining the size of the first boss 9 by a patterning process, etching away the area outside the pattern definition, and stopping the etching on the barrier layer 6.

[0082] A covering layer 10 is deposited on the surface and sidewalls of the first boss 9 to form a second boss, including: depositing a covering layer 10 (e.g., silicon oxide) and etching to form a second boss having a covering layer 10 on the sidewalls of the first boss 9, wherein the covering layer 10 on the sidewalls of the first boss 9 defines a source / drain region below the covering layer 10 on the sidewalls of the first boss 9.

[0083] According to an embodiment of the present disclosure, a method of etching the second silicon germanium layer 51 may include dry etching or wet etching.

[0084] According to an embodiment of the present disclosure, etching is performed downward from the second doping layer 32 located at the upper portion along the second direction to the first doping layer 22 close to the substrate 1, a cavity 109 is formed on the substrate 1, and the first silicon germanium layer 41 and the second silicon germanium layer 51 are respectively etched outward from the cavity 109 along the first direction to remove the silicon germanium material adjacent to the N-type channel, and a portion of the silicon germanium material in the first silicon germanium layer 41 is retained as the N-type channel, including:

[0085] like Fig.15 As shown, the first silicon germanium layer 41 is etched in the first direction to a second etching depth, so that a second annular space 107 is formed between two first doping layers 22 adjacent to the first silicon germanium layer 41, wherein the second etching depth c is less than the first etching depth b (c<b);

[0086] like Fig.16 As shown, an active area protruding from the surrounding area is formed on the substrate 1 by photolithography pattern transfer and etching;

[0087] removing the sacrificial layer 8;

[0088] like Fig.17 As shown, a first filling layer 108 is filled on the substrate 1, the first filling layer 108 is flush with the core mold layer 7, and the core mold layer 7 is exposed;

[0089] Removing the core mold layer 7;

[0090] like Fig.18 As shown, the first cavity formed after removing the core film layer 7 is used as an etching pattern, and etching is performed downward (for example, dry anisotropic etching can be used) to the first silicon germanium layer 41 adjacent to the substrate 1, and a cavity 109 is formed on the substrate 1, so that the first silicon germanium layer 41 and the second silicon germanium layer 51 are exposed in the cavity 109;

[0091] like Fig.18 As shown, the first silicon germanium layer 41 and the remaining second silicon germanium layer 51 are etched outward from the cavity 109 in a first direction to form a third annular space 110 between the two second doped layers 32, and part of the silicon germanium material of the first silicon germanium layer 41 is retained as the first channel 21, so that a fourth annular space 111 is formed between the two first doped layers 22.

[0092] In such an embodiment, Fig.15 As shown, the second etching depth c and the first etching depth b are both smaller than the thickness a of the covering layer 10 covering the side wall of the first protrusion 9, that is, a>b>c.

[0093] According to an embodiment of the present disclosure, a method of etching the first silicon germanium layer 41 may include dry etching or wet etching.

[0094] According to an embodiment of the present disclosure, the core mold layer 7 may be removed by a wet method.

[0095] According to an embodiment of the present disclosure, etching inwardly along a first direction on the first silicon germanium layer 41 and depositing a silicon layer 104 as an N-type channel includes:

[0096] A fourth protrusion 102 is formed on the substrate 1, and a first annular space 103 is formed between the two second doping layers 32;

[0097] like Fig.29 As shown, a protective layer 106 is filled in the first annular space 103;

[0098] like Fig.30 As shown, the fourth protrusion 102 is used as a mask to etch downward to the first doping layer 22 adjacent to the substrate 1;

[0099] like Fig.31 As shown, an active area protruding from the surrounding area is formed on the substrate 1 by photolithography pattern transfer and etching;

[0100] like Fig.32 As shown, the first silicon germanium layer 41 is etched along the first direction to a second etching depth, so that a second annular space 107 is formed between the two first doping layers 22, wherein the second etching depth e is greater than the first etching depth d;

[0101] like Fig.33 As shown, a silicon layer 104 is deposited at least on the second annular space 107, and the silicon layer 104 in the second annular space 107 forms a second annular groove 121, and the silicon layer 104 in the second annular space 107 is used as an N-type channel.

[0102] In such an embodiment, Fig.34 As shown, the second etching depth e and the first etching depth d are both smaller than the thickness a of the cover layer 10 covering the side wall of the first protrusion 9, that is, a>e>d.

[0103] According to an embodiment of the present disclosure, etching is performed downward from the second doped layer 32 located at the upper portion to the first doped layer 22 located near the substrate 1 to form a cavity 109 on the substrate 1, and the first silicon germanium layer 41 and the second silicon germanium layer 51 are etched outward from the cavity 109 to remove the silicon germanium material adjacent to the N-type channel, and a portion of the silicon germanium material in the second silicon germanium layer 51 is retained as a P-type channel, including:

[0104] like Fig.34 As shown, the protective layer 106 in the first annular space 103 is removed;

[0105] removing the sacrificial layer 8;

[0106] like Fig.35 As shown, a first filling layer 108 is filled on the substrate 1, so that the first filling layer 108 is flush with the core mold layer 7, and the core mold layer 7 is exposed;

[0107] Removing the core mold layer (e.g. by wet method);

[0108] like Fig.36 As shown, the first cavity formed after removing the core mold layer 7 is used as the etching pattern, and etching is performed downward to the first silicon germanium layer 41 to form a cavity 109 on the surface of the first silicon germanium layer 41 adjacent to the substrate 1, so that the first silicon germanium layer 41 and the second silicon germanium layer 51 are exposed in the cavity 109;

[0109] like Fig.37 As shown, the second silicon germanium layer 51 and the remaining first silicon germanium layer 41 are etched outward from the cavity 109 along the first direction to form a third annular space 110 between the two first doped layers 22, and part of the silicon germanium material of the second silicon germanium layer 51 is retained as a P-type channel to form a fourth annular space 111 between the two second doped layers 32.

[0110] According to an embodiment of the present disclosure, a gate dielectric layer and a gate are formed on the periphery of an N-type channel and a P-type channel, respectively, including:

[0111] like Fig.19 and Fig.38 As shown, a second filling layer 112 is filled in the cavity 109, and the second filling layer 112, the first filling layer 108 and the cover layer 10 form an etching layer 113;

[0112] like Fig. 20 , Fig.21 and Fig.39 As shown, the etching layer 113 is etched to reduce the height of the etching layer 113 to below the active area, exposing the annular structure located in the active area; wherein, Fig.21 This is a top view of the ring structure. Fig.21 yes Fig. 20 Cross-section along AA;

[0113] like Fig.23 As shown, after removing the protective layer 106 filled in the first annular groove 105, the annular structure is etched using a fin cutting mask so that the annular structure has an opening to form a first substrate; wherein, Fig.23 is a top view of the first substrate;

[0114] A gate dielectric layer 114 is deposited on the surface of the first substrate, so that an annular first groove is formed in the first annular groove 105, an annular second groove is formed in the second annular space 107, an annular third groove is formed in the third annular space 110, and an annular fourth groove is formed in the fourth annular space 111, as a second substrate;

[0115] Depositing a metal gate on the periphery of the second substrate;

[0116] Etching the metal gates outside the first groove, the second groove, the third groove and the fourth groove, wherein the metal gates in the first groove and the third groove serve as the second gate 33, and the metal gates in the second groove and the fourth groove serve as the first gate 23, to form a third substrate;

[0117] like Fig.24 , Fig.25 , Fig.40 and Fig.41 As shown, the gate dielectric layer 114 at the opening is protected by a photomask, and the gate dielectric layer in other areas on the surface of the third substrate outside the photomask protection area is removed, wherein the gate dielectric layer 114 in the first annular groove 105 and the third annular space 110 is used as the second gate dielectric layer 34, and the gate dielectric layer 114 in the first annular space 103 and the fourth annular space 111 is used as the first gate dielectric layer 24; wherein, Fig.24 A top view after removing the gate dielectric layer 114 outside the fin cutting mask;

[0118] like Figure 26 to Figure 28 , Fig.42 As shown, through the interconnection method of sidewall interconnection, the remaining first doped layer 22 adjacent to the substrate 1 is led out through the first source 115, the second doped layer 32 located above is led out through the second source 116, the adjacent second doped layer 32 and the first doped layer 22 are led out through the drain 117, and the first gate 23 and the second gate 33 are led out through the gate electrode 118. Among them, Fig.26 For Fig.24 A cross-sectional view of a complementary field effect transistor BB from the perspective shown, Fig. 27 For Fig.24 Cross-sectional view of complementary field effect transistor CC from the perspective shown.

[0119] According to an embodiment of the present disclosure, when the first field effect transistor 2 is a P-type field effect transistor, before etching the ring structure using a fin cutting mask, the method further includes: Fig. 22 As shown, the protection layer 106 filled in the first annular groove 105 is removed.

[0120] In an exemplary embodiment, the protection layer 106 filled in the first annular groove 105 may be removed by wet etching.

[0121] In an illustrative embodiment, the cross-sectional shape of the annular structure with an opening in the horizontal direction may be a long strip or a C-shape.

[0122] In an illustrative embodiment, a method for preparing a complementary field effect transistor includes:

[0123] Performing N-type well layer implantation on the substrate to form a base 1;

[0124] like Figure 5 As shown, a first growth layer 4 and a second growth layer 5 are sequentially epitaxially grown on a substrate 1;

[0125] like Figure 6 As shown, a barrier layer 6, a core mode layer 7 and a sacrificial layer 8 are sequentially deposited on the second growth layer 5;

[0126] like Figure 7 As shown, through a patterning process, etching is performed from the top of the sacrificial layer 8 downward to the barrier layer 6 to etch the sacrificial layer 8 and the core mold layer 7 outside the pattern definition area, and a first boss 9 is formed on the surface of the barrier layer 6;

[0127] like Figure 8 As shown, a capping layer 10 is deposited on the surface and sidewall of the first boss 9, and the barrier layer 6 is etched using the second boss as a mask to form a third boss 101;

[0128] like Fig. 9 As shown, anisotropic etching is used to retain the capping layer 10 and etch from the second growth layer 5 to between the second doping layer 32 adjacent to the first growth layer 4 and the first doping layer 22 adjacent to the second growth layer 5, that is, Fig. 9 Between t1 and t2, a fourth boss 102 is formed;

[0129] like Fig.10 As shown, the second silicon germanium layer 51 of the second growth layer 5 is etched inward to a first etching depth by selective dry or wet etching, so that a first annular space 103 is formed between the second doping layers of the second growth layer 5;

[0130] like Fig.11 As shown, a silicon layer 104 is formed on the wall surface of the first annular space 103, and a first annular groove 105 is formed between the silicon layers 104 located in the first annular space 103;

[0131] like Fig.13 As shown, a protective layer 106 is filled in the first annular groove 105 to protect the silicon layer 104 located in the first annular space 103; and

[0132] like Fig.14 As shown, the fourth boss 102 is used as a mask to remove the silicon layer 104 on the sidewall of the fourth boss 102, and the process is etched downward along the second direction to the first doped layer 22 adjacent to the substrate 1, and the silicon layer 104 in the first annular space 103 is retained as an N-type channel;

[0133] like Fig.15As shown, the first silicon germanium layer 41 in the first growth layer 4 is etched inward to a second etching depth c by selective dry or wet etching, so that an annular second annular space 107 is formed between two first doping layers 22 adjacent to the first silicon germanium layer 41;

[0134] like Fig.16 As shown, the periphery of the fourth protrusion 102 is etched by photolithography pattern transfer to form an active area on the substrate 1;

[0135] like Fig.17 As shown, etching is performed downward from the top surface of the fourth boss 102 to remove the sacrificial layer 8; a first filling layer 108 is filled on the substrate 1, and chemical mechanical polishing is used so that the first filling layer 108 is flush with the core mold layer 7 and the core mold layer 7 is exposed;

[0136] Removing the core mold layer 7;

[0137] like Fig.18 As shown, the first cavity formed after removing the core film layer 7 is used as an etching pattern, and wet or dry etching is used to etch downward (for example, dry anisotropic etching can be used) to the first silicon germanium layer 41 adjacent to the substrate 1, and a cavity 109 is formed on the substrate 1, so that the first silicon germanium layer 41 and the second silicon germanium layer 51 are exposed in the cavity 109;

[0138] The first silicon germanium layer 41 and the remaining second silicon germanium layer 51 are etched outward in a first direction from the cavity 109 by atomic layer etching to form a third annular space 110 between the two second doped layers 32, and part of the silicon germanium material of the first silicon germanium layer 41 is retained as the first channel 21 to form a fourth annular space 111 between the two first doped layers 22.

[0139] like Fig.19 As shown, a second filling layer 112 is filled in the cavity 109, and the second filling layer 112, the first filling layer 108 and the cover layer 10 form an etching layer 113 and the surface is planarized by chemical mechanical grinding;

[0140] like Fig. 20 and Fig.21 As shown, the etching layer 113 is etched by wet or dry etching to reduce the height of the etching layer 113 below the active area, exposing the annular structure located in the active area;

[0141] like Fig. 22 As shown, the protection layer 106 filled in the first annular groove 105 is removed by wet etching;

[0142] like Figure 23 to Figure 28 As shown, the annular structure is etched using a fin cutting mask so that the annular structure has an opening to form a first substrate.

[0143] In this way, after a gate dielectric layer is deposited on the surface of the first substrate, an annular first groove is formed in the first annular groove 105, an annular second groove is formed in the second annular space 107, an annular third groove is formed in the third annular space 110, and an annular fourth groove is formed in the fourth annular space 111, as a second substrate;

[0144] Depositing a metal gate on the periphery of the second substrate;

[0145] The metal gates outside the first groove, the second groove, the third groove and the fourth groove are etched, wherein the metal gates located in the first groove and the third groove serve as the gate of the N-type field effect transistor, and the metal gates located in the second groove and the fourth groove serve as the gate of the P-type field effect transistor, to form a third substrate.

[0146] The gate dielectric layer at the opening of the photomask is removed from other areas of the surface of the third substrate outside the photomask protection area, wherein the gate dielectric layer in the first annular groove and the third annular space is used as the second gate dielectric layer, and the gate dielectric layer in the first annular space and the fourth annular space is used as the first gate dielectric layer;

[0147] The remaining doped layers are connected by sidewall interconnection and drilling to be used as source and drain layers of the N-type field effect transistor and the P-type field effect transistor respectively through source and drain electrodes, and the gate is connected through the gate electrode 118 .

[0148] According to the method for preparing complementary field effect transistors provided in the embodiments of the present disclosure, not only can the use of masks be saved, but also two layers of masks are not required to respectively define the gate widths of the N-type field effect transistor and the P-type field effect transistor, which is conducive to further reducing the size of the complementary field effect transistor and can save costs.

[0149] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A complementary field effect transistor, characterized in that: include: Base (1); A first field effect transistor (2) of a vertical structure, arranged on the substrate (1); as well as A second field effect transistor (3) with a vertical structure, arranged on the first field effect transistor (2); The first field effect transistor (2) comprises a first channel (21), the second field effect transistor (3) comprises a second channel (31), one of the first channel (21) and the second channel (31) is an N-type channel, the other of the first channel (21) and the second channel (31) is a P-type channel, the N-type channel is made of silicon material, and the P-type channel is made of silicon germanium material, so that the source-drain current of the first field effect transistor is close to the source-drain current of the second field effect transistor, and the first field effect transistor and the second field effect transistor share a drain and a gate.

2. The complementary field effect transistor according to claim 1, characterized in that: The first field effect transistor (2) further comprises: Two first doped layers (22) are stacked on the substrate (1), wherein the first channel (21) is arranged between the two first doped layers (22), and the first doped layer at the bottom is led out through a first source electrode; Two electrically connected first gate electrodes (23), arranged between the two first doping layers (22), and respectively located on both sides of the first channel (21) in a first direction parallel to the substrate (1); and A first gate dielectric layer (24), arranged between the first channel (21) and the first gate (23), suitable for electrically isolating the first channel (21) and the first gate (23); The second field effect transistor (3) further comprises: Two second doped layers (32) are stacked on the first field effect transistor (2), wherein the second channel (31) is arranged between the two second doped layers (32), wherein adjacent first doped layers and second doped layers are led out through a common drain, and the second doped layer located on the top is led out through a second source; Two electrically connected second gates (33), arranged between the two second doping layers (32) and respectively located on both sides of the second channel (31) in the first direction, wherein the two second gates are electrically connected to the two first gates; The second gate dielectric layer (34) is arranged between the second channel (31) and the second gate (33), and is suitable for electrically isolating the second channel (31) and the second gate (33).

3. The complementary field effect transistor according to claim 1, characterized in that: A first distance between the N-type channel and a first side wall (25) of the first doping layer (22) is greater than a second distance between the P-type channel and the first side wall.

4. The complementary field effect transistor according to claim 1, characterized in that: The substrate (1) comprises: substrate; A well layer (11) located between the substrate and the first field effect transistor (2); Wherein, when the first channel (21) is of N type, the well layer (11) is of P type, and when the first channel (21) is of P type, the well layer (11) is of N type, so as to electrically isolate the substrate from the first field effect transistor (2).

5. A method for preparing a complementary field effect transistor according to any one of claims 1 to 4, characterized in that: include: A first growth layer (4) and a second growth layer (5) are sequentially epitaxially grown on a substrate (1), wherein the first growth layer (4) comprises two stacked first doping layers (22) and a first silicon germanium layer (41) located between the two first doping layers (22), and the second growth layer (5) comprises two stacked second doping layers (32) and a second silicon germanium layer (51) located between the two second doping layers (32); Etching inwardly along a first direction parallel to the substrate (1) and depositing a silicon layer (104) as an N-type channel in one of the first silicon germanium layer (41) and the second silicon germanium layer (51); Etching downward from the second doped layer (32) located at the top along a second direction perpendicular to the substrate (1) to the first doped layer (22) close to the substrate (1), forming a cavity (109) on the substrate, and etching the first silicon germanium layer (41) and the second silicon germanium layer (51) outward from the cavity (109) along the first direction, respectively, to remove silicon germanium material adjacent to the N-type channel, and retaining a portion of silicon germanium material in the other of the first silicon germanium layer (41) and the second silicon germanium layer (51) as a P-type channel; A gate dielectric layer and a gate are formed on the periphery of the N-type channel and the P-type channel respectively.

6. The preparation method according to claim 5, characterized in that: The second silicon germanium layer (51) is etched inwardly along a first direction and a silicon layer (104) is deposited as an N-type channel, comprising: Depositing a barrier layer (6), a core mode layer (7) and a sacrificial layer (8) in sequence on the second growth layer (5); The sacrificial layer (8) and the core mold layer (7) are sequentially etched to form a patterned sacrificial layer (8) and a core mold layer (7), wherein the patterned sacrificial layer (8) and the core mold layer (7) form a first boss (9) on the barrier layer (6); Depositing a covering layer (10) on the surface and sidewall of the first boss (9) to form a second boss; Using the second boss as a mask, etching the barrier layer (6) to form a third boss (101); Using the third boss (101) as a mask, etching from the second growth layer (5) to between the second doped layer (32) adjacent to the first growth layer (4) and the first doped layer (22) adjacent to the second growth layer (5), to form a fourth boss (102); Etching the second silicon germanium layer (51) along the first direction to a first etching depth, so that a first annular space (103) is formed between the two second doped layers (32); Depositing the silicon layer (104) in the first annular space (103), and making the silicon layer (104) in the first annular space (103) form a first annular groove (105); Filling a protective layer (106) in the first annular groove (105); Using the fourth boss (102) as a mask, the silicon layer (104) on the side wall of the fourth boss (102) is removed, and etching is performed downward along the second direction to the first doped layer (22) adjacent to the substrate (1), retaining the silicon layer (104) located in the first annular space (103) as the N-type channel.

7. The preparation method according to claim 6, characterized in that: The second doped layer (32) located at the top is etched downwards along the second direction to the first doped layer (22) close to the substrate (1), a cavity (109) is formed on the substrate, and the first silicon germanium layer (41) and the second silicon germanium layer (51) are respectively etched outwards along the first direction from the cavity (109) to remove the silicon germanium material adjacent to the N-type channel, and a portion of the silicon germanium material in the first silicon germanium layer (41) is retained as a P-type channel, comprising: Etching the first silicon germanium layer (41) to a second etching depth in the first direction, so that a second annular space (107) is formed between two of the first doping layers (22) adjacent to the first silicon germanium layer (41), wherein the second etching depth is less than the first etching depth; By photolithography pattern transfer etching, an active area protruding from the surrounding area is formed on the substrate (1); Removing the sacrificial layer (8); Filling a first filling layer (108) on the substrate (1), wherein the first filling layer (108) is flush with the core mold layer (7) and the core mold layer (7) is exposed; Using the first cavity formed after removing the core mold layer (7) as an etching pattern, etching downward to the first silicon germanium layer (41) adjacent to the substrate (1), forming the cavity (109) on the substrate (1), so that the first silicon germanium layer (41) and the second silicon germanium layer (51) are exposed in the cavity (109); The first silicon germanium layer (41) and the remaining second silicon germanium layer (51) are etched outwards in the first direction from within the cavity (109) to form a third annular space (110) between the two second doped layers (32), and part of the silicon germanium material of the first silicon germanium layer (41) is retained as the first channel (21) to form a fourth annular space (111) between the two first doped layers (22).

8. The preparation method according to claim 5, characterized in that: The first silicon germanium layer (41) is etched inwardly along a first direction and a silicon layer (104) is deposited as an N-type channel, comprising: Depositing a barrier layer (6), a core mode layer (7) and a sacrificial layer (8) in sequence on the second growth layer (5); The sacrificial layer (8) and the core mold layer (7) are sequentially etched to form a patterned sacrificial layer (8) and a core mold layer (7), wherein the patterned sacrificial layer (8) and the core mold layer (7) form a first boss (9) on the barrier layer (6); Depositing a covering layer (10) on the surface and sidewall of the first boss (9) to form a second boss; Using the second boss as a mask, etching the barrier layer (6) to form a third boss (101); Using the third boss (101) as a mask, etching the second growth layer (5), the first growth layer (4) to between the second doped layer (32) adjacent to the first growth layer (4) and the first doped layer (22) adjacent to the second growth layer (5), so as to form a fourth boss (102); Etching the second silicon germanium layer (51) to a first etching depth along a first direction, so that a first annular space (103) is formed between the two second doped layers (32); Filling the first annular space (103) with a protective layer (106); Using the fourth protrusion (102) as a mask, etching downward to the first doping layer (22) adjacent to the substrate (1); By photolithography pattern transfer etching, an active area protruding from the surrounding area is formed on the substrate (1); Etching the first silicon germanium layer (41) to a second etching depth along the first direction, so that a second annular space (107) is formed between the two first doping layers (22), wherein the second etching depth is greater than the first etching depth; A silicon layer (104) is deposited at least on the second annular space (107), and the silicon layer (104) in the second annular space (107) forms a second annular groove (121), and the silicon layer (104) in the second annular space (107) serves as the N-type channel.

9. The preparation method according to claim 8, characterized in that: Etching downward from the second doped layer (32) located at the top to the first doped layer (22) located near the substrate (1) to form a cavity (109) on the substrate (1), and etching outward from the cavity (109) the first silicon germanium layer (41) and the second silicon germanium layer (51) to remove the silicon germanium material adjacent to the N-type channel and retain a portion of the silicon germanium material in the second silicon germanium layer (51) as a P-type channel, comprising: removing the protective layer (106) in the first annular space (103); Removing the sacrificial layer (8); Filling a first filling layer (108) on the substrate (1) so that the first filling layer (108) is flush with the core mold layer (7) and the core mold layer (7) is exposed; Using the first cavity formed after removing the core mold layer (7) as an etching pattern, etching downward to the first silicon germanium layer (41) to form a cavity (109) on the surface of the first silicon germanium layer (41) adjacent to the substrate (1), so that the first silicon germanium layer (41) and the second silicon germanium layer (51) are exposed in the cavity (109); The second silicon germanium layer (51) and the remaining first silicon germanium layer (41) are etched outward from the cavity (109) along a first direction to form a third annular space (110) between the two first doped layers (22), and a portion of the silicon germanium material of the second silicon germanium layer (51) is retained as a P-type channel to form a fourth annular space (111) between the two second doped layers (32).

10. The preparation method according to claim 7 or 9, characterized in that: A gate dielectric layer and a gate are formed on the periphery of the N-type channel and the P-type channel respectively, including: The cavity (109) is filled with a second filling layer (112), and the second filling layer (112), the first filling layer (108) and the cover layer (10) form an etching layer (113); Etching the etching layer (113) so that the height of the etching layer (113) is reduced to below the active area, exposing the annular structure located in the active area; After removing the protective layer (106) filled in the first annular groove (105), etching the annular structure using a fin cutting mask so that the annular structure has an opening, thereby forming a first substrate; A gate dielectric layer (114) is deposited on the surface of the first substrate, so that an annular first groove is formed in the first annular groove (105), an annular second groove is formed in the second annular space (107), an annular third groove is formed in the third annular space (110), and an annular fourth groove is formed in the fourth annular space (111), as a second substrate; Depositing a metal gate on the periphery of the second substrate; Etching the metal gate outside the first groove, the second groove, the third groove and the fourth groove, wherein the metal gates located in the first groove and the third groove serve together as the second gate (33), and the metal gates located in the second groove and the fourth groove serve as the first gate (23), to form a third substrate; Protecting the gate dielectric layer (114) at the opening by means of a photomask, and removing the gate dielectric layer in other areas on the surface of the third substrate outside the photomask protection area, wherein the gate dielectric layer (114) in the first annular groove (105) and the third annular space (110) serves as the second gate dielectric layer (34), and the gate dielectric layer in the first annular space (103) and the fourth annular space (111) serves as the first gate dielectric layer (24); By means of a sidewall interconnection method, the remaining first doped layer (22) adjacent to the substrate (1) is led out through a first source electrode (115), the second doped layer (32) located above is led out through a second source electrode (116), the adjacent second doped layer (32) and the first doped layer (22) are led out through a drain electrode (117), and the first gate electrode (23) and the second gate electrode (33) are led out through a gate electrode (118).

Images