Semiconductor structure and forming method thereof

Abstract

A method includes bonding a second workpiece to a first workpiece, performing a first plasma etch process on a backside of the first workpiece to form a first trench, and forming a first backside conductive feature in the first trench. The first workpiece includes: a first transistor including a source / drain (S / D) feature; a second transistor adjacent to the first transistor and including a gate structure; a diode; and an interconnect structure including a plurality of metal wires and vias. A first interconnect layer of the interconnect structure includes a metal line electrically coupled to the gate structure and the source / drain feature. The second workpiece includes a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate disposed over the first dielectric layer. The metal feature is electrically coupled to the gate structure through the diode and the plurality of metal lines and vias.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor structure and a method for forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be formed using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] As feature sizes continue to decrease, some IC features (such as source / drain metal contacts and power line connections) can be formed on the back side of the semiconductor substrate. This enables better spacing management while optimizing power consumption. However, when forming backside vias and power line connections, charge accumulation during the etching process can damage the integrated circuit device. Therefore, although existing semiconductor structures are generally adequate for their intended purposes, existing semiconductor structures are not yet completely satisfactory in all aspects. Summary of the invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a workpiece, the workpiece including: a diode, located in a substrate, a first transistor, including source / drain (S / D) features located in and above the substrate, and an internal wiring structure, arranged on the substrate and including a multilayer dielectric structure and a plurality of front-side conductive features arranged in the multilayer dielectric structure, wherein the diode is electrically coupled to the source / drain feature through a first portion of the plurality of front-side conductive features of the internal wiring structure; providing a carrier component, the carrier component including a carrier substrate and a bonding layer located above the carrier substrate; forming a first groove passing through the bonding layer; forming a metal feature in the first groove, attaching the carrier component to the internal wiring structure so that the metal feature directly contacts one of the plurality of front-side conductive features, wherein the metal feature is electrically coupled to the diode through a second portion of the plurality of front-side conductive features of the internal wiring structure; performing a first plasma etching process on the back side of the substrate to form a second groove exposing the bottom surface of the source / drain feature; and forming a first back-side conductive feature electrically coupled to the source / drain feature in the second groove.

[0005] An embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a first workpiece, the first workpiece including: a first transistor including a source / drain (S / D) feature, a second transistor adjacent to the first transistor and including a gate structure, a diode adjacent to the second transistor, and an internal connection structure including a plurality of metal lines and vias, wherein a first internal connection layer of the internal connection structure includes a metal line electrically coupled to both the gate structure and the source / drain feature; providing a second workpiece, the second workpiece including: a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate disposed on the first dielectric layer; attaching the second workpiece to the first workpiece so that the metal feature is electrically coupled to the gate structure through the diode and the plurality of metal lines and vias; performing a first plasma etching process on the back side of the first workpiece to form a first trench, wherein the source / drain feature is exposed in the first trench; and forming a first backside conductive feature in the first trench.

[0006] An embodiment of the present invention provides a semiconductor structure including: a first substrate; a first transistor, including a fin structure protruding from the first substrate and a metal gate structure disposed on the fin structure; a diode, disposed in the first substrate and adjacent to the first transistor; a second transistor, adjacent to the first transistor and including a source / drain (S / D) feature; a first backside conductive structure, disposed below the source / drain feature and electrically coupled to the source / drain feature; an internal connection structure, disposed on the first substrate, wherein the internal connection structure includes a multi-layer dielectric structure and a plurality of front-side conductive features embedded in the multi-layer dielectric structure; a dielectric layer, disposed on the internal connection structure; a metal feature, disposed to pass through the dielectric layer and contact one of the plurality of front-side conductive features; and a second substrate, disposed on the dielectric layer and the metal feature, wherein the plurality of front-side conductive features include a first portion of a P-well connected to the metal feature and the diode, and a second portion of an N-well connected to the source / drain feature, the metal gate structure and the diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method for fabricating a semiconductor structure according to various aspects of the present disclosure.

[0009] Figure 2 According to various aspects of this disclosure Figure 1 Top views of part or all of a workpiece during various stages of the method are shown.

[0010] Figure 3 According to various aspects of the present disclosure, Figure 1 During the various stages of the method shown, along Figure 2 A cross-sectional view of a portion or the entirety of a workpiece taken along line CC' is shown.

[0011] Figure 4 , Figure 5 and Figure 6 According to various aspects of the present disclosure, Figure 1 During the various stages of the method shown, along Figure 2 The cross-sectional views of the parts of the workpiece are taken along the lines AA' and BB' shown.

[0012] Figure 7 , Figure 8 and Fig. 9 According to various aspects of the present disclosure, Figure 1 Cross-sectional views of parts or the whole of a carrier member during various stages of the method are shown.

[0013] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 and Fig.16 According to various aspects of the present disclosure, Figure 1 During the various stages of the method shown, along Figure 2 The illustrated cross-sectional views are partial or entire cross-sectional views of the workpiece and the carrier taken along the lines AA′ and BB′. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the present disclosure below, forming another feature located on a feature, connected to and / or coupled to a feature may include an embodiment in which another feature is formed in a direct contact manner, and may also include an embodiment in which an insertion can be made in the feature to form an additional feature so that the feature may not be in direct contact. In addition, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "up", "down", "top", "bottom", etc. and their derivative terms (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to simplify the relationship between one feature and another feature of the present disclosure. Spatially relative terms are intended to cover different orientations of devices including features.

[0015] In addition, when "about," "approximately," and similar terms are used to describe numbers or ranges of numbers, the terms are intended to encompass numbers within a reasonable range that takes into account variations that inherently occur during manufacturing, as understood by those of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range that includes the number (e.g., within + / - 10% of the number) based on known manufacturing tolerances associated with manufacturing features having properties associated with the number. For example, a material layer having a thickness of "about 5 nanometers" may encompass a range of sizes from 4.25 nanometers to 5.75 nanometers, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. Further, the present disclosure may reuse reference numbers and / or letters in various examples. Such repetition is for the purposes of brevity and clarity and does not, by itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Attempts have been made to introduce multi-gate devices, such as fin field-effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors, to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effect (SCE). MBC transistors have a gate structure that can extend partially or completely around a channel region to abut the channel region on two or more sides. Since the gate structure of an MBC transistor surrounds the channel region, the MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. The channel region of an MBC transistor may be formed by nanowires, nanosheets, or other nanostructures, and for this reason, the MBC transistor may also be referred to as a nanostructure transistor.

[0017] Traditionally, multi-gate devices (e.g., FinFET and GAA devices) are built in a stacked fashion with transistors at the lowest level and interconnects (vias and wiring) on ​​top of the transistors to provide connectivity to the transistors. Power rails (e.g., metal lines for voltage sources and ground planes) are also located above the transistors and can be part of the interconnects. As integrated circuits continue to scale down, the power rails are also scaled down. This inevitably increases the voltage drop across the power rails and increases the power consumption of the integrated circuits. How to form power rails and vias on the back side of the IC with reduced resistance and reduced coupling capacitance is an area of ​​interest. This increases the number of metal tracks in the structure that can be used to directly connect to source / drain contacts and vias. The gate density is also increased to achieve greater device integration compared to existing structures without backside power rails. The backside power rails can have a wider size than the first level metal (M0) track located on the front side of the structure, which beneficially reduces the power rail resistance.

[0018] Plasma treatments (e.g., plasma etching processes) may be used to form backside power rails and vias and may cause plasma induced damage (PID) in previously formed multi-gate devices, resulting in channel resistance degradation, threshold voltage shifts, circuit leakage, device yield failures, and / or reduced device reliability. Thus, while existing semiconductor structures are generally adequate for their intended purposes, existing semiconductor structures are not yet completely satisfactory in all aspects.

[0019] The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure that reduces plasma induced damage (PID). In some embodiments, the method disclosed herein includes: providing a workpiece and a carrier piece, laminating the carrier piece on the workpiece, performing a plasma etching process on the back side of the workpiece to form a groove, and forming a backside conductive feature in the groove. The workpiece may include a diode, a first transistor including a source / drain (S / D) feature, a second transistor including a metal gate structure, and an interconnect structure disposed thereon. The carrier piece may include a carrier substrate, a bonding layer, and a metal feature passing through the bonding layer. After laminating the workpiece and the carrier piece, the metal feature is electrically coupled to the front side conductive feature of the interconnect structure. In this way, an electrical connection (or conductive path) is formed between the metal gate structure and the metal feature. Therefore, the charge induced by the plasma etching process can be released through the conductive path instead of accumulating around the gate dielectric layer of the metal gate structure of the second transistor or even flowing into the gate dielectric layer, thereby advantageously reducing or even eliminating the PID caused by the charge.

[0020] Various aspects of the present disclosure will now be described in more detail with reference to the drawings. In this regard, Figure 1 is a flow chart of a method 100 for fabricating a semiconductor structure 400 according to various aspects of the present disclosure. Figures 2 to 16 The method 100 is described. Figures 2 to 16 It is a partial top view or cross-sectional view of a workpiece 400 (including a workpiece 200 and a carrier 300) at different stages of manufacture according to the embodiment shown in method 100. Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some of the steps described may be replaced, eliminated, or moved for additional embodiments of the method. For the sake of brevity, not all steps are described in detail herein. For the sake of brevity, portions of the workpiece 400 taken along line A-A' and line B-B' are referred to as zone 200A and zone 200B, respectively. Although zone 200A and zone 200B may not be located in the same plane, both zone 200A and zone 200B are in the same plane. Figures 4 to 6 and Figures 10 to 16 Since the workpiece 400 will be made into a semiconductor structure at the end of the manufacturing process, the workpiece 400 may be referred to as a semiconductor structure 400 as the context requires. For the avoidance of doubt, Figures 2 to 16 The X direction, Y direction and Z direction in the figure are perpendicular to each other and are used consistently throughout the disclosure. Throughout the disclosure, except for the situation excluding this situation, the same reference numerals represent the same features.

[0021] Reference Figures 1 to 4, the method 100 includes block 12 , in which a workpiece 200 is provided. Figure 2 According to this disclosure, various aspects will be experienced Figure 1 Top views of a portion or all of a workpiece 200 are shown at various stages of operations in method 100 . Figure 3 Shown along Figure 2 A cross-sectional view of the workpiece 200 is shown taken along line CC′. Figure 4 Shown along Figure 2 The cross-sectional views of regions 200A and 200B of the workpiece 200 are taken along lines AA′ and BB′.

[0022] like Figures 2 to 4 As shown, the workpiece 200 includes a substrate 202. In one embodiment, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductor materials such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs).

[0023] In an embodiment, the workpiece 200 includes a plurality of active regions (eg, active regions 204a, 204b, 204c) protruding from the substrate 202. Depending on the context, the active regions 204a, 204b, 204c may be individually or collectively referred to as active regions 204. Figure 2 As shown in FIG. 2 , each of the active regions 204 extends longitudinally along the X direction. The active regions 204 may have a fin-shaped structure and are therefore referred to as fins 204 . Figure 2 The number of active regions 204 shown is for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. Figure 2 and Figure 3 In the illustrated embodiment, the workpiece 200 includes an MBC transistor (e.g., Figure 2 The transistors T1, T2 and T3 are shown, and the active region 204 includes a semiconductor layer 206 stack (such as source / drain features 214a, 214b, 214c, 214d and 214e) suspended between each pair of source / drain features. Figure 3204 ). Source / drain features 214a, 214b, 214c, 214d, and 214e may be referred to individually or collectively as source / drain features 214, depending on the context. The semiconductor layer 206 stack serves as a transistor channel for the MBC transistor. Therefore, the semiconductor layer 206 is also referred to as a channel layer 206. Each of the channel layers 206 may be formed of silicon (Si) (e.g., single crystal silicon). Alternatively, the channel layer 206 may include germanium, silicon germanium, or another suitable semiconductor material. Initially, the channel layer 206 is formed as part of a semiconductor layer stack that includes the channel layer 206 and other semiconductor layers (e.g., sacrificial layers) formed of different materials. As part of the process of forming the active region 204, the semiconductor layer stack is also patterned into a fin that protrudes above the substrate 202. During the gate replacement process, the semiconductor layer stack is selectively etched to remove other semiconductor layers, leaving the channel layer 206 suspended above the substrate 202 and between the corresponding source / drain features 214. This is also referred to as a channel release process.

[0024] In this embodiment, the workpiece 200 also includes isolation features 208 (eg, Figure 4 ), to isolate two adjacent active regions 204. The isolation feature 208 may also be referred to as a shallow trench isolation (STI) feature, and may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials.

[0025] In an embodiment, the workpiece 200 includes a metal gate structure (e.g., metal gate structures 210a, 210b, 210c, and 210d) disposed on and wrapped around a channel layer 206 in a channel region of the active region 204 and extending longitudinally along the Y direction. Depending on the context, the metal gate structures 210a, 210b, 210c, and 210d may be individually or collectively referred to as metal gate structures 210. Figure 2The number of metal gate structures 210 shown is for illustrative purposes only and should not be construed as limiting the scope of the present disclosure. In the illustrated embodiment, the metal gate structure 210a has a first portion sandwiched between the source / drain feature 214b and the source / drain feature 214c and a second portion sandwiched between the source / drain feature 214a and the source / drain feature 214e, and the metal gate structure 210b has a portion sandwiched between the source / drain feature 214a and the source / drain feature 214d. In the illustrated embodiment, the metal gate structures 210c and 210d are disposed above the active region 204c. The metal gate structures 210a and 210c may be formed by separating a continuous metal gate structure into two portions by a gate isolation structure 222 (described below). The gate isolation structure 222 may also be configured to provide electrical isolation and physical isolation between the metal gate structure 210b and the metal gate structure 210d. The metal gate structures 210 each include a high-k dielectric layer (i.e., having a dielectric constant greater than that of silicon oxide, which is about 3.9; not shown) disposed on the active region 204 and a metal gate electrode (not shown) disposed on the high-k dielectric layer. The metal gate electrode may also include at least one work function metal layer disposed on the high-k dielectric layer and a bulk conductive layer disposed on the at least one work function metal layer. The work function metal layer may be a p-type work function metal layer or an n-type work function metal layer. Exemplary work function materials include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, other suitable work function materials, or combinations thereof. The bulk conductive layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), other suitable materials, or combinations thereof. The metal gate structure 210 may further include many other layers (not shown), such as an interface layer disposed between the active region 204 and a high-k dielectric layer, a hard mask layer, a cap layer, a barrier layer, other suitable layers, or a combination thereof. The various layers of the metal gate structure 210 may be deposited by any suitable method, such as chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plating, other suitable methods, or a combination thereof. A polishing process (such as a chemical mechanical planarization / polishing (CMP) process) may be performed to remove excess material from the top surface of the metal gate structure 210 to planarize the top surface of the workpiece 200.

[0026] In some embodiments, the metal gate structure 210 is formed after other components of the workpiece 200 (e.g., source / drain features 214) are fabricated. Such a process is generally referred to as a gate replacement process, and the gate replacement process includes: forming a dummy gate structure (not shown) as a placeholder for the metal gate structure 210, forming the source / drain features 214, forming a dielectric structure 228 on the dummy gate structure and the source / drain features 214, planarizing the dielectric structure 228 by, for example, CMP to expose the top surface of the dummy gate structure, removing the dummy gate structure in the dielectric structure 228 to form a trench exposing the channel region of the active region 204, removing the sacrificial layer for channel release, and forming the metal gate structure 210 in the trench and around the channel layer 206 to complete the gate replacement process. Although not shown, in some embodiments, the metal gate structure 210 may be partially recessed, and a dielectric cap layer may be formed on the recessed metal gate structure 210.

[0027] In an embodiment, the workpiece 200 further includes a gate spacer 212 (eg, Figure 3 ). The gate spacer 212 may include a dielectric material, such as an oxygen-containing material (e.g., silicon oxide, silicon oxycarbide, aluminum oxide, aluminum oxynitride, hafnium oxide, titanium oxide, aluminum zirconium oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, silicon oxycarbonitride, etc.), a nitrogen-containing material (e.g., tantalum carbonitride, silicon nitride (SiN), zirconium nitride, silicon carbonitride, etc.), a silicon-containing material (e.g., hafnium silicide, silicon, zirconium silicide, etc.), other suitable materials or combinations thereof. The gate spacer 212 may be a single-layer structure or a multi-layer structure. It should be noted that the composition of the gate spacer 212 is different from the composition of the surrounding dielectric components (e.g., the dielectric structure 228), so that there may be an etching selectivity between the gate spacer 212 and the surrounding dielectric components during a subsequent etching process. In an embodiment, the gate spacer 212 includes SiN. The gate spacer 212 may be formed by first depositing a blanket layer of a spacer material on the workpiece 200 and then performing an anisotropic etching process to remove a portion of the spacer material.

[0028] In some embodiments, the workpiece 200 includes source / drain features 214 formed in and / or on the source / drain regions of the active region 204, each source / drain feature 214 being disposed adjacent to the metal gate structure 210a and / or the metal gate structure 210b. Depending on the context, the source / drain features 214 may be individually or collectively referred to as a source or a drain. In an embodiment, the source / drain feature 214a is a source feature. The source / drain feature 214 may be formed by any suitable technique (e.g., one or more epitaxial growth processes after an etching process). In one example, one or more etching processes are performed to remove a portion of the active region 204, thereby forming a recess (not shown) in the source / drain region. A cleaning process may be performed to clean the recess using a hydrofluoric acid (HF) solution or other suitable solution. Subsequently, one or more epitaxial growth processes are performed to grow the source / drain features 214 in the recess. Each of the source / drain features 214 may be adapted to form a p-type FinFET device, or alternatively may be adapted to form an n-type FinFET device. The p-type source / drain features may include one or more epitaxial layers formed of silicon germanium (epiSiGe) doped with a p-type dopant, such as boron, germanium, indium, and / or other p-type dopants. The n-type source / drain features may include one or more epitaxial layers formed of silicon (epi Si) or silicon carbide (epi SiC) doped with an n-type dopant, such as arsenic, phosphorus, and / or other n-type dopant.

[0029] In some embodiments, the workpiece 200 further includes an internal spacer 216 (eg, Figure 3 ). In some embodiments, the internal spacer 216 comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or a combination thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or carbon oxynitride). In some embodiments, the internal spacer 216 comprises a low-k dielectric material, such as the low-k dielectric material described herein. The internal spacer 216 may be formed by a deposition process and an etching process. For example, after etching the S / D trenches and before epitaxially growing the S / D features 214 from the S / D trenches, an etching process may be used to recess the sacrificial layer between adjacent channel layers 206 to form a gap in the vertical direction between adjacent channel layers 206. Then, one or more dielectric materials are deposited (e.g., using CVD or ALD) to fill the gap. Another etching process is performed to remove the dielectric material outside the gap, thereby forming the internal spacer 216.

[0030] In some embodiments, the dielectric structure 228 is disposed over the source / drain features 214 and may include a contact etch-stop layer (CESL) and an interlayer dielectric (ILD) layer formed over the CESL. The ILD layer includes a dielectric material such as tetraethylorthosilicate (TEOS), silicon oxide, a low-k dielectric material, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borondoped silicate glass (BSG)), other suitable dielectric materials, or combinations thereof. The ILD layer may include a multilayer structure having a plurality of dielectric materials and may be formed by a deposition process such as, for example, CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. The CESL may include silicon nitride, silicon oxynitride, silicon nitride with oxygen or carbon, other suitable materials or combinations thereof, and may be formed by CVD, PVD, ALD, other suitable methods or combinations thereof. An ILD layer may be deposited after depositing the CESL.

[0031] In an embodiment, the workpiece 200 includes a diode (eg, a P / N junction) 205 (eg, a diode 205) disposed in and / or on the substrate 202. Figure 2 and Figure 4204a and 204b). The diode 205 may be any suitable diode. In the present embodiment, the diode 205 is a P / N junction diode and includes a P-well 207 and an N-well 209 directly contacting the P-well 207. In the illustrated embodiment, the P-well 207 and the N-well 209 are arranged side by side along the Y direction, and the N-well 209 is closer to the transistor T1 than the P-well 207. In the illustrated embodiment, the distance between the N-well 209 and the metal gate structure 210a along the Y direction is less than the distance between the P-well 207 and the metal gate structure 210a along the Y direction. In some other embodiments, the P-well 207 and the N-well 209 may be in other relative positions, such as side by side along another direction (e.g., the X direction) or stacked together in the vertical direction. In the illustrated embodiment, the P-well 207 and the N-well 209 are disposed below the isolation feature 208 and between the active area 204b and the active area 204c. In some other embodiments, the P-well 207 and the N-well 209 are disposed at other locations, such as in a portion of one of the active regions 204 (e.g., the active region 204c) and / or between two adjacent isolation features 208. The P-well 207 may be doped with a p-type dopant such as boron, indium, other p-type dopants, or a combination thereof. The N-well 209 may be doped with an n-type dopant such as phosphorus, arsenic, other n-type dopants, or a combination thereof. An ion implantation process, a diffusion process, and / or other suitable doping processes may be performed to form the P-well 207 and the N-well 209.

[0032] exist Figure 4In the embodiment shown, the workpiece 200 includes a gate isolation structure 222, which is disposed between the metal gate structure 210a and the metal gate structure 210c along the Y direction and is in direct contact with the metal gate structure 210a and the metal gate structure 210c. The gate isolation structure 222 is a dielectric feature that separates one or more long metal gate structures into short metal gate structures. In an exemplary process, the long metal gate structure is formed in a first patterning process and then cut into short metal gate structures 210a and 210c in a second patterning process so that the metal gate structures 210a and 210c have designed dimensions. The gate isolation structure 222 can be formed by forming a trench by a patterning process and filling the trench with one or more dielectric materials by a deposition process. The patterning process includes a photolithography process and an etching process, and a hard mask can be used to define the area for the gate isolation structure 222. The etching process can include wet etching, dry etching, or a combination thereof to etch the conductive material through the long metal gate structure. The etching process may use one or more etchants. CMP may be performed after the deposition process to remove excess material of the gate isolation structure 222 deposited on the dielectric structure 228 and the metal gate structure 210 and to planarize the top surface of the workpiece 200. The gate isolation structure 222 and the isolation feature 208 may together provide isolation functions—isolating the metal gate structure 210a and the metal gate structure 210c from each other and isolating the metal gate structures 210a and 210c from nearby conductors including the diode 205.

[0033] Reference Figure 1 and Figures 5 and 6 The method 100 includes block 14 , in which contacts, vias, and front-side interconnect structures 260 are formed on the workpiece 200 . Figure 5 and Figure 6 Shown along Figure 2 The workpiece 200 is a cross-sectional view taken along line AA′ and line BB′.

[0034] about Figure 5, diode contacts 225a and 225b are formed on the P-well 207 and the N-well 209, respectively, and a source / drain contact 230 is formed on the source / drain feature 214a. In the illustrated embodiment, the source / drain contact 230 is electrically coupled to the source / drain feature 214a. In an example, an etching process is used to remove a portion of the dielectric structure 228 to form a contact trench, so that the source / drain feature 214a is exposed in the contact trench. A deposition process (such as PVD, CVD or metal organic chemical vapor deposition (MOCVD)) is then performed to form the source / drain contact 230 on the source / drain feature 214a. A CMP process may be performed to remove excess material and planarize the top surface. The S / D contact 230 may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), or a combination thereof. The workpiece 200 may also include a silicide feature 232 between the source / drain contact 230 and the source / drain feature 214a to further reduce the contact resistance. Forming the silicide feature 232 may include: depositing one or more metals into the contact trench using CVD, PVD, ALD, or other suitable methods; performing an annealing process on the workpiece 200 to cause a reaction between the one or more metals and the S / D feature 214a to produce the silicide feature 232; and removing unreacted portions of the one or more metals to leave the silicide feature 232 in the contact trench. The silicide features 232 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. Alternatively, silicide formation may be skipped, and the source / drain contacts 230 may directly contact the source / drain features 214a.

[0035] In an embodiment, the diode contacts 225a and 225b are electrically coupled to the P-well 207 and the N-well 209, respectively. In an example, an etching process is used to remove a portion of the gate isolation structure 222 and a portion of the isolation feature 208 to form a contact trench, so that the P-well 207 and the N-well 209 are exposed in the contact trench, respectively. A deposition process (such as PVD, CVD, or metal organic chemical vapor deposition (MOCVD)) is then performed to form diode contacts 225a and 225b that are connected to the P-well 207 and the N-well 209, respectively. A CMP process may be performed to remove excess material and planarize the top surface. The diode contacts 225a and 225b may include a material similar to the source / drain contact 230. The diode contacts 225a and 225b and the source / drain contact 230 may be formed simultaneously or in any suitable sequential order.

[0036] The operation in block 14 of the method 100 also includes forming a dielectric layer 238 over the workpiece 200. In some embodiments, the dielectric layer 238 may include silicon oxide, tetraethyl orthosilicate (TEOS) oxide, un-doped silicate glass (USG) or doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fused silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), and / or other suitable dielectric materials. The dielectric layer 238 may be deposited using plasma-enhanced CVD (PECVD), FCVD, spin coating, or a suitable deposition technique. In some embodiments, after forming the dielectric layer 238, the workpiece 200 may be annealed to improve the integrity of the dielectric layer 238. In some embodiments, before forming the dielectric layer 238, an etch stop layer is deposited over the workpiece 200. The formation and composition of the etch stop layer may be similar to the formation and composition of the CESL of the dielectric structure 228 .

[0037] After forming the dielectric layer 238, the gate via 235 is formed to electrically couple to the metal gate structure 210a, and the vias 240a, 240b, and 240c are formed to electrically couple to the diode contacts 225a and 225b and the source / drain contacts 230, respectively. In an embodiment, the gate via 235 and the vias 240a, 240b, and 240c are formed to extend through the dielectric layer 238 by any suitable method. For example, a via metal material is deposited into a via trench extending through the dielectric layer 238 by, for example, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like. A CMP process is then used to remove excess material and planarize the top surface. Each of the gate via 235 and the vias 240a, 240b, and 240c may include a conductive barrier layer and a metal fill layer located on the conductive barrier layer. The conductive barrier layer is used to prevent the metal material of the metal filling layer from diffusing into the dielectric layer (e.g., dielectric layer 238) adjacent to the gate via 235 and the vias 240a, 240b, and 240c. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride (e.g., titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN)), or a combination thereof, and may be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer is omitted.

[0038] Reference Figure 6, the operation in block 14 of method 100 also includes forming a front-side interconnect structure 260 on the workpiece 200. The front-side interconnect structure 260 includes a dielectric structure 258 (e.g., multiple interlayer dielectric (ILD) layers and / or multiple etch stop layers (ESL)) and a front-side conductive feature (e.g., metal line, metal via) disposed in the dielectric structure 258. The dielectric structure 258 may include a dielectric material similar to the dielectric material of the dielectric structure 228 and the dielectric layer 238. The front-side interconnect structure 260 may include one or more interconnect layers. In the illustrated embodiment, the front-side interconnect structure 260 includes a metal zero interconnect layer M0 (M0 level), a via zero interconnect layer V0 (V0 level), ..., and a metal x interconnect layer Mx (Mx level). For simplicity, the levels between the V0 level and the Mx level are not shown. Each of the interconnect layers may be referred to as a metal level. The metal lines formed at the M0 level may be referred to as M0 metal lines (e.g., M0 metal lines 245a, 245b, and 245c). Similarly, vias or metal lines formed at the V0 level, the M1 level, ..., and the Mx level may be referred to as V0 vias (e.g., V0 vias 250a, 250b, and 250c), M1 metal lines, ..., and Mx metal lines (e.g., Mx metal line 257), respectively, and x may be an integer in the range of 1 to 10. Each level of the front-side interconnect structure 260 includes a layer of front-side conductive features (e.g., metal lines, metal vias) disposed in a dielectric layer of the dielectric structure 258. In some embodiments, the front-side conductive features at the same level (e.g., M0 level) of the front-side interconnect structure 260 are formed simultaneously. In some embodiments, the front conductive features at the same level of the front interconnect structure 260 have top surfaces that are substantially planar with each other and / or bottom surfaces that are substantially planar with each other.

[0039] The front side conductive features (e.g., metal lines, metal vias) may include copper, copper alloys, titanium, tantalum, tungsten, cobalt, molybdenum, ruthenium, or conductive nitrides (e.g., titanium nitride, titanium aluminum nitride, tungsten nitride, tantalum nitride) or other conductive materials or combinations thereof, and may be formed using a damascene process, a dual damascene process, chemical vapor deposition (CVD), physical vapor deposition, atomic layer deposition (ALD), and / or other suitable processes. In some embodiments, the front side conductive features include copper (Cu). Each of the metal lines and metal vias may include a conductive barrier layer (e.g., TiN or TaN) surrounding a metal core (e.g., copper).

[0040] The front side conductive features electrically couple various electrical components of the workpiece 200, such as the gate via 235 and the vias 240a, 240b, and 240c. Figure 6In the illustrated embodiment, gate via 235 connects metal gate structure 210a to M0 metal line 245b, via 240a connects diode contact 225a to M0 metal line 245a, via 240b connects diode contact 225b to M0 metal line 245b, and via 240c connects source / drain contact 230 to M0 metal line 245c. In some other embodiments not shown, gate via 235 and via 240b are not connected to the same M0 metal line; instead, gate via 235 and via 240b are connected to two different M0 metal lines, which are connected together by a metal line (e.g., M1 metal line) disposed at a higher level. The V0 level includes V0 vias 250a, 250b, and 250c that connect M0 metal lines 245a, 245b, and 245c to M1 metal lines (not shown), respectively. In an embodiment, the V0 via 250a is electrically coupled to the Mx metal line 257 through a first stack S1 of metal lines and metal vias (e.g., M1, M2, ..., M(x-1) metal lines and V1, V2, ..., V(x-1) vias) disposed between the V0 via 250a and the Mx metal line 257. It should be noted that the Mx metal line 257 is located at the topmost interconnect layer (Mx level) of the front-side interconnect structure 260. In an embodiment, the V0 vias 250b and 250c are electrically connected to the metal line 255 through a second stack S2 and a third stack S3 of metal lines and metal vias, respectively. The second stack S2 and the third stack S3 of metal lines and metal vias may each include M1, M2, ..., M(x-1) metal lines and V1, V2, ..., V(x-1) vias or a combination of levels of metal lines and metal vias. In some embodiments, the first stack S1, the second stack S2, and the third stack S3 of metal lines and metal vias are not in direct contact with each other. In an embodiment, the first stack S1, the second stack S2, and the third stack S3 of metal lines and metal vias are spaced apart from each other. Metal line 255 may be located at any one of the M1 level, the M2 level, ..., and the Mx level. In some embodiments, Mx metal line 257 and metal line 255 may be located at the same level or at different levels. That is, metal line 255 is located at a level lower than Mx metal line 257 or at the same level as Mx metal line 257. In an embodiment, metal line 255 is located at the M1 level and is in direct contact with both V0 vias 250b and 250c.

[0041] For simplicity, the M0 metal line 245a, the V0 via 250a, the Mx metal line 257, and the first stack S1 of metal lines and metal vias are collectively referred to as the first portion 265 of the front-side conductive features. Figure 6The M0 metal lines 245b and 245c, the V0 vias 250b and 250c, the metal line 255, and the second and third stacks S2 and S3 of metal lines and metal vias are collectively referred to as the second portion 267 of the front conductive features, as shown in FIG. Figure 6 For simplicity, the interconnect structures 260 located above the V0 level in the regions 200A and 200B are merged. It should be understood that Figure 6 The front conductive features shown may not be located in the same vertical plane. For example, the Mx metal line 257 may not overlap the M0 metal line 245a in the vertical direction. It should be understood that unless otherwise required, Figure 6 The vias and metal lines of the interconnect structure 260 are shown only to provide a simplified example and are not intended to be limiting.

[0042] Reference Figure 1 and Figure 7 The method 100 includes block 16 in which a carrier component 300 is formed. The carrier component 300 includes a carrier substrate 302 and a bonding layer 304 disposed on the carrier substrate 302 . Figure 7 A cross-sectional view of a carrier member 300 is shown. In an embodiment, the carrier substrate 302 includes a composition similar to the substrate 202 so that the charge can be discharged through the carrier substrate 302. In an embodiment, both the substrate 202 and the carrier substrate 302 are formed of silicon. In an embodiment, the bonding layer 304 has a different material composition than the carrier substrate 302. In some embodiments, the bonding layer 304 includes a dielectric material and the carrier substrate 302 includes a semiconductor material. The bonding layer 304 may include an oxide (e.g., silicon oxide or a similar oxide) deposited by CVD (e.g., high density plasma (HDP)), ALD, PVD, thermal oxidation, or a similar process. Other suitable materials and processes may be used to form the carrier member 300.

[0043] Reference Figure 1 and Figure 8 The method 100 includes block 18 where a first trench 306 is formed through the bonding layer 304 . Figure 8 A cross-sectional view of a carrier member 300 is shown. The first trench 306 may be formed by any suitable method. In an example, a patterning process is performed on the carrier member 300 to form the first trench 306. The first trench 306 may terminate at a region of the carrier substrate 302 and expose the region. The first trench 306 may terminate at a surface of the carrier substrate 302. In some embodiments, the patterning process includes an etching process, such as a dry etching process or a wet etching process. An etching mask layer may be used during such an etching process.

[0044] Reference Figure 1and Fig. 9 The method 100 includes block 20 where a metal feature 308 is formed in a first trench 306 . Fig. 9 A cross-sectional view of the carrier 300 is shown. In an embodiment, one or more conductive materials may be deposited on the carrier 300 (including in the first trench 306). A CMP process is then used to remove excess material and planarize the top surface. The metal feature 308 may include a conductive barrier layer and a metal fill layer located on the conductive barrier layer. The conductive barrier layer is used to prevent the metal material of the metal fill layer from diffusing into a dielectric layer (e.g., bonding layer 304) adjacent to the metal feature 308. The conductive barrier layer may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride (e.g., titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or a combination thereof), and may be formed by CVD, PVD, ALD, and / or other suitable processes. In some embodiments, the conductive barrier layer is omitted. The metal filling layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru) or other metals, and may be formed by CVD, PVD, ALD, plating or other suitable processes. In an embodiment, the metal filling layer includes Cu.

[0045] Reference Figure 1 and Fig.10 The method 100 includes block 22 , in which the carrier 300 is flipped over and attached to the workpiece 200 . Fig.10 A cross-sectional view is shown of a combination of a workpiece 200 and a carrier 300. For the sake of brevity, the combination of the workpiece 200 and the carrier 300 may be referred to as a workpiece 400.

[0046] The bonding layer 304 bonds the carrier substrate 302 to the workpiece 200. For example, the interconnect structure 260 is bonded to the carrier substrate 302 through the bonding layer 304. When the bonding is completed, the Mx metal line 257 is bonded to and electrically coupled to the metal feature 308. In an embodiment, the Mx metal line 257 is in direct contact with the metal feature 308. Since the Mx metal line 257 is electrically coupled to the P-well 207, and the N-well 209 is electrically coupled to the source / drain feature 214a, a conductive path CP is formed. In an embodiment, the conductive path CP is formed by the source / drain feature 214a, the source / drain contact 230, the via 240c, the second portion 267 of the front conductive feature, the via 240b, the diode contact 225b, the diode 205, the diode contact 225a, the via 240a, the first portion 265 of the front conductive feature, and the metal feature 308. The components forming the conductive path CP are electrically coupled together. The conductive path CP includes two parts: a first part (CP-1) formed by the source / drain feature 214a, the source / drain contact 230, the via 240c, the second part 267 of the front conductive feature, the via 240b, the diode contact 225b, and the N-well 209 of the diode 205; and a second part (CP-2) formed by the P-well 207 of the diode 205, the diode contact 225a, the via 240a, the first part 265 of the front conductive feature, and the metal feature 308.

[0047] Reference Figure 1 and Fig.11 , the method 100 includes block 24, in which a first plasma etching process 402 is performed on the back side of the workpiece 200 to form a second trench 406 exposing the source / drain feature 214a. In some embodiments, a hard mask 404 having an opening is formed below the workpiece 200. While using the hard mask 404 as an etching mask, the first plasma etching process 402 is performed to remove a portion of the substrate 202 to form the second trench 406. At least a portion of the bottom surface of the source / drain feature 214a is exposed in the second trench 406. The hard mask 404 can then be selectively removed after the second trench 406 is formed. During the first plasma etching process 402, charges 408 (e.g., electrons) can be generated, and the charges 408 can flow from the opening of the hard mask 404 into the workpiece 200, as shown in FIG. Fig.11As shown. When the workpiece 200 is etched, at least some of the charges 408 may be released to the carrier substrate 302 via the conductive path CP. The charges 408 (if any) in the workpiece 200 travel via the conductive path CP instead of accumulating in the workpiece 200 (e.g., accumulating in the gate via 235, the metal gate structure 210a, and the channel layer 206), thereby preventing the components of the transistor T1 (e.g., the metal gate structure 210a, the channel layer 206) from being damaged during the first plasma etching process 402. In an embodiment, the transistor T1 (e.g., including the metal gate structure 210a and the channel layer 206 surrounded by the metal gate structure 210a) and the gate via 235 do not have the charges 408 during the first plasma etching process 402. In some embodiments, the carrier substrate 302 is grounded during the execution of the first plasma etching process 402, and the charges 408 are released.

[0048] The conductive path CP provides a discharge path for the charge 408 generated during an etching process (e.g., the first plasma etching process 402). The conductive path CP can minimize etching damage (e.g., PID damage), reduce the area required for protection circuitry, reduce (or eliminate) the impact on the performance of devices (e.g., transistor T1) of the workpiece 200, and / or enhance the etching process margin that can be used to etch the workpiece 200 to form backside conductive features (because the conductive path CP can effectively release etching-induced charges, thereby improving the processing tolerance of the semiconductor structure (e.g., allowing a higher power plasma environment)). In addition to providing a discharge path for charges generated during an etching process (e.g., charges generated during a plasma etching process), the conductive path CP can also be used as a discharge path for charges generated during other manufacturing processes and / or operations of the semiconductor structure, particularly charges caused during any plasma environment process (e.g., plasma enhanced ALD (PEALD) process, plasma enhanced CVD (PECVD) process).

[0049] Reference Figure 1 and Fig.12 The method 100 includes block 26 of forming a backside via 416 (or first backside conductive feature 416 ) electrically coupled to the source / drain feature 214 a in the second trench 406 . In an embodiment, the conductive path CP is further formed by the backside via 416 .

[0050] In an embodiment, the backside via 416 is spaced apart from the substrate 202 by a dielectric liner 414. The dielectric liner 414 may include a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. For example, the dielectric liner 414 may be formed by blanket depositing a dielectric material layer over the backside of the workpiece 200 in a conformal manner using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, a PVD process, or other suitable process. In the illustrated embodiment, the deposition of the dielectric material layer is followed by an etch-back (e.g., anisotropic) process to remove the dielectric material layer from the horizontal surface and expose the bottom surface of the S / D feature 214a. The dielectric material layer may remain on the sidewalls of the second trench 406 as the dielectric liner 414. In some embodiments, the etch-back process may include a wet etching process, a dry etching process, a multi-step etching process, and / or combinations thereof.

[0051] In an embodiment, a backside via 416 is then disposed in the second trench 406 over the dielectric liner 414. The backside via 416 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. The dielectric liner 414 provides electrical isolation between the backside via 416 and the substrate 202. In an embodiment, a backside silicide feature 412 is formed between the S / D feature 214a and the backside via 416 to further reduce contact resistance. Forming the backside silicide feature 412 may include: depositing one or more metals into the second trench 406; performing an annealing process on the workpiece 200 to cause a reaction between the one or more metals and the S / D feature 214a to produce the backside silicide structure 412; and removing unreacted portions of the one or more metals, leaving the backside silicide feature 412 in the second trench 406. In the case of forming the backside silicide feature 412, the conductive path CP is further formed by the backside silicide feature 412. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (e.g., an alloy of two or more metals), and may be deposited using CVD, PVD, ALD, or other suitable methods. The backside silicide feature 412 may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), combinations thereof, or other suitable compounds. A planarization operation (e.g., a CMP process) is performed to remove excess material of the backside via 416 and the dielectric liner 414. Alternatively, the backside via 416 directly contacts the S / D feature 214a.

[0052] In the present embodiment, the backside via 416 extends through the substrate 202. In some other embodiments, after the carrier 300 is bonded to the workpiece 200, the substrate 202 below the source / drain features 214a is replaced with a replacement dielectric layer (not shown), the second trench 406 is formed by etching through (e.g., by a first plasma etching process 402) the replacement dielectric layer to expose the source / drain features 214a, and the backside via 416 is formed in the second trench 406. In such an embodiment, the dielectric liner 414 may be omitted.

[0053] Reference Figure 1 and Fig.13, method 100 includes block 28, in which a dielectric layer 418 is formed under the back side of workpiece 200. Dielectric layer 418 may include a dielectric material similar to that in dielectric layer 238 and may be formed using a similar method as dielectric layer 238 (e.g., PECVD, FCVD, spin coating, or a suitable deposition technique).

[0054] Reference Figure 1 and Fig.14 The method 100 includes block 30 where a second plasma etching process 422 is performed to form a third trench 424 extending through the dielectric layer 418 to expose the backside via 416 .

[0055] In some embodiments, a hard mask 428 having an opening is formed under the dielectric layer 418. While using the hard mask 428 as an etching mask, a second plasma etching process 422 is performed to remove a portion of the dielectric layer 418 to form a third trench 424. At least a portion of the bottom surface of the backside via 416 is exposed in the third trench 424. The hard mask 428 can then be selectively removed after the third trench 424 is formed. Similar to the first plasma etching process 402, during the second plasma etching process 422, charges (e.g., electrons) 408' can be generated, and the charges 408' can flow from the opening of the hard mask 428 into the workpiece 200, such as Fig.14 As shown. When the dielectric layer 418 is etched, at least some of the charges 408' may be released to the carrier substrate 302 via the conductive path CP. The charges 408' (if any) in the workpiece 200 travel via the conductive path CP instead of accumulating in the workpiece 200 (e.g., accumulating in the gate via 235, the metal gate structure 210a, and the channel layer 206), thereby preventing the components of the transistor T1 (e.g., the metal gate structure 210a, the channel layer 206) from being damaged during the second plasma etching process 422. In an embodiment, during the second plasma etching process 422, the transistor T1 (e.g., including the metal gate structure 210a and the channel layer 206 surrounded by the metal gate structure 210a) and the gate via 235 do not have the charges 408. In some embodiments, the carrier substrate 302 is grounded during the execution of the second plasma etching process 422, and the charges 408 are released. The benefits of the conductive path CP during the second plasma etching process 422 are similar to those described above with respect to the first plasma etching process 402 .

[0056] Reference Figure 1 and Fig.15 The method 100 includes block 32 of forming a second backside conductive feature 430 in the third trench 424. The second backside conductive feature 430 is electrically coupled to the backside via 416, and a conductive path CP is further formed by the second backside conductive feature 430.

[0057] The formation of the second backside conductive features 430 may be similar to the frontside conductive features. For example, the second backside conductive features 430 may be formed using a damascene process, a dual damascene process, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or other suitable processes. A CMP process is then used to remove excess material and planarize the top surface. The second backside conductive features 430 may include materials similar to the frontside conductive features and may include a conductive barrier layer (e.g., TiN or TaN) surrounding a metal core (e.g., copper). Although not shown, the second backside conductive features 430 are electrically isolated from the substrate 202 by an etch stop layer.

[0058] Reference Figure 1 and Fig.16 , the method 100 includes block 34, where additional processes are performed. For example, additional dielectric layer 432 and additional backside conductive features (e.g., backside conductive features 434 and 436) may be formed by repeating steps similar to the dielectric layer 418 and the second backside conductive feature 430 (e.g., blocks 28, 30, and 32) one or more times to complete the backside interconnect structure 440. The additional backside conductive features are electrically coupled to the second backside conductive feature 430. Similarly, the charge 442 generated during the formation of the backside conductive features 434 and 436 may also be discharged through the conductive path CP. In some embodiments, the method further includes separating the carrier 300 from the workpiece 200 after forming the backside interconnect structure 440.

[0059] The dielectric layer 418, the second backside conductive feature 430, the additional dielectric layer 432 and the additional backside conductive features (eg, backside conductive features 434 and 436) together form a backside interconnect structure 440, such as Fig.16 As shown. Backside via 416, second backside conductive feature 430 and additional backside conductive feature together form backside conductive feature. Dielectric layer 418 and additional dielectric layer 432 together form backside dielectric structure. Now, conductive path CP includes three parts: first part (CP-1), second part (CP-2) and third part (CP-3) formed by backside conductive feature. Now, conductive path CP is formed by backside conductive feature, source / drain feature 214a, source / drain contact 230, via 240c, second part 267 of front side conductive feature, via 240b, diode contact 225b, diode 205, diode contact 225a, via 240a, first part 265 of front side conductive feature and metal feature 308. In an embodiment, backside conductive feature can transfer power to transistor and is called power rail. In an embodiment, carrier substrate 302 is grounded.

[0060] In the illustrated embodiment, the backside interconnect structure 440 includes a backside metal zero level BM0 (BM0 level), a backside via zero interconnect layer BV0 (BV0 level), ..., and a backside metal z interconnect layer BMz (BMz level). For the sake of simplicity, the levels between the BV0 level and the BMz level are not shown. Each of the BM0 level, the BV0 level, ..., and the BMz level may be referred to as a backside metal level. The metal line formed at the BM0 level may be referred to as a BM0 metal line (e.g., the second backside conductive feature 430). Similarly, the vias or metal lines formed at the BV0 level and the BMz level may be referred to as BV0 vias and BMz metal lines, respectively, and z is an integer ranging from 1 to 10. Each level of the backside interconnect structure 440 includes a backside conductive feature (e.g., metal line, metal via) disposed in one or more dielectric layers (e.g., dielectric layers 418 and 432).

[0061] exist Fig.16 In the illustrated embodiment, the BM0 level includes a second backside conductive feature 430. The BV0 level includes a backside conductive feature 434 (or a BV0 via 434) disposed in the additional dielectric layer 432 and formed below and electrically coupled to the second backside conductive feature 430. The BMz level includes a backside conductive feature 436 (or a BMz metal line 436) disposed in the additional dielectric layer 432, wherein the BMz metal line 436 is located below and electrically coupled to the backside conductive feature 434 (e.g., through metal lines and metal vias in levels BM(z-1) to BM1).

[0062] In reference Figure 2 and Figures 4 to 16 In the above described embodiment, the backside via 416 is formed directly under the source / drain feature 214a, and the conductive path CP includes a bypass path (e.g., CP-2) for transferring the charge generated during the formation of the backside via and / or other conductive features of the backside interconnect structure 440. The positional relationship between the source / drain feature 214a, the metal gate structure 210a, and the diode 205 is merely an example and is not intended to limit the present disclosure to the contents explicitly shown therein. For example, in some other embodiments, one or more backside vias and / or other conductive features of the backside interconnect structure 440 may be formed under other source / drain features (e.g., source / drain feature 214e, source / source features adjacent to the metal gate structure 210c or the metal gate structure 210d (not shown)), and the charge generated during the formation of the backside vias and / or other conductive features of the backside interconnect structure 440 may also be discharged in a manner similar to that described above with respect to the method 100.

[0063] Still refer to Fig.16 , an equivalent circuit 500 of a portion of the workpiece 400 is shown. The transistor T1 includes a gate structure (G) corresponding to the metal gate structure 210a and a source feature (S) and a drain feature (D) corresponding to the source / drain features 214b and 214c. When the carrier substrate 302 is grounded, the charges (e.g., charges 408, 408', 442) generated during the plasma etching process (e.g., plasma etching processes 402 and 422) can be discharged through the conductive path CP (e.g., the second portion CP-2) instead of being accumulated at the gate structure of the transistor T1. Therefore, the transistor T1 does not have the charges generated during the plasma etching process.

[0064] It should be understood that the method 100 described herein may be applied to form a semiconductor device including the semiconductor device described above and as shown in FIG. Figures 2 to 16 Multiple structures of workpiece 200, 300 and / or 400 are shown. In such an embodiment, multiple conductive paths CP can be formed. Multiple backside conductive features in the same backside metal interconnect layer (eg, BMO level) can be formed simultaneously.

[0065] Although not intended to be limiting, one or more embodiments of the present disclosure provide numerous benefits to semiconductor devices and their formation. For example, the present disclosure provides a semiconductor structure that includes a semiconductor structure that reduces plasma induced damage (PID) during and / or after a manufacturing process (e.g., a plasma etching process of the back side of the semiconductor structure). The semiconductor structures and methods disclosed herein also reduce the area required for protection circuits, reduce (or eliminate) the impact on device (e.g., transistor) performance, and / or enhance the etching process margin (etching process window) that can be used to etch the semiconductor structure to form backside conductive features. This should not be construed as limiting the disclosed semiconductor structures and methods to reduce other types of plasma induced damage. For example, it is contemplated that the disclosed semiconductor structures and methods can reduce any damage induced by a process using a plasma environment. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, and not all embodiments require specific advantages.

[0066] The present disclosure provides many different embodiments. Semiconductor structures and methods for making the same are disclosed herein. In one exemplary aspect, the present disclosure is about a method. The method includes: providing a workpiece; providing a carrier member, the carrier member including a carrier substrate and a bonding layer located on the carrier substrate; forming a first trench through the bonding layer; and forming a metal feature in the first trench. The workpiece includes: a diode located in a substrate; a first transistor including a source / drain (S / D) feature located in and on the substrate; and an interconnect structure disposed on the substrate. The interconnect structure includes a multilayer dielectric structure and a plurality of front-side conductive features disposed in the multilayer dielectric structure. The diode is electrically coupled to the S / D feature through a first portion of the plurality of front-side conductive features of the interconnect structure. The method also includes: attaching the carrier member to the interconnect structure so that the metal feature directly contacts one of the plurality of front-side conductive features. The metal feature is electrically coupled to the diode through a second portion of the plurality of front-side conductive features of the interconnect structure. The method further includes performing a first plasma etching process on the back side of the substrate to form a second trench exposing a bottom surface of the S / D feature; and forming a first backside conductive feature electrically coupled to the S / D feature in the second trench.

[0067] In some embodiments, the diode includes a P-well and an N-well. The workpiece also includes: a second transistor adjacent to the diode and including an active region and a metal gate structure disposed on the active region; a gate via disposed on the metal gate structure and contacting the metal gate structure; a first contact disposed on the P-well and electrically connecting the P-well to a second portion of the plurality of front-side conductive features of the interconnect structure; a second contact disposed on the N-well and electrically connecting the N-well to a first portion of the plurality of front-side conductive features of the interconnect structure; and a third contact disposed on the S / D feature and electrically connecting the S / D feature to a first portion of the plurality of front-side conductive features of the interconnect structure. In some embodiments, a first conductive path electrically coupling the S / D feature to the N-well is formed by the second contact, the third contact, and the first portion of the plurality of front-side conductive features. A second conductive path electrically coupling the P-well to the carrier substrate is formed by the first contact, the second portion of the plurality of front-side conductive features, and the metal feature. In some embodiments, the metal gate structure is connected to the first portion of the plurality of front-side conductive features through the gate via. In some embodiments, during the first plasma etching process, the second transistor has no charge. In some embodiments, a conductive path electrically coupling the carrier substrate to the S / D feature is formed by the metal feature, the second portion of the plurality of front side conductive features, the diode, and the first portion of the plurality of front side conductive features. In some embodiments, the method further includes electrically grounding the carrier substrate. In some embodiments, the method further includes: forming a dielectric layer below the bottom surface of the workpiece; performing a second plasma etching process on the back side of the workpiece to form a third trench in the dielectric layer, the third trench exposing the bottom surface of the first back side conductive feature; and forming a second back side conductive feature in the third trench. In some embodiments, the workpiece further includes an isolation feature disposed above the diode.

[0068] In another exemplary aspect, the disclosure relates to a method. The method includes providing a first workpiece and providing a second workpiece. The first workpiece includes: a first transistor including a source / drain (S / D) feature; a second transistor adjacent to the first transistor and including a gate structure; a diode adjacent to the second transistor; and an interconnect structure including a plurality of metal lines and vias. A first interconnect layer of the interconnect structure includes a metal line electrically coupled to both the gate structure and the source / drain feature. The second workpiece includes: a first dielectric layer; a metal feature extending through the first dielectric layer; and a carrier substrate disposed on the first dielectric layer. The method also includes: attaching the second workpiece to the first workpiece so that the metal feature is electrically coupled to the gate structure through the diode and the plurality of metal lines and vias; and performing a first plasma etching process on the back side of the first workpiece to form a first trench. The S / D feature is exposed in the first trench. The method also includes forming a first backside conductive feature in the first trench.

[0069] In some embodiments, during the first plasma etching process, the second transistor has no charge. In some embodiments, during the first plasma etching process, a conductive path electrically coupling the S / D feature to the carrier substrate is formed by the plurality of metal lines and vias, the diode, and the metal feature. In some embodiments, the gate structure wraps around the second transistor and the plurality of nanostructures of the first transistor. In some embodiments, the diode includes a P-well and an N-well laterally adjacent to the P-well, and the distance between the N-well and the gate structure is less than the distance between the P-well and the gate structure. The plurality of metal lines and vias include a first portion connected to the metal feature and the P-well and a second portion connected to each of the N-well, the gate structure, and the S / D feature. The first portion is spaced apart from the second portion. In some embodiments, the method further includes electrically grounding the carrier substrate. In some embodiments, the method further includes: forming a second dielectric layer below the first backside conductive feature; and performing a second plasma etching process on the backside of the first workpiece to form a second trench through the second dielectric layer. The first backside conductive feature is exposed in the second trench. The method further includes forming a second backside conductive feature in the second trench.

[0070] In another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a first substrate; a first transistor including a fin structure protruding from the first substrate and a metal gate structure disposed on the fin structure; a diode disposed in the first substrate and adjacent to the first transistor; a second transistor adjacent to the first transistor and including a source / drain (S / D) feature; a first backside conductive structure disposed below the S / D feature and electrically coupled to the S / D feature; and an interconnect structure disposed on the first substrate. The interconnect structure includes a multilayer dielectric structure and a plurality of frontside conductive features embedded in the multilayer dielectric structure. The semiconductor structure also includes: a dielectric layer disposed on the interconnect structure; a metal feature disposed to pass through the dielectric layer and contact one of the plurality of frontside conductive features; and a second substrate disposed on the dielectric layer and the metal feature. The plurality of frontside conductive features include a first portion of a P-well connected to the metal feature and the diode, and a second portion of an N-well connected to the S / D feature, the metal gate structure, and the diode.

[0071] In some embodiments, the semiconductor structure further comprises: a first contact connecting the P-well to a first portion of a plurality of front-side conductive features; a second contact connecting the N-well to a second portion of the plurality of front-side conductive features; a gate via connecting a metal gate structure to a second portion of the plurality of front-side conductive features; and a third contact connecting an S / D feature to a second portion of the plurality of front-side conductive features. In some embodiments, the semiconductor structure further comprises a second back-side conductive structure, the second back-side conductive structure being located below the first back-side conductive structure and contacting the first back-side conductive structure. In some embodiments, the first back-side conductive structure comprises a plurality of back-side metal lines and back-side vias.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: An artifact is provided, the artifact comprising: The diode, located in the substrate, a first transistor including source / drain (S / D) features in and above the substrate, and an interconnect structure disposed on the substrate and comprising a multi-layer dielectric structure and a plurality of front-side conductive features disposed in the multi-layer dielectric structure, wherein the diode is electrically coupled to the source / drain feature through a first portion of the plurality of front-side conductive features of the interconnect structure; Providing a carrier component, the carrier component comprising a carrier substrate and a bonding layer located on the carrier substrate; forming a first trench through the bonding layer; forming a metal feature in the first trench, attaching the carrier member to the interconnect structure such that the metal feature directly contacts one of the plurality of front conductive features, wherein the metal feature is electrically coupled to the diode through a second portion of the plurality of front conductive features of the interconnect structure; performing a first plasma etching process on the back side of the substrate to form a second trench exposing a bottom surface of the source / drain feature; and A first backside conductive feature is formed in the second trench electrically coupled to the source / drain feature.

2. The method for forming a semiconductor structure according to claim 1, wherein: The diode includes a P well and an N well, and The artifacts also include: a second transistor, adjacent to the diode and comprising an active region and a metal gate structure disposed on the active region, A gate through hole is disposed on the metal gate structure and contacts the metal gate structure, a first contact disposed above the P-well and electrically connecting the P-well to the second portion of the plurality of front-side conductive features of the interconnect structure, a second contact disposed above the N-well and electrically connecting the N-well to the first portion of the plurality of front-side conductive features of the interconnect structure, and A third contact is disposed on the source / drain feature and electrically connects the source / drain feature to the first portion of the plurality of front-side conductive features of the interconnect structure.

3. The method for forming a semiconductor structure according to claim 2, wherein: A first conductive path electrically coupling the source / drain feature to the N-well is formed by the second contact, the third contact, and the first portion of the plurality of front conductive features, and A second conductive path electrically coupling the P-well to the carrier substrate is formed by the first contact, the second portions of the plurality of front-side conductive features, and the metal feature.

4. The method for forming a semiconductor structure according to claim 2, wherein: The metal gate structure is connected to the first portion of the plurality of front-side conductive features through the gate via.

5. The method for forming a semiconductor structure according to claim 1, wherein: A conductive path electrically coupling the carrier substrate with the source / drain features is formed by the metal feature, the second portion of the plurality of front-side conductive features, the diode, and the first portion of the plurality of front-side conductive features.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also included is electrically grounding the carrier substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a dielectric layer below a bottom surface of the workpiece; performing a second plasma etching process on the back side of the workpiece to form a third trench in the dielectric layer, the third trench exposing a bottom surface of the first back side conductive feature; as well as A second backside conductive feature is formed in the third trench.

8. A method for forming a semiconductor structure, comprising: A first workpiece is provided, wherein the first workpiece comprises: a first transistor including source / drain (S / D) features, a second transistor, adjacent to the first transistor and comprising a gate structure, a diode adjacent to the second transistor, and an interconnect structure including a plurality of metal lines and vias, wherein a first interconnect layer of the interconnect structure includes metal lines electrically coupled to both the gate structure and the source / drain features; A second workpiece is provided, the second workpiece comprising: a first dielectric layer, a metal feature extending through the first dielectric layer, and a carrier substrate, disposed on the first dielectric layer; attaching the second workpiece to the first workpiece such that the metal feature is electrically coupled to the gate structure through the diode and the plurality of metal lines and vias; performing a first plasma etching process on the back side of the first workpiece to form a first trench, wherein the source / drain feature is exposed in the first trench; and A first backside conductive feature is formed in the first trench.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: During the performing of the first plasma etching process, the second transistor has no charge.

10. A semiconductor structure comprising: a first substrate; A first transistor, comprising a fin structure protruding from the first substrate and a metal gate structure disposed on the fin structure; a diode, disposed in the first substrate and adjacent to the first transistor; a second transistor adjacent to the first transistor and including a source / drain (S / D) feature; a first backside conductive structure disposed below the source / drain feature and electrically coupled to the source / drain feature; an interconnect structure disposed on the first substrate, wherein the interconnect structure comprises a multi-layer dielectric structure and a plurality of front-side conductive features embedded in the multi-layer dielectric structure; A dielectric layer is disposed on the inner connection structure; a metal feature disposed through the dielectric layer and contacting one of the plurality of front-side conductive features; as well as A second substrate is disposed on the dielectric layer and the metal features, The plurality of front-side conductive features include a first portion connected to the metal feature and a P-well of the diode, and a second portion connected to the source / drain feature, the metal gate structure, and an N-well of the diode.

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