Semiconductor structure

Abstract

Embodiments of the present application describe a method that includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite the first sidewall. The method further includes depositing a shallow trench isolation (STI) material on the substrate. Deposition of the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method further includes performing a first etch process on the STI material, etching a first portion of the STI material at a first etch rate, and etching a second portion of the STI material at a second etch rate that is greater than the first etch rate. The method further includes performing a second etch process on the STI material, etching a first portion of the STI material at a third etch rate, and etching a second portion of the STI material at a fourth etch rate that is less than the third etch rate. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

[0001] Divisional application

[0002] This application is a divisional application entitled “Semiconductor structure and method for forming the same” filed on May 28, 2021, with patent application number 202110592473.5. Technical Field

[0003] Embodiments of the present application generally relate to the field of semiconductors, and more particularly, to semiconductor structures. Background Art

[0004] As semiconductor technology advances, the demand for higher storage capacity, faster processing systems, higher performance and lower costs continues to grow. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices. Fin field effect transistors (finFETs) have been developed to reduce device footprint and improve device performance. FinFETs are field effect transistors (FETs) formed on fins that are oriented vertically relative to the flat surface of the wafer. Summary of the invention

[0005] Some embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a fin protruding from a substrate, the fin comprising a first sidewall and a second sidewall formed opposite to the first sidewall; depositing a shallow trench isolation (STI) material on the substrate, comprising: depositing a first portion of the shallow trench isolation material in contact with the first sidewall; and depositing a second portion of the shallow trench isolation material in contact with the second sidewall; performing a first etching process on the shallow trench isolation material, etching the first portion of the shallow trench isolation material at a first etching rate, and etching the second portion of the shallow trench isolation material at a second etching rate greater than the first etching rate; and performing a second etching process on the shallow trench isolation material, etching the first portion of the shallow trench isolation material at a third etching rate, and etching the second portion of the shallow trench isolation material at a fourth etching rate less than the third etching rate.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor structure, comprising: forming a plurality of fins protruding from a substrate, the plurality of fins comprising a first outermost fin and a second outermost fin, wherein: the first outermost fin comprises a first inner sidewall and a first outer sidewall formed opposite to the first inner sidewall; and the second outermost fin comprises: a second inner sidewall opposite to the first inner sidewall; and a second outer sidewall formed opposite to the second inner sidewall; depositing a shallow trench isolation (STI) material on the substrate, comprising: depositing a first portion of the shallow trench isolation material between the first inner sidewall and the second inner sidewall; and depositing a second portion of the shallow trench isolation material in contact with the first outer sidewall and the second outer sidewall; performing a first etching process on the shallow trench isolation material, etching the first portion of the shallow trench isolation material at a first etching rate, and etching the second portion of the shallow trench isolation material at a second etching rate greater than the first etching rate; and performing a second etching process on the shallow trench isolation material, etching the first portion of the shallow trench isolation material at a third etching rate, and etching the second portion of the shallow trench isolation material at a fourth etching rate less than the third etching rate.

[0007] Some other embodiments of the present application provide a semiconductor structure, comprising: a plurality of fins, the plurality of fins protruding from a substrate and comprising a first outermost fin and a second outermost fin, wherein: the first outermost fin comprises a first sidewall and a second sidewall opposite to each other; the second outermost fin comprises a third sidewall and a fourth sidewall opposite to each other, wherein the second sidewall and the third sidewall face each other; and the top surfaces of the first outermost fin and the second outermost fin are aligned in a horizontal plane; and a shallow trench isolation (STI) material, located on the substrate, the shallow trench isolation material comprising: a first portion, the first portion contacting the first sidewall and comprising a first top surface, wherein a first height is measured from the first top surface to the horizontal plane; and a second portion, the second portion being located between the first outermost fin and the second outermost fin and comprising a second top surface, wherein a second height is measured from the second top surface to the horizontal plane, and the second height is greater than the first height. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a flow chart of a method for forming a semiconductor structure according to some embodiments.

[0010] Figure 2-Figure 6 Various views of semiconductor fins and STI materials at various stages of their fabrication process are shown in accordance with some embodiments.

[0011] Figure 7-Figure 11 is a flow chart of a method for forming a semiconductor structure according to some embodiments.

[0012] Fig.12 is a cross-sectional view of a semiconductor device according to some embodiments.

[0013] Fig.13 is an isometric view of a semiconductor device according to some embodiments.

[0014] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] As used herein, the term "nominal" refers to an expected or target value for a characteristic or parameter of a component or process operation set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. The range of values ​​is typically due to slight variations in manufacturing processes and / or tolerances.

[0018] In some embodiments, the terms "about" and "substantially" may refer to a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by a person skilled in the relevant art based on the teachings herein.

[0019] The present invention provides methods for forming finFET devices. The term "finFET" refers to a FET formed on a fin that is oriented vertically relative to the flat surface of a wafer. As used herein, the term "vertical" refers to a surface that is nominally perpendicular to a substrate. These methods can also be used to form any suitable semiconductor structure, such as a horizontal or vertical all-around gate field effect transistor (GAAFET).

[0020] Despite the implementation of various enhancement techniques, such as new device structures for enhanced electrostatic control, transmission enhancement through strained channels, improved dopant activation, and parasitic resistance reduction, the performance and scalability of silicon-based transistors have reached fundamental limits. As device sizes are scaled down to achieve higher packaging densities, shrinking silicon-based transistors has become a challenge. FinFETs have been developed to reduce device footprint and improve device performance. The fins of FinFETs can be formed on a semiconductor substrate by one or more photolithography processes including double patterning or multiple patterning processes. After the fins are formed, a shallow trench isolation (STI) material layer can be deposited on the substrate and around the fins to provide electrical isolation between adjacent fins. The source / drain region and channel region of the FET can be formed on the portion of the fin protruding from the top surface of the STI material. However, as the device size is scaled down, the height of the STI material may vary across the wafer and result in inconsistencies in the fin height. For example, due to the loading effect, the step height of the STI material between the fins can be greater than the step height of the STI material formed around the outermost fin of a group of fins.

[0021] Various embodiments of the present invention describe methods for forming a semiconductor device having a substantially consistent STI step height. STI materials surrounding a plurality of fins may be deposited on a substrate, followed by an etch back process to expose portions of the fins. A semiconductor device formed using the method disclosed herein may have a substantially consistent STI step height on a plurality of fins. For example, an internal STI step height (e.g., an STI step height between adjacent fins) may be substantially equal to an external STI step height (e.g., an STI step height of an outermost fin). A plurality of etching processes may be used to achieve a substantially consistent STI step height. For example, the etch back process may include an etching process that removes STI materials at different rates according to the location of the target STI material. For example, a thermal etching process may etch an STI material formed near the outermost fin at a higher etching rate than an STI material formed between a pair of adjacent fins. A plasma activated etching process may remove STI materials from between adjacent fins at a greater rate than removing STI materials adjacent to the outermost fin. The etched STI material may be exposed to a radical treatment process, during which the surface of the etched STI material may be exposed to hydrogen radicals. The radical treatment process can adjust the surface profile of the STI material and further etch the STI material. The combination of multiple etching and treatment processes can provide the benefit of a substantially consistent STI step height throughout multiple fins. For example, the inner STI step height can be substantially similar to the outer STI step height. In some embodiments, the STI step height can be adjusted using etching and treatment processes to achieve different step heights based on device requirements. For example, the inner STI step height can be greater than the outer step height.

[0022] Figure 1 is a flow chart of a method 100 for forming an STI material having substantially uniform step heights according to some embodiments. For purposes of illustration, reference will be made to Figure 2-Figure 6 The example manufacturing process shown is used to describe Figure 1 The operations shown are described in detail. Depending on the specific application, the operations may be performed in a different order or not at all. It should be noted that method 100 may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after method 100, and some other processes may only be briefly described here.

[0023] refer to Figure 1 According to some embodiments, in operation 110, a fin structure is formed on a substrate. Figure 2As shown, a plurality of fins 204 may be formed on the substrate 202 and protrude from the top surface of the substrate 202. In some embodiments, the substrate 202 may be a wafer and formed using a suitable material, such as an elemental semiconductor, a compound semiconductor, an alloy semiconductor, and any suitable material. In some embodiments, the substrate 202 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 202 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide; or (iv) a combination thereof. In addition, according to design requirements (e.g., a p-type substrate or an n-type substrate), the substrate 202 may be doped. In some embodiments, the substrate 202 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0024] Fin 204 runs along the Y axis. Figure 3 , but additional fins are formed between the pair of fins 204 to form a plurality of fins, and the pair of fins 204 represent the outermost fins of the plurality of fins. The additional fins are referred to herein as inner fins and are not shown for simplicity. Figure 3 As shown, the outermost fin 204 may have an inner sidewall 204A facing the inner fins and an outer sidewall 204B on the opposite side. The inner fins may have inner sidewalls opposite the inner sidewalls of the adjacent inner fins and the inner sidewall 204A of the outermost fin 204. The top surfaces of the fins 204 may be substantially coplanar (e.g., aligned on the same horizontal plane).

[0025] In some embodiments, the fin 204 may include a material similar to the substrate 202. In some embodiments, the fin 204 may be formed by photolithographic patterning and etching of the substrate 202. Based on the disclosure herein, it will be appreciated that other materials for the fin 204 are also within the scope and spirit of the present invention. The fin 204 is a current-carrying structure of the finFET. The channel region (not shown) of the finFET may be formed in a portion of the fin structure 204. In some embodiments, each of the fins 204 may include a plurality of nanowire structures (not shown) for forming a GAAFET device. The fin 204 may be formed by etching the substrate 202 using a patterned first hard mask layer 206 and a second hard mask layer 208 formed on an unetched substrate 202. In some embodiments, the first hard mask layer 206 is a thin film including silicon oxide formed using a thermal oxidation process. In some embodiments, the second hard mask layer 208 may be formed of silicon nitride using low pressure chemical vapor deposition (LPCVD) or plasma enhanced CVD (PECVD). In some embodiments, the fin 204 may include a top portion 204A having a substantially uniform width along the X-axis and a bottom portion 204B having a gradually varying width along the Z-axis.

[0026] refer to Figure 1 According to some embodiments, in operation 120, a shallow trench isolation (STI) material is deposited on the substrate and around the fin structure. Figure 3As shown, STI material 310 is deposited on substrate 202 and around fin 204. STI material 310 may include an inner portion 310A deposited on substrate 202 and between adjacent fins 204. STI material 310 may also include an outer portion 310B deposited on substrate 202 and on the outer sidewalls of the outermost fins 204. Inner portion 310A may be formed between the outermost fins and between adjacent inner fins formed between the outermost fins. STI material 310 may electrically isolate adjacent fins from adjacent active and passive components (not shown here) integrated or deposited on substrate 202. STI material 310 may be made of a dielectric material. In some embodiments, STI material 310 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, and / or other suitable insulating materials. In some embodiments, STI material 310 may be formed by depositing a flowable dielectric material, such as flowable silicon oxide, flowable silicon nitride, flowable silicon oxynitride, flowable silicon carbide, or flowable silicon oxycarbide. For example, flowable silicon oxide may be deposited using flowable CVD (FCVD). In some embodiments, STI material 310 may be deposited using other suitable CVD processes, physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable deposition process. After depositing STI material 310, a planarization process may be used to remove hard mask layers 206 and 208 so that the top surfaces of fin 204 and STI material 310 are substantially coplanar (e.g., flush with each other).

[0027] refer to Figure 1 In operation 130, shallow trench isolation (STI) material is etched back using one or more etching processes and treatment processes, according to some embodiments. Exemplary operation 130 may include: operation 132, which includes performing a first etching process; operation 134, which includes performing a second etching process; and operation 136, which includes an optional free radical treatment process 136. Operations 132 and 134 may remove STI material 310 at different etching rates depending on the location of the target STI material. For example, operation 132 may be a thermal etching process that etches an outer portion 310B of STI material 310 at a greater etching rate than an inner portion 310A of STI material 310. Conversely, operation 134 may be a plasma activated etching process that removes inner portion 310A at a greater rate than removing outer portion 310B. The etching processes and treatment processes described in operation 130 may be performed in different orders or not performed depending on the specific application.

[0028] refer to Figure 1 According to some embodiments, in operation 132, a first etching process is performed. Figure 4As shown, a first etching process 402 may be performed to etch back a portion of the STI material 310. In some embodiments, the first etching process 402 may be a thermal etching process using ammonia (NH3) and hydrogen fluoride (HF) as precursors. The first etching process 402 may be a non-plasma etching process and is performed at a high temperature. The first etching process 402 may etch the STI material 310 at different rates depending on the location of the target STI material. For example, the etching rate E1 of the first etching process 402 in the outer portion 310B of the STI material 310 is greater than the etching rate E2 of the inner portion 310A of the STI material 310. The difference in etching rate may be attributed to a pattern loading effect, which is a phenomenon caused by differences in radiation energy absorption in different regions of a semiconductor device or die due to different patterning (e.g., pattern density, aspect ratio of a component, composition of a component / reflectivity of a component, etc.). In some embodiments, a ratio N1 of the etching rate E1 to the etching rate E2 may be about 1 to about 2, or any suitable ratio. For example, the ratio N1 may be greater than or equal to about 1 and less than about 2. A difference in etching rate greater than the above range of N1 can result in etching inconsistency, which is a difficult problem to solve. The value of ratio N1 can depend on the spacing between adjacent fins of the plurality of fins. Reducing the spacing between the fins can result in a greater difference in etching rate between etching rates E1 and E2. The precursor flow rate and etching temperature can be adjusted so that ratio N1 is within the above range.

[0029] The first etching process 402 may continue until the STI material of the nominal etching height is removed. In some embodiments, the height of the STI material removed from the outer portion 310B of the STI material may be represented as H1, which is the height measured from the top surface of the fin 204 and the top flat surface of the etched outer portion 310B. Similarly, the height of the STI material removed from the inner portion 310A of the STI material may be represented as H2, which is the height measured from the top surface of the fin 204 and the top flat surface of the etched inner portion 310A. In some embodiments, the total height of the STI material to be removed may be represented as H, which is the height measured from the top surface of the fin 204 and the target top surface of the remaining STI material. In some embodiments, the ratio N2 of the height H1 to the height H2 may be equal to the ratio N1. In some embodiments, the first etching process 402 may remove a majority of the entire STI to be removed. In some embodiments, the ratio N3 of the height H1 to the total height H may be between about 0.65 and about 0.90. Ratios N3 outside the above range may result in limited device performance gain or reduced yield.

[0030] In some embodiments, the gas source can distribute the precursor for the first etching process 402 at a predetermined flow rate. For example, the gas source can distribute the ammonia precursor to the etching chamber at about 5 standard cubic centimeters per minute (sccm) to about 110sccm, about 10sccm to about 100sccm, or any suitable flow rate. The gas source can also distribute the hydrogen fluoride precursor at about 80sccm to about 1200sccm, about 90sccm to about 1100sccm, about 100sccm to about 1000sccm, or any suitable flow rate. Flow rate values ​​beyond the above range will result in limited device performance gain or reduced yield. In some embodiments, the etching chamber can be a chamber configured to perform a Siconi etching process (e.g., a plasma-assisted dry etching process). In some embodiments, silicon oxide can be used to form the STI material 310. The chemical reaction during the first etching process 402 can include generating ammonium fluoride (NH4F) molecules using the distributed precursor. When exposed to ammonium fluoride molecules, the silicon oxide material of the STI material 310 can react to form ammonium hexafluorosilicate ((NH4)2SiF6), which in turn reacts with water and forms silicon tetrafluoride byproduct (SiF4). Some chain chemical reactions of the first etch process 402 can be represented using the following chemical representations: NH3+HF→NH4F and SiO2+NH4F→(NH4)2SiF6+H2O→SiF4(g)+NH3(g)+HF(g).

[0031] In some embodiments, the first etching process 402 may be performed at a temperature between about 25° C. and about 50° C. For example, the etching chamber used to perform the first etching process 402 may be maintained at about 25° C. to about 30° C., about 30° C. to about 35° C., about 35° C. to about 40° C., about 40° C. to about 45° C., about 45° C. to about 50° C., or any suitable temperature. Temperatures below or above the above ranges may result in low chemical reactivity of the precursors, which in turn may result in low etching rates or ineffective etching.

[0032] refer to Figure 1 According to some embodiments, in operation 134, a second etching process is applied to further remove the STI material. Figure 5As shown, a second etching process 502 may be performed to further etch back the STI material 310. In some embodiments, the second etching process 502 may be a plasma activated etching process using ammonia (NH3) and nitrogen trifluoride (NF3) as precursors. The second etching process 502 may be a plasma activated etching process using a plasma etching device. The plasma may be generated by a plasma generator in a plasma generation process, such as a transformer coupled plasma generator, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, etc. The plasma generator generates radio frequency power, which generates plasma from ammonia and nitrogen trifluoride, for example, by applying a voltage higher than the excitation voltage to an electrode in a chamber containing the precursor. According to some embodiments, the second etching process 502 may remove the outer portion of the STI material 310 at a lower rate than the inner portion of the STI material compared to the first etching process 402. For example, the etching rate E3 of the second etching process 502 in the outer portion 310B of the STI material 310 may be lower than the etching rate E4 of the inner portion 310A. The etching rate difference can be attributed to the generation of fluorinated ammonium radicals, which can help etch in tight spaces, such as STI materials located between adjacent fins. In some embodiments, during the first etching process 402 and the second etching process 502, trace amounts of oxygen remaining in the processing chamber can form a native oxide layer on the fin 204. The plasma species (e.g., NH3 and NF3) used in the second etching process 502 can etch the native oxide at a slower etching rate than the plasma species (e.g., NH3 and HF) used in the first etching process 402, thereby providing more free radicals in the tight spaces between the fins for increasing the etching rate of the STI material 310. In some embodiments, the ratio N4 of the etching rate E3 to the etching rate E4 can be less than or equal to 1 and greater than about 0.5. Etching rate differences greater than the above-mentioned N4 range can cause difficulties in providing substantially consistent etching on multiple fins. The precursor flow rate and plasma intensity can be adjusted so that the ratio N4 is within the above-mentioned range. The second etching process 502 can continue until the STI material of the nominal etching height is removed. In some embodiments, the height of the STI material removed from the outer portion 310B of the STI material during the second etching process 502 can be represented as H3. Similarly, the height of the STI material removed from the inner portion 310A of the STI material during the second etching process 502 can be represented as H4. In some embodiments, a ratio N5 of the height H3 to the height H4 can be equal to the ratio N4. In some embodiments, the second etching process 502 can remove a smaller amount of STI material than the first etching process 402. In some embodiments, a ratio N6 of the height H3 to the total height H can be between about 0.10 and about 0.35.In some embodiments, the second etching process 502 can be used to counteract the difference in surface unevenness (e.g., heights H1 and H2) caused by the first etching process 402, so that the top surfaces of the inner portion 310A and the outer portion 310B are substantially coplanar (e.g., flush) after the first etching process 402 and the second etching process 502. The second etching process can continue until a nominal fin height (e.g., the height of the fin 204 protruding from the STI material 310) is reached, or until the top surfaces of the inner portion 310A and the outer portion 310B are substantially coplanar. In some embodiments, the second etching process can be performed until the top surface of the inner portion 310A is lower than the top surface of the outer portion 310B.

[0033] In some embodiments, the gas source may distribute precursors for the second etching process 502 at a predetermined flow rate. For example, the gas source may distribute an ammonia precursor into the etching chamber at about 5 sccm to about 320 sccm, about 7 sccm to about 310 sccm, about 10 sccm to about 300 sccm, or any suitable flow rate. The gas source may also distribute a nitrogen trifluoride precursor at about 35 sccm to about 600 sccm, about 40 sccm to about 550 sccm, about 50 sccm to about 500 sccm, or any suitable flow rate. In some embodiments, silicon oxide may be used to form the STI material 310. The chemical reaction during the second etching process 502 may include using the distributed precursor and generating ammonium fluoride (NH4F) radicals and ammonium fluoride molecules under plasma. When exposed to the ammonium fluoride molecules and radicals, the silicon oxide material of the STI material 310 may react to generate ammonium hexafluorosilicate, which in turn reacts with water and generates silicon tetrafluoride byproducts. Some chain chemical reactions of the second etching process 502 can be represented using the following chemical representations: NH3+NF4→Plasma (RF)→NH4F+NH4F.HF and SiO2+NH4F→(NH4)2SiF6+H2O→SiF4(g)+NH3(g)+HF(g). In some embodiments, an annealing process can be used during or after the etching process. For example, an annealing process can be performed to enhance the generation of silicon tetrafluoride gas. In some embodiments, the annealing process can be performed at a temperature between about 30°C and about 80°C. Annealing processes performed at temperatures below about 30°C can result in insufficient sublimation of (NH4)2SiF6, which in turn can result in poor etching performance (e.g., residue or defect generation). Annealing processes performed at temperatures above about 80°C can result in unstable plasma species, which in turn can result in plasma degradation.

[0034] In some embodiments, the second etching process 502 can be performed in a plasma chamber. A radio frequency (RF) source can be applied to a plasma chamber to excite ions from a precursor and generate a plasma. The power of the RF source can be between about 25W and about 75W. For example, the power can be between about 25W and about 40W, between about 40W and about 50W, between about 50W and about 75W, or any suitable RF power. RF power below the above range can result in low chemical reactivity of the precursor, resulting in low etching rate or ineffective etching. RF power greater than the above range can result in difficulty in providing a consistent etching rate.

[0035] refer to Figure 1 According to some embodiments, in operation 136, a free radical treatment process is applied to the STI material. Figure 6 As shown, a free radical treatment process 602 is applied to the top surface of the STI material 310. In some embodiments, the free radical treatment process may be optional. The free radical treatment process may be a hydrogen free radical treatment process, in which the surface of the STI material 310 is exposed to hydrogen free radicals. Hydrogen free radicals easily react with group IV substances to form tetrahydride compounds. The hydrogen free radical treatment process may be performed in a chamber such as an etching chamber. In some embodiments, the free radical treatment process 602 may be performed in a processing chamber for performing the first etching process 402 and the second etching process 502. In some embodiments, the free radical treatment process 602 may be a plasma-assisted free radical treatment process. For example, a plasma-assisted free radical treatment process may use hydrogen or helium as a precursor. For example, one or more gas sources are allocated in the etching chamber. The gas source includes a precursor gas and an inert gas. The precursor gas may include hydrogen (H2), and the inert gas may include argon (Ar), helium (He), or a combination thereof. After the precursor gas is allocated to the processing chamber, a plasma is generated. The plasma may be generated in a plasma generation process by a plasma generator. When exposed to hydrogen plasma, the material at the surface of STI material 310 (e.g., silicon oxide) breaks apart and recombine with free hydrogen ions to form silane (SiH4) and water (H2O), thereby removing the dielectric material at the top surface of STI material 310. Byproducts can be removed from the processing chamber by vacuuming during formation. Figure 6 As shown, dielectric material may be uniformly removed from inner portion 310A and outer portion 310B of STI material 310. In some embodiments, the height of STI material removed from inner portion 310A and outer portion 310B of STI material during free radical treatment process 602 may be represented as H5. In some embodiments, a ratio N7 of height H5 to total height H may be less than about 0.05.

[0036] Figure 7-Figure 11is a flow chart of a method for etching back STI material to expose a plurality of fins according to some embodiments. For illustration purposes, Figure 7-Figure 11 The operation shown can be similar to Figure 2-Figure 6 For example, Figure 7-Figure 11 Each of the methods described in can be used to perform Figure 1 The operations 130 described in the above are described in detail. Depending on the specific application, the operations may be performed in a different order or not at all. It should be noted that Figure 7-Figure 11 The method described in is used to etch back STI materials, and may not produce a complete semiconductor device. Therefore, it should be understood that additional processes may be provided before, during, and after the method disclosed herein, and some other processes may only be briefly described.

[0037] refer to Figure 7 , method 700 may include operation 702 including a plasma activated etching process, operation 704 including a thermal etching process, and operation 706 including a free radical treatment process. In some embodiments, the plasma activated etching process in operation 702 may be similar to that in reference Figure 5 For example, the plasma activated etching process in operation 702 can have different etching rates for the inner portion and the outer portion of the STI material. In some embodiments, the height of the material removed from the outer portion of the STI material can be between about 10% and 35% of the total height of the STI material to be removed. In some embodiments, the thermal etching process in operation 704 can be similar to Figure 4 4. For example, the thermal etching process of operation 704 may remove STI material in the outer portion of the STI material at a greater rate than the inner portion of the STI material. In some embodiments, the material removed from the outer portion of the STI material during operation 704 may be between about 65% and about 90% of the total height of the STI material to be removed. The second operations 702 and 704 may be followed by operation 706, which includes performing a process similar to Figure 6 The free radical treatment process of the free radical treatment process 602 described in the method 700 may be performed. For example, a hydrogen free radical treatment process may be performed to further remove the STI material. After the operations described in the method 700, the top surfaces of the inner portion and the outer portion of the etched back STI material may be substantially coplanar. In some embodiments, the top surface of the inner portion may be lower than the top surface of the outer portion.

[0038] refer to Figure 8 , method 800 may include operation 802 including a thermal etching process, operation 804 including a free radical treatment process, and operation 806 including a plasma activated etching process. In some embodiments, the thermal etching process of operation 802 may be similar to Figure 48. For example, the thermal etching process of operation 802 may remove STI material in the outer portion of the STI material at a greater rate than the inner portion of the STI material. In some embodiments, the material removed from the outer portion of the STI material during operation 802 may be between about 65% and about 90% of the total height of the STI material to be removed. Operation 804 may include a process similar to Figure 6 The free radical treatment process of the free radical treatment process 602 described in the above description. For example, a hydrogen free radical treatment process can be performed to further remove the STI material. In some embodiments, the plasma activated etching process in operation 804 can be similar to the free radical treatment process 602 described in the above description. Figure 5 The second etching process 502 is described. For example, the plasma activated etching process in operation 804 can have different etching rates at the inner portion and the outer portion of the STI material. In some embodiments, the height of the material removed from the outer portion of the STI material can be between about 10% and 35% of the total height of the STI material to be removed.

[0039] refer to Fig. 9 , method 900 may include operation 902 including a plasma activated etching process, operation 904 including a free radical treatment process, and operation 906 including a thermal etching process. In some embodiments, the plasma activated etching process in operation 902 may be similar to that in reference Figure 5 The second etching process 502 described above can be described. For example, the plasma activated etching process in operation 902 can have different etching rates for the inner portion and the outer portion of the STI material. In some embodiments, the height of the material removed from the outer portion of the STI material can be between about 10% and 35% of the total height of the STI material to be removed. Operation 904 can include similar Figure 6 The free radical treatment process of the free radical treatment process 602 described in the above embodiment can be similar to the free radical treatment process 602 described in the above embodiment. For example, a hydrogen free radical treatment process can be performed to further remove the STI material. In some embodiments, the thermal etching process of operation 906 can be similar to Figure 4 4. For example, the thermal etching process of operation 906 can remove STI material in the outer portion of the STI material at a greater rate than the inner portion of the STI material. In some embodiments, the material removed from the outer portion of the STI material during operation 906 can be between about 65% and about 90% of the total height of the STI material to be removed.

[0040] refer to Fig.10, method 1000 may include operation 1002 including a thermal etching process, operation 1004 including a first free radical treatment process, operation 1006 including a plasma activated etching process, and operation 1008 including a second thermal etching process. In some embodiments, the thermal etching process of operation 1002 may be similar to Figure 4 1004 may include a first etching process 402 as described in 1004. For example, the thermal etching process of operation 1002 may remove STI material in the outer portion of the STI material at a greater rate than the inner portion of the STI material. In some embodiments, the material removed from the outer portion of the STI material during operation 1002 may be between about 65% and about 90% of the total height of the STI material to be removed. Operation 1004 may include a process similar to Figure 6 The first free radical treatment process of the free radical treatment process 602 described in FIG. For example, a hydrogen free radical treatment process may be performed to further remove the STI material. In some embodiments, the plasma activated etching process in operation 1006 may be similar to that in reference to FIG. Figure 5 The second etch process 502 described above can be described. For example, the plasma activated etch process in operation 1006 can have different etch rates for the inner portion and the outer portion of the STI material. In some embodiments, the height of the material removed from the outer portion of the STI material can be between about 10% and 35% of the total height of the STI material to be removed. In some embodiments, the second free radical treatment process in operation 1008 can be similar to the first free radical treatment in operation 1004. In some embodiments, each of the first free radical treatment process and the second free radical treatment process in operations 1004 and 1008 can etch back about 1% to about 5% of the total STI material to be removed.

[0041] refer to Fig.11 , method 1100 may include operation 1102 including a plasma activated etching process, operation 1104 including a first free radical treatment process, operation 1106 including a thermal etching process, and operation 1108 including a second free radical treatment process. In some embodiments, the plasma activated etching process in operation 1102 may be similar to that in reference Figure 5 The second etching process 502 described above may be described. For example, the plasma activated etching process in operation 1102 may have different etching rates for the inner portion and the outer portion of the STI material. In some embodiments, the height of the material removed from the outer portion of the STI material may be between about 10% and 35% of the total height of the STI material to be removed. Operation 1104 may include similar Figure 6 The first free radical treatment process of the free radical treatment process 602 described in FIG. For example, a hydrogen free radical treatment process may be performed to further remove the STI material. In some embodiments, the thermal etching process of operation 1106 may be similar to Figure 4 1004. For example, the thermal etching process of operation 1106 may remove STI material in the outer portion of the STI material at a greater rate than the inner portion of the STI material. In some embodiments, the material removed from the outer portion of the STI material during operation 1002 may be between about 65% and about 90% of the total height of the STI material to be removed. In some embodiments, the second free radical treatment process in operation 1108 may be similar to the first free radical treatment in operation 1104. In some embodiments, each of the first free radical treatment process and the second free radical treatment process in operations 1104 and 1108 may etch back about 1% to about 5% of the total STI material to be removed.

[0042] The thermal etching process and the plasma activated etching process can provide the etched back STI material with a substantially coplanar top surface. In some embodiments, the etching process can also cause the top surface of the inner portion of the etched back STI material to be lower than the top surface of the outer portion of the etched back STI material. Fig.12 As shown, the top surface of the inner portion 310A can be lower than the top surface of the outer portion 310B. For example, the height H6 of the STI material removed from between the fins 204 can be greater than the height H of the STI material removed from outside the fins 204. In some embodiments, the ratio of H6 to H can be greater than or equal to about 1 and less than about 1.2. In some embodiments, the difference between the heights H6 and H can be less than about 5 nm. For example, the difference can be between about 3 nm and about 5 nm. Increasing the difference between the heights H6 and H can provide more effective fin area and a smaller gate-channel capacitance (C) between the fin-fin spacing. gc ).

[0043] refer to Figure 1 According to some embodiments, in operation 140, a structure of a semiconductor device may be formed on the STI material and on the fin structure. Fig.13 As shown, after the STI material has been etched back, additional structures may be formed on the protruding fins.

[0044] Fig.13 1 is an isometric view of a semiconductor structure 1300 according to some embodiments of the present invention. The semiconductor structure 1300 includes a finFET formed using fin and STI materials using reference Figure 1-Figure 12For example, the semiconductor structure 1300 includes a substrate 202, a plurality of fins 204, an STI material 310, and a gate structure 1380. The gate structure 1380 is disposed over the sidewalls and top surface of each of the fins 204. The gate structure 1380 includes a gate dielectric layer 1302 and a gate electrode 1307. In some embodiments, one or more additional layers or structures may be included in the gate structure 1380.

[0045] Fig.13 A hard mask 1320 is shown disposed on a top surface of the gate electrode 1307. The hard mask 1320 is used to pattern the gate structure 1380, such as by etching. In some embodiments, the hard mask 1320 includes a dielectric material, such as silicon nitride. Fig.13 The isometric view of is obtained after a patterning process (eg, etching) of the gate dielectric layer and the gate electrode layer to form the gate structure 1380. An integrated circuit may include multiple of this and similar gate structures.

[0046] Each of the plurality of fins 204 includes a pair of source / drain (S / D) terminals S / D 1308. S / D 1308 is formed in, on, and / or around the fin 204. The channel region of the fin 204 is located below the gate structure 1380. S / D 1308 can be formed using a doped semiconductor material, such as doped crystalline silicon. In some embodiments, S / D 1308 can be formed using silicon germanium.

[0047] The STI material 310 may partially fill the recess and may include a dielectric material such as silicon oxide, spin-on glass, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric material, other suitable insulating materials, and / or combinations thereof. The STI material 310 may include a multi-layer structure, such as, for example, a structure having one or more liner layers. The STI material 310 may also be formed by depositing an enhanced gap fill layer using a multi-step deposition and treatment process to eliminate voids and seams in the gap fill material. Figure 1-Figure 12 The STI material 310 is etched back using the method described in .

[0048] According to some embodiments, the gate structure 1380 may include a gate dielectric layer 1302, a gate electrode 1307, and / or one or more additional layers. In some embodiments, the gate structure 1380 uses polysilicon as the gate electrode 1307. Although the gate structure 1380 is described as using polysilicon or amorphous silicon as the gate electrode 1307, the gate structure 1380 may be a sacrificial gate structure, such as a gate structure formed in a replacement gate process of a metal gate structure. The metal gate structure may include a barrier layer, a gate dielectric layer, a work function layer, a fill metal layer, and / or other suitable materials for the metal gate structure. In some embodiments, the metal gate structure may include a capping layer, an etch stop layer, and / or other suitable materials.

[0049] P-type and n-type work function metals may be included in the metal gate structure. The work function is associated with the material composition of the work function layer. Therefore, the material of the work function layer may be selected to adjust its work function so as to achieve a desired threshold voltage V by the device formed in the corresponding region. th .

[0050] A fill metal layer may be deposited over the work function metal layer. The fill metal layer fills the remaining portion of the trench or opening formed by removing the sacrificial gate structure. The fill metal layer may include Al, W, copper (Cu), and / or other suitable materials. The fill metal may be formed by ALD, CVD, physical vapor deposition (PVD), plating, other suitable processes, and / or combinations thereof.

[0051] The semiconductor structure 1300 includes a fin 204 and a gate structure 1380. The semiconductor structure 1300 may include a plurality of gate structures 108 formed above the fin 204. The semiconductor structure 1300 may include additional processing to form various components, such as a lightly doped drain (LDD) region and a doped S / D structure. The term "LDD region" is used to describe a lightly doped region disposed between a channel region of a transistor and at least one of the S / D regions of the transistor. The LDD region may be formed in the fin 204 by doping. Ion implantation may be used, for example, for doping processes. Other processes may be used to dope the LDD region.

[0052] Various embodiments of the present invention describe methods for forming a semiconductor device having a substantially consistent STI step height. STI material surrounding a plurality of fins may be deposited on a substrate, followed by an etch back process to expose portions of the fins. A semiconductor device formed using the method disclosed herein may have a substantially consistent STI step height on a plurality of fins. In some embodiments, the internal STI step height may be substantially equal to or less than the external STI step height. A plurality of etching processes may be used to achieve a substantially consistent STI step height. For example, the etch back process may include an etching process that removes the STI material at different rates depending on the location of the target STI material. The etched STI material may be exposed to a radical treatment process that may adjust the surface profile of the STI material and further etch the STI material.

[0053] In some embodiments, a method includes forming a fin protruding from a substrate, the fin including a first sidewall and a second sidewall formed opposite to the first sidewall. The method also includes depositing a shallow trench isolation (STI) material on the substrate. Depositing the STI material includes depositing a first portion of the STI material in contact with the first sidewall and depositing a second portion of the STI material in contact with the second sidewall. The method also includes performing a first etching process on the STI material, etching the first portion of the STI material at a first etching rate, and etching the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material, etching the first portion of the STI material at a third etching rate, and etching the second portion of the STI material at a fourth etching rate less than the third etching rate.

[0054] In some embodiments, the first etching process includes dispensing ammonia and hydrogen fluoride precursors into an etching chamber. In some embodiments, the first etching process also includes maintaining the temperature of the etching chamber between about 25° C. and about 50° C. In some embodiments, the second etching process includes dispensing ammonia and nitrogen trifluoride precursors into the etching chamber. In some embodiments, the second etching process also includes generating a plasma on the ammonia and nitrogen trifluoride precursors. In some embodiments, the method also includes forming another fin protruding from the substrate and adjacent to the fin, wherein the other fin includes: a third sidewall opposite to the second sidewall, wherein the first portion of the STI material is formed between the second sidewall and the third sidewall; and a fourth sidewall formed opposite to the third sidewall. In some embodiments, the ratio of the first etching rate to the second etching rate is greater than or equal to about 1 and less than about 2. In some embodiments, the ratio of the third etching rate to the fourth etching rate is less than or equal to 1 and greater than about 0.5. In some embodiments, the method also includes performing a free radical treatment process on the shallow trench isolation material after the first etching process and the second etching process. In some embodiments, the free radical treatment process includes dispensing hydrogen and an inert gas into the etching chamber.

[0055] In some embodiments, a method includes forming a plurality of fins protruding from a substrate, the plurality of fins including a first outermost fin and a second outermost fin, wherein: the first outermost fin includes a first inner sidewall and a first outer sidewall formed opposite to the first inner sidewall; the second outermost fin includes a second inner sidewall opposite to the first inner sidewall and a second outer sidewall formed opposite to the second inner sidewall. The method also includes depositing a shallow trench isolation (STI) material on the substrate, including depositing a first portion of the STI material between the first inner sidewall and the second inner sidewall, and depositing a second portion of the STI material in contact with the first outer sidewall and the second outer sidewall. The method also includes performing a first etching process on the STI material, etching the first portion of the STI material at a first etching rate, and etching the second portion of the STI material at a second etching rate greater than the first etching rate. The method also includes performing a second etching process on the STI material, etching the first portion of the STI material at a third etching rate, and etching the second portion of the STI material at a fourth etching rate less than the third etching rate.

[0056] In some embodiments, the first etching process includes dispensing ammonia and hydrogen fluoride precursors into an etching chamber. In some embodiments, the first etching process also includes maintaining a temperature of the etching chamber between about 25° C. and about 50° C. In some embodiments, the second etching process includes dispensing ammonia and nitrogen trifluoride precursors into the etching chamber. In some embodiments, the second etching process also includes generating a plasma on the ammonia and nitrogen trifluoride precursors.

[0057] In some embodiments, a semiconductor structure includes a plurality of fins protruding from a substrate, and includes a first outermost fin and a second outermost fin, wherein: the first outermost fin has a first sidewall and a second sidewall opposite to each other; the second outermost fin has a third sidewall and a fourth sidewall opposite to each other, wherein the second sidewall and the third sidewall face each other; and the top surfaces of the first outermost fin and the second outermost fin are aligned on a horizontal plane. The semiconductor structure also includes a shallow trench isolation (STI) material on the substrate, the STI material including a first portion in contact with the first sidewall and having a first top surface, wherein the first height is measured from the first top surface to the horizontal plane. The STI material also includes a second portion, the second portion is located between the first outermost fin and the second outermost fin and has a second top surface, wherein the second height is measured from the second top surface to the horizontal plane, and the second height is greater than the first height.

[0058] In some embodiments, the second portion contacts the second sidewall and the third sidewall. In some embodiments, the semiconductor structure further comprises one or more internal fins that protrude from the substrate and are located between the first outermost fin and the second outermost fin. In some embodiments, the ratio of the second height to the first height is greater than or equal to about 1 and less than about 1.2. In some embodiments, the semiconductor structure further comprises source / drain terminals and a gate structure formed on the plurality of fins.

[0059] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor structure comprising: a plurality of fins protruding from a substrate and comprising a first outermost fin and a second outermost fin, and one or more inner fins located between the first outermost fin and the second outermost fin, wherein: The first outermost fin includes a first side wall and a second side wall opposite to each other; The second outermost fin includes a third sidewall and a fourth sidewall opposite to each other, wherein the second sidewall and the third sidewall face each other; and Top surfaces of the first outermost fin and the second outermost fin are aligned in a horizontal plane; and A shallow trench isolation (STI) material is located on the substrate, and the shallow trench isolation material includes: a first portion contacting the first sidewall and comprising a first top surface, wherein a first height is measured from the first top surface to the horizontal plane; and A second portion is located between the first outermost fin and one of the one or more inner fins and includes a second top surface, wherein a second height is measured from the second top surface to the horizontal plane and is greater than the first height.

2. The semiconductor structure according to claim 1, wherein: The second portion contacts the second side wall and the third side wall.

3. The semiconductor structure according to claim 1, wherein: A ratio of the second height to the first height is greater than 1 and less than 1.

2. 4 . The semiconductor structure of claim 1 , further comprising source / drain terminals and a gate structure formed on the plurality of fins.

5. The semiconductor structure according to claim 1, wherein: The difference between the second height and the first height ranges from 3 nm to 5 nm.

6. The semiconductor structure according to claim 1, wherein: The plurality of fins protrude from the first top surface and the second top surface of the shallow trench isolation material.

7. A semiconductor device comprising: A first fin and a second fin protruding from the substrate, wherein top surfaces of the first fin and the second fin are aligned in a horizontal plane; A shallow trench isolation (STI) material, located on the substrate, includes: an inner portion between the first fin and the second fin and comprising a first planar top surface, wherein a first height is measured between the first planar top surface and the horizontal plane; and an outer portion, outside the first fin and the second fin, and comprising a second flat top surface, wherein a second height is measured between the second flat top surface and the horizontal plane, and the first height is greater than the second height; A gate structure is on the shallow trench isolation material and the first fin and the second fin.

8. The semiconductor device according to claim 7, wherein: The gate structure includes a gate dielectric layer on the first planar top surface, the second planar top surface, and the first fin and the second fin.

9. A semiconductor device comprising: A first fin and a second fin are located on a substrate and include a channel region and a source / drain region, wherein top surfaces of the first fin and the second fin are coplanar; A shallow trench isolation (STI) material is located on the substrate and includes a first portion between the first fin and the second fin, and a second portion outside the first fin and the second fin, wherein: The first portion includes a first top surface a first distance from the top surfaces of the first fin and the second fin; the second portion comprising a second top surface a second distance from the top surfaces of the first fin and the second fin; The channel region and the source / drain regions protrude from the first top surface and the second top surface; and The first distance is greater than the second distance; and A common gate structure is on the channel region and the first top surface and the second top surface.

10. The semiconductor device according to claim 9, wherein The first fin and the second fin further include a lightly doped region between the channel region and the source / drain region.

Images