Array substrate and preparation method thereof, display panel and display device

Abstract

The invention relates to an array substrate and a preparation method thereof, a display panel and a display device.The array substrate comprises a substrate and an array layer, the array layer comprises a composite transistor, and the composite transistor comprises a first function part, a second function part and a control end; the first function part is arranged on the substrate, and the second function part is arranged on the side, away from the substrate, of the first function part; wherein the first function part comprises a first electrode part, a first active layer and a first insulating layer located between the first active layer and the control end, and the second function part comprises a second electrode part, a second active layer and a second insulating layer located between the second active layer and the control end. The first electrode portion is connected with the first active layer and the second electrode portion is connected with the second active layer, and one of the first insulating layer and the second insulating layer includes a storage layer configured to store a charge. According to the scheme, the layout area occupied by the transistor with the storage function can be reduced, the display pixel density is improved, and the influence on the display performance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] With the continuous development of display technology, in order to achieve static display, transistor devices with storage functions have received widespread attention in the industry.

[0003] In the prior art, in order to make transistor devices have storage functions, memories are usually embedded in pixels to manufacture transistor devices with storage functions. Adding transistors with storage functions in pixels increases the area occupied by the layout, reducing the pixel density of the display. It is crucial to place transistors with storage functions in the circuit without affecting other performance of the flat panel display. Summary of the invention

[0004] The embodiments of the present invention provide an array substrate and a method for manufacturing the same, a display panel and a display device, which can reduce the area occupied by transistors with storage functions, improve the pixel density of the display, and reduce the impact on the display performance.

[0005] In the first aspect, an array substrate is proposed according to an embodiment of the present invention, comprising a substrate and an array layer, wherein the array layer is arranged on the substrate, the array layer comprises a compound transistor, the compound transistor comprises a first functional part, a second functional part and a control end, the first functional part is arranged on the substrate and the second functional part is arranged on a side of the first functional part away from the substrate, and the control end is at least arranged between the first functional part and the second functional part; wherein the first functional part comprises a first electrode part, a first active layer and a first insulating layer located between the first active layer and the control end, the second functional part comprises a second electrode part, a second active layer and a second insulating layer located between the second active layer and the control end, the first electrode part is connected to the first active layer and the second electrode part is connected to the second active layer, and one of the first insulating layer and the second insulating layer comprises a storage layer, and the storage layer is configured to store charges.

[0006] According to one aspect of an embodiment of the present invention, the composite transistor includes a control terminal, the control terminal is arranged between the first insulating layer and the second insulating layer, and the first functional part and the second functional part share the control terminal.

[0007] According to one aspect of an embodiment of the present invention, a first active layer is disposed on a substrate, a first insulating layer is disposed on a side of the first active layer facing away from the substrate, a control end is disposed between the first insulating layer and the second insulating layer and the second insulating layer covers the control end and the first insulating layer, and a second active layer is disposed on a side of the second insulating layer facing away from the control end.

[0008] According to one aspect of the embodiments of the present invention, the first active layer is disposed on the substrate, the first insulating layer is disposed on a side of the first active layer away from the substrate, the first insulating layer includes a barrier layer and a storage layer, and the barrier layer and the storage layer are stacked;

[0009] Preferably, the barrier layer is disposed at least on one side of the storage layer close to the control end;

[0010] Preferably, the dielectric constant of the storage layer is greater than the dielectric constant of the barrier layer;

[0011] Preferably, the storage layer comprises a metal layer or a SiN x layer, and the barrier layer includes a SiO layer.

[0012] According to one aspect of the embodiments of the present invention, the barrier layer includes a first barrier layer and a second barrier layer, and the first barrier layer and the second barrier layer are stacked on both sides of the storage layer in the thickness direction of the storage layer.

[0013] According to one aspect of the embodiment of the present invention, the first barrier layer is disposed on a side of the storage layer close to the first active layer, the second barrier layer is disposed on a side of the storage layer close to the control end, and the thickness of the second barrier layer is greater than the thickness of the first barrier layer;

[0014] Preferably, the thickness of the storage layer is between the thickness of the first barrier layer and the thickness of the second barrier layer.

[0015] According to one aspect of the embodiment of the present invention, the second functional portion includes a first metal and a second metal, the first metal and the second metal are arranged on a side of the second active layer away from the second insulating layer, and the second electrode portion is connected to the second active layer through the first metal and the second metal;

[0016] Preferably, the first electrode portion includes a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are respectively connected to the first active layer;

[0017] Preferably, the first metal includes a source metal, the second metal includes a drain metal, the second electrode portion includes a second source and a second drain, the second source and the source metal are connected, and the second drain and the drain metal are connected.

[0018] In a second aspect, a method for preparing an array substrate is provided according to an embodiment of the present invention, comprising:

[0019] Providing a substrate, and forming a first active layer on the substrate;

[0020] forming a first insulating layer on a side of the first active layer facing away from the substrate;

[0021] forming a control terminal on a side of the first insulating layer away from the first active layer;

[0022] forming a second insulating layer on a side of the control terminal away from the first insulating layer, the second insulating layer covering the control terminal and the first insulating layer, and one of the first insulating layer and the second insulating layer comprising a storage layer;

[0023] forming a second active layer on a side of the second insulating layer away from the control terminal;

[0024] forming a planarization layer on a side of the second active layer away from the second insulating layer, wherein the planarization layer covers the second active layer;

[0025] Etching the planarization layer to obtain a first via hole and a second via hole, wherein the first via hole is connected to the first active layer and the second via hole is connected to the second active layer;

[0026] A first electrode portion is formed in the first via hole and connected to the first active layer, and a second electrode portion is formed in the second via hole and connected to the second active layer.

[0027] In a third aspect, a display panel is provided according to an embodiment of the present invention, comprising an array substrate as described in any one of the above items.

[0028] In a fourth aspect, a display device is provided according to an embodiment of the present invention, comprising the display panel as described above.

[0029] The embodiment of the present invention provides an array substrate and a preparation method thereof, a display panel and a display device. A composite transistor is arranged in an array layer so that the composite transistor has a first functional part and a second functional part which are stacked. The first electrode part is connected to the first active layer and the second electrode part is connected to the second active layer, and the first insulating layer and the second insulating layer are spaced apart in between, so that the first functional part and the second functional part are stacked. A storage layer is arranged in one of the first insulating layer and the second insulating layer, and the storage layer is used to store charges, so that the storage function of the composite transistor is realized. Therefore, while one of the first functional part and the second functional part is used for switch driving, the other one is used to complete the charge storage function, so that the composite transistor has multiple functions at the same time, and the stacked structure of the composite transistor saves the plane occupied space, reduces the area occupied by the layout, thereby improving the pixel density of the display, reducing the influence of the storage transistor on the display performance, and improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Features, advantages, and technical effects of exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

[0031] Figure 1 is a structural schematic diagram of an array substrate according to an embodiment of the present invention;

[0032] Figure 2 is a structural schematic diagram of another array substrate according to an embodiment of the present invention;

[0033] Figure 3 is a working principle diagram of a composite transistor according to an embodiment of the present invention;

[0034] Figure 4 is a flow chart of preparing an array substrate according to an embodiment of the present invention;

[0035] Figure 5 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0036] Figure 6 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0037] Figure 7 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0038] Figure 8 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0039] Fig. 9 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0040] Fig.10 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0041] Fig.11 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0042] Fig.12 is a structural diagram of a preparation process of an array substrate according to an embodiment of the present invention;

[0043] Fig.13 It is a structural diagram of the preparation process of the array substrate according to an embodiment of the present invention.

[0044] Reference numerals:

[0045] 100-array substrate; 10-substrate; 20-array layer; 21-composite transistor;

[0046] 1-first functional part; 2-second functional part; 3-control end;

[0047] 1a-first electrode portion; 1b-first active layer; 1c-first insulating layer;

[0048] 2a-second electrode portion; 2b-second active layer; 2c-second insulating layer;

[0049] 4-storage layer; 5-barrier layer; 51-first barrier layer; 52-second barrier layer;

[0050] 11a-first source; 12a-first drain; 21a-second source; 22a-second drain;

[0051] 6-first metal; 7-second metal; 8-planarization layer; 11-first via hole; 12-second via hole.

[0052] In the drawings, the same reference numerals are used for the same components. The drawings are not drawn to scale. DETAILED DESCRIPTION

[0053] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed in order to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention. In the drawings and the following description, at least part of the known structures and technologies are not shown in order to avoid unnecessary ambiguity of the present invention; and, for clarity, the size of some structures may be exaggerated. In addition, the features, structures or characteristics described below may be combined in one or more embodiments in any suitable manner.

[0054] The directional words appearing in the following description are all directions shown in the figures, and do not limit the specific structures of the array substrate and its preparation method, display panel and display device of the present invention. In the description of the present invention, it should also be noted that, unless otherwise clearly specified and limited, the terms "installation" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0055] In order to better understand the present invention, Figures 1 to 13 An array substrate and a manufacturing method thereof, a display panel and a display device according to embodiments of the present invention are described in detail.

[0056] See also Figure 1 and Figure 2According to an embodiment of the present invention, an array substrate 100 is proposed, comprising a substrate 10 and an array layer 20, wherein the array layer 20 is arranged on the substrate 10, the array layer 20 comprises a composite transistor 21, the composite transistor 21 comprises a first functional part 1, a second functional part 2 and a control terminal 3, the first functional part 1 is arranged on the substrate 10 and the second functional part 2 is arranged on a side of the first functional part 1 away from the substrate 10; wherein the first functional part 1 comprises a first electrode part 1a, a first active layer 1b and a first insulating layer 1c located between the first active layer 1b and the control terminal 3, the second functional part 2 comprises a second electrode part 2a, a second active layer 2b and a second insulating layer 2c located between the second active layer 2b and the control terminal 3, the first electrode part 1a is connected to the first active layer 1b and the second electrode part 2a is connected to the second active layer 2b, and one of the first insulating layer 1c and the second insulating layer 2c comprises a storage layer 4, and the storage layer 4 is configured to store charges.

[0057] In this embodiment, a composite transistor 21 is arranged on the array layer 20. The composite transistor 21 has an upper and lower stacked structure of a first functional part 1 and a second functional part 2, wherein the control terminal 3 may be a gate, which mainly plays a role in switching control of the first functional part 1 and the second functional part 2. Optionally, the gate of the control terminal 3 may be made of metal molybdenum (Mo).

[0058] The first functional part 1 is located as a whole below the second functional part 2. The first functional part 1 specifically includes a first electrode part 1a, a first active layer 1b and a first insulating layer 1c. The first active layer 1b may be a semiconductor layer, for example, made of low-temperature polycrystalline silicon (LTPS), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) and the like. The first insulating layer 1c is disposed between the first active layer 1b and the control end 3 to serve as an interval insulator. The first electrode part 1a includes a first source 11a and a first drain 12a, which are respectively connected to the first active layer 1b.

[0059] The second functional part 2 specifically includes a second electrode part 2a, a second active layer 2b and a second insulating layer 2c. The second active layer 2b can be a semiconductor layer, for example, using materials such as indium gallium zinc oxide (IGZO) and indium zinc oxide (IZO). The second insulating layer 2c is arranged between the second active layer 2b and the control end 3 to play a role of spacing insulation. The second electrode part 2a includes a second source 21a and a second drain 22a, which are respectively connected to the second active layer 2b.

[0060] The first functional part 1 and the second functional part 2 have different functions in the composite transistor 21 , one of which mainly plays the role of a driving switch, and the other mainly plays the role of storing charges. The main difference lies in the different structures of the corresponding first insulating layer 1c and the second insulating layer 2c.

[0061] For example, a storage layer 4 can be set in the first insulating layer 1c. When the control terminal 3 is turned on, the storage layer 4 can capture and store the migrated charges so that they are located in the storage layer 4 and no longer migrate, thereby forming a capacitor structure in the first functional part 1. Optionally, the storage layer 4 can be made of a material with a high dielectric constant such as silicon nitride or metal.

[0062] At the same time, the second insulating layer 2c does not have a storage layer 4, and only plays a role of spacing insulation between the second active layer 2b and the control end 3. When the control end 3 is turned on, the second functional part 2 can be turned on through the second insulating layer 2c to form a control switch as a whole. Optionally, the second insulating layer 2c as a whole can be made of materials such as silicon nitride or silicon oxide.

[0063] In this way, in the composite transistor 21, when the control terminal 3 is turned on, the first functional part 1 at the bottom can form a capacitor structure to store charge, and the second functional part 2 simultaneously forms a drive switch to control the conduction of the circuit, so that the composite transistor 21 has two functions. Of course, according to actual needs, the first functional part 1 at the bottom can be set as a drive switch structure, and the second functional part 2 at the top can be set as a capacitor structure, and the position of the storage layer 4 can be adjusted in the molding process. The specific functions of the first functional part 1 and the second functional part 2 are not particularly limited in this application.

[0064] For an example, see Figure 3 , the M position in the figure represents the composite transistor 21 in this embodiment, wherein C is the corresponding first functional part 1, which has a charge storage function, D is the corresponding second functional part 2, which has a driving switch function, and E is the control terminal 3 of the composite transistor M. A and B in the circuit are respectively driving transistors of conventional structures, the first functional part C is connected to the driving transistor A through the first electrode part 1a, and the second functional part D is connected to the driving transistor B through the second electrode part 2a.

[0065] When the driving transistor A is turned off and B is turned on, the second functional part D in the composite transistor M works normally and is turned on, and a single-gate transistor is formed at this position, which plays the role of a driving switch; when the driving transistor A is turned on and B is turned off, the first functional part C in the composite transistor M works normally, and a capacitor with a charge storage function is formed at this position; when the driving transistors A and B are turned on at the same time, a storage capacitor is formed at the first functional part C, and the second functional part D works normally and is turned on, and the voltage at the second functional part D can be regulated by charging and discharging the capacitor. The composite transistor M formed by the upper and lower stacked structure of the first functional part C and the second functional part D has a charge storage function, thereby saving the space occupied by the capacitor.

[0066] The embodiment of the present invention provides an array substrate 100, wherein a composite transistor 21 is arranged in an array layer 20, so that the composite transistor 21 has a first functional portion 1 and a second functional portion 2 which are stacked, wherein the first electrode portion 1a is connected to the first active layer 1b and the second electrode portion 2a is connected to the second active layer 2b, and the first insulating layer 1c and the second insulating layer 2c are separated in between, thereby realizing the stacked arrangement of the first functional portion 1 and the second functional portion 2, wherein a storage layer 4 is arranged in one of the first insulating layer 1c and the second insulating layer 2c, and the storage layer 4 is used to store charges, thereby realizing the storage function of the composite transistor 21, so that while one of the first functional portion 1 and the second functional portion 2 is used for switch driving, the other is used to complete the charge storage function, so that the composite transistor 21 has multiple functions at the same time, and the stacked structure of the composite transistor 21 saves the plane occupied space, reduces the area occupied by the layout, thereby improving the pixel density of the display, reducing the influence of the storage transistor on the display performance, and improving the display effect.

[0067] As an optional embodiment, the first functional part 1 and the second functional part 2 share a control terminal 3, and the control terminal 3 can control the opening and closing of the first functional part 1 and the second functional part 2 at the same time.

[0068] In order to save the number of control terminals 3 and thus reduce the difficulty of the molding process, in this embodiment, the first functional part 1 and the second functional part 2 in the composite transistor 21 share the same control terminal 3, and the control terminal 3 can synchronously control the conduction of the first functional part 1 and the second functional part 2.

[0069] Optionally, the control terminal 3 can be set between the first functional part 1 and the second functional part 2 to facilitate the synchronous control of the two. The position of the control terminal 3 can also be adjusted according to actual needs. Of course, the control terminal 3 can also be set in the first functional part 1 and the second functional part 2 respectively for independent control. The present application does not limit this.

[0070] An embodiment of the present invention provides an array substrate 100, which synchronously controls the first functional part 1 and the second functional part 2 by setting a common control terminal 3 in the compound transistor 21, thereby simplifying the overall structure of the compound transistor 21 and reducing the complexity of the overall structure. At the same time, it is easy to process and reduces the process difficulty, and also improves the convenience of operation.

[0071] As an optional embodiment, the first active layer 1b is arranged on the substrate 10, the first insulating layer 1c is arranged on the side of the first active layer 1b away from the substrate 10, the control end 3 is arranged between the first insulating layer 1c and the second insulating layer 2c and the second insulating layer 2c covers the control end 3 and the first insulating layer 1c, and the second active layer 2b is arranged on the side of the second insulating layer 2c away from the control end 3.

[0072] In this embodiment, the control terminal 3 is arranged between the first functional part 1 and the second functional part 2, specifically between the first insulating layer 1c and the second insulating layer 2c. The bottom of the control terminal 3 is the first insulating layer 1c to separate the first active layer 1b and the control terminal 3, and the top of the control terminal 3 is the second insulating layer 2c to separate the second active layer 2b and the control terminal 3, so that the first functional part 1 can form a top gate structure and the second functional part 2 can form a bottom gate structure, thereby realizing the sharing of the intermediate control terminal 3.

[0073] At this time, a storage layer 4 can be set on any one of the first insulating layer 1c and the second insulating layer 2c on both sides of the control terminal 3. When the control terminal 3 is turned on, it can simultaneously drive the functional parts on both sides to work, one side forms a capacitor to store charge, and the other side forms a switch conduction circuit, thereby realizing the dual functions of the compound transistor 21.

[0074] An embodiment of the present invention provides an array substrate 100, which realizes the sharing of the intermediate control terminal 3 by the first functional part 1 and the second functional part 2 by arranging the control terminal 3 between the first insulating layer 1c and the second insulating layer 2c, thereby facilitating the synchronous conduction of the two sides. On the basis of ensuring the conduction effect, it is also convenient for process molding and reduces the process difficulty.

[0075] As an alternative embodiment, see Figure 2 The first active layer 1b is arranged on the substrate 10, the first insulating layer 1c is arranged on the side of the first active layer 1b away from the substrate 10, and the first insulating layer 1c includes a barrier layer 5 and a storage layer 4, and the barrier layer 5 and the storage layer 4 are stacked.

[0076] Optionally, after the storage layer 4 is set in the first insulating layer 1c, a blocking layer 5 can be set to match it. The blocking layer 5 and the storage layer 4 are stacked up and down. The main function of the blocking layer 5 is to block the migration of charges. When the control end 3 is turned on, the charges migrate to the storage layer 4, and the charges can be better controlled in the storage layer 4. Even if the charges migrate up and down, they will be blocked by the blocking layer 5.

[0077] Optionally, the dielectric constant of the storage layer 4 is required to be larger than that of the barrier layer 5, and a material with a high dielectric constant, such as a metal layer or SiN x layer, etc., so as to better accommodate the stored charges. The blocking layer 5 can be a SiO layer, etc., to better limit the charges.

[0078] Optionally, the blocking layer 5 is at least arranged on one side of the storage layer 4 close to the control end 3. This is mainly to take into account the problem that charges may migrate back in the storage layer 4. The blocking layer 5 can block part of the charges and prevent them from migrating to the control end 3.

[0079] An embodiment of the present invention provides an array substrate 100, which provides a blocking layer 5 and a storage layer 4 in a first insulating layer 1c. While the storage layer 4 is used to store charges, the blocking layer 5 is used to prevent the migration of stored charges, thereby forming a better barrier to the migration of charges, thereby effectively confining the charges in the storage layer 4, improving the charge storage capacity of the first functional part 1, and having a larger capacitance.

[0080] As an alternative embodiment, see Figure 2 The barrier layer 5 includes a first barrier layer 51 and a second barrier layer 52, and the first barrier layer 51 and the second barrier layer 52 are stacked on both sides of the storage layer 4 in its thickness direction.

[0081] Optionally, in this embodiment, the barrier layer 5 is set to a double-layer structure, specifically including a first barrier layer 51 and a second barrier layer 52. The first barrier layer 51 and the second barrier layer 52 can be made of the same material, such as a material with a lower dielectric constant such as silicon oxide. The middle storage layer 4 can be made of a material with a higher dielectric constant such as silicon nitride or metal. The present application does not specifically limit the specific material between the film layers.

[0082] The first blocking layer 51 and the second blocking layer 52 can respectively block the charge migration on both sides of the storage layer 4 to prevent the charges accumulated in the middle storage layer 4 from migrating to the control terminal 3 and the first active layer 1 b , thereby forming charge blocking on both sides of the storage layer 4 at the same time.

[0083] An embodiment of the present invention provides an array substrate 100, which forms simultaneous blocking on both sides of the storage layer 4 by respectively arranging a first blocking layer 51 and a second blocking layer 52 on both sides of the storage layer 4, thereby limiting the migration of charges toward the control end 3 and the first active layer 1b, more effectively accumulating charges in the middle storage layer 4, and further fully improving the charge storage capacity of the first functional part 1.

[0084] As an optional embodiment, the first barrier layer 51 is arranged on the side of the storage layer 4 close to the first active layer 1b, and the second barrier layer 52 is arranged on the side of the storage layer 4 close to the control end 3, and the thickness of the second barrier layer 52 is greater than the thickness of the first barrier layer 51.

[0085] Optionally, the first blocking layer 51 is arranged between the first active layer 1b and the storage layer 4, which can effectively block the charges in the storage layer 4 from migrating toward the first active layer 1b. At the same time, the second blocking layer 52 is arranged between the storage layer 4 and the control end 3, which can effectively prevent the charges in the storage layer 4 from migrating back, thereby better confining the charges in the middle storage layer 4.

[0086] Optionally, the thickness of the second blocking layer 52 can be made greater than that of the first blocking layer 51, so as to have better charge blocking ability. This is mainly because the charges in the storage layer 4 may migrate more in the reverse direction toward the control end 3, so it is necessary to improve the charge blocking ability of the second blocking layer 52.

[0087] Optionally, the thickness of the storage layer 4 is between the thickness of the first barrier layer 51 and the thickness of the second barrier layer 52. For example, the thickness of the first barrier layer 51 can be set to 15nm, the thickness of the middle storage layer 4 can be set to 25nm, and the second barrier layer 52 can be set to 30nm, so that the thickness of each sub-film layer in the first insulating layer 1c forms a gradient structure.

[0088] An embodiment of the present invention provides an array substrate 100, on the basis of respectively arranging a first blocking layer 51 and a second blocking layer 52 on both sides of a storage layer 4, by adjusting the thickness between each film layer, thereby forming a targeted barrier to the charges on both sides thereof, which complies with the law of charge migration, has a better charge blocking effect, and better confines the charges to the middle storage layer 4.

[0089] As an alternative embodiment, see Figure 1 and Figure 2 The second functional part 2 includes a first metal 6 and a second metal 7, and the first metal 6 and the second metal 7 are arranged on a side of the second active layer 2b away from the second insulating layer 2c, and the second electrode part 2a is connected to the second active layer 2b through the first metal 6 and the second metal 7.

[0090] In the present embodiment, the first metal 6 and the second metal 7 are deposited on the top surface of the second active layer 2b, and are electrically connected to the second source 21a and the second drain 22a in the second electrode portion 2a, respectively. Specifically, the source and the drain can be distinguished by different access voltages. Optionally, the first metal 6 and the second metal 7 can be made of metal molybdenum, metal titanium or metal aluminum, etc., which is not limited in the present application.

[0091] Compared with ion implantation into the second active layer 2b to obtain source and drain doping regions, in this embodiment, the first metal 6 and the second metal 7 are directly deposited on the second active layer 2b, and then the second electrode portion 2a is connected to the first metal 6 and the second metal 7, thereby reducing the mask process.

[0092] Optionally, the first electrode portion 1a includes a first source 11a and a first drain 12a, the first source 11a and the first drain 12a are respectively connected to the first active layer 1b, the first metal 6 includes a source metal, the second metal 7 includes a drain metal, the second electrode portion 2a includes a second source 21a and a second drain 22a, the second source 21a is connected to the source metal and the second drain 22a is connected to the drain metal, so that the composite transistor 21 forms a complete upper and lower stacked composite structure.

[0093] An embodiment of the present invention provides an array substrate 100, which forms a first metal 6 and a second metal 7 by depositing on the top surface of the second active layer 2b, so that the second electrode portion 2a can be connected to the first metal 6 and the second metal 7 respectively to form the source and drain of the second functional portion 2. The deposition process facilitates molding, reduces the mask process, and reduces the process difficulty, which is beneficial to the molding of the composite transistor 21.

[0094] See also Figure 4 According to an embodiment of the present invention, a method for preparing an array substrate 100 is provided, comprising:

[0095] S1, providing a substrate 10, and forming a first active layer 1b on the substrate 10;

[0096] S2, forming a first insulating layer 1c on a side of the first active layer 1b facing away from the substrate 10;

[0097] S3, forming a control terminal 3 on a side of the first insulating layer 1c away from the first active layer 1b;

[0098] S4, forming a second insulating layer 2c on a side of the control terminal 3 away from the first insulating layer 1c, wherein the second insulating layer 2c covers the control terminal 3 and the first insulating layer 1c;

[0099] S5, forming a second active layer 2b on a side of the second insulating layer 2c away from the control terminal 3;

[0100] S6, forming a planarization layer 8 on a side of the second active layer 2b away from the second insulating layer 2c, wherein the planarization layer 8 covers the second active layer 2b;

[0101] S7, etching the planarization layer 8 to obtain a first via hole 11 and a second via hole 12, wherein the first via hole 11 is connected to the first active layer 1b and the second via hole 12 is connected to the second active layer 2b;

[0102] S8. Form a first electrode portion 1a in the first via hole 11 to connect with the first active layer 1b, and form a second electrode portion 2a in the second via hole 12 to connect with the second active layer 2b.

[0103] In step S1, if Figure 5 and Figure 6As shown, first, the first functional part 1 is prepared, and a first active layer 1b is deposited on the substrate 10. The first active layer 1b is a semiconductor layer, which can be a polysilicon layer or an oxide layer. In the subsequent step S2, the first insulating layer 1c is deposited to form a first insulating layer. If the first insulating layer 1c has a storage function, a multilayer structure of a barrier layer 5 and a storage layer 4 is specifically deposited separately. For example, the barrier layer 5 can be silicon oxide, and the storage layer 4 can be silicon nitride.

[0104] In step S3, if Figure 7 As shown, metal is continuously deposited on the first insulating layer 1 c and etched and patterned to form a control terminal 3 . The control terminal 3 may be made of metal molybdenum and can control the switch of the first functional part 1 .

[0105] Then continue to shape the second functional part 2, such as Figures 8 to 10 As shown, in steps S4 and S5, the second insulating layer 2c and the second active layer 2b are continuously deposited on the control end 3. At this time, the second insulating layer 2c may not have a storage function and may only use a single material of silicon nitride or silicon oxide. The second active layer 2b is usually a semiconductor layer of an oxide material.

[0106] Then, it is necessary to continue to deposit a planarization layer 8 in step S6 to make the entire top surface flat. The planarization layer 8 is also an insulating layer, which covers the entire second functional portion 2. In step S7, the planarization layer 8 is etched to obtain the first via hole 11 and the second via hole 12. Fig.11 and Fig.12 shown.

[0107] The first via hole 11 and the second via hole 12 have different depths. The first via hole 11 exposes the first active layer 1b at the bottom, so the first via hole 11 is a deep hole; the second via hole 12 exposes the second active layer 2b at the top, so the second via hole 12 is a shallow hole.

[0108] Finally, in step S8, the first electrode portion 1a and the second electrode portion 2a are deposited at the first via hole 11 and the second via hole 12, respectively, so that the first electrode portion 1a is deposited in the first via hole 11 and connected to the first active layer 1b, and the second electrode portion 2a is deposited in the second via hole 12 and connected to the second active layer 2b, forming a first functional portion 1 and a second functional portion 2 stacked up and down as a whole, and obtaining a composite transistor 21 structure, as shown in FIG. Fig.13 shown.

[0109] According to an embodiment of the present invention, a display panel is provided, comprising the array substrate 100 as described in any one of the above items.

[0110] According to an embodiment of the present invention, a display device is provided, including the display panel as described above.

[0111] Optionally, the display device may be any product involving OLED display, such as lighting, car lights, mobile phones, televisions, tablets, car displays, etc. This application does not specifically limit the specific type of the display device.

[0112] The embodiment of the present invention provides an array substrate and a preparation method thereof, a display panel and a display device. A composite transistor is arranged in an array layer so that the composite transistor has a first functional part and a second functional part which are stacked. The first electrode part is connected to the first active layer and the second electrode part is connected to the second active layer, and the first insulating layer and the second insulating layer are spaced apart in between, so that the first functional part and the second functional part are stacked. A storage layer is arranged in one of the first insulating layer and the second insulating layer, and the storage layer is used to store charges, so that the storage function of the composite transistor is realized. Therefore, while one of the first functional part and the second functional part is used for switch driving, the other one is used to complete the charge storage function, so that the composite transistor has multiple functions at the same time, and the stacked structure of the composite transistor saves the plane occupied space, reduces the area occupied by the layout, thereby improving the pixel density of the display, reducing the influence of the storage transistor on the display performance, and improving the display effect.

[0113] Although the present invention has been described with reference to preferred embodiments, various modifications may be made thereto and parts thereof may be replaced by equivalents without departing from the scope of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there are no structural conflicts. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; an array layer, arranged on the substrate, the array layer comprising a composite transistor, the composite transistor comprising a first functional portion, a second functional portion and a control end, the first functional portion being arranged on the substrate and the second functional portion being arranged on a side of the first functional portion away from the substrate, and the control end being arranged at least between the first functional portion and the second functional portion; Among them, the first functional part includes a first electrode part, a first active layer and a first insulating layer located between the first active layer and the control end, the second functional part includes a second electrode part, a second active layer and a second insulating layer located between the second active layer and the control end, the first electrode part is connected to the first active layer and the second electrode part is connected to the second active layer, one of the first insulating layer and the second insulating layer includes a storage layer, and the storage layer is configured to store charges.

2. The array substrate according to claim 1, characterized in that: The composite transistor includes a control terminal, which is disposed between the first insulating layer and the second insulating layer, and the first functional unit and the second functional unit share the control terminal.

3. The array substrate according to claim 2, characterized in that: The first active layer is arranged on the substrate, the first insulating layer is arranged on the side of the first active layer away from the substrate, the control end is arranged between the first insulating layer and the second insulating layer, and the second insulating layer covers the control end and the first insulating layer, and the second active layer is arranged on the side of the second insulating layer away from the control end.

4. The array substrate according to claim 1, characterized in that: The first active layer is arranged on the substrate, the first insulating layer is arranged on a side of the first active layer away from the substrate, the first insulating layer comprises a barrier layer and the storage layer, and the barrier layer and the storage layer are stacked; Preferably, the barrier layer is at least arranged on a side of the storage layer close to the control end; Preferably, the dielectric constant of the storage layer is greater than the dielectric constant of the barrier layer; Preferably, the storage layer comprises a metal layer or a SiN x layer, wherein the barrier layer comprises a SiO layer.

5. The array substrate according to claim 4, characterized in that: The barrier layer includes a first barrier layer and a second barrier layer, and the first barrier layer and the second barrier layer are stacked and arranged on both sides of the storage layer in the thickness direction thereof.

6. The array substrate according to claim 5, characterized in that: The first barrier layer is disposed on a side of the storage layer close to the first active layer, the second barrier layer is disposed on a side of the storage layer close to the control end, and the thickness of the second barrier layer is greater than that of the first barrier layer; Preferably, the thickness of the storage layer is between the thickness of the first barrier layer and the thickness of the second barrier layer.

7. The array substrate according to claim 1, characterized in that: The second functional portion includes a first metal and a second metal, the first metal and the second metal are arranged on a side of the second active layer away from the second insulating layer, and the second electrode portion is connected to the second active layer through the first metal and the second metal; Preferably, the first electrode portion includes a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are respectively connected to the first active layer; Preferably, the first metal includes a source metal, the second metal includes a drain metal, the second electrode portion includes a second source and a second drain, the second source is connected to the source metal, and the second drain is connected to the drain metal.

8. A method for preparing an array substrate, characterized in that: include: providing a substrate, and forming a first active layer on the substrate; forming a first insulating layer on a side of the first active layer facing away from the substrate; forming a control terminal on a side of the first insulating layer away from the first active layer; forming a second insulating layer on a side of the control end away from the first insulating layer, the second insulating layer covering the control end and the first insulating layer, and one of the first insulating layer and the second insulating layer comprising a storage layer; forming a second active layer on a side of the second insulating layer away from the control end; forming a planarization layer on a side of the second active layer away from the second insulating layer, wherein the planarization layer covers the second active layer; Etching the planarization layer to obtain a first via hole and a second via hole, wherein the first via hole is connected to the first active layer and the second via hole is connected to the second active layer; A first electrode portion is formed in the first via hole and connected to the first active layer, and a second electrode portion is formed in the second via hole and connected to the second active layer.

9. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 7.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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