Semiconductor structure, manufacturing method thereof and memory system

Abstract

The embodiment of the invention provides a semiconductor structure, a manufacturing method thereof and a memory system, and the semiconductor structure comprises a plurality of transistor groups which are located in a semiconductor layer; the plurality of transistor groups are arranged in an array along a first direction and a second direction which are crossed; each transistor group comprises a first transistor and a second transistor which are arranged along a first direction; a plurality of first connection structures, each first connection structure extending along the second direction and connected with one end of a row of first transistors arranged along the second direction; a plurality of second connection structures, each second connection structure extending along a second direction and connected with one end of a row of second transistors arranged along the second direction; the projection area of the first connecting structure on the first plane and the projection area of the second connecting structure on the first plane are partially overlapped or adjacently arranged or arranged at intervals. The first plane is perpendicular to a surface of the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof, and a memory system. Background Art

[0002] Semiconductor structures, such as Dynamic Random Access Memory (DRAM), are one of the most important access components in electronic systems. Usually, a transistor and a capacitor are used to form a 1T1C structure as a storage unit. This 1T1C structure enables dynamic random access memory to have a high degree of integration and low cost, and it has an irreplaceable position in computer access devices. With the rapid development of semiconductor technology, dynamic random access memory is rapidly developing in the direction of high density and high quality. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a memory system.

[0004] Among them, an embodiment of the present disclosure provides a semiconductor structure, including:

[0005] A plurality of transistor groups are located in the semiconductor layer; the plurality of transistor groups are arranged in an array along a first direction and a second direction intersecting each other; each of the transistor groups comprises: a first transistor and a second transistor arranged along the first direction;

[0006] a plurality of first connection structures, each of which extends along the second direction and is connected to one end of a row of the first transistors arranged along the second direction;

[0007] a plurality of second connection structures, each of which extends along the second direction and is connected to one end of a row of the second transistors arranged along the second direction;

[0008] The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

[0009] In some embodiments, the first transistor includes a first semiconductor column extending along a third direction; the second transistor includes a second semiconductor column extending along the third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction;

[0010] The size of the first semiconductor column in the third direction is a first distance; the size of the second semiconductor column in the third direction is a second distance; wherein the first distance is greater than the second distance.

[0011] In some embodiments, the first semiconductor column includes a first channel portion; a first source electrode and a first drain electrode are respectively located at two ends of the first channel portion that are opposite to each other in the third direction;

[0012] The second semiconductor column comprises: a second channel portion; a second source electrode and a second drain electrode, respectively located at two ends of the second channel portion that are oppositely arranged in the third direction;

[0013] Among them, one end of the first source electrode away from the first channel portion and one end of the second source electrode away from the second channel portion are basically flush along the first direction; the first connecting structure is connected to a row of the first drain electrodes arranged along the second direction, and the second connecting structure is connected to a row of the second drain electrodes arranged along the second direction; the size of the first connecting structure in the third direction is the same as the size of the second connecting structure in the third direction.

[0014] In some embodiments, the first semiconductor column further includes: a first doped portion located between the first drain and the first channel portion; the second semiconductor column further includes: a second doped portion located between the second drain and the second channel portion;

[0015] Among them, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the sum of the sizes of the first channel portion and the first doped portion in the third direction is greater than the sum of the sizes of the second channel portion and the second doped portion in the third direction.

[0016] In some embodiments, the first channel portion and the second channel portion have the same size in the third direction, and the size of the first doped portion in the third direction is greater than the size of the second doped portion in the third direction.

[0017] In some embodiments, a projection area of ​​the first doped portion on a first plane at least partially overlaps with a projection area of ​​the second connection structure on the first plane; and the first plane is perpendicular to the surface of the semiconductor layer.

[0018] In some embodiments, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the size of the first channel portion in the third direction is larger than the size of the second channel portion in the third direction.

[0019] In some embodiments, the first transistor further includes a first gate; the first gate is located on at least one side of two opposite sides of the first channel portion in the second direction;

[0020] The second transistor further includes a second gate; the second gate is located on at least one of two opposite sides of the second channel portion in the second direction.

[0021] In some embodiments, the semiconductor structure further comprises:

[0022] A plurality of word lines extend along the first direction; each of the word lines is connected to the gate of each transistor in a row of transistor groups arranged along the first direction.

[0023] In some embodiments, the semiconductor structure further comprises:

[0024] A plurality of storage structures are located at a side of the plurality of transistor groups away from the first connection structure / the second connection structure, and each of the storage structures is connected to the remaining end of each transistor in the plurality of transistor groups.

[0025] An embodiment of the present disclosure further provides a memory system, including: a semiconductor structure as described in the above embodiment of the present disclosure.

[0026] An embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0027] obtaining a semiconductor layer;

[0028] A plurality of transistor groups arranged in an array along a first direction and a second direction intersecting each other are formed in the semiconductor layer; each of the transistor groups comprises: a first transistor and a second transistor arranged in parallel along the first direction;

[0029] forming a plurality of first connection structures extending along the second direction, each of the first connection structures being connected to one end of a row of the first transistors arranged along the second direction;

[0030] forming a plurality of second connection structures extending along the second direction, each of the second connection structures being connected to one end of a row of the second transistors arranged along the second direction;

[0031] The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

[0032] In some embodiments, the first transistor includes a first semiconductor column extending along a third direction; the first semiconductor column includes a first channel portion, and a first source and a first drain respectively located at two ends of the first channel portion oppositely disposed in the third direction;

[0033] The second transistor includes a second semiconductor column extending along the third direction; the second semiconductor column includes: a second channel portion, and a second source and a second drain respectively located at two ends of the second channel portion that are oppositely arranged in the third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction;

[0034] Among them, one end of the first source electrode away from the first channel portion and one end of the second source electrode away from the second channel portion are basically flush along the first direction; the first connecting structure is connected to a row of the first drain electrodes arranged along the second direction, and the second connecting structure is connected to a row of the second drain electrodes arranged along the second direction; the size of the first connecting structure in the third direction is the same as the size of the second connecting structure in the third direction.

[0035] In some embodiments, the first semiconductor column further includes a first doped portion located between the first drain and the first channel portion; the second semiconductor column further includes: a second doped portion located between the second drain and the second channel portion;

[0036] The method further includes: forming a first doped portion before forming the first drain; and forming a second doped portion before forming the second drain;

[0037] Among them, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the sum of the sizes of the first channel portion and the first doped portion in the third direction is greater than the sum of the sizes of the second channel portion and the second doped portion in the third direction.

[0038] In some embodiments, the first channel portion and the second channel portion have the same size in the third direction, and the size of the first doped portion in the third direction is greater than the size of the second doped portion in the third direction.

[0039] In some embodiments, a projection area of ​​the first doped portion on a first plane at least partially overlaps with a projection area of ​​the second connection structure on the first plane; and the first plane is perpendicular to the surface of the semiconductor layer.

[0040] In some embodiments, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the size of the first channel portion in the third direction is larger than the size of the second channel portion in the third direction.

[0041] In some embodiments, the method further comprises:

[0042] forming a first gate on at least one of two opposite sides of the first channel portion along the second direction; and

[0043] A second gate is formed on at least one of two opposite sides of the second channel portion along the second direction.

[0044] In some embodiments, the method further comprises:

[0045] A plurality of word lines extending along the first direction are formed; each of the word lines is connected to the gate of each transistor in a row of transistor groups arranged along the first direction.

[0046] In some embodiments, the method further comprises:

[0047] A plurality of storage structures are formed on the first end of each transistor in the transistor group; each of the storage structures is connected to an end of each transistor in the plurality of transistor groups away from the first connection structure / the second connection structure.

[0048] The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory system; wherein the semiconductor structure includes: a plurality of transistor groups located in a semiconductor layer; the plurality of transistor groups are arranged in an array along an intersecting first direction and a second direction; each of the transistor groups includes: a first transistor and a second transistor arranged along the first direction; a plurality of first connection structures, each of which extends along the second direction and is connected to one end of a row of the first transistors arranged along the second direction; a plurality of second connection structures, each of which extends along the second direction and is connected to one end of a row of the second transistors arranged along the second direction; wherein the projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer. In the embodiment of the present disclosure, by staggering the first connection structure connected to the first transistor and the second connection structure connected to the second transistor, the distance between the first connection structure and the second connection structure is increased, thereby reducing the coupling effect between the first connection structure and the second connection structure, thereby reducing the coupling capacitance between the first connection structure and the second connection structure; further, the reduction in coupling capacitance can reduce the requirements of the memory for the capacitance of the storage node; in addition, the sense margin of the sensitive amplifier in the sensing stage can be increased, so that the signal can be amplified quickly and effectively, thereby improving the performance of the semiconductor structure; and it is beneficial to further reduce the size of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of a storage unit circuit structure using a 1T1C architecture provided in an embodiment of the present disclosure;

[0050] Figure 2 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0051] Figures 3a to 3q A schematic diagram of a cross-sectional structure of a semiconductor structure during the manufacturing process provided by an embodiment of the present disclosure;

[0052] Figures 4a to 4c A schematic cross-sectional structure diagram of a first semiconductor column and a second semiconductor structure with different sizes provided in an embodiment of the present disclosure.

[0053] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0054] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0056] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0057] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0060] The semiconductor structure involved in the embodiments of the present disclosure is to be used in subsequent processes to form at least a portion of the final device structure. Here, the final device may include a memory system, and the memory system includes but is not limited to a dynamic random access memory. The following description is only based on the dynamic random access memory as an example. However, it should be noted that the description of the dynamic random access memory in the following embodiments is only used to illustrate the present disclosure and is not used to limit the scope of the present disclosure.

[0061] With the development of dynamic random access memory technology, its array architecture has evolved from 8F 2 Go to 6F 2 Then to 4F 2 In addition, based on the demand for ions and leakage current in dynamic random access memory, the architecture of the memory has evolved from planar array transistor to recessed gate array transistor, from recessed gate array transistor to buried channel array transistor, and then from buried channel array transistor to vertical channel array transistor.

[0062] It should be understood that, whether it is a planar transistor or a buried transistor, the dynamic random access memory includes a peripheral circuit and a memory cell array; wherein the peripheral circuit may include any suitable digital, analog and / or mixed signal circuit configured to facilitate the memory to implement various operations such as read operations, write operations, and erase operations. For example, the peripheral circuit may include control logic (such as a control circuit or controller), a data buffer, a decoder (a decoder may also be called a decoder), a driver, and a read-write circuit. When the control logic receives a read-write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage obtained from the driver to the corresponding bit line and word line based on the decoded address to implement data reading and writing, and perform data exchange with the outside through the data buffer.

[0063] The memory cell array may include a plurality of memory cells; each memory cell may include a transistor and a capacitor, that is, the dynamic random access memory is a structure of 1 transistor (T, Transistor) and 1 capacitor (C, Capacitor) (1T1C); its working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0064] Exemplary, reference Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a storage unit circuit structure using a 1T1C architecture provided in an embodiment of the present disclosure. Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source of transistor T is electrically connected to one of the electrode plates of capacitor C, the other electrode plate of capacitor C can be connected to a reference voltage, the reference voltage can be a ground voltage or other voltages, and the gate of transistor T is connected to the word line (WL); different voltages are applied through the word line WL to control the transistor T to be turned on or off, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is turned on.

[0065] However, with the development of semiconductor technology, the size of memory is gradually shrinking, so that the distance between the bit line BL and the adjacent bit line BL is gradually reduced. In this case, a coupling effect may occur between the bit line BL and the adjacent bit line BL, generating a coupling capacitance; at the same time, as the coupling capacitance between the bit line BL and the adjacent bit line BL becomes larger and larger, the sensing margin of the sense amplifier becomes smaller and smaller during the sensing stage of the memory, thereby causing the problem of insufficient sensing margin (or sensing margin loss), so that the sense amplifier cannot quickly and effectively amplify the signal, thereby reducing the reading performance of the memory.

[0066] In view of this, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can increase the distance between a bit line BL and an adjacent bit line BL. Figure 2 , Figure 2 A schematic diagram of a process for manufacturing a semiconductor structure provided by an embodiment of the present disclosure, such as Figure 2 As shown, the method comprises the following steps:

[0067] Step S201: obtaining a semiconductor layer;

[0068] Step S202: forming a plurality of transistor groups arranged in an array along a first direction and a second direction intersecting each other in the semiconductor layer; each of the transistor groups comprises: a first transistor and a second transistor arranged in parallel along the first direction;

[0069] Step S203: forming a plurality of first connection structures extending along the second direction, each of the first connection structures being connected to one end of a row of the first transistors arranged along the second direction;

[0070] Step S204: forming a plurality of second connection structures extending along the second direction, each of the second connection structures being connected to one end of a row of the second transistors arranged along the second direction;

[0071] The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

[0072] In some embodiments, the first transistor includes a first semiconductor column extending along a third direction; the second transistor includes a second semiconductor column extending along a third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction; each of the first connection structures is connected to one end of a row of first semiconductor columns arranged along the second direction; each of the second connection structures is connected to one end of a row of second semiconductor columns arranged along the second direction.

[0073] It should be understood that in order to achieve partial overlap, adjacent arrangement or interval arrangement of the projection area of ​​the first connection structure on the first plane and the projection area of ​​the second connection structure on the first plane, a variety of different methods can be used to achieve this. For example, in the first method, when the dimensions of the first connection structure and the second connection structure along the third direction are the same, the dimensions of the first semiconductor column and the second semiconductor column in the transistor group along the third direction can be set to be different; in the second method, when the dimensions of the first semiconductor column and the second semiconductor column along the third direction are the same, the dimensions of the first connection structure and the second connection structure along the third direction can be set to be different; in the third method, the dimensions of the first connection structure and the first transistor along the third direction can be set to be simultaneously smaller than or simultaneously larger than the dimensions of the second connection structure and the second transistor along the third direction.

[0074] Specifically, the size of the first semiconductor column in the third direction is the first distance; the size of the second semiconductor column in the third direction is the second distance, and the size of the first connection structure in the third direction is the third distance; the size of the second connection structure in the third direction is the fourth distance; in the above method one, the first distance is greater than or less than the second distance, and the third distance is equal to the fourth distance; in the above method two, the first distance is equal to the second distance, and the third distance is greater than or less than the fourth distance; in the above method two, the first distance is greater than the second distance, and the third distance is greater than the fourth distance; or, the first distance is less than the second distance, and the third distance is less than the fourth distance.

[0075] In order to clearly understand the inventive concept of the present disclosure, the following embodiments are described by taking the first distance being greater than the second distance and the third distance being equal to the fourth distance as an example; it should be understood that the present disclosure embodiments are explained by taking this method as an example and are not intended to limit the scope of the present disclosure. Figure 2 , Figures 3a to 3q , Figures 4a to 4c , the method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is described in detail. In addition, it should be understood that Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 3a to 3q A cross-sectional schematic diagram of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure, Figures 4a to 4c A schematic diagram of the cross-sectional structure of a first semiconductor column and a second semiconductor column with different sizes provided in an embodiment of the present disclosure.

[0076] Execute step S201, such as Figure 3a As shown, a semiconductor layer 301 is obtained. Here, the constituent materials of the semiconductor layer 301 include but are not limited to silicon (Si). It should be understood that the semiconductor layer can be directly provided by a manufacturer or can be made by corresponding equipment. Exemplarily, when the semiconductor layer is made by corresponding equipment, the semiconductor layer is obtained, including: providing a substrate ( Figure 3a ), a semiconductor layer 301 is formed on a substrate. The substrate may include a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate. Methods for forming the semiconductor layer 301 include, but are not limited to, physical vapor deposition (PVD, Physical Vapor Deposition) processes, chemical vapor deposition (CVD, Chemical Vapor Deposition), atomic layer deposition (ALD, Atomic Layer Deposition) and other processes.

[0077] Execute step S202, such as Figure 3b to Figure 3q As shown, a plurality of transistor groups arranged in an array along a first direction and a second direction intersecting each other are formed in the semiconductor layer 301 .

[0078] Here, directions that may be involved in the embodiments of the present disclosure are defined. It is defined that the first direction and the second direction are both parallel to the surface of the semiconductor layer, and the third direction is perpendicular to the surface of the semiconductor layer; the first direction and the second direction intersect (including perpendicular), and the first direction and the second direction are both perpendicular to the third direction; in order to clearly describe the present disclosure, here and below, the first direction is perpendicular to the second direction and the third direction as an example for explanation; illustratively, the first direction is the X-axis direction shown in the accompanying drawings; the second direction is the Y-axis direction shown in the accompanying drawings; the third direction is the Z-axis direction shown in the accompanying drawings, and the first plane is the YOZ plane shown in the accompanying drawings. It should be noted that the description of the directions in the following embodiments is only used to illustrate the present disclosure and is not intended to limit the scope of the present disclosure.

[0079] refer to Figure 3b , forming a plurality of first grooves 302 arranged along the X-axis direction and extending along the Y-axis direction. Figure 3c , forming an isolation structure 303 in the first groove 302. The constituent material of the isolation structure includes an insulating material; the method of forming the isolation structure includes but is not limited to PVD, CVD, ALD and other processes. Forming a plurality of second grooves ( Figure 3c Next, refer to Figure 3d , a gate structure 304 is formed in the second groove; in some other embodiments, a word line extending along the first direction is also formed in the second groove. The gate structure may include a gate oxide layer and a gate. In the embodiment of the present disclosure, the gate includes a first gate and a second gate, and the gate oxide layer includes a first gate oxide layer corresponding to the first gate, and a second gate oxide layer corresponding to the second gate; the structures and relative positions of the first gate, the second gate, the first gate oxide layer, the second gate oxide layer, and the word line are described in detail below, which will not be repeated here. Reference Figure 3e , flip the semiconductor layer and grind the semiconductor layer to expose the other end of the isolation structure 303, wherein the grinding process includes but is not limited to a chemical mechanical polishing process (CMP). At this time, the isolation structure 303 and the gate structure 304 divide the remaining semiconductor layer into a plurality of active pillars 305a arranged in an array.

[0080] It should be noted that Figure 3b The opening diameter width of each first groove shown in the figure decreases with the increase of the opening depth, that is, the cross-section of the first groove is larger at the top and smaller at the bottom, and this morphology is caused by the limitations of the process equipment; preferably, the opening diameter width of each first groove and second groove remains unchanged with the increase of the opening depth.

[0081] refer to Figure 3f, a portion of each active pillar is removed to form an initial active pillar 305 b and a first opening 306 .

[0082] refer to Figure 3g , the multiple initial active pillars arranged along the X-axis direction are divided into two groups, namely the first group and the second group, in an interval distribution manner. In other words, the multiple initial active pillars in the first group and the multiple initial active pillars in the second group are arranged alternately; the initial active pillars in the first group are named as first initial active pillars 305-1, and the initial active pillars in the second group are named as second initial active pillars 305-2, and the multiple first initial active pillars 305-1 and the multiple second initial active pillars 305-2 are arranged alternately. Next, a mask layer 307 is formed in the first opening 306 located above the first initial active pillar 305-1; the constituent material of the mask layer 307 includes but is not limited to photoresist (PR); the method of forming the mask layer 307 includes but is not limited to spin coating process, such as crystal coating and dynamic spraying.

[0083] refer to Figure 3h , using the first opening located above the second initial active pillar 305-2, the second initial active pillar 305-2 is etched to remove part of the second initial active pillar 305-2, forming an intermediate active pillar 305-3 (the remaining second initial active pillar) and a second opening 308; the etching process includes but is not limited to dry etching, wet etching or a combination thereof. Figure 3h As shown, a plurality of first preliminary active pillars 305-1 and a plurality of intermediate active pillars 305-3 are alternately arranged along the X-axis direction, and a size H1 of the first preliminary active pillars 305-1 in the Z-axis direction is greater than a size H2 of the intermediate active pillars 305-3 in the Z-axis direction.

[0084] refer to Figure 3i , remove the mask layer; the removal process includes but is not limited to dry etching, wet etching or a combination thereof. And doping the first initial active pillar 305-1 and the intermediate active pillar 305-3 to form a first active pillar 309 and a second active pillar 310 respectively. The doping type (such as N-type, P-type) of the first active pillar 309 and the second active pillar 310 can be selected and set according to actual conditions. The doping method includes but is not limited to ion implantation, thermal diffusion and other processes. It should be understood that the size of the first active pillar 309 in the Z-axis direction is H1, and the size of the second active pillar 310 in the Z-axis direction is H2, and H1>H2. A first active pillar 309 and a second active pillar 310 arranged adjacent to each other constitute an active pillar group.

[0085] The first active column is used to form a first channel portion of the first semiconductor column; the second active column is used to form a second channel portion of the second semiconductor column; here, reference Figure 3i, the first active pillar 309 is the first channel portion 315; the second active pillar 310 is the second channel portion 316. In other embodiments, the first channel portion and the second channel portion may be formed by other methods, which will not be described in detail here.

[0086] refer to Figure 3i The first channel portion 315 includes a first end 315a and a second end 315b, and the first end 315a and the second end 315b are two ends of the first channel portion 315 that are oppositely arranged in the Z-axis direction; the second channel portion 316 includes a third end 316a and a fourth end 316b, and the third end 316a and the fourth end 316b are two ends of the second channel portion 316 that are oppositely arranged in the Z-axis direction; the first opening 306 exposes the second end 315b, and the second opening 308 exposes the fourth end 316b.

[0087] refer to Figure 3j , a first source 311 is formed at the first end 315a, and a first drain 312 is formed at the second end 315b; and a second source 313 is formed at the third end 316a, and a second drain 314 is formed at the fourth end 316b; wherein, the methods of forming the first source 311, the first drain 312, the second source 313, and the second drain 314 may include selective epitaxial growth (SEG), ion implantation, and the like; illustratively, the first drain 312 and the second drain 314 are formed by selective epitaxial growth in the embodiment of the present disclosure. For example, a first epitaxial layer is formed at the second end 315b by selective epitaxial growth, and the first epitaxial layer is doped to form the first drain 312. And, a second epitaxial layer is formed at the fourth end 316b by selective epitaxial growth, and the second epitaxial layer is doped to form the second drain 314. The constituent materials of the first epitaxial layer and the second epitaxial layer may include but are not limited to polycrystalline silicon (Poly) and silicon germanium (SiGe). The doping types (such as N-type and P-type) of the first epitaxial layer and the second epitaxial layer may be selected and set according to actual conditions. It should be understood that the doping type of the first epitaxial layer is different from the doping type of the first channel portion; the doping type of the second epitaxial layer is different from the doping type of the second channel portion.

[0088] refer to Figure 3j The first source 311 , the first channel portion 315 , and the first drain 312 together constitute a first semiconductor column 401 , and the second source 313 , the second channel portion 316 , and the second drain 314 together constitute a second semiconductor column 402 .

[0089] It should be understood that the sizes of the first source 311 and the second source 313 in the Z-axis direction, and the sizes of the first drain 312 and the second drain 314 in the Z-axis direction can be the same or different. In the case where the sizes of the first source 311 and the second source 313 in the Z-axis direction are the same, and the sizes of the first drain 312 and the second drain 314 in the Z-axis direction are the same, the size of the first semiconductor column 401 in the Z-axis direction is greater than the size of the second semiconductor column 402 in the Z-axis direction. In other words, the size of the first semiconductor column 401 in the Z-axis direction is the first distance; the size of the second semiconductor column 402 in the Z-axis direction is the second distance, and the first distance is greater than the second distance.

[0090] In some embodiments, the method further includes: forming a first gate on at least one of two opposite sides of the first channel portion along the second direction; and forming a second gate on at least one of two opposite sides of the second channel portion along the second direction.

[0091] refer to Figure 3k , a first gate 317 is formed on both sides of the first channel portion 315 that are opposite to each other along the Y-axis direction. In other embodiments, the first gate 317 can also be arranged only on any one side of the two sides of the first channel portion 315 that are opposite to each other along the Y-axis direction; or, the first gate can also be arranged around the first channel portion 315 in a surrounding, semi-surrounding or other manner, and the specific position of the first gate 317 can be set according to the actual needs of the transistor; here, the first gate 317 is located on two sides of the first channel portion 315 that are opposite to each other along the Y-axis direction as an example for explanation.

[0092] refer to Figure 3l , a second gate 318 is formed on both sides of the second channel portion 316 that are opposite to each other along the Y-axis direction. In other embodiments, the second gate 318 can also be arranged on only one of the two sides of the second channel portion 316 that are opposite to each other along the Y-axis direction; or, the second gate 318 can also be formed around the second channel portion 316 in a surrounding, semi-surrounding or other manner, and the specific position of the second gate 318 can be set according to the actual needs of the transistor; here, the second gate 318 is located on the two sides of the second channel portion 316 that are opposite to each other along the Y-axis direction as an example for explanation.

[0093] Here, the constituent materials of the first gate 317 and the second gate 318 may include metal or polysilicon (Poly). Methods for forming the first gate 317 and the second gate 318 include, but are not limited to, PVD, CVD, ALD and other processes.

[0094] In some embodiments, the method further includes: forming a first gate oxide layer (Gate oxide layer) between the first gate and the first channel portion Figure 3k), and forming a second gate oxide layer ( Figure 3l The first gate oxide layer and the second gate oxide layer can both effectively suppress the short channel effect. The materials of the first gate oxide layer and the second gate oxide layer can both include but are not limited to silicon oxide. The methods for forming the first gate oxide layer and the second gate oxide layer include but are not limited to PVD, CVD, ALD and other processes.

[0095] refer to Figure 3k , the first semiconductor column and the first gate constitute a first transistor 501; Figure 3l The second semiconductor column and the second gate constitute a second transistor 502; a first transistor 501 and a second transistor 502 arranged adjacent to each other constitute a transistor group, and a plurality of transistor groups are arranged in an array.

[0096] Execute step S203 and step S204: form a plurality of first connection structures and a plurality of second connection structures extending along the second direction, wherein the plurality of first connection structures and the plurality of second connection structures are alternately arranged along the first direction; wherein each first connection structure is connected to one end of a row of first transistors arranged along the second direction; and each second connection structure is connected to one end of a row of second transistors arranged along the second direction.

[0097] refer to Figure 3m , Figure 3n , a first connection structure 319 extending along the Y-axis direction is formed on a side of the first drain 312 away from the first channel portion 315; each first connection structure 319 is connected to the first drain 312 of a row of first transistors arranged along the Y-axis direction; Figure 3m , Figure 3o , a second connection structure 320 extending along the Y-axis direction is formed on the side of the second drain 314 away from the second channel portion 316, and each second connection structure 320 is connected to a second drain 314 of a row of second transistors arranged along the Y-axis direction. A plurality of first connection structures 319 and a plurality of second connection structures 320 are alternately arranged along the X-axis direction. The constituent materials of the first connection structure 319 and the second connection structure 320 include but are not limited to metals, such as tungsten; metal silicide; in some specific embodiments, the first connection structure and the second connection structure are both used to form a bit line. Methods for forming the first connection structure and the second connection structure include but are not limited to PVD, CVD, ALD and other processes.

[0098] Here, reference Figure 3m, the end of the first source electrode 311 away from the first channel portion 315 is substantially flush with the end of the second source electrode 313 away from the second channel portion 316 along the X-axis direction. Here, substantially flush includes that the ends of the first source electrode 311 and the second source electrode 313 away from the corresponding channel portion are completely flush, and the ends of the first source electrode and the second source electrode 313 away from the corresponding channel portion are not flush within the process error range.

[0099] It should be noted that the reference Figure 3m , the size of the first connection structure 319 in the Z-axis direction (the third distance) and the size of the second connection structure 320 in the Z-axis direction (the fourth distance) may be the same or different. Wherein, when the third distance is equal to the fourth distance, the first connection structure and the second connection structure are staggered in the Z-axis direction, that is, the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane partially overlap or are adjacently arranged or spaced apart; in other words, since the size of the first semiconductor column in the Z-axis direction (the first distance) is greater than the size of the second semiconductor column in the Z-axis direction (the second distance), the distance between the first connection structure and the second connection structure increases, thereby reducing the coupling effect and coupling capacitance between the first connection structure and the second connection structure. Furthermore, since the distance between the first connection structure and the second connection structure increases, the sensing margin of the sensitive amplifier increases, thereby enabling the sensitive amplifier to quickly and effectively amplify the signal, thereby improving the performance of the semiconductor structure (such as the reading performance of the memory).

[0100] It should be understood that, when the first distance is greater than the second distance, and the third distance is equal to the fourth distance, the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane are partially overlapped, adjacently arranged, or spaced apart. In other words, the specific relative position between the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane is determined by the difference between the first distance and the second distance (i.e., the height difference between the first semiconductor column and the second semiconductor column); wherein, when the height difference between the first semiconductor column and the second semiconductor column is less than the size of the first connection structure in the Z-axis direction, the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane are partially overlapped. When the height difference between the first semiconductor column and the second semiconductor column is equal to the size of the first connection structure in the Z-axis direction, the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane are adjacently arranged. When the height difference between the first semiconductor column and the second semiconductor column is greater than the dimension of the first connection structure in the Z-axis direction, the projection area of ​​the first connection structure on the YOZ plane is spaced from the projection area of ​​the second connection structure on the YOZ plane.

[0101] It should be understood that, under the condition that there is a height difference between the first semiconductor column and the second semiconductor column, the first connection structure and the second connection structure can be staggered in the Z-axis direction. In other words, the greater the height difference between the first semiconductor column and the second semiconductor column in the Z-axis direction, the greater the distance between the first connection structure and the second connection structure, that is, the smaller the coupling effect between the first connection structure and the second connection structure, the better the performance of the semiconductor structure (such as the reading performance of the memory).

[0102] In some embodiments, reference Figure 3p The method further includes: forming a protective layer 321; the protective layer 321 covers the surface of the first connection structure and the second connection structure to protect the first connection structure and the second connection structure from being damaged. The constituent material of the protective layer 321 includes but is not limited to silicon oxide. The method of forming the protective layer includes but is not limited to PVD, CVD, ALD and other processes.

[0103] In some embodiments, the method further includes: forming a plurality of word lines extending along the first direction; each of the word lines is connected to a gate of each transistor in a row of transistor groups arranged along the first direction.

[0104] Specifically, a plurality of word lines extending along the X-axis direction are formed, and each word line is connected to a first gate (not shown in the figure) of a first transistor in a row of transistors arranged along the X-axis direction, and a second gate (not shown in the figure) of a second transistor. The constituent materials of the word line include but are not limited to metals, such as tungsten. Methods for forming the word line include but are not limited to processes such as PVD, CVD, and ALD.

[0105] It should be noted that, in some specific embodiments, the semiconductor structure only includes a plurality of first gates and a plurality of second gates, and no word line is formed separately. In this case, the plurality of first gates are connected with the plurality of second gates to form a word line.

[0106] In some embodiments, the method further includes: forming multiple storage structures on the first end of each transistor in the transistor group; each of the storage structures is connected to an end of each transistor in the multiple transistor groups away from the first connection structure / the second connection structure.

[0107] refer to Figure 3q, a storage structure 322 is formed on a side of the first source 311 of the first transistor away from the first channel portion 315, and a storage structure 322 is formed on a side of the second source 313 of the second transistor away from the second channel portion 316, and the storage structure 322 may include a capacitor; the capacitor includes: a first electrode layer connected to the first source and the second source, respectively, a dielectric layer covering the first electrode layer, and a second electrode layer covering the dielectric layer. The materials of the first electrode layer and the second electrode layer may include but are not limited to titanium nitride (TiN). The material of the dielectric layer includes a high dielectric constant (High-K) material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value. In some specific examples, the material of the dielectric layer may include but is not limited to hafnium oxide (HfO2). The methods for forming the first electrode layer, the dielectric layer, and the second electrode layer include but are not limited to PVD, CVD, ALD and other processes.

[0108] It should be noted that in the embodiment of the present disclosure, the order of forming the first source, the second source, the first drain, the second drain, the first gate, the second gate, the first gate oxide layer, the second gate oxide layer, the first connection structure, the second connection structure, the word line, and the storage structure can be selected and set according to actual conditions and is not limited here.

[0109] In the above embodiments, the first semiconductor column includes a first source electrode, a first channel portion, and a first drain electrode arranged in sequence along the Z-axis direction; the second semiconductor column includes a second source electrode, a second channel portion, and a second drain electrode arranged in sequence along the Z-axis direction. In other embodiments, reference is made to Figure 4a , Figure 4b , Figure 4c , the first semiconductor column further includes a first doping portion 324, located between the first drain 312 and the first channel portion 315; the second semiconductor column further includes: a second doping portion 325, located between the second drain 314 and the second channel portion 316; based on this, the method further includes: forming the first doping portion before forming the first drain; and forming the second doping portion before forming the second drain. In some embodiments, the first doping portion and the second doping portion can be understood as lightly doped drains (LDD, Lightly Doped Drain); hot carrier effects can be prevented. The constituent materials of the first doping portion and the second doping portion include but are not limited to silicon. The method of forming the first doping portion and the second doping portion includes but is not limited to PVD, CVD, ALD, ion implantation, thermal diffusion and other processes. The doping type of the first doping portion is the same as the doping type of the first drain, the doping type of the second doping portion is the same as the doping type of the second drain, and the doping concentration of the first doping portion is less than the doping concentration of the first drain, and the doping concentration of the second doping portion is less than the doping concentration of the second drain.

[0110] That is to say, when the first source and the second source have the same size in the Z-axis direction and the first drain and the second drain have the same size in the Z-axis direction, the sum of the sizes S1 of the first channel portion and the first doped portion in the Z-axis direction and the sum of the sizes S2 of the second channel portion and the second doped portion in the Z-axis direction can be adjusted to be different, so that there is a height difference between the first semiconductor column and the second semiconductor column, thereby achieving the staggered arrangement of the first connection structure and the second connection structure in the Z-axis direction.

[0111] The sum S1 of the dimensions of the first channel portion and the first doped portion in the third direction may be greater than the sum S2 of the dimensions of the second channel portion and the second doped portion in the Z-axis direction; that is, S1>S2. The sum S1 of the dimensions of the first channel portion and the first doped portion in the Z-axis direction may also be less than the sum S2 of the dimensions of the second channel portion and the second doped portion in the third direction; that is, S1<S2.

[0112] Here, take S1>S2 as an example. Among them, the height difference between the first channel portion and the second channel portion, and the height difference between the first doping portion and the second doping portion can be adjusted so that the sizes of the first semiconductor column and the second semiconductor column in the Z-axis direction are different. For example, the size of the first channel portion in the Z-axis direction is larger than the size of the second channel portion in the Z-axis direction, and the size of the first doping portion in the Z-axis direction is larger than the size of the second doping portion in the Z-axis direction. For example, the first doping portion and the second doping portion have the same size in the Z-axis direction, and the size of the first channel portion in the Z-axis direction is larger than the size of the second channel portion in the Z-axis direction. For example, the first channel portion and the second channel portion have the same size in the Z-axis direction, and the size of the first doping portion in the Z-axis direction is larger than the size of the second doping portion in the Z-axis direction.

[0113] The following is combined with Figure 4a , 4b 4c, a detailed description is given by taking the first channel portion and the second channel portion having the same size in the Z-axis direction, the first doped portion having a size in the Z-axis direction greater than the second doped portion having a size in the Z-axis direction, so that the first semiconductor column and the second semiconductor column have different sizes in the Z-axis direction. It should be understood that the following contents on size are only used to illustrate the present disclosure and are not used to limit the scope of the present disclosure.

[0114] Specifically, when the first channel portion and the second channel portion have the same size in the Z-axis direction, the relative position of the projection area of ​​the first connection structure in the YOZ plane and the projection area of ​​the second connection structure in the YOZ plane can be different by adjusting the amount by which the first doping portion 324 is larger than the second doping portion 325, that is, the size of the height difference between the first doping portion 324 and the second doping portion 325.

[0115] Exemplary, reference Figure 4a, when the height difference between the first doped portion 324 and the second doped portion 325 is smaller than the size of the second connection structure in the Z-axis direction, the projection area of ​​the first connection structure 319 on the YOZ plane partially overlaps with the projection area of ​​the second connection structure 320 on the YOZ plane. Here, the first drain 312 and the second drain 134 have the same size in the Z-axis direction.

[0116] Exemplary, reference Figure 4b , when the height difference between the first doped portion 324 and the second doped portion 325 is equal to the size of the second connection structure in the Z-axis direction, the projection area of ​​the first connection structure 319 on the YOZ plane is adjacent to the projection area of ​​the second connection structure 320 on the YOZ plane. Here, the first drain 312 and the second drain 134 have the same size in the Z-axis direction.

[0117] Exemplary, reference Figure 4c , when the height difference between the first doped portion 324 and the second doped portion 35 is greater than the size of the second connection structure in the Z-axis direction, the projection area of ​​the first connection structure 319 on the YOZ plane is spaced from the projection area of ​​the second connection structure 320 on the YOZ plane. Here, the first drain 312 and the second drain 314 have the same size in the Z-axis direction.

[0118] It should be understood that the greater the height difference between the first doped portion 324 and the second doped portion 325, the greater the distance between the first connection structure 319 and the second connection structure 320, the smaller the coupling effect between the two, the larger the sensing margin, and the better the reading performance of the memory; it should also be noted that the doping concentrations of the first doped portion 324 and the second doped portion 325 are small and will be depleted. Therefore, the capacitance generated between the first doped portion 324 and the adjacent second connection structure 320, and between the second doped portion 325 and the adjacent first connection structure 319 is small, and its impact on the semiconductor structure or memory can be ignored.

[0119] It should be noted that in the embodiment of the present disclosure, the height difference between the first channel portion and the second channel portion, the height difference between the first drain and the second drain, and the height difference between the first source and the second source can be adjusted to make the sizes of the first semiconductor column and the second semiconductor column different in the Z-axis direction, so as to achieve that the projection area of ​​the first connection structure on the YOZ plane and the projection area of ​​the second connection structure on the YOZ plane partially overlap or are arranged adjacently or spaced apart, which will not be described one by one here. Based on the above-mentioned method for manufacturing a semiconductor structure, the present disclosure also provides a semiconductor structure, including: a plurality of transistor groups, located in a semiconductor layer; the plurality of transistor groups are arranged in an array along the intersecting first and second directions; each of the transistor groups includes: a first transistor and a second transistor arranged along the first direction;

[0120] a plurality of first connection structures, each of which extends along the second direction and is connected to one end of a row of the first transistors arranged along the second direction;

[0121] a plurality of second connection structures, each of which extends along the second direction and is connected to one end of a row of the second transistors arranged along the second direction;

[0122] The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

[0123] In some embodiments, the first transistor includes a first semiconductor column extending along a third direction; the second transistor includes a second semiconductor column extending along the third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction; the size of the first semiconductor column in the third direction is a first distance; the size of the second semiconductor column in the third direction is a second distance; wherein the first distance is greater than the second distance.

[0124] In some embodiments, the first semiconductor column includes a first channel portion; a first source and a first drain, respectively located at two ends of the first channel portion opposite to each other in the third direction; the second semiconductor column includes: a second channel portion; a second source and a second drain, respectively located at two ends of the second channel portion opposite to each other in the third direction; wherein an end of the first source away from the first channel portion and an end of the second source away from the second channel portion are substantially flush along the first direction; the first connection structure is connected to a row of the first drains arranged along the second direction, and the second connection structure is connected to a row of the second drains arranged along the second direction; a size of the first connection structure in the third direction is the same as a size of the second connection structure in the third direction.

[0125] In some embodiments, the first semiconductor column further includes: a first doped portion located between the first drain and the first channel portion; the second semiconductor column further includes: a second doped portion located between the second drain and the second channel portion; wherein, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the sum of the sizes of the first channel portion and the first doped portion in the third direction is greater than the sum of the sizes of the second channel portion and the second doped portion in the third direction.

[0126] In some embodiments, the first channel portion and the second channel portion have the same size in the third direction, and the size of the first doped portion in the third direction is greater than the size of the second doped portion in the third direction.

[0127] In some embodiments, a projection area of ​​the first doped portion on a first plane at least partially overlaps with a projection area of ​​the second connection structure on the first plane; and the first plane is perpendicular to the surface of the semiconductor layer.

[0128] In some embodiments, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the size of the first channel portion in the third direction is larger than the size of the second channel portion in the third direction.

[0129] In some embodiments, the first transistor further includes a first gate; the first gate is located on at least one side of the first channel portion on two opposite sides in the second direction; the second transistor further includes a second gate; the second gate is located on at least one side of the second channel portion on two opposite sides in the second direction.

[0130] In some embodiments, the semiconductor structure further includes: a plurality of word lines extending along the first direction; each of the word lines is connected to a gate of each transistor in a row of transistor groups arranged along the first direction.

[0131] In some embodiments, the semiconductor structure further comprises: a plurality of storage structures located on a side of the plurality of transistor groups away from the first connection structure / the second connection structure, each of the storage structures being connected to the remaining end of each transistor in the plurality of transistor groups. The present disclosure also provides a memory system comprising: a semiconductor structure as described in the above embodiments of the present disclosure.

[0132] The specific embodiments of the present disclosure are disclosed, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of transistor groups are disposed in the semiconductor layer; The plurality of transistor groups are arranged in an array along a first direction and a second direction intersecting each other; each of the transistor groups comprises: a first transistor and a second transistor arranged along the first direction; a plurality of first connection structures, each of which extends along the second direction and is connected to one end of a row of the first transistors arranged along the second direction; a plurality of second connection structures, each of the second connection structures extending along the second direction and connected to one end of a row of the second transistors arranged along the second direction; The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The first transistor includes a first semiconductor column extending along a third direction; the second transistor includes a second semiconductor column extending along the third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction; The size of the first semiconductor column in the third direction is a first distance; the size of the second semiconductor column in the third direction is a second distance; wherein the first distance is greater than the second distance.

3. The semiconductor structure according to claim 2, characterized in that: The first semiconductor column includes a first channel portion; a first source electrode and a first drain electrode, respectively located at two ends of the first channel portion that are oppositely arranged in the third direction; The second semiconductor column comprises: a second channel portion; a second source electrode and a second drain electrode, respectively located at two ends of the second channel portion that are oppositely arranged in the third direction; Among them, one end of the first source electrode away from the first channel portion and one end of the second source electrode away from the second channel portion are basically flush along the first direction; the first connecting structure is connected to a row of the first drain electrodes arranged along the second direction, and the second connecting structure is connected to a row of the second drain electrodes arranged along the second direction; the size of the first connecting structure in the third direction is the same as the size of the second connecting structure in the third direction.

4. The semiconductor structure according to claim 3, characterized in that: The first semiconductor column further includes: a first doped portion located between the first drain and the first channel portion; the second semiconductor column further includes: a second doped portion located between the second drain and the second channel portion; Among them, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the sum of the sizes of the first channel portion and the first doped portion in the third direction is greater than the sum of the sizes of the second channel portion and the second doped portion in the third direction.

5. The semiconductor structure according to claim 4, characterized in that: The first channel portion and the second channel portion have the same size in the third direction, and the first doped portion has a size greater than the second doped portion in the third direction.

6. The semiconductor structure according to claim 5, characterized in that: A projection area of ​​the first doped portion on the first plane at least partially overlaps with a projection area of ​​the second connection structure on the first plane; The first plane is perpendicular to the surface of the semiconductor layer.

7. The semiconductor structure according to claim 3, characterized in that: The first source electrode and the second source electrode have the same size in the third direction, the first drain electrode and the second drain electrode have the same size in the third direction, and the size of the first channel portion in the third direction is larger than the size of the second channel portion in the third direction.

8. The semiconductor structure according to claim 3, characterized in that: The first transistor further includes a first gate; the first gate is located on at least one side of two opposite sides of the first channel portion in the second direction; The second transistor further includes a second gate; the second gate is located on at least one of two opposite sides of the second channel portion in the second direction.

9. The semiconductor structure according to claim 3, characterized in that: The semiconductor structure further comprises: A plurality of word lines extend along the first direction; each of the word lines is connected to the gate of each transistor in a row of transistor groups arranged along the first direction.

10. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A plurality of storage structures are located at a side of the plurality of transistor groups away from the first connection structure / the second connection structure, and each of the storage structures is connected to the remaining end of each transistor in the plurality of transistor groups.

11. A memory system, characterized in that: include: A semiconductor structure as claimed in any one of claims 1 to 10.

12. A method for manufacturing a semiconductor structure, characterized in that: The method comprises: obtaining a semiconductor layer; A plurality of transistor groups arranged in an array along a first direction and a second direction intersecting each other are formed in the semiconductor layer; each of the transistor groups comprises: a first transistor and a second transistor arranged in parallel along the first direction; forming a plurality of first connection structures extending along the second direction, each of the first connection structures being connected to one end of a row of the first transistors arranged along the second direction; forming a plurality of second connection structures extending along the second direction, each of the second connection structures being connected to one end of a row of the second transistors arranged along the second direction; The projection area of ​​the first connection structure on the first plane partially overlaps with the projection area of ​​the second connection structure on the first plane or is arranged adjacently or spaced apart; and the first plane is perpendicular to the surface of the semiconductor layer.

13. The manufacturing method according to claim 12, characterized in that: The first transistor includes a first semiconductor column extending along a third direction; the first semiconductor column includes a first channel portion, and a first source and a first drain respectively located at two ends of the first channel portion that are oppositely disposed in the third direction; The second transistor includes a second semiconductor column extending along the third direction; The second semiconductor column comprises: a second channel portion, and a second source and a second drain respectively located at two ends of the second channel portion that are oppositely arranged in the third direction; the third direction is perpendicular to the surface of the semiconductor layer, and the first direction and the second direction are both perpendicular to the third direction; Among them, one end of the first source electrode away from the first channel portion and one end of the second source electrode away from the second channel portion are basically flush along the first direction; the first connecting structure is connected to a row of the first drain electrodes arranged along the second direction, and the second connecting structure is connected to a row of the second drain electrodes arranged along the second direction; the size of the first connecting structure in the third direction is the same as the size of the second connecting structure in the third direction.

14. The manufacturing method according to claim 13, characterized in that: The first semiconductor column further includes a first doped portion located between the first drain and the first channel portion; the second semiconductor column further includes: a second doped portion located between the second drain and the second channel portion; The method further includes: forming a first doped portion before forming the first drain; and forming a second doped portion before forming the second drain; Among them, the first source and the second source have the same size in the third direction, the first drain and the second drain have the same size in the third direction, and the sum of the sizes of the first channel portion and the first doped portion in the third direction is greater than the sum of the sizes of the second channel portion and the second doped portion in the third direction.

15. The manufacturing method according to claim 14, characterized in that: The first channel portion and the second channel portion have the same size in the third direction, and the first doped portion has a size greater than the second doped portion in the third direction.

16. The manufacturing method according to claim 15, characterized in that: A projection area of ​​the first doped portion on the first plane at least partially overlaps with a projection area of ​​the second connection structure on the first plane; The first plane is perpendicular to the surface of the semiconductor layer.

17. The manufacturing method according to claim 13, characterized in that: The first source electrode and the second source electrode have the same size in the third direction, the first drain electrode and the second drain electrode have the same size in the third direction, and the size of the first channel portion in the third direction is larger than the size of the second channel portion in the third direction.

18. The manufacturing method according to claim 13, characterized in that: The method further comprises: forming a first gate on at least one of two opposite sides of the first channel portion along the second direction; and A second gate is formed on at least one of two opposite sides of the second channel portion along the second direction.

19. The manufacturing method according to claim 18, characterized in that: The method further comprises: A plurality of word lines extending along the first direction are formed; each of the word lines is connected to the gate of each transistor in a row of transistor groups arranged along the first direction.

20. The manufacturing method according to claim 12, characterized in that: The method further comprises: A plurality of storage structures are formed on the first end of each transistor in the transistor group; each of the storage structures is connected to an end of each transistor in the plurality of transistor groups away from the first connection structure / the second connection structure.

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