Power semiconductor device with moisture barrier

Abstract

A power semiconductor device includes a package, a power semiconductor die located within the package, and a moisture barrier located on an upper surface and a side surface of an exterior of the package.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 17 / 747,128 filed on May 18, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to power semiconductor devices, and more particularly to packaged power semiconductor devices. Background Art

[0004] A power semiconductor device refers to a device including one or more power semiconductor dies that are designed to carry large currents and / or are capable of blocking high voltages. In this article, a power semiconductor die refers to a semiconductor die that can pass at least 1 ampere of current during normal operation and / or can block at least 100 volts during reverse blocking operation. Power semiconductor dies are often made of wide bandgap semiconductor materials, such as semiconductor materials based on silicon carbide ("SiC") or gallium nitride ("GaN"). A variety of power semiconductor dies are known in the art, including, for example, power metal oxide semiconductor field effect transistors ("MOSFET"), power insulated gate bipolar junction transistors ("IGBT"), power Schottky diodes, etc. Power semiconductor dies are often packaged to provide packaged power semiconductor devices.

[0005] A power MOSFET is a widely used power semiconductor die. A power MOSFET is a three-terminal device having gate, drain and source terminals and a semiconductor layer structure often referred to as a semiconductor body. A source region and a drain region separated by a channel region are formed in the semiconductor body, and a gate electrode (which may serve as a gate terminal or be electrically connected to the gate terminal) is disposed adjacent to the channel region. The MOSFET can be turned on (to conduct current through the channel region between the source region and the drain region) by applying a bias voltage to the gate electrode, and the MOSFET can be turned off (to block current from flowing through the channel region) by removing the bias voltage (or reducing the bias voltage to below a threshold level).

[0006] Power semiconductor devices are commercially available in both discrete and multi-chip power packages. Discrete power packaged power semiconductor devices include a single power semiconductor die, such as a packaged MOSFET, Schottky diode, IGBT, etc. Multi-chip power packaged power semiconductor devices refer to power semiconductor modules that include two or more power semiconductor dies arranged in a common package (and usually interconnected). Discrete packaged power semiconductor devices comprise a large portion of the power electronics industry because they can be implemented at very low cost and are easily combined to form more complex circuits.

[0007] Packaged power semiconductor devices typically generate a lot of heat during device operation. To prevent this heat from damaging the device, the semiconductor die is typically attached to a submount that acts as a heat sink for removing heat from the package. For example, a copper or aluminum lead frame and / or a copper-clad ceramic substrate is typically used as a submount. The upper side of the submount may be plated with nickel or silver or another metal, which facilitates attaching the semiconductor die to the submount. Summary of the invention

[0008] According to some embodiments of the present invention, a packaged power semiconductor device is provided, the power semiconductor device comprising a package, a power semiconductor die within the package, and a moisture barrier on an upper surface and a side surface outside the package.

[0009] In some embodiments, the package includes a plastic overmold. In some embodiments, the moisture barrier is directly located on the plastic overmold. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the plastic overmold. In some embodiments, the moisture barrier is also located on at least a portion of the bottom of the exterior of the package.

[0010] In some embodiments, the semiconductor die has a first terminal and a second terminal, and the package further comprises: a first lead electrically connected to the first terminal, the first lead extending out of the plastic overmold, and a second lead electrically connected to the second terminal, the second lead extending out of the plastic overmold. In some embodiments, the first lead comprises a widened segment extending through an outer surface of the plastic overmold and a narrowed segment extending outwardly from the widened segment, and the moisture barrier covers at least a portion of the widened segment.

[0011] In some embodiments, the package further includes a base, and the semiconductor die is mounted on an upper surface of the base.

[0012] In some embodiments, the base includes a lead frame or a power substrate, and the plastic overmold and the base together encapsulate the semiconductor die.

[0013] In some embodiments, the semiconductor die further includes a third terminal located on a side of the semiconductor layer structure of the semiconductor die opposite the first and second terminals, and the third terminal is electrically connected to the base.

[0014] In some embodiments, the package includes a base and a housing, and the moisture barrier completely covers a bottom surface of the base.

[0015] In some embodiments, the moisture barrier includes at least one of parylene, silicone, polyurethane, or acrylic material.

[0016] In some embodiments, the moisture barrier comprises a coating having a thickness of 1-10 microns.

[0017] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, the power semiconductor device is mounted on the printed circuit board, and a portion of the moisture barrier is located between the package and the printed circuit board.

[0018] In some embodiments, the packaged electronic device is mounted on a metal pad on a printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

[0019] In some embodiments, the moisture barrier is a first moisture barrier, and the power semiconductor device further comprises a second moisture barrier covering the upper surface and side surfaces of the semiconductor die. In some embodiments, the second moisture barrier also covers portions of the first and second leads.

[0020] In some embodiments, the semiconductor die is a silicon carbide based vertical MOSFET or Schottky diode.

[0021] In some embodiments, the semiconductor die is a first semiconductor die and the power semiconductor device further includes a second semiconductor die within the package.

[0022] In some embodiments, the moisture barrier covers some but not all of the portions of the first and second leads that are external to the plastic overmold.

[0023] According to a further embodiment of the present invention, a power semiconductor device is provided, which includes a housing, a semiconductor die having a first terminal and a second terminal, and a moisture barrier located on the upper surface and side surfaces of the semiconductor die, and the moisture barrier is positioned between the semiconductor die and the housing.

[0024] In some embodiments, the housing comprises a plastic overmold.

[0025] In some embodiments, the housing and the base comprise a package for a power semiconductor device, and the semiconductor die is mounted on an upper surface of the base.

[0026] In some embodiments, the base includes a lead frame or a power substrate, and the plastic overmold and the base together encapsulate the semiconductor die.

[0027] In some embodiments, the package further includes a first lead electrically connected to the first terminal and a second lead electrically connected to the second terminal, and the moisture barrier further covers portions of the first and second leads within the plastic overmold.

[0028] In some embodiments, the moisture barrier directly contacts the semiconductor die and the plastic overmold.

[0029] In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the semiconductor die.

[0030] In some embodiments, the moisture barrier and the housing are different materials.

[0031] In some embodiments, the moisture barrier is a second moisture barrier and the power semiconductor device further includes a first moisture barrier on an exterior of the plastic overmold.

[0032] In some embodiments, the plastic overmold is located on a top surface and side surfaces of the base, and wherein at least a portion of a bottom surface of the base is free of the plastic overmold.

[0033] In some embodiments, the first moisture barrier covers the bottom surface of the base.

[0034] In some embodiments, the moisture barrier includes at least one of parylene, silicone, polyurethane, or acrylic material.

[0035] In some embodiments, the moisture barrier comprises a coating having a thickness of 1-10 microns.

[0036] In some embodiments, the power semiconductor device is provided in combination with a printed circuit board, and the power semiconductor device is mounted on the printed circuit board, and a portion of the moisture barrier is located between the plastic overmold and the printed circuit board.

[0037] In some embodiments, a power semiconductor device is mounted on a printed circuit board and includes terminals mounted on a heat sink, and the moisture barrier electrically insulates the semiconductor die from the heat sink.

[0038] According to yet further embodiments of the present invention, a manufacturing method is provided in which a semiconductor die having a first terminal and a second terminal is packaged in a package including a base and a housing to provide a preliminary power semiconductor device. A moisture barrier is formed on the preliminary power semiconductor device to form a power semiconductor device configured to be mounted on a printed circuit board.

[0039] In some embodiments, the housing comprises a plastic overmold. In some embodiments, the moisture barrier is located directly on the exterior of the plastic overmold. In some embodiments, the moisture barrier is a conformal moisture barrier that conforms to the exterior of the plastic overmold.

[0040] In some embodiments, the package further includes a first lead and a second lead, the method further including electrically connecting the first lead to the first terminal, the first lead extending out of the plastic overmold, and electrically connecting the second lead to the second terminal, the second lead extending out of the plastic overmold.

[0041] In some embodiments, the first lead includes a widened segment extending through an outer surface of the plastic overmold and a narrowed segment extending outwardly from the widened segment, and the moisture barrier covers at least a portion of the widened segment.

[0042] In some embodiments, the base includes a lead frame or a power substrate, and the plastic overmold and the base together encapsulate the semiconductor die.

[0043] In some embodiments, the moisture barrier is formed to completely cover the bottom surface of the package.

[0044] In some embodiments, forming the moisture barrier comprises forming the moisture barrier via chemical vapor deposition. In some embodiments, forming the moisture barrier comprises forming the moisture barrier by immersing the preliminary power semiconductor device in a solution of a moisture barrier material. In some embodiments, forming the moisture barrier comprises spraying the moisture barrier material onto the preliminary power semiconductor device.

[0045] In some embodiments, the method further comprises, before forming the moisture barrier, 0 C to remove moisture from the plastic overmold.

[0046] In some embodiments, the moisture barrier is formed within two hours after the overmold plastic is formed or after a baking process applied to the overmold plastic to remove moisture therefrom is completed.

[0047] In some embodiments, the moisture barrier includes at least one of parylene, silicone, polyurethane, or acrylic material.

[0048] In some embodiments, the moisture barrier comprises a coating having a thickness of 1-10 microns.

[0049] In some embodiments, the method further includes mounting the power semiconductor device on a printed circuit board such that a portion of the moisture barrier is between the package and the printed circuit board.

[0050] In some embodiments, the power semiconductor device is mounted on a metal pad on a printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

[0051] In some embodiments, the moisture barrier is a first moisture barrier, and the method further includes forming a second moisture barrier covering the upper surface and side surfaces of the semiconductor die and portions of the first and second leads, the second moisture barrier being positioned between the semiconductor die and the second portion of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1Ais a top perspective view of a discretely packaged power semiconductor device according to an embodiment of the present invention.

[0053] Figure 1B yes Figure 1A A perspective view of a discrete packaged power semiconductor device with its moisture barrier and overmold package removed.

[0054] Figure 1C yes Figure 1A Schematic cross-section of a discrete power semiconductor electronic device.

[0055] Figure 2 is a schematic cross-sectional view of a packaged power semiconductor device including a power substrate according to a further embodiment of the present invention.

[0056] Figure 3 is a schematic side cross-sectional view of a packaged power semiconductor device according to additional embodiments of the present invention, wherein the moisture barrier completely encapsulates the base.

[0057] Figure 4A is a schematic cross-sectional view of a power semiconductor device including a package with an internal moisture barrier according to yet a further embodiment of the present invention.

[0058] Figure 4B yes Figure 4A Schematic cross-sectional view of a modified version of a package for a power semiconductor device further comprising an external moisture barrier.

[0059] Figure 5-7 is a schematic side cross-sectional view of a packaged power semiconductor device according to a further embodiment of the present invention.

[0060] Figure 8 is a flow chart of a method of manufacturing a packaged power semiconductor device according to an embodiment of the present invention.

[0061] Note that when multiple similar elements are shown in the figures, they can be identified using two-part reference numerals. Such elements can be individually referred to herein by their full reference numerals (e.g., floating lead 136-1) and collectively referred to by the first part of their reference numerals (e.g., floating lead 136). DETAILED DESCRIPTION

[0062] Power semiconductor devices are designed to block high voltages during reverse blocking operations and pass high current levels during on-state operations. For example, power semiconductor devices may need to block hundreds or thousands of volts and / or pass tens or hundreds of amperes. Operations at these voltage and current levels can generate significant heat within the power semiconductor die. Due to the high heat levels, many discrete power semiconductor devices are packaged in ceramic air cavity packages, where the power semiconductor die is mounted on a metal base and enclosed in an air cavity in a ceramic housing (these packages are referred to as ceramic air cavity packages). The ceramic housing and metal base can withstand the heat generated by the power semiconductor die during operation and can efficiently dissipate this heat. However, the use of ceramic air cavity packaging increases the size and cost of the packaged power semiconductor device.

[0063] Most semiconductor devices that operate at low power levels are packaged by encapsulating the semiconductor die in a plastic overmold. In recent years, plastic overmold packages suitable for power semiconductor devices have been developed. When using a plastic overmold package, the semiconductor die is typically mounted on a base and the leads are electrically connected to corresponding terminals on the semiconductor die. The plastic overmold material (such as, for example, an epoxy molding compound) is then injection molded to encapsulate the power semiconductor die and at least a portion of the base. The leads extend through the plastic overmold package so that electrical connections can be made between the semiconductor die and external devices (e.g., input terminals, output terminals, bias voltage sources, etc.). The base, leads, and plastic overmold package together constitute the package for the power semiconductor die.

[0064] Discretely packaged power semiconductor devices are usually mounted on printed circuit boards of larger electronic systems. Unfortunately, standard epoxy molding compounds easily absorb moisture from the environment. This moisture absorption may be mainly in the form of direct diffusion of moisture through epoxy resin. Moisture absorption by power semiconductor die encapsulated by plastic overmolds can cause problems. In particular, during the solder reflow process used to attach discrete power semiconductor devices to printed circuit boards of larger electronic systems, the moisture absorbed in the plastic overmold will expand. As the plastic overmold expands, it will fall off the semiconductor die. In some cases, the plastic overmold will break or even explode instead. In general, the shedding of the overmold package will cause premature failure of the device (for example, when the device undergoes thermal cycling during normal operation, the shedding will increase, which will weaken or destroy the connection between the power semiconductor die terminal and the package lead), while the rupture (or explosion) of the plastic overmold usually causes the device to fail immediately.

[0065] To reduce the likelihood of device failure due to moisture absorption, power semiconductor devices encapsulated in plastic overmolds can be rated based on an industry standard moisture sensitivity scale promulgated by IPC International, a global association of entities involved in the manufacture of electronic devices. This moisture sensitivity scale is set forth in document IPC / JEDEC J-STD-0 33. Document IPC / JEDEC J-STD-033 specifies eight different moisture sensitivity levels and, for each level, specifies the maximum amount of time that a packaged semiconductor device can be kept outside of a moisture barrier bag before the device is soldered to a printed circuit board. For example, according to the IPC / JEDEC J-STD-033 standard, an electronic device with an IPC / JEDEC J-STD-033 moisture sensitivity rating level of "3" must be stored at temperatures below 30 °C before being soldered to a printed circuit board. 0 C and relative humidity below 60% should not be stored outside the moisture barrier bag for more than one week to ensure that the device is not at a higher risk of failure due to moisture.

[0066] Higher moisture sensitivity rating levels can severely limit the amount of time an electronic device can be outside of a moisture barrier bag before the device is soldered to a printed circuit board of a larger system. For example, an electronic device with an IPC / JEDEC J-STD-033 moisture sensitivity rating level of "5a" can only be maintained outside of a moisture barrier bag for 24 hours. Electronic device manufacturers who assemble electronic devices that include discrete packaged power semiconductor devices must consider the moisture sensitivity rating level of the discrete packaged power semiconductor devices during the manufacturing process to ensure that the device is not subject to excessive moisture absorption, which could cause damage or destruction to the packaged power semiconductor devices, particularly during solder reflow operations. This can complicate the manufacturing process and increase the risk that a larger electronic system may fail prematurely due to moisture absorption-induced failures of the power semiconductor devices included in the larger electronic system.

[0067] According to an embodiment of the present invention, a packaged power semiconductor device is provided, which includes a packaged and separate moisture barrier. The overmold package can be formed of a plastic material such as, for example, an epoxy molding compound. The moisture barrier can be conformally coated on the plastic overmold package. As known in the art, a conformal coating refers to a layer of material coated (e.g., formed or deposited) on the surface of an underlying structure, which generally conforms to or "tracks" the shape of the surface of the underlying structure. The conformal coating has a generally uniform thickness (e.g., the variation of the portion located on the flat surface of the underlying structure is less than 10-15%, but slightly larger variations may occur at corners or other non-planar areas). The moisture barrier can include any material that significantly or completely prevents moisture from entering the overmold package. For example, acrylic materials, polyurethanes, silicones and / or polyparaxylene are all materials that can be conformally formed or deposited as a coating, which will act as such a moisture barrier. The moisture barrier can be formed on the plastic overmold package, for example, by automated spraying, dipping, condensation processes or chemical vapor deposition. Adding such a moisture barrier to a packaged power semiconductor device can significantly extend the time that the device can remain outside the moisture barrier bag before the device is soldered to a customer printed circuit board. The moisture barrier can also reduce the likelihood of device failure due to moisture during normal operation of the device. The moisture barrier can be applied directly after the plastic overmold package is formed (e.g., after a baking operation for curing the plastic overmold), or during a subsequent processing step. The packaged power semiconductor device can optionally be subjected to a slow baking operation designed to remove moisture from the device before the moisture barrier is applied.

[0068] In some embodiments, a moisture barrier may be applied to substantially or completely cover the plastic overmold encapsulation material. In this document, reference to "substantially" means within + / -10%. The moisture barrier may not be applied or may be only partially applied to exposed metal elements of the packaged power semiconductor device that are designed to be soldered to external elements such as metal pads. In other embodiments, the moisture barrier may completely encapsulate the entire body of the packaged power semiconductor device, and only the distal portions of the leads may be free of the moisture barrier. In such embodiments, the moisture barrier may be part of the main heat dissipation path from the semiconductor die to an external heat sink (such as a heat sink surface mounted on a customer printed circuit board). The moisture barrier may be thin enough to have good thermal conductivity while also electrically isolating the packaged power semiconductor device from the heat sink.

[0069] As described above, the package leads of the power semiconductor device of the plastic overmold package extend through the plastic overmold so that each lead has an encapsulated segment and an exposed segment. In some embodiments, the moisture barrier can extend to the portion of the exposed segment of the lead adjacent to the plastic overmold package. This can help ensure that the leads themselves do not provide a path for moisture to enter the overmold package. In addition, as will be discussed below, the moisture barrier can advantageously increase the "creepage distance" between adjacent leads, which can improve device performance.

[0070] Although the above-described moisture barrier is provided on (e.g., conformally formed on) the exterior surface of the plastic overmold package, the teachings of the present invention are not limited thereto. For example, in other embodiments, a moisture barrier may be formed on the semiconductor die, base, and leads (and possibly bond wires) after the leads are electrically connected to the terminals of the semiconductor die, but before the plastic overmold is formed to encapsulate the semiconductor die. In such embodiments, the moisture barrier will be located between the semiconductor die and the plastic overmold package. This "internal" moisture barrier may be provided as a separate moisture barrier, or may be combined with the aforementioned moisture barrier formed on the exterior surface of the plastic overmold package.

[0071] Embodiments of the present invention will now be discussed in more detail with reference to the accompanying drawings. It will be appreciated that the features of the different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Therefore, it will be appreciated that various features of the present invention are described below with respect to specific examples, but these features can be added to other embodiments and / or used to replace the example features of other embodiments to provide many additional embodiments. Therefore, it should be understood that the present invention encompasses these different combinations. In addition, although the example embodiments focus on MOSFET implementations, it will be appreciated that the same technology can be used in other packaged electronic devices, such as IGBTs, Schottky diodes, gate-controlled thyristors, etc.

[0072] Figures 1A-1C Schematically illustrates a packaged power semiconductor device according to some embodiments of the present invention. In particular, Figure 1A is a top perspective view of a packaged power semiconductor device 100, Figure 1B is a perspective view of a power semiconductor device 100 with its moisture barrier and plastic overmold package removed, and Figure 1C is a schematic side cross-sectional view of device 100 .

[0073] refer to Figures 1A-1C, the packaged power semiconductor device 100 includes a power semiconductor die 110 mounted on the upper surface of a base, wherein the base in this embodiment includes a lead frame 130. The power semiconductor die 110 can be a semiconductor device designed to block high voltage levels (e.g., hundreds of volts or more) and / or carry large currents. The power semiconductor die 110 can include a semiconductor layer structure formed using, for example, silicon and / or wide bandgap semiconductor materials (such as silicon carbide and / or gallium nitride-based and / or aluminum nitride-based semiconductor systems, such as GaN, AlGaN, InGaN, AlN, etc.). Other wide bandgap materials can be used, such as devices formed in other III-V semiconductor systems or II-VI semiconductor systems. The power semiconductor die 110 can include, for example, MOSFETs, MISFETs, IGBTs, Schottky diodes, gate-controlled thyristors, etc. The power semiconductor die 110 can have a vertical structure, wherein the upper side of the die includes at least one terminal and the lower side of the die 110 also includes at least one terminal.

[0074] In the depicted embodiment, the power semiconductor die 110 is a discrete power MOSFET having a vertically extending drift region through which current flows during on-state operation. Figure 1C As shown in , the MOSFET includes a semiconductor layer structure 112. The semiconductor layer structure 112 can be formed of a wide bandgap semiconductor material (such as, for example, silicon carbide). A gate terminal 114 and a source terminal 116 are provided on the upper surface of the semiconductor layer structure 112, and a drain terminal 118 is located on the lower surface of the semiconductor layer structure 112. Each of the terminals 114, 116, 118 can be implemented as an exposed metal pad. Typically, the gate terminal / pad 114 is smaller than the source terminal / pad 116, and the drain terminal 118 can be approximately the same size as or larger than the source terminal / pad 116. Since the source terminal 116 and the drain terminal 118 are located on opposite sides of the semiconductor layer structure 112, the MOSFET 110 is a vertical device.

[0075] The lead frame 130 includes a die attach region 132 and integrated leads 134 on its upper surface. The bottom surface of the MOSFET 110 may be attached to the die attach region 132 of the lead frame 130 using any suitable bonding material or technique. In the depicted embodiment, the MOSFET 110 is bonded to the lead frame 130 using a die attach material 122. The drain terminal 118 of the MOSFET 110 is electrically connected to the integrated leads 134 through the die attach material 122 and the lead frame 130. A pair of floating leads 136-1, 136-2 is provided, and one or more bond wires 124 physically and electrically connect the gate and source terminals 114, 116 on the upper side of the MOSFET 110 to the respective floating leads 136-1, 136-2. In the depicted embodiment, a single bond wire 124 connects the gate terminal 114 to the floating lead 136-1, while three bond wires 124 connect the source terminal 116 to the floating lead 136-2. It should be noted that in this document, the term "bond wire" is used broadly to cover traditional bond wires as well as other functionally equivalent structures such as ribbons or clips that can be used in place of real wires.

[0076] The plastic overmold package 150 encapsulates at least the upper surface of the power semiconductor die 110 and the lead frame 130, and at least a portion of each side surface of the lead frame 130. The leads 134, 136 extend through the plastic overmold package 150 so that each lead 134, 136 has a first segment located within the plastic overmold package 150 and a second segment located outside the plastic overmold package 150. The plastic overmold package 150 covers and protects the MOSFET 110. Although embodiments of the present invention will be described primarily with respect to devices including epoxy molding compound as an overmold package, it will be appreciated that embodiments of the present invention are not limited thereto. For example, in other embodiments, the package may include silicone gel or another compound. The package 150 may hold the floating leads 136 in their proper positions.

[0077] The lead frame 130, the leads 134, 136, and the overmold package 150 together form a package 120 for the power semiconductor die 110. Although one integrated lead 134 and two floating leads 136 are provided, it will be appreciated that embodiments of the present invention are not limited thereto. For example, in other embodiments, three floating leads 136 may be provided without providing an integrated lead 134. It will also be appreciated that multiple leads may be provided for one or more of the terminals 114, 116, 118 of the power semiconductor die 110. For example, the source and / or drain terminals 116, 118 may each be connected to two leads. It will also be appreciated that the number of terminals and / or the number of leads may vary depending on the type of semiconductor die 110. For example, a Schottky diode includes only two terminals (an anode terminal and a cathode terminal), and therefore only two leads may be provided for the packaged Schottky diode. The floating leads 136 may be initially integrated with the lead frame 130 , but may be separated from the lead frame 130 during the manufacturing process and may be held in place by the overmold encapsulation 150 .

[0078] like Figure 1C As can be best seen in , a moisture barrier 160 is provided on the exterior surface of the plastic overmold package 150. The moisture barrier 160 may be formed after the overmold package 150 is formed and cured. In some embodiments, the moisture barrier 160 may be conformally formed on the plastic overmold package 150. The plastic overmold package 150 may include a rigid material that protects the MOSFET 110 during processing. In contrast, the moisture barrier 160 may be a less rigid material that significantly or completely prevents moisture from entering the overmold package and has good coating properties so that a continuous coating can be applied, which presents a barrier that blocks moisture from entering the plastic overmold package 150. In example embodiments, the moisture barrier may include an acrylic material, a polyurethane material, a silicone material, and / or a polyparaxylene material. All of these materials may be conformally formed or deposited as a coating and will significantly or completely prevent moisture from entering the overmold package.

[0079] The moisture barrier 160 may include a thin layer that may be formed / deposited on the exterior surface of the plastic overmold package 150 and, optionally, may be formed / deposited on portions of the lead frame 130 and / or selected portions of the leads 134, 136 that extend outside of the overmold package 150. For example, Figure 1CAs shown in , the moisture barrier 160 can extend onto some or all of the side surfaces of the lead frame 130. The moisture barrier 160 can also partially extend onto the portion of each lead 134, 136 that extends outside the overmold package 150. In an example embodiment, the moisture barrier 160 can have a thickness between 1-10 microns. In some embodiments, the moisture barrier 160 can be conformally coated onto the plastic overmold package.

[0080] For example, the moisture barrier 160 may be formed on the plastic overmold package 150 by a spray or sputtering process. For example, the moisture barrier may be sprayed onto the overmold package 150 in liquid form using an automated spray process, which ensures that the thickness of the moisture barrier coating is substantially uniform (it should be noted that variations in coating thickness at corners should be expected), and the material may be cured to form the moisture barrier 160. Alternatively, after the plastic overmold package 150 is formed, the packaged electronic device 100 may be dipped into a vat of moisture barrier material to form the moisture barrier 160. During this dipping process, the packaged power semiconductor device 100 may be held by one or more of the leads 134, 136, as the distal ends of the leads 134, 136 are typically not covered by the moisture barrier 160, so that the leads 134, 136 may be connected to external devices (e.g., by bond wires).

[0081] In other embodiments, the moisture barrier 160 can be formed by a chemical deposition process. In particular, after forming the plastic overmold package 150 (including curing), the packaged power semiconductor device 100 can be placed in a chemical vapor deposition chamber, and the source material of the moisture barrier 160 can be injected into the chamber in a gaseous form. The packaged power semiconductor device 100 can be positioned in another part of the chamber at a lower temperature and / or pressure, and the gaseous material can condense onto the outer surface of the packaged power semiconductor device 100 to form the moisture barrier 160. During any of the manufacturing processes discussed above, the portions of the packaged power semiconductor device 100 that should not be applied with a moisture barrier can be covered with a mask (e.g., Kapton tape, photoresist, etc.). In the case where any moisture barrier material is deposited on the mask, the mask can be removed subsequently. In other cases, a fixture used as a mask can be provided. For example, when chemical vapor deposition is used to form the moisture barrier 160, a fixture can be provided in the chemical vapor deposition chamber, the fixture including an opening that tightly accommodates the respective ends of the leads 134, 136 of the packaged power semiconductor device 100. The packaged power semiconductor device 100 can be installed in the chamber by inserting the ends of the leads 134, 136 into the fixture. Therefore, all portions of the packaged power semiconductor device 100 except the leads 134, 136 will be exposed, and the moisture barrier 160 can be formed by chemical vapor deposition to coat the entire exterior of the packaged power semiconductor device except the ends of the leads 134, 136.

[0082] The moisture barrier 160 may be applied directly after the plastic overmold package 150 is formed (including curing). This can help ensure that moisture does not penetrate the plastic overmold package 150 before the moisture barrier 160 is formed. The packaged power semiconductor device 100 may optionally be subjected to a slow bake operation designed to remove moisture from the device 100 prior to applying the moisture barrier 160. For example, the packaged power semiconductor device 100 may be baked at 125 0 C for at least eight hours to remove moisture therefrom, and then a moisture barrier 160 may be formed on the overmold package 150. Alternatively, the packaged power semiconductor device 100 may be baked at a lower temperature for a longer time, or at a higher temperature for a shorter time. In general, the longer the baking operation and the higher the temperature, the greater the ability of the baking operation to remove any moisture present within the device. For example, if the moisture barrier 160 is not applied shortly after the overmold package 150 is formed, a slow bake may be performed.

[0083] It will be appreciated that the materials discussed above that may be used to form the moisture barrier 160 and the techniques discussed above for forming the moisture barrier 160 may be used to form any of the moisture barriers discussed below that are included in packaged power semiconductor devices according to embodiments of the present invention.

[0084] like Figure 1C As shown in , the leads 134, 136 extend through the plastic overmold package 150 so that each lead 134, 136 has an encapsulated segment and an exposed segment. In some embodiments, the moisture barrier 160 can extend to the exposed segments of the leads 134, 136 adjacent to the plastic overmold package 150. This can help ensure that the leads 134, 136 themselves do not provide a path for moisture to enter the overmold package 150. In addition, the moisture barrier 160 can advantageously increase the "creepage distance" between adjacent leads, which refers to the shortest distance along the surface of the dielectric material between two conductive parts. Here, the creepage distance is the distance between the exposed portions of adjacent leads 134, 136 along the surface of the intermediate dielectric material. Since the moisture barrier 160 covers a portion of the leads 134, 136, the creepage distance is increased. This can allow the packaged power semiconductor device 100 to be rated for a higher operating voltage and / or allow the device to operate in a more polluted environment.

[0085] As indicated in the above discussion, the packaged power semiconductor device 100 includes a semiconductor die 110 having at least a first terminal 114 and a second terminal 116. A package including a plastic overmold 150 at least partially covers the semiconductor die 110. The package may also include a first lead 136-1 electrically connected to the first terminal 114 and a second lead 136-2 electrically connected to the second terminal 116. The first and second leads 136-1, 136-2 each extend out of the plastic overmold 150. A moisture barrier 160 is located on the upper surface and side surfaces of the plastic overmold 150.

[0086] In some embodiments, the moisture barrier 160 may be directly located on the upper, side, and bottom surfaces of the overmold package 150. In some embodiments, the first and second terminals 114, 116 may be located on a first surface of the semiconductor layer structure 112 of the semiconductor die 110, and the semiconductor die 110 may also include a third terminal 118 located on a side of the semiconductor layer structure 112 opposite the first and second terminals 114, 116. The package 120 may also include a base 130, and the semiconductor die 110 may be mounted on an upper surface of the base 130. In some embodiments, the moisture barrier 160 may completely cover the bottom surface of the package 120.

[0087] In some embodiments, moisture barrier 160 includes at least one of polyparaxylene, silicone, polyurethane, or acrylic material, and / or moisture barrier 160 may have a thickness between 1-10 microns. Figure 1A-1B As shown in , in some embodiments, the first lead 136 - 1 may include a widened segment extending through the outer surface of the overmold package 150 and a narrowed segment extending outward from the first widened segment, and the moisture barrier 160 may cover at least a portion of the widened segment.

[0088] In some embodiments, the packaged electronic device 100 can be mounted on a printed circuit board (such as a customer printed circuit board), and a portion of the moisture barrier 160 can be located between the overmold package 150 and the printed circuit board. For example, the packaged electronic device 100 can be mounted on a metal pad on a customer printed circuit board (e.g., using screws or clips), and the moisture barrier 160 can electrically insulate the semiconductor die 110 from the metal pad.

[0089] As described above, packaged power semiconductor devices (such as device 100) are typically mounted on printed circuit boards of larger electronic systems. These larger printed circuit boards are often referred to as customer motherboards. The packaged power semiconductor device 100 will typically be mounted on a heat sink on the customer motherboard so that heat discharged through the main thermal interface of the packaged power semiconductor device 100 (here, the path through the drain terminal 118 and the lead frame 130) can also be discharged from the customer motherboard. In many cases, the heat sink 1 surface is mounted on the customer motherboard. In some cases, the exposed metal portion of the packaged power semiconductor device 100 (e.g., the bottom surface of the base 130) can be mounted on the heat sink. In some cases, the leads 134, 136 of the packaged power semiconductor device 100 can be mounted in corresponding plated through holes of the customer motherboard. In some cases, the exposed metal portion of the packaged power semiconductor device 100 can be mounted on the heat sink, and the leads 134, 136 can also be mounted in corresponding plated through holes of the customer motherboard.

[0090] As from Figure 1CAs can be seen, since the drain terminal 118 is electrically connected to the bottom of the lead frame 130, the primary thermal interface may not be electrically isolated from the power semiconductor die 110. It is often necessary to electrically isolate the semiconductor die 110 from the heat sink on the customer's motherboard. This can be achieved by inserting a so-called "thermal pad" in the form of a thin dielectric layer (e.g., a silicone layer) between the packaged power semiconductor device 100 and the heat sink on the customer's motherboard, which electrically isolates the power semiconductor die 110 from the heat sink. The packaged power semiconductor device can be mechanically attached to the customer's motherboard (e.g., a heat sink for the motherboard) using, for example, screws or spring clips with the thermal pad between the packaged power semiconductor device and the customer's motherboard, and the device leads can be soldered to the motherboard. For packaged semiconductor devices operating at lower voltages (e.g., tens of volts) and current levels, it is acceptable and convenient to use such a thermal pad to electrically isolate the power semiconductor die 110 from the customer's motherboard. However, for power semiconductor devices designed to block hundreds or even thousands of volts, the capacitive coupling across the thermal pad can be strong enough to negatively impact the performance of the semiconductor device and / or degrade the material of the thermal pad, which can result in a short circuit between the primary thermal interface and the metal pad on the customer's motherboard. Such a short circuit typically renders the packaged power semiconductor device inoperable and can also damage or even destroy the device.

[0091] Figure 2 is a schematic cross-sectional view of a discrete packaged power semiconductor device 200 according to a further embodiment of the present invention. The packaged power semiconductor device 200 is similar to the above reference Figures 1A-1C The packaged power semiconductor device 100 is discussed, but also includes a power substrate 240. As will be discussed below, the power substrate 240 includes an insulating substrate that electrically isolates the power semiconductor die 110 from a customer motherboard.

[0092] By comparison Figure 1C and Figure 2 As can be seen, the only difference between the packaged power semiconductor device 200 and the packaged power semiconductor device 100 is that the packaged power semiconductor device 200 further includes (1) a power substrate 240 attached to the bottom surface of the lead frame 130, and (2) a plastic overmold 250 and a moisture barrier 260, both of which extend to cover the side surfaces of the power substrate 240. Thus, the components of the packaged power semiconductor device 200 that are the same or substantially identical to the corresponding components of the packaged power semiconductor device 100 are used in the same manner as described above. Figures 1A-1C The same reference numerals used in the drawings are used to mark the same components, and further description of these similar components will generally be omitted. The same convention applies throughout this application.

[0093] like Figure 2As shown in , the power substrate 240 includes a ceramic substrate 242. A lower metal cladding layer 246-1 is formed on the lower side of the ceramic substrate 242, and an upper metal cladding layer 246-2 is formed on the upper side of the ceramic substrate 242. The lead frame 130 is mounted on the upper metal cladding layer 246-2 using the substrate attachment material 126. As used herein, the term "power substrate" refers to a dielectric substrate having metal cladding layers on both sides thereof. There are two main types of power substrates. The first type is called an active metal brazing ("AMB") power substrate, which includes first and second metal brazing layers 244-1, 244-2 for bonding the first and second metal cladding layers 246-1, 246-2 to the ceramic substrate 242, respectively. In contrast to welding, brazing can be used to bond metal to a dielectric surface. Metal brazing materials have some similarities to solder, but the bonding process is performed at a higher temperature and is usually performed in a vacuum. The resulting bond has higher reliability compared to conventional solder attachment. The second type of power substrate is called a direct bond substrate (or more commonly a direct bond copper or "DBC" power substrate because the metal cladding layers 246-1, 246-2 are typically copper layers). DBC power substrates are formed by pressing the metal cladding layers 246-1, 246-2 directly onto the dielectric substrate 242 while performing a heat treatment in a controlled atmosphere. DBC power substrates are not as reliable as AMB power substrates.

[0094] The plastic overmold 250 differs from the plastic overmold 150 in that the plastic overmold 250 extends to cover the side surfaces of the power substrate 240. A moisture barrier 260 is conformally coated on the plastic overmold 250 and on selected portions of the power substrate 240 and the leads 134, 136. The lead frame 130, the leads 134, 136, the power substrate 240, and the plastic overmold 250 form a package 220 for the power semiconductor die 110. The moisture barrier 260 protects the package 220 from moisture ingress. The power substrate 240 serves as the primary thermal interface for dissipating heat generated in the power semiconductor die 110 out of the device package 220.

[0095] Although the packaged power semiconductor device 200 includes the lead frame 130 and the power substrate 240, it will be appreciated that in other embodiments the lead frame 130 may be omitted and the integrated leads 134 of the lead frame may be replaced with third floating leads 136. In such embodiments, the power semiconductor die 110 may be mounted directly on the upper cladding layer 246-2 via the die attach material 122.

[0096] Figures 1A-1C and Figure 2The packaged power semiconductor device 100 , 200 in FIG. 1 includes a moisture barrier 160 , 260 that does not cover a majority of the exposed bottom surface of the base 130 , 240 . Figure 3 is a schematic side cross-sectional view of a discretely packaged power semiconductor device 300 including a moisture barrier 360 completely covering the exposed bottom surface of the base 130 according to an additional embodiment of the present invention.

[0097] By comparison Figure 1C and Figure 3 As can be seen, the packaged power semiconductor device 300 can be identical to the packaged power semiconductor device 100 except that the packaged power semiconductor device 300 includes a moisture barrier 360 that extends to substantially or completely cover the bottom surface of the lead frame 130. Thus, the moisture barrier 360 can completely encapsulate the entire body of the package 120, such that only the distal portions of the leads 134, 136 can be free of the moisture barrier 360. The moisture barrier 360 can be part of a heat dissipation path from the semiconductor die 110 to an external heat sink, such as a heat sink on a customer printed circuit board. Because the moisture barrier 360 completely encapsulates the lead frame 130 (except for the integrated leads 134), it electrically isolates the packaged electronic device 300 from the printed circuit board or heat sink (not shown) on which the packaged electronic device 300 is mounted. Moreover, because the moisture barrier 360 can be very thin, it can exhibit good thermal conductivity and therefore does not interfere with the heat dissipation path that will extend through the moisture barrier 360. In some embodiments, the moisture barrier 360 can eliminate any need for a thermal pad between the packaged power semiconductor device and the heat sink, while also eliminating any need to include a power substrate in the packaged power semiconductor device. In other words, in some embodiments, the lead frame of the packaged power semiconductor device can be directly attached to the heat sink without any intervening thermal pad because the moisture barrier 360 can electrically isolate the lead frame 130 from the customer motherboard / heat sink.

[0098] Although the packaged power semiconductor device 300 includes the lead frame 130, it will be understood that it may also include a power substrate 240 (eg, Figure 2 ), or it may include a power substrate instead of the lead frame 130 .

[0099] As discussed above, during the solder reflow process that is often used to mount the device to the customer's printed circuit board, power semiconductor devices that include plastic overmold encapsulation packages may be particularly susceptible to moisture-related damage. As mentioned above, if moisture accumulates in the plastic overmold, it may cause the plastic overmold to detach from the semiconductor die, or cause the plastic overmold package to rupture. In addition, if moisture penetrates the power semiconductor die, even a very small amount of moisture may cause problems. Although the power semiconductor die typically includes a passivation layer that serves as a moisture barrier, the top surface of most power semiconductor dies includes a metal bonding pad that serves as a terminal of the device. (One or more) passivation layers do not cover these pads, so bonding wires or leads can be soldered to the pads. The seam between the metal bonding pad and the passivation on the top surface of the semiconductor die may be susceptible to moisture ingress.

[0100] Although the above-described moisture barrier 160, 260, 360 is provided on the exterior surface of the plastic overmold package (e.g., conformally formed thereon), the teachings of the present invention are not limited thereto. In particular, according to further embodiments of the present invention, a packaged power semiconductor device is provided that includes an internal moisture barrier that is conformally applied to the semiconductor die and the base after electrical connections are made to the terminals of the power semiconductor die but before the plastic overmold package is applied. The internal moisture barrier can be positioned between the power semiconductor die and the overmold package.

[0101] Figure 4A 4 is a schematic side cross-sectional view of a packaged power semiconductor device 400 according to a further embodiment of the present invention, the device including such an internal moisture barrier 470. Figure 4A As shown in FIG. 4 , the packaged power semiconductor device 400 may be similar to the above reference Figures 1A-1CThe packaged power semiconductor device 100 discussed is very similar. The packaged power semiconductor device 400 differs from the packaged power semiconductor device 100 in two respects. First, the packaged power semiconductor device 400 does not include the external moisture barrier 160 included in the packaged electronic device 100. Second, the packaged power semiconductor device 400 includes an internal moisture barrier 470 that is conformally coated directly on the semiconductor die 110, the lead frame 130, the bond wires 124, and portions of the leads 134, 136. The internal moisture barrier 470 is formed after the power semiconductor die 110 is attached to the lead frame 130 and the wire bonds 124 are bonded to the terminals 114, 116 and the floating leads 136. Therefore, the internal moisture barrier 470 does not negatively affect the electrical connections within the device 400. The internal moisture barrier 470 can completely coat the upper surface and side surfaces of the power semiconductor die 110. The internal moisture barrier 470 may also coat some or all of the upper surface and / or side surfaces of the lead frame 130. The internal moisture barrier 470 may also coat portions of the bonding wires 124 and the leads 134, 136 ( Figures 4A-4B The internal moisture barrier coating the bond wires 124 is not shown.

[0102] Thus, the packaged power semiconductor device 400 includes a semiconductor die 110 having a first terminal 114 and a second terminal 116, a first lead 136-1 electrically connected to the first terminal 114 and a second lead 136-2 electrically connected to the second terminal 116, an internal moisture barrier 470 covering the upper and side surfaces of the semiconductor die 110 and portions of the first and second leads 136-1, 136-2, and a plastic overmold 150 covering the internal moisture barrier 470. In some embodiments, the internal moisture barrier 470 may be a conformal internal moisture barrier 470.

[0103] Figure 4B yes Figure 4A A schematic cross-sectional view of a modified version 400' of the packaged power semiconductor device 400. In addition to the device 400' also including the above reference Figures 1A-1C Except for the discussed outer moisture barrier 160, the packaged power semiconductor device 400' is identical to the packaged power semiconductor device 400. Therefore, further description of the packaged power semiconductor device 400' will be omitted.

[0104] Figure 5is a schematic side cross-sectional view of a packaged power semiconductor device 500 according to a further embodiment of the present invention. Packaged power semiconductor device 500 is similar to packaged power semiconductor device 200, except that leads 136-1, 136-2 are directly soldered to respective terminals 114, 116, thereby eliminating any need for bond wires. Leads 136-1 and 136-2 are shown extending from different sides of device 500, such that the leads 136-1 and 136-2 are directly soldered to respective terminals 114, 116, thereby eliminating any need for bond wires. Figure 5 The two leads can be better seen in the cross-sectional view of FIG. It will be appreciated that any embodiment of the invention discussed herein may have such directly welded leads that are used in place of the floating leads 136 that are physically and electrically connected to the terminals 114, 116 via the bond wires 124.

[0105] Figure 6 6 is a schematic side cross-sectional view of a packaged power semiconductor device 600 according to a further embodiment of the present invention. The packaged power semiconductor device 600 is similar to the packaged power semiconductor device 100, except that the integrated lead 134 is replaced by a third floating lead 136-3. The electrical connection between the drain of the power semiconductor die 110 and the third floating lead 136-3 is through the drain terminal 118, the die attach material 122, the lead frame 130, and the bonding wire 124. It will be appreciated that any of the embodiments of the present invention discussed herein may have Figure 6 The lead arrangement shown in .

[0106] Although embodiments of the present invention are primarily discussed with reference to discretely packaged power semiconductor devices including a single semiconductor die 110, it will be appreciated that embodiments of the present invention are not limited thereto. Figure 7 The packaged power semiconductor device 700 is shown in the form of a power semiconductor module including two power semiconductor dies 110-1, 110-2. In an example embodiment, the two power semiconductor dies 110-1, 110-2 may be power MOSFETs that are electrically connected (eg, in series or in parallel). Figure 7As shown in FIG. 1 , a pair of floating gate leads 136-1, 136-2 are electrically connected to gate terminals 114-1, 114-2 of respective power semiconductor dies 110-1, 110-2 via bonding wires 124 (in other embodiments, both gate terminals 114 may be connected to a single floating gate lead 136). The source terminals 116-1, 116-2 of each die 110 may be connected to one or more floating source leads 136. The drain terminals 118-1, 118-2 are connected to respective integrated drain leads 134-1, 134-2 (in other embodiments, a single drain lead 134 may be provided that is electrically connected to the drain terminals of both power semiconductor dies 110-1, 110-2). The power semiconductor dies 110-1, 110-2 are encapsulated in the overmold package 150, and the moisture barrier 160 (e.g., conformal moisture barrier 160) covers at least the upper surface and side surfaces of the plastic overmold package 150. The moisture barrier 160 may also partially extend onto the bottom surface of the plastic overmold 150 (or may completely cover the bottom surface of the plastic overmold 150). Therefore, it will be appreciated that the moisture barrier according to embodiments of the present invention may also be applied to a multi-chip module. It will also be appreciated that the multi-chip module may alternatively or additionally include the above-referenced Figures 4A-4B Internal moisture barrier 470 discussed.

[0107] It will be appreciated that when multiple power semiconductor dies 110 are included in a packaged power semiconductor device according to embodiments of the present invention, the semiconductor dies 110 may be the same or different and may be electrically connected to each other and to the leads 134, 136 of the package in a variety of ways. Thus, in example embodiments, multiple power MOSFETs connected in series or in parallel may be provided, multiple power Schottky diodes connected in series or in parallel may be provided, one or more power MOSFETs and one or more power Schottky diodes may be connected in series or in parallel, and so forth.

[0108] Figure 8 1 is a flow chart of a method for manufacturing a packaged power semiconductor device according to an embodiment of the present invention. Figure 8As shown in , operations may begin by mounting a semiconductor die having a first terminal and a second terminal on a base (block 800). A first lead is electrically connected to the first terminal and a second lead is electrically connected to the second terminal (block 810). A plastic overmold is formed that encapsulates at least a portion of the semiconductor die and the base (block 820). Thus, blocks 800-820 illustrate packaging the semiconductor die in a package that includes a base, leads, and a housing (here, a plastic overmold) to provide a preliminary power semiconductor device. A moisture barrier is formed on the preliminary power semiconductor device (block 830) to provide a power semiconductor device configured to be mounted on a printed circuit board (such as a customer's motherboard).

[0109] In some cases, a moisture barrier is formed on a customer motherboard to protect the motherboard from environmental conditions. While this can help protect components on the motherboard (including any packaged power semiconductor devices mounted thereon) from subsequent moisture ingress, it does not provide any protection against moisture damage that may occur during the solder reflow process used to mount the packaged electronic devices on the motherboard. Additionally, in many cases, it may be desirable to perform a slow bake operation on the electronic devices, which is used to remove moisture from the devices, prior to applying any moisture protection. In some cases, performing such a slow bake operation on a printed circuit board may be impossible because the printed circuit board may include components that cannot withstand such a slow bake process.

[0110] Although embodiments of the present invention have been discussed above with reference to packaged power semiconductor devices including power semiconductor dies, it will be appreciated that embodiments of the present invention are not limited thereto. For example, all of the embodiments disclosed herein may include one or more radio frequency ("RF") semiconductor dies in place of a power semiconductor die. For example, a semiconductor die included in a packaged power semiconductor device may include a high power, high electron mobility transistor ("HEMT") amplifier designed to amplify RF signals.

[0111] A packaged power semiconductor device according to an embodiment of the present invention may be designed to block voltages of 500 volts or more, and the current may be rated at at least 25 amps. In some embodiments, a packaged power semiconductor device may be designed to block voltages of at least 750 volts, 1000 volts, or 1500 volts, and or the current may be rated at at least 50 amps, at least 75 amps, or at least 100 amps. In some embodiments, a packaged power semiconductor device according to an embodiment of the present invention may be designed to block voltages between 650 and 1700 volts, and the current may be rated between 25 and 100 amps.

[0112] Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the present invention are shown. However, it will be appreciated that the present invention may be implemented in many different forms and should not be construed as being limited to the above-described embodiments. Instead, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0113] It will be understood that, although the terms first, second, etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more associated listed items.

[0114] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise", "include", "have" and / or "contain" when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0115] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it may be directly on or directly extending to another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly on" another element or extending "directly" "on" another element, there are no intermediate elements. It should also be understood that when an element is referred to as being "attached," "connected," or "coupled" to another element, it may be directly attached, directly connected, or directly coupled to another element, or there may be intermediate elements. In contrast, when an element is referred to as being "directly attached," "directly connected," or "directly coupled" to another element, there are no intermediate elements.

[0116] Relative terms such as "below" or "above" or "up" or "lower" or "top" or "bottom" may be used herein to describe the relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It should be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0117] As used herein, the term "plurality" means "two or more".

[0118] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, the shapes of the drawings may vary, for example, due to manufacturing techniques and / or tolerances.

[0119] In the drawings and specification, typical embodiments of the invention have been disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A power semiconductor device, comprising: Package; a power semiconductor die, the power semiconductor die being located within the package; as well as A moisture barrier is located on the upper and side surfaces of the exterior of the package.

2. The power semiconductor device of claim 1, wherein the package comprises a plastic overmold.

3. The power semiconductor device of claim 2, wherein the moisture barrier is located directly on the plastic overmolding.

4. The power semiconductor device of claim 3, wherein the moisture barrier is a conformal moisture barrier that conforms to the plastic overmold.

5. The power semiconductor device of claim 4, wherein the moisture barrier is also located on at least a portion of a bottom portion of the exterior of the package.

6. The power semiconductor device of any one of claims 2-5, wherein the semiconductor die has a first terminal and a second terminal, and the package further comprises: a first lead electrically connected to the first terminal, the first lead extending out of the plastic overmold; as well as A second lead is electrically connected to the second terminal, the second lead extending out of the plastic overmold.

7. The power semiconductor device of claim 6, wherein the first lead includes a widened segment extending through an outer surface of the plastic overmold and a narrowed segment extending outwardly from the widened segment, and the moisture barrier covers at least a portion of the widened segment.

8. A power semiconductor device as claimed in claim 6 or 7, wherein the package further comprises a base, and the semiconductor die is mounted on an upper surface of the base.

9. The power semiconductor device of claim 8, wherein the base comprises a lead frame or a power substrate, and wherein the plastic overmold and the base together encapsulate the semiconductor die.

10. The power semiconductor device of claim 8 or 9, wherein the semiconductor die further comprises a third terminal located on a side of the semiconductor layer structure of the semiconductor die opposite to the first terminal and the second terminal, wherein the third terminal is electrically connected to the base.

11. The power semiconductor device of any one of claims 1-7, wherein the package comprises a base and a housing, and the moisture barrier completely covers a bottom surface of the base.

12. The power semiconductor device of any one of claims 1-11, wherein the moisture barrier comprises at least one of parylene, silicone, polyurethane or acrylic material.

13. The power semiconductor device of any one of claims 1-12, wherein the moisture barrier comprises a coating having a thickness of 1-10 microns.

14. A power semiconductor device as claimed in any one of claims 1 to 13, in combination with a printed circuit board, wherein the power semiconductor device is mounted on the printed circuit board and a portion of the moisture barrier is located between the package and the printed circuit board.

15. The power semiconductor device of claim 14, wherein the packaged electronic device is mounted on a metal pad on a printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad. 16 . The power semiconductor device according to claim 1 , wherein the moisture barrier is a first moisture barrier, the power semiconductor device further comprising a second moisture barrier covering an upper surface and side surfaces of the semiconductor die.

17. The power semiconductor device of claim 16, wherein the second moisture barrier also covers portions of the first lead and the second lead.

18. The power semiconductor device of any one of claims 1-17, wherein the semiconductor die is a vertical MOSFET or a Schottky diode based on silicon carbide.

19. The power semiconductor device of any of claims 1-18, wherein the semiconductor die is a first semiconductor die, the power semiconductor device further comprising a second semiconductor die within a package.

20. The power semiconductor device of claim 6, wherein the moisture barrier covers some but not all of the portions of the first lead and the second lead that are outside of the plastic overmold.

21. A power semiconductor device, comprising: case; a semiconductor die having a first terminal and a second terminal; as well as A moisture barrier is located on the upper surface and the side surfaces of the semiconductor die, the moisture barrier being positioned between the semiconductor die and the housing.

22. The power semiconductor device of claim 21, wherein the housing comprises a plastic overmold.

23. The power semiconductor device of claim 22, wherein the housing and the base constitute a package for the power semiconductor device, and the semiconductor die is mounted on an upper surface of the base.

24. The power semiconductor device of claim 23, wherein the base comprises a lead frame or a power substrate, and wherein the plastic overmold and the base together encapsulate the semiconductor die.

25. The power semiconductor device of claim 24, wherein the package further comprises: a first lead electrically connected to a first terminal; as well as a second lead electrically connected to the second terminal, The moisture barrier also covers portions of the first lead and the second lead that are within the plastic overmold.

26. A power semiconductor device as claimed in any one of claims 22 to 25, wherein the moisture barrier directly contacts both the semiconductor die and the plastic overmold.

27. A power semiconductor device as claimed in any one of claims 21 to 26, wherein the moisture barrier is a conformal moisture barrier that conforms to the semiconductor die.

28. A power semiconductor device as claimed in any one of claims 21 to 27, wherein the moisture barrier and the housing are different materials.

29. The power semiconductor device of claim 24, wherein the moisture barrier is a second moisture barrier, the power semiconductor device further comprising a first moisture barrier on an exterior of the plastic overmold.

30. The power semiconductor device of claim 29, wherein the plastic overmold is on a top surface and side surfaces of the base, and wherein at least a portion of a bottom surface of the base is free of the plastic overmold.

31. The power semiconductor device of claim 29, wherein the first moisture barrier covers a bottom surface of the base.

32. The power semiconductor device of any of claims 21-31, wherein the moisture barrier comprises at least one of parylene, silicone, polyurethane, or acrylic material.

33. A power semiconductor device as claimed in any one of claims 21 to 32, wherein the moisture barrier comprises a coating having a thickness of 1 to 10 microns.

34. A power semiconductor device as claimed in any one of claims 21 to 33 in combination with a printed circuit board, wherein the power semiconductor device is mounted on the printed circuit board and a portion of the moisture barrier is located between the plastic overmoulding and the printed circuit board.

35. The power semiconductor device of claim 34, wherein the power semiconductor device is mounted on a printed circuit board and includes terminals mounted on a heat sink, and the moisture barrier electrically isolates the semiconductor die from the heat sink.

36. A method of manufacturing, the method comprising: packaging a semiconductor die having a first terminal and a second terminal in a package including a base and a housing to provide a preliminary power semiconductor device; as well as A moisture barrier is formed on the preliminary power semiconductor device to form a power semiconductor device configured to be mounted on a printed circuit board.

37. The method of claim 36, wherein the housing comprises a plastic overmold.

38. The method of claim 37, wherein the moisture barrier is located directly on the exterior of the plastic overmoulding.

39. A method as claimed in claim 37 or 38, wherein the moisture barrier is a conformal moisture barrier that conforms to the exterior of the plastic overmould.

40. The method of claim 39, wherein the package further comprises a first lead and a second lead, the method further comprising: electrically connecting a first lead to the first terminal, the first lead extending out of the plastic overmold; as well as A second lead is electrically connected to the second terminal, the second lead extending out of the plastic overmold.

41. The method of claim 40, wherein the first lead includes a widened segment extending through the outer surface of the plastic overmold and a narrowed segment extending outwardly from the widened segment, and the moisture barrier covers at least a portion of the widened segment.

42. The method of any of claims 37-41, wherein the base comprises a lead frame or a power substrate, and wherein the plastic overmold and the base together encapsulate the semiconductor die.

43. A method as claimed in any one of claims 36 to 42, wherein the moisture barrier is formed to completely cover the bottom surface of the package.

44. The method of any of claims 36-43, wherein forming the moisture barrier comprises forming the moisture barrier via chemical vapor deposition.

45. The method of any one of claims 36-43, wherein forming the moisture barrier comprises forming the moisture barrier by immersing the preliminary power semiconductor device in a solution of a moisture barrier material.

46. ​​The method of any of claims 36-43, wherein forming the moisture barrier comprises spraying a moisture barrier material onto the preliminary power semiconductor device.

47. The method of any one of claims 37-46, further comprising: forming the moisture barrier at least 120 0 C to remove moisture from the plastic overmold.

48. The method of any one of claims 37-47, wherein the moisture barrier is formed within two hours after the overmold plastic is formed or after a baking process applied to the overmold plastic to remove moisture therefrom is completed.

49. The method of any of claims 36-48, wherein the moisture barrier comprises at least one of parylene, silicone, polyurethane, or acrylic material.

50. The method of any one of claims 36-49, wherein the moisture barrier comprises a coating having a thickness of 1-10 microns.

51. The method of any of claims 36-50, further comprising mounting the power semiconductor device on a printed circuit board such that a portion of the moisture barrier is located between the package and the printed circuit board.

52. The method of claim 51, wherein the power semiconductor device is mounted on a metal pad on a printed circuit board, and the moisture barrier electrically insulates the semiconductor die from the metal pad.

53. A method as described in any one of claims 36-52, wherein the moisture barrier is a first moisture barrier, the method further comprising forming a second moisture barrier, the second moisture barrier covering the upper surface and side surfaces of the semiconductor die and portions of the first lead and the second lead, the second moisture barrier being positioned between the semiconductor die and the second portion of the package.

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