Dead time adjusted pulse width modulator

Abstract

A pulse width modulator circuit (100) is provided with a pulse width modulator circuit (100) for providing a first pulse width modulated signal and a second pulse width modulated signal (PWMTSD); a circuit system (126) of a pulse width modulated signal (PWBSD) having a dead time period between the first pulse width modulated signal and the second pulse width modulated signal; an input (e.g. To an ADC 120) for receiving a signal (iLsense) representative of a current in a load (106) adapted to be driven in response to the first pulse width modulated signal and the second pulse width modulated signal; and circuitry (114) coupled to the input for adjusting the dead time period in response to the signal representative of the current.

Description

Background Art

[0001] The described examples relate to electronic circuits and, more particularly, to pulse width modulators with dead time adjustment.

[0002] Pulse width modulation (PWM) is used in various categories of electronic circuits and devices, including, for example, voltage converters, such as voltage source inverters (VSIs). A VSI converts a direct current (DC) voltage into an alternating current (AC) waveform. In a PWM VSI, a single-phase or three-phase AC waveform is created by switching a DC signal on and off to create a PWM output at a frequency faster than the desired output AC voltage, and the PWM output is filtered to approximate and produce the desired AC voltage. The duty cycle of the PWM output is adjusted to vary the magnitude of the output AC voltage. In addition, a single-phase AC voltage is described above, and in some systems, multiple AC voltages may also be generated. For example, in a three-phase system, three different AC voltages are generated, each of which is 120 degrees out of phase with respect to the other two phases, in which case each of the above may be represented in triplicate to produce each of the three corresponding AC signals. In any case, in a typical single-phase circuit or in each portion (branch) of a multi-phase circuit, a typical rail-to-rail circuit path in a PWM switch configuration includes two switches, a first switch connected to a relatively high voltage and a second switch connected to a relatively low voltage, the switches being enabled in a complementary manner, i.e., only the first switch or the second switch is enabled (turned on and conducting) at a time. Efforts are usually made (or required) to ensure that the first switch and the second switch cannot conduct at the same time, a situation sometimes referred to as shoot-through, which would short one rail to the other. To prevent this, a so-called dead time (or blanking) time is inserted between the period when one of the two switches is enabled and the period when the other of the two switches is enabled, so that during the dead time, both switches are deactivated.

[0003] While dead time insertion reduces the risk of shoot-through, it also has certain disadvantages. For example, the dead time duration may be calculated based on certain circuit expectations, and thus a conservatively long dead time may be included, which may bring commensurate disadvantages from the duration. In particular, dead time insertion typically introduces waveform distortion and fundamental voltage gain or loss in the VSI, and thus extended dead time may increase these effects. Certain approaches have been taken to adjust errors or reduce adverse effects caused by dead time insertion, for example, as shown in U.S. Patent No. 10,547,236, entitled “Dead Band Compensation,” issued on January 28, 2020, which is jointly owned with the present application and is hereby incorporated by reference herein. In the use of additional external sensors associated with evaluating and adjusting dead time insertion, some other sensors may also increase circuit size and corresponding cost.

[0004] Examples are provided herein that may improve upon various of the above considerations as well as other concepts, as further detailed below. Summary of the invention

[0005] In one example, there is a pulse width modulator circuit having a circuit system for providing a first pulse width modulated signal and a second pulse width modulated signal, wherein the first pulse width modulated signal and the second pulse width modulated signal have a dead time period therebetween; an input terminal for receiving a signal representing a current in a load, the load being adapted to be driven in response to the first pulse width modulated signal and the second pulse width modulated signal; and a circuit system coupled to the input terminal for adjusting the dead time period in response to the signal representing the current.

[0006] Other aspects are disclosed and claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Indicates the VSI instance.

[0008] Figure 2A A timing signal diagram of the PWM operation of the VSI during the positive half period is depicted.

[0009] Figure 2B A timing signal diagram of the PWM operation of the VSI during the negative half period is depicted.

[0010] Figure 3A A timing signal diagram showing additional PWM operation of the VSI is depicted.

[0011] Figure 3B Draws from Figure 3A The time period during which the positive half cycle is extracted.

[0012] Figure 3C Draws from Figure 3A The time period during which the negative half cycle is extracted.

[0013] Figure 4 For operation Figure 1 Flowchart of the VSI PWM method.

[0014] Figure 5 An alternative example VSI is depicted. DETAILED DESCRIPTION

[0015] Figure 1 1 is a voltage source inverter (VSI) 100 as an example of a system implementing PWM dead-time adjustment. VSI 100 may be implemented as one or more integrated circuit (IC) devices and have various functional / structural boundaries. Figure 1In the embodiment of the present invention, the VSI 100 includes a pulse width modulator 102 and an inverter 104 switched by the pulse width modulator 102, and the pulse width modulator and the inverter together drive a load 106. For example, the load 106 may include an inductor 106_L and a resistor 106_R connected in series. In some other examples, the load may be a motor, such as an induction motor, a permanent magnet synchronous motor, and various other types.

[0016] The pulse width modulator 102 includes a controller 108 and a first switch driver 110 and a second switch driver 112. The controller 108 may be implemented by a multi-bit microcontroller, such as available from Texas Instruments Incorporated in various forms (e.g., C2000). The controller 108 may include various internal functional blocks that are typically integrated and assembled into a single IC package. For example, Figure 1The controller 108 is shown to include a central processing unit (CPU) 114, an input / output (I / O) interface 116, a memory 118, which may include various forms of storage, including to provide a portion of a register file 118_REG, one or more levels (e.g., cache) of data / program storage, and an analog-to-digital converter (ADC) 120. Further in conjunction with PWM functionality, the controller 108 also includes a counter 122, which is bidirectionally coupled to the CPU 114; a PWM peripheral 124, which is coupled to receive signaling from the CPU 114; and a deadband generator 126, which is coupled to receive a control signal PWM_C from the PWM peripheral 124, and outputs a PWM_T_SD signal to the first switch driver 110 and a PWM_B_SD signal to the second switch driver 112 ("T" and "B" are used to indicate the top and bottom of the general switch architecture corresponding to the inverter 104, respectively). Some or all of these controller blocks may be coupled to communicate with a system bus 128, and various of these blocks may communicate with each other over the system bus or externally, for example, via an I / O interface 116. The CPU 114 generally includes structure and functionality commensurate with the computational requirements of the application for which the controller 108 is designed and specified. With respect to PWM functionality, general programming is stored in a medium that is readable by the CPU 114, such as the memory 118, and this programming, when executed by the CPU 114, generates PWM-implementing control signals. For example, the CPU 114 controls the PWM peripheral 124 to output a pulse width modulated signal PWM_C. In response to PWM_C and substantially synchronous with PWM_C, the deadband generator 126 outputs substantially complementary signals PWM_T_SD and PWM_B_SD to the first switch driver 110 and the second switch driver 112, respectively, but in addition to being substantially synchronous with PWM_C, when either of PWM_T_SD and PWM_B_SD is high, additional dead time is inserted between alternating times, thereby ensuring that there is a period (dead time) when both of these signals are low. The dead time inserted by the deadband generator 126 can be programmed by the CPU 114 and can be determined using various methods. For example, the CPU 114 can write values ​​to one or more registers in the deadband generator 126, according to which the deadband generator 126 can support independent values ​​of either the rising edge delay and the falling edge delay in the signal transitions of PWM_T_SD and PWM_B_SD relative to PWM_C, so as to adjust both the overall total dead time and the timing of the dead time before or after the signal transitions. The width of the pulse to be generated is calculated by the CPU 114 based on a particular method and written to the PWM peripheral 124. In some examples, the method includes field oriented motor control, and in other examples, the method may refer to current or voltage mode control.Each of the first switch driver 110 and the second switch driver 112 includes circuitry that is operable to receive corresponding signals in PWM_T_SD and PWM_B_SD and convert the signals into sufficiently strong and corresponding signals PWM_T and PWM_B to operate the switching operation described in detail below. Therefore, the first switch driver 110 and the second switch driver 112 may include one or more configured power transistors (e.g., metal oxide field effect transistors) that are configured to be triggered according to the corresponding digital states of PWM_T_SD and PWM_B_SD, such as so that generally, although modified as described below, when PWM_T_SD is asserted (e.g., active high), the first switch driver 110 asserts the corresponding drive control signal PWM_T, and when PWM_B_SD is asserted (e.g., active high), the second switch driver 112 asserts the corresponding drive control signal PWM_B. Therefore, generally, the controller 108 can implement PWM operation by adjusting the timing and duration of each period in which it asserts PWM_T_SD and PWM_B_SD. Furthermore, these signals are controlled to never be on at the same time, and the period during which these signals are both at logic zero is referred to as dead time, resulting in the terminology of dead band generator 126. The duration of this dead time is programmable and is calculated based on the characteristics of inverter 104. Controller 108 may generate PWM signals PWM_T_SD and PWM_B_SD using a modulation technique such as vector control or sine-triangle control. In some examples, dead band generator 126 may be part of PWM peripheral 124.

[0017] The inverter 104 includes a coupling and a circuit system for adapting the received drive control signals PWM_T and PWM_B to convert a DC voltage difference into an approximate analog output voltage Vout, which is coupled to a load 106. In the illustrated example, the DC voltage difference is between a relatively high voltage shown as Vdc and a relatively low voltage shown as ground. More specifically, a first node 130 is connected to receive Vdc, and a second node 132 is connected to ground. A third node 134 provides a first output voltage signal, and a fourth node 136 provides a second output voltage signal, wherein Vout is the difference between the third node 134 and the fourth node 136, and the load 106 is coupled between the third node 134 and the fourth node 136 (and thereby receives Vout). A first capacitor 138 has a first terminal connected to the first node 130 and a second terminal connected to the fourth node 136, and thereby provides a voltage of +Vdc / 2 during switching. The second capacitor 140 has a first terminal connected to the fourth node 136 and a second terminal connected to the second node 132 and thereby provides a voltage of -Vdc / 2 during switching. p142 has a first terminal connected to the first node 130 and a second terminal connected to the third node 134, wherein the switch S p 142 is controlled to be opened and closed by PWM_T in response to PWM_T_SD. n 144 has a first terminal connected to the third node 134 and a second terminal connected to the second node 132, wherein the switch S n 144 is controlled to open and close by PWM_B in response to PWM_B_SD. p 142 and switch S n Each of capacitors 138 and 144 may be implemented using a silicon transistor, such as a metal oxide field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) or a silicon carbide MOSFET or gallium nitrate (GaN), with the corresponding control signal PWM_T or PWM_B connected to its corresponding gate. In certain configurations of inverter 104, capacitors 138 and 140 may be implemented using a switch similar to switch S p 142 and switch S n 144 power switch instead. Positive side diode D p 146 has an anode connected to the third node 134 and a cathode connected to the first node 130. Negative side diode D n 148 has an anode connected to the second node 132 and a cathode connected to the third node 134. Switch S p 142 and S n 144 and diode D p 146 and D n The combination of the third node 134 and the load 106 is called a half-bridge circuit. The current sensor 150 is connected between the third node 134 and the load 106. The current sensor 150 is used to sense the current i passing through the load 106. L , as described below, and in response, the current sensor 150 outputs a corresponding signal i L In some examples, a current sensor 150 may be connected to node 134, and in one example to node 136. In some other inverter configurations, such as a three-phase inverter, current sensors may be connected to all output nodes.

[0018] The load 106 may take or include various forms of electrical drives, wherein the VSI 100 drives the load with Vout. For example, the load 106 may be a motor driven by a single-phase voltage, or in an alternative example, the half-bridge circuit may be tripled and provide three different continuous (e.g., sinusoidal) waveforms under appropriate control, each waveform being 120 degrees out of phase with respect to the other two waveforms driving the three-phase motor. Specifically, when Vout varies in a substantially sinusoidal curve, the fundamental current i Lis generated via the load 106 to have a waveform having substantially the same shape (eg, sinusoidal), but i L Vout may be phase shifted from Vout depending on the load characteristics, which are a combination of inductance, resistance, and capacitance, to name a few. L >0 is considered a positive half cycle, and i L <0 is considered a negative half cycle. When the VSI 100 drives a motor as the load 106, the current sensor 150 is used to detect the current through the motor in order to provide motor control, such as field oriented control, or for current limiting / protection purposes. Such current sensors 150 can use the load current i L The generated magnetic field is used as a parameter to measure i L and generates i in response L Examples of this include Hall or fluxgate current sensors. Alternatively, an inline shunt resistor can be used with an amplifier to measure the motor current i L The amplifier may or may not be isolated. In some instances, the amplifier also includes a delta-sigma modulator. In all cases, in VSI 100, the current level sensed by current sensor 150 is shown as i L _sense, which indicates that a portion of the i through the load 106 L The amount of i L _sense is coupled back to the controller 108, for example, to the controller's ADC 120. Thus, and as described in detail below, this coupling provides feedback to the controller 108 (e.g., via its ADC 120) by which the controller 108 can measure the current i in the load 106. L The magnitude, direction and slope of PWM_T_SD and PWM_B_SD are used together with PWM_T_SD and PWM_B_SD to appropriately adjust the dead time inserted into the PWM signal driving the load 106.

[0019] Figure 2A A timing signal diagram 200P is shown, which shows the VSI 100 at i L During the positive half period, i.e. L >0. Timing signal diagram 200P includes three signals, each having a horizontal time axis (e.g., ms) and a vertical voltage axis (e.g., volts, not to scale). First signal PWM_T_SD 202 represents the output of first switch driver 110, second signal PWM_B_SD 204 represents the output of second switch driver 112, and third signal 206 represents Vout, the output from inverter 104 and applied across load 106. Typically, PWM_T_SD and PWM_B_SD (both in Figure 1The transition in PWM_T and PWM_B (shown in FIG. 2 ) causes a corresponding response in Vout, albeit delayed by some time due to the propagation delay of the switch driver and the delay associated with the power switch. In addition, as shown below, during the entire positive half period, switch 142S p and S n operation and through the negative side diode D n The alternative current path of 148 provides the same current path, which follows Figure 1 Conventional positive polarity.

[0020] exist Figure 2A Before t1 in PWM_B is high and closes (eg, turns on, for a transistor) the negative side switch S n 144, current i L Flows through the negative switch S n 144 to the load 106, and Vout is -Vdc / 2. At t1, PWM_B transitions from high to low, thereby opening (eg, turning off, for a transistor) the negative side switch S n 144. Due to the inductive properties of the load 106 (eg, the inductor 106_L), the instantaneous current continues to flow in the same direction, now no longer through the negative side switch S n 144 but instead switched to the negative side diode D n 148 and continue to flow in the positive direction, still keeping Vout at -Vdc / 2. Similarly from t1 to t2, the negative side switch S n 144 and positive side switch S p The switches 142 are both open (in the off state), providing a dead time DT1, and Vout continues to be at -Vdc / 2. At t2, PWM_T transitions from low to high, closing (turning on) the positive side switch S p 142. This causes Vout to switch from -Vdc / 2 to +Vdc / 2 and current to flow from Vdc through the positive side switch S p 142 to the load 106. At t3, PWM_T changes from high to low, turning off the positive side switch S p 142, and the negative side switch S n 144 remains off, and the dead time DT2 begins, and here the current direction continues to flow into the inductive load 106, from the positive side switch S p 142 is transferred to the negative side diode D n 148, and at t3, Vout transitions from +Vdc / 2 to -Vdc / 2, and continues at this value until t6. In particular, at t4, PWM_B transitions to a high value (as before t1), closing the negative side switch S n144, so current flows through the switch to the load 106. At t5, PWM_B transitions from high to low, starting the next dead time (not explicitly labeled), and the previous process repeats as described above.

[0021] According to the foregoing, during the positive half cycle, the controller 108 outputs the signals PWM_T_SD and PWM_B_SD and the corresponding inputs PWM_T and PWM_B to the inverter 104 so that only one of PWM_T_SD and PWM_B_SD is asserted at a time (high active). In addition, Vout switches between the rails with a duty cycle greater than 50% to keep the average Vout positive, and i L Continue to flow in the same direction (according to Figure 1 In particular, any inductive portion of load 106 (including, contemplatedly, where load 106 is a motor having a conductive path including an inductor) resists sudden changes in current due to its stored magnetic energy. Thus, during the positive half-cycle and when PWM_T is de-asserted (and, therefore, the positive side switch S p 142 disconnected), i L Continues to flow through the negative side diode D n 148. Basically, in the positive half cycle, Vout is aligned with the pulse width of PWM_T, and when PWM_T is asserted, Vout is high (+Vdc / 2). The dead time pattern is repeated for each PWM period, e.g., t5, t6 in FIG. 2 correspond to t1, t2 and t3, t4 correspond to t7, t8, etc. In all events, the nominal minimum period of the dead time (i.e., when both PWM_T and PWM_B are deasserted (and the positive side switch S p 136 and negative side switch S n 138 is disconnected)) to ensure safe operation without shoot-through, the operating properties including, for example, propagation delay through the first switch driver 110 and the second switch driver 112 and the implementation of the switch S p 136 and S n 138 transistor (MOSFET, IGBT) delay and rise / fall time. However, as shown below, further examples are provided to respond to the received i through the load 106 L The nominal dead time is adaptively and advantageously adjusted based on sensing related feedback.

[0022] Figure 2B A timing signal diagram 200N is shown, which shows the VSI 100 at i L During the negative half period, i.e. L< 0 when PWM operation. The timing signal diagram 200N includes Figure 2A The same three signals, but Figure 2B Each of the corresponding negative i L Typically, the first two signals 202 and 204 are Figure 2A Vout is unchanged, while the third signal 206, again representing Vout, is different due to effects occurring in the negative half period, as described in further detail below.

[0023] exist Figure 2B Before t11, PWM_B is high and the load current i L flows through the load to the negative side switch S n 144, and Vout is -Vdc / 2. At t11, PWM_B changes from high to low, turning off the negative side switch S n 144. On the negative side switch S n The current flowing in 144 is transferred to the positive side diode D due to the inductive nature of the load 106. p 146 and continues to flow in the negative direction, causing Vout to transition from -Vdc / 2 to +Vdc / 2. Between t11 and t12, the positive side switch S p 142 and negative side switch S n 144 are both in the off state and provide a dead time DT3. Also between t11 and t12, Vout continues to be at +Vdc / 2. At t12, PWM_T transitions from low to high, turning on the positive side switch S p 142. This causes current to flow from the positive side diode D p 146 is switched to the positive side switch S p 142, and Vout continues to be at +Vdc / 2. At t13, PWM_T transitions from high to low, turning off the positive side switch S p 142, and the current iL flows from the positive side switch S p 142 is transferred to the positive side diode D p 146. Vout continues to be at +Vdc / 2 until t14, where PWM_B is made high. Between t13 and t14, the positive side switch S p 142 and negative side switch S n 144 are all turned off, thereby providing a dead time DT4.

[0024] According to the foregoing, during the negative half cycle, the controller 108 again outputs the signals PWM_T_SD and PWM_B_SD and the corresponding inputs PWM_T and PWM_B to the inverter 104 so that only one of PWM_T_SD and PWM_B_SD is asserted at a time (high active). In addition, Vout switches between the rails with a duty cycle of less than 50% to keep the average Vout negative, and i L Continue to flow in the same direction (according to Figure 1 Likewise, any inductive portion of load 106 (including, contemplatedly, where load 106 is a motor having a conductive path including an inductor) resists sudden changes in current due to its stored magnetic energy. Thus, during the negative half-cycle and when PWM_B is de-asserted (and, therefore, the negative side switch S is switched on) during each of the dead times DT3 or DT4, n 144 disconnected), i L Continues to flow through the positive side diode D p 146. Basically, in the negative half cycle, Vout is aligned with the pulse width of PWM_B, and when PWM_B is de-asserted, Vout is high (+Vdc / 2). The dead time pattern is repeated for each PWM period. For example, Figure 2B t15, t16 in the figure correspond to t11, t12 and t17, t18 correspond to t13, t14, etc. In all cases, the nominal minimum period of the dead time (i.e., when both PWM_T and PWM_B are deasserted (and the positive side switch S p 136 and negative side switch S n 138 is disconnected)) to ensure safe operation without shoot-through, the operating properties including, for example, propagation delay through the first switch driver 110 and the second switch driver 112 and the implementation of the positive side switch S p 136 and negative side switch S n 138 transistor (MOSFET, IGBT) delay and rise / fall time. However, as shown below, further examples are provided to respond to the received i through the load 106 L The nominal dead time is adaptively and advantageously adjusted based on sensing related feedback.

[0025] Figure 3A A timing signal diagram 300 is shown that illustrates additional PWM operation of the VSI 100. Figure 3A , the first dotted ellipse indicates the first time excerpt portion 300_1, which is Figure 3B Further details are given in Figure 3A In FIG. 1 , the second dotted ellipse indicates the second time excerpt portion 300_2, which is Figure 3C Typically, Figure 3A In FIG. 1 , timing signal diagram 300 (and excerpts 300_1 and 300_2) plots time (e.g., ms) along the horizontal axis, voltage (e.g., volts) on the left vertical axis, and current (e.g., amperes) on the right vertical axis. In addition, three signals are shown, all of which are from earlier diagrams and referenced in Figures 3A to 3C Legend, including PWM_C, Vout and i L , where the left vertical volt axis is about PWM_C and Vout, and the right vertical ampere axis is about i L .generally, Figure 3A I L of approximately two complete cycles, and Figure 3B Draws the picture when i L >0 during exactly one period of PWM_C (i.e., during i L The part i that occurs during the positive half cycle L ,and Figure 3C Draws the picture when i L <0 during exactly one period of PWM_C (i.e., during i L The part i that occurs during the negative half cycle L .

[0026] Figures 3A to 3C Each of the above is further described in detail with respect to the adaptive dead time adjustment of the VSI 100. In part, upon recognizing that L The change relationship (such as Figure 3A The VSI 100 operates in a case where the VSI 100 is not only piecewise linear in its approximation to a continuous waveform, but also has further transitions associated with certain transitions of PWM_C and Vout. In general, Figure 3B and 3C The enlarged diagrams of FIG. 1 and FIG. 2 each illustrate that during a period of time, when PWM_C is asserted and Vout is relatively high, i L rises, and when PWM_C is deasserted and Vout is relatively low, i L However, as detailed below, Figure 3B Further information on the relationship between the rising transition of PWM_C and the rise of Vout Figure 2A The dead time DT1 during the positive half cycle i L The behavior is described in detail, Figure 3C Further information on the relationship between the falling transition of PWM_C and the falling transition of Vout Figure 2B The dead time DT4 during the negative half cycle i L Describe the behavior in detail.

[0027] Figure 3B Drawing from Figure 3A The first signal excerpt 300_1 is enlarged in the horizontal time scale to further illustrate the i L i during part of the positive half cycle L Behavior. Figure 3B In the Figure 2A The dead time DT1 occurs between the rising transition of PWM_C and the rising transition of Vout. However, during the dead time DT1, i L The immediately preceding decreasing behavior continues until the end of DT1, that is, until Vout changes from low to high, at which time, i L No longer decreases, i.e., its trajectory value flattens or begins to increase. Therefore, and as shown and described in detail below, the VSI 100 structure provides monitoring i L And this trajectory change relative to the trajectory at the time of the immediately preceding rise of PWM_C is detected, thereby respectively detecting the functionality of the end and start of the dead time DT1.

[0028] Figure 3C Drawing from Figure 3A The second signal excerpt 300_2 has the horizontal time scale enlarged to further illustrate the i L During the negative half cycle part of i L Behavior. Figure 3C In the Figure 2B The dead time DT4 occurs between the falling transition of PWM_C and the falling transition of Vout. However, during the dead time DT4, i L The immediately preceding increase behavior continues until the end of DT4, that is, until Vout changes from high to low, at which time, i L is no longer increasing, i.e., its trajectory value flattens or begins to decrease. Therefore, and as shown and described in detail below, the VSI 100 structure provides and monitors i L And the functionality of detecting such trajectory change relative to the immediately preceding fall in PWM_C, thereby detecting the end and start of the dead time DT4, respectively.

[0029] Figure 4 For operation Figure 1 1. Flowchart of PWM method 400 for VSI 100. In general, PWM method 400 may be implemented by a program executed by controller 108, which in response outputs PWM_T and PWM_B to the half-bridge circuit of inverter 104 and responds to i from inverter 104. L_sense and adaptively adjust the dead time included in the duration of each PWM_T and PWM_B pulse to improve the performance of the VSI 100. The flowchart is used to generally depict certain steps, but is not intended to be limiting, because the steps may overlap rather than occur purely sequentially, or the steps may be added, removed, rearranged, or the changes in the process (or state) may be implemented in various forms. In the illustration provided, the PWM method 400 begins at step 402, where the controller 108 operates to output PWM_C, so that generally PWM_C is transformed as described above, outputting Vout=+Vdc / 2 for a relatively long period of time at a duty cycle greater than 50%, thereby causing i L positive half cycle, and when the duty cycle is less than 50%, the output Vout = -Vdc / 2 lasts for a relatively long period of time, causing i L Negative half cycle. Figure 1 In the example of , step 402 may be implemented by the CPU 114 writing the desired pulse width to be generated by the PWM peripheral 124 .

[0030] Step 404 evaluates the PWM_C duty cycle as a condition for the next action. Step 404 may operate simultaneously with step 402, such that when step 402 adjusts and outputs PWM_C pulses, step 404 checks the duty cycle on such pulses. In particular, step 404 determines whether the PWM_C duty cycle is within a range between X percent and Y percent, for example, where X=40% and Y=60%. Return to Figure 3A It should be noted that, for example, when the duty cycle falls within this range, 40% < duty cycle < 60%, i L Relatively close to its zero crossing point, that is, i L =0A, which occurs between its positive and negative half cycles. Therefore, step 404 conditionally checks to determine whether PWM_C represents a duty cycle such that i L Relatively close to its zero crossing, where the relative measurement is defined by the values ​​of X and Y, where the range between the values ​​can be expanded or reduced as desired. If the PWM_C duty cycle is outside the indicated range, the method 400 returns to step 402 (and continues to be monitored by step 404), however, if the PWM_C duty cycle is within the indicated range, the method continues to step 406. The indicated range varies with the performance of the sensor, ADC, and slope detector in accurately detecting the slope change of the load current. Subsequently, the range can be expanded or shortened to facilitate the detection of the slope change of the load current.

[0031] Step 406 Evaluation i L is in its positive half cycle (e.g. Figure 3B ) or its negative half cycle (e.g., Figure 3C), and as a response indicates the method flow. Therefore, if i L In its positive half cycle, such as from Figure 3A and Figure 3B As shown in the first time excerpt portion 300_1, the method 400 proceeds to step 408, and if i L In its negative half cycle, such as from Figure 3A and Figure 3C As shown in the second time excerpt portion 300_2, the method 400 proceeds to step 410.

[0032] Step 408 takes two actions at the next PWM_C rising edge. As a first action, step 408, for example, Figure 1 , where the incremented count will represent the time measurement. For example, and returning to Figure 3B As shown in FIG. 4 , during the positive half cycle, in step 408, the CPU 114 starts the counter at t1 at the rising edge of PWM_C. As a second action, step 408 also starts counting i L Sampling, for example Figure 1 In the ADC 120, the L The number of samples and the sampling interval are configurable, and an average value between samples may also be included to improve the current sensing accuracy. Next, the method 400 proceeds from step 408 to step 412.

[0033] Step 412 is based on i L _sense, and as long as those ADC sample values ​​continue to decrease, the conditional step loops by returning to step 412. Figure 3B In the example shown in the figure, step 408 has already started at t1. L In the case of ADC samples of _sense, it should be noted that in the case of step 412 applied to those samples, then starting at t1 i L _sense continues to decrease until t2. Therefore, for this duration between t1 and t2, as the periodic ADC sampling indicates i L _sense continues to decrease, step 412 will continue to return to step 412. However, at t2, the successive ADC samples will be L_sense will flatten out or one sample value will increase more than the inversion of the immediately preceding sample value to indicate a change in trajectory. Step 412 detects this change in condition because the samples are no longer decreasing, but are constant or increasing. It should also be noted that this change in condition occurs at the end of DT1, that is, the detection of this change is the detection of the end of the dead time. Once this condition is detected, the CPU 114 stops the counter 122, and step 412 directs the method 400 to step 414.

[0034] After the method 400 has detected the end of the dead time following the rising transition of PWM_C, step 414 is reached. When step 414 is reached, the method 400 will also accumulate a time measurement of the actual duration of the dead time in the form of a count in the counter 122. In this regard, it should be noted that the dead time is generally set to a maximum value, i.e., a maximum value that is to be met under an expected set of conditions and is long enough to ensure the goal of avoiding shoot-through. The maximum value is commonly established based on various considerations, such as delays of the switching devices through the PWM architecture, which in the VSI 100 includes switches (e.g., switches S in the first switch driver 110 and the second switch driver 112 and in the inverter 104). p and S n ). In addition, the maximum dead time is usually extended by a safety margin to account for the unpredictability or unknown nature of certain factors, such as due to manufacturing, parameter and environmental variations from device to device, etc. Although the dead time provides a value to avoid shoot-through, there is a trade-off, namely, during the positive half cycle, e.g. Figure 3B As shown in L The signal quality degradation during the dead time is greater than the actual dead time. However, in the VSI 100, and having reached step 414, there is a time measurement of the actual dead time, rather than the nominal dead time, as detected by step 412. LThe change of the trajectory and the accumulated count of the dead time. Therefore, when the method 400 reaches step 414, the measurement of the actual dead time has been accumulated compared to the designed maximum dead time. In response, step 414 can compensate for excessive voltage loss. For example, if the actual dead time is less than the maximum dead time configured in the dead band generator 126, then its value can be reprogrammed to reflect the actual measured dead time. In addition, the CPU 114 adds the measured dead time to the calculated pulse width PWM_C to account for the voltage loss. This results in a better quality output voltage Vout from the inverter 104. Therefore, in the absence of other changes, the subsequent positive half-cycle assertion of PWM_C is controlled in response to the measured actual dead time. Next, the method 400 continues to step 416.

[0035] Step 416 represents a potential return to step 402 to repeat the previous steps. For example, in step 416, the counter 122 can be reset and the process can return to step 402, such as Figure 4 In the example, the number of steps repeated may be fixed or adjustable, and in some examples, each i L In this way, the method 400 is repeated only once in most i L No processing or other resources need to be occupied during the cycle, but evaluating once per cycle may be sufficient to improve operation, voltage consumption, and signal distortion. In addition, since these steps only occur (or repeat) when PWM_C is within the duty cycle range set by X and Y (e.g., 40% to 60%), it should be noted that within such a range, the detection i L The sensitivity of trajectory changes is enhanced because any such changes have a larger magnitude in the range, such as from Figure 3A i L The discontinuity shown in the figure is visible because i L In this range (and close to the zero crossing).

[0036] In the foregoing description of method 400 after a positive half cycle is detected at step 406, recall that method 400 proceeds to step 410 after a negative half cycle is detected at step 406. Step 410 and subsequent steps 418 and 420 are comparable in some respects to steps 408, 412, and 414, but L The directionality of the detection trajectory is reversed, as is the count correction in step 420.

[0037] Step 410 takes two actions at the next PWM_C falling edge. As a first action, step 410 starts counting, thereby accumulating a time measurement (again, for example, using Figure 1 counter 122), and as a second action, the step starts toL Sampling (again, for example, by ADC 120) L _sense). These actions can be, for example, relative to Figure 3C It is taken during the negative half cycle, and at t13, with the falling edge of PWM_C, counting and sampling begins.

[0038] Then, as long as I L _sense ADC samples continue to increase, step 418 then conditionally loops by returning to step 418. Again, by Figure 3C In the example, step 410 has already started at t13. L In the case of ADC samples of _sense, it should be noted that in the case of step 418 applied to those samples, then starting at t13, i L _sense continues to increase until t14. Therefore, for this duration between t13 and t14, step 418 will continue to loop because the periodic ADC sampling indicates a continued increase in sample value. However, at t14, the consecutive ADC samples will be at the same rate as i L _sense will flatten out or one sample value will decrease more than the inversion of the immediately preceding sample value to indicate a change in trajectory. This change in condition is detected by step 418 because the samples are no longer increasing, but instead are constant or decreasing, which occurs at the end of DT4, thereby detecting the end of the dead time. Once this condition is detected, the CPU 114 stops the counter 122, and step 418 directs the method 400 to step 420.

[0039] After the method 400 has detected the end of the dead time following the falling transition of PWM_C, step 420 is reached, and when step 420 is reached, the method 400 will also have accumulated a time measurement of the actual duration of the dead time in the form of counts in counter 118_CTR. Here again, the accumulated dead time measurement is an actual dead time measurement compared to the nominal value, and similar to step 414 above, can be used to compensate for undesirable voltage distortion and gain that may be caused by an overly conservative or device-independent nominal dead time imposition. In fact, in the case of a negative half cycle, Figure 3C Vout is shown to remain high during the dead time, thereby extending the voltage pulse beyond the ideal voltage pulse in order to smoothly approximate the desired i Lsine wave. Thus, step 420 may compensate for the extended voltage period (in effect, voltage gain), for example, by subtracting from the PWM register count. In response, step 420 may compensate for the excessive voltage gain, for example, if the actual dead time is less than the maximum dead time configured in the dead band generator 126, then its value may be reprogrammed to reflect the actual measured dead time. In addition, the CPU 114 subtracts the calculated pulse width PWM_C from the measured dead time to calculate the voltage gain. This results in a better quality output voltage Vout from the inverter 104. Thus, in the absence of other changes, the subsequent negative half cycle assertion of PWM_C is controlled in response to the reduced count. Next, the method 400 continues to step 416, which operates as described earlier.

[0040] Figure 5 An alternative example VSI 100A is shown, which is Figure 1 The VSI 100 is identical except that Figure 1 The controller 108 is shown as an alternative example controller 108A. The controller 108A includes an additional slope detector 502, which is coupled to the CPU 114 and the counter 122, and the slope detector is also coupled to receive the feedback current value i L _sense, rather than the value coupled to ADC 120 (or in addition). In this regard, controller 108A has a slope detector 502 as a means for performing Figure 4 The functions of steps 412 and 418 of the embodiment of the present invention are integrated (and possibly dedicated) hardware, i.e., in any of those steps, the trajectory of the values ​​described above as previously monitored by the ADC values ​​also corresponds to a change in slope, e.g., Figures 3A to 3C Therefore, in Figure 5 In the example of FIG. 4 , the slope detector 502 may be operable to detect when the slope flattens or changes to begin increasing in step 412, or similarly to detect when the slope flattens or changes to decrease in step 418. In either case, the slope detector 502 may indicate such detection events to the CPU 114 (e.g., by interrupting or setting a CPU monitoring flag in the memory 118), and the CPU 114 may perform the following operations based on the remaining Figure 4 Alternatively, as by Figure 5 , the slope detector 502 may indicate such a detection event directly to the CPU 114 and stop the counter 122. In some examples, the counter 122 may be started by the CPU 114 and stopped by the slope detector 502. In other examples, the counter 122 may be started and stopped by the CPU 114. The CPU 114 also resets the counter 122 to zero after reading the count value.

[0041] According to the above, the described example provides an electronic circuit system including a pulse width modulator with adaptive dead time adjustment. Such an electronic circuit system can be implemented in power conversion / power converters, and can be used in many applications and can meet long-term needs, because power conversion products are expected to be continuous and prolific market needs. Examples of such applications include industrial devices, servo drives, solar inverters, uninterruptible power supplies, heating, ventilation and air conditioning, elevators, etc. Adaptive PWM can avoid direct pass, adapt to device parameter changes, and improve voltage gain / loss and distortion. In addition, adaptive PWM can be implemented, for example, without an external voltage sensor, and in many cases utilizes sensors already included in the load driven in the system, such as when the load is a motor including a current sensor, and hardware on a microcontroller, such as an included ADC or slope detector. Therefore, product and system performance are improved, and cost and / or complexity are reduced. As another benefit, additional modifications can be made in the described embodiments, and other embodiments are also possible within the scope of the appended claims.

Claims

1. A pulse width modulator circuit, comprising: a circuit system for providing a first pulse width modulated signal and a second pulse width modulated signal, wherein the first pulse width modulated signal and the second pulse width modulated signal have a dead time period between them; an input for receiving a signal representative of current in a load, the load being adapted to be driven in response to the first pulse width modulated signal and the second pulse width modulated signal; and Circuitry is coupled to the input for adjusting the dead-band period in response to the signal representative of current.

2. The pulse width modulator circuit of claim 1, wherein the circuitry for providing a pulse width modulated signal and the circuitry for adjusting the dead time period comprise a controller.

3. The pulse width modulator circuit of claim 1, wherein the circuitry for adjusting the dead-band period comprises an analog-to-digital converter.

4. The pulse width modulator circuit of claim 3, wherein the circuitry for adjusting the dead-band time period further comprises a central processing unit.

5. The pulse width modulator circuit of claim 1, wherein the circuitry for adjusting the dead-band time period comprises a central processing unit.

6. The pulse width modulator circuit of claim 1, wherein the circuitry for adjusting the dead-band period includes circuitry for detecting a change in trajectory of the signal representative of current.

7. A pulse width modulator circuit as claimed in claim 6, wherein the circuitry for detecting a change in trajectory comprises an analog to digital converter.

8. The pulse width modulator circuit of claim 6, wherein the circuitry for detecting a change in trajectory comprises a slope detector integrated into a controller.

9. The pulse width modulator circuit of claim 6, wherein the circuit system for detecting a change in trajectory comprises: circuitry for detecting a decreasing change in said signal representative of current during a first half cycle of a complete cycle of said current in said load; and Circuitry for detecting an increased change in the signal representative of current during a second half cycle of the complete cycle of the current in the load.

10. The pulse width modulator circuit of claim 1, wherein the circuit system for adjusting the dead time period comprises: a pulse width modulator peripheral for generating a pulse width modulated control signal, generating the first pulse width modulated signal and the second pulse width modulated signal in response to the pulse width modulated control signal; counter; and Circuitry is coupled to the counter for starting the counter in response to a transition of the pulse width modulation control signal and stopping the counter in response to a change in trajectory of the signal representative of current.

11. The pulse width modulator circuit of claim 10, wherein the transition is a low to high transition during a positive half cycle of the current in a load.

12. The pulse width modulator circuit of claim 10, wherein the transition is a high to low transition during a negative half cycle of the current in a load.

13. The pulse width modulator circuit according to claim 1, and further comprising: for coupling an output voltage to an output terminal of the load, the current in the load being responsive to the output voltage; a pulse width modulator peripheral for generating a pulse width modulated control signal, generating the first pulse width modulated signal and the second pulse width modulated signal in response to the pulse width modulated control signal; and Circuitry is provided for measuring an actual dead time between a transition of the pulse width modulated control signal and a transition of the output voltage.

14. A pulse width modulator circuit as claimed in claim 13 and further comprising circuitry for detecting the transition in the output voltage in response to a change in trajectory of the signal representative of the current.

15. The pulse width modulator circuit of claim 13, wherein the circuitry for providing first and second pulse width modulated signals adjusts at least a first of the dead time periods in response to the measurement of the actual dead time.

16. A pulse width modulator system, comprising: a circuit system for providing a first pulse width modulated signal and a second pulse width modulated signal, wherein the first pulse width modulated signal and the second pulse width modulated signal have a dead time period between them; an input for receiving a signal representative of a current in a load, the load being adapted to be driven in response to the first pulse width modulated signal and the second pulse width modulated signal; circuitry coupled to the input for adjusting the dead-band period in response to the signal representative of current; a first switch driver adapted to receive the first pulse width modulation signal; a second switch driver adapted to receive the second pulse width modulation signal; a first switch circuit coupled to an output terminal of the first switch driver; and A second switch circuit is coupled to the output terminal of the second switch driver.

17. The pulse width modulator system of claim 16 and further comprising: for coupling an output voltage to an output terminal of the load, the current in the load being responsive to the output voltage; and A current sensor is coupled to the output terminal and is operable to provide the signal representative of the current.

18. The pulse width modulator system of claim 16 and further comprising: for coupling an output voltage to an output terminal of the load, the current in the load being responsive to the output voltage; a pulse width modulator peripheral for generating a pulse width modulated control signal, generating the first pulse width modulated signal and the second pulse width modulated signal in response to the pulse width modulated control signal; and Circuitry for measuring an actual dead time between a transition of the pulse width modulated control signal and a change in trajectory of the signal representative of the current.

19. A method of operating a pulse width modulator circuit, comprising: providing a first pulse width modulation signal and a second pulse width modulation signal, wherein a dead time period is provided between the first pulse width modulation signal and the second pulse width modulation signal; receiving a signal representative of a current in a load, the load being adapted to be driven in response to the first pulse width modulated signal and the second pulse width modulated signal; and The dead-band period is adjusted in response to the signal representative of current.

20. The method of claim 19, wherein the adjusting step includes adjusting the deadband period in response to a change in trajectory of the signal representative of current.

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