Comparator, light detection element, and electronic device

Abstract

[Problem] To provide a comparator, a light detection element, and an electronic device that reduce noise. [Solution] A comparator for comparing a signal with a reference signal to output a comparison result, and comprising a differential circuit for outputting a differential voltage between the signal and the reference signal, and an active load circuit electrically connected to the differential circuit. The differential circuit includes a first transistor and a second transistor disposed on a surface of a substrate. The first transistor and the second transistor have channel regions extending in a direction substantially perpendicular to the surface of the substrate.

Description

Technical Field

[0001] Embodiments according to the present disclosure relate to a comparator, a light detection element, and an electronic device. Background Art

[0002] In a solid-state imaging device such as a CIS (complementary metal oxide semiconductor (CMOS) image sensor), it is necessary to reduce the noise of a comparator and an AD conversion circuit used in a pixel circuit. In order to reduce the noise, a structure has been proposed in which the size of an input transistor and the size of a reference transistor constituting a differential pair of a comparator are different (see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2019-140531 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] However, this method cannot sufficiently reduce the noise characteristics.

[0008] Provided are a comparator, a light detection element, and an electronic device capable of reducing noise.

[0009] Solution to the problem

[0010] In order to solve the above problem, according to the present disclosure, a comparator is provided, which compares a signal with a reference signal and outputs a comparison result, and includes:

[0011] a differential circuit that outputs a differential voltage between the signal and a reference signal; and

[0012] An active load circuit is electrically connected to the differential circuit, wherein:

[0013] The differential circuit includes a first transistor and a second transistor disposed on a surface of the substrate; and

[0014] The first transistor and the second transistor have a channel region extending in a direction substantially perpendicular to a surface of the substrate.

[0015] The channel regions of the first transistor and the second transistor may have a concavo-convex shape along a direction substantially perpendicular to the channel length direction.

[0016] The channel regions of the first transistor and the second transistor do not need to have a concavo-convex shape along the channel length direction.

[0017] The active load circuit may include a third transistor and a fourth transistor disposed on a surface of the substrate, and

[0018] The channel regions of the third transistor and the fourth transistor may have a concavo-convex shape along a channel length direction.

[0019] The active load circuit may include a third transistor and a fourth transistor disposed on a surface of the substrate, and

[0020] The gate insulating films of the third transistor and the fourth transistor may be thicker than the gate insulating films of the first transistor and the fourth transistor.

[0021] The active load circuit may include a third transistor and a fourth transistor disposed on a surface of the substrate,

[0022] The first transistor and the second transistor may be n-type transistors, and

[0023] The third transistor and the fourth transistor may be p-type transistors.

[0024] The channel length directions of the third transistor and the fourth transistor may be substantially perpendicular or substantially parallel to the (100) crystal plane of the substrate.

[0025] The substrate may be a 45 degree notch substrate, and

[0026] Channel length directions of the third transistor and the fourth transistor may be substantially perpendicular or substantially parallel to the notch plane on the surface of the substrate.

[0027] The substrate may be a 0 degree notch substrate, and

[0028] The channel length directions of the third transistor and the fourth transistor may be directions inclined at about 45 degrees or about 135 degrees with respect to the notch plane on the surface of the substrate.

[0029] The active load circuit may include a third transistor and a fourth transistor disposed on a surface of the substrate,

[0030] The first transistor and the second transistor may be p-type transistors, and

[0031] The third transistor and the fourth transistor may be n-type transistors.

[0032] The channel length directions of the first transistor and the second transistor may be substantially perpendicular or substantially parallel to the (110) crystal plane of the substrate.

[0033] The substrate may be a 45 degree notch substrate, and

[0034] The channel length directions of the first transistor and the second transistor may be directions inclined at about 45 degrees or about 135 degrees with respect to the notch plane on the surface of the substrate.

[0035] The substrate may be a 0 degree notch substrate, and

[0036] The channel length directions of the first transistor and the second transistor may be substantially perpendicular or substantially parallel to the notch plane on the surface of the substrate.

[0037] According to the present disclosure, there is provided a light detection element, comprising:

[0038] a pixel portion including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; and

[0039] a comparator, comparing the pixel signal with a reference signal and outputting a comparison result,

[0040] The comparator includes:

[0041] a differential circuit that outputs a differential voltage between a pixel signal and a reference signal; and

[0042] An active load circuit is electrically connected to the differential circuit, wherein:

[0043] The differential circuit includes a first transistor and a second transistor disposed on a surface of the substrate; and

[0044] The first transistor and the second transistor have a channel region extending in a direction substantially perpendicular to a surface of the substrate.

[0045] The pixel portion may be disposed on the first substrate.

[0046] The comparator may be disposed on a second substrate different from the first substrate,

[0047] The first substrate and the second substrate may be laminated, and

[0048] The pixel portion and the comparator may be electrically connected through a through electrode provided on the first substrate or the second substrate or through a wiring junction between a wiring of the first substrate and a wiring of the second substrate.

[0049] The pixel portion and the comparator may be disposed on the same first substrate.

[0050] The comparator may be disposed above the pixel portion of the first substrate, and

[0051] The pixel portion and the comparator may be electrically connected through a contact plug provided in an interlayer insulating film between the pixel portion and the comparator.

[0052] The differential circuit may be disposed on the first substrate.

[0053] The active load circuit may be disposed on a second substrate different from the first substrate.

[0054] The first substrate and the second substrate may be laminated, and

[0055] The differential circuit and the active load circuit may be electrically connected by bonding the wiring of the first substrate and the wiring of the second substrate.

[0056] The pixel portion and the differential circuit may be arranged on the same first substrate.

[0057] The differential circuit may be disposed over the pixel portion of the first substrate; and

[0058] The pixel portion and the differential circuit may be electrically connected via a contact plug provided in an interlayer insulating film between the pixel portion and the differential circuit.

[0059] The pixel portion and the comparator may be disposed on the same first substrate.

[0060] The differential circuit can be provided in the same layer as the transistor of the pixel portion,

[0061] The active load circuit may be disposed above the pixel portion of the first substrate, and

[0062] The differential circuit and the active load circuit may be electrically connected through a contact plug provided in an interlayer insulating film between the differential circuit and the active load circuit.

[0063] According to the present disclosure, an electronic device is provided, including a light detecting element. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 is a block diagram showing an example of a functional configuration of the imaging apparatus according to the first embodiment.

[0065] Figure 2 is a diagram illustrating an example of a schematic configuration of an imaging apparatus.

[0066] Figure 3 is a diagram illustrating an example of a schematic configuration of an imaging apparatus.

[0067] Figure 4 : is a schematic cross-sectional view showing the configuration of a pixel sharing unit, a column signal processing section, and a pixel signal processing section according to the first embodiment.

[0068] Figure 5 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit and a comparator section.

[0069] Figure 6 is a diagram showing an example of the configuration of a p-type transistor according to the first embodiment.

[0070] Figure 7 is a diagram showing an example of the configuration of an n-type transistor according to the first embodiment.

[0071] Figure 8 is a schematic plan view showing an example of a plan layout of a first substrate.

[0072] Fig. 9 is a schematic plan view showing an example of a plan layout of the second substrate.

[0073] Fig.10 is a diagram showing an example of the configuration of a p-type transistor according to a modification of the first embodiment.

[0074] Fig.11 is a plan view showing a configuration example of a p-type transistor.

[0075] Fig.12 is a plan view showing a configuration example of a p-type transistor.

[0076] Fig.13 is a plan view showing a configuration example of a p-type transistor.

[0077] Fig.14 is a plan view showing a configuration example of a p-type transistor.

[0078] Fig.15 is a conceptual diagram showing a configuration example of a solid-state imaging device according to the third embodiment.

[0079] Fig.16 : is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit and a comparator section according to the third embodiment.

[0080] Fig.17 is a conceptual diagram showing a configuration example of a solid-state imaging device according to a fourth embodiment.

[0081] Fig.18 : is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit and a comparator section according to the fourth embodiment.

[0082] Fig.19 is a conceptual diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment.

[0083] Fig. 20 : is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit and a comparator section according to the fifth embodiment.

[0084] Fig.21 : is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit and a comparator section according to the sixth embodiment.

[0085] Fig. 22 is a diagram showing an example of the configuration of a p-type transistor according to the sixth embodiment.

[0086] Fig.23 is a diagram showing an example of the configuration of an n-type transistor according to the sixth embodiment.

[0087] Fig.24 is a plan view showing a configuration example of a p-type transistor.

[0088] Fig.25 is a plan view showing a configuration example of a p-type transistor.

[0089] Fig.26 is a plan view showing a configuration example of a p-type transistor.

[0090] Fig. 27 is a plan view showing a configuration example of a p-type transistor.

[0091] Fig.28 It is a diagram showing an embodiment in which the sixth embodiment is combined with the third embodiment.

[0092] Fig.29 It is a diagram showing an embodiment in which the sixth embodiment is combined with the fourth embodiment.

[0093] Fig.30 It is a diagram showing an embodiment in which the sixth embodiment is combined with the fifth embodiment.

[0094] Fig.31 : is a schematic cross-sectional view showing the configuration of a pixel sharing unit, a column signal processing section, and a pixel signal processing section according to the seventh embodiment.

[0095] Fig.32 yes Figure 1 The equivalent circuit diagram of the pixel sharing unit is shown.

[0096] Fig.33 is a diagram showing an example of a connection pattern between a plurality of pixel sharing units and a plurality of vertical signal lines.

[0097] Fig.34 It is shown Figure 3 A schematic cross-sectional view of an example of a specific configuration of an imaging device is shown.

[0098] Fig.35A It is shown Fig.34 A schematic diagram showing an example of a planar configuration of a main portion of a first substrate is shown.

[0099] Fig.35B It is shown Fig.35A A schematic diagram of the planar configuration of the pad portion together with the main portion of the first substrate is shown.

[0100] Fig.36 It is shown Fig.34Schematic diagram of an example of a planar configuration of the second substrate (semiconductor layer) shown.

[0101] Fig.37 It is shown Fig.34 Schematic diagram showing an example of a planar configuration of a pixel circuit and main parts of a first substrate together with a first wiring layer.

[0102] Fig.38 It is shown Fig.34 Schematic diagram showing an example of a planar configuration of a first wiring layer and a second wiring layer.

[0103] Fig.39 It is shown Fig.34 Schematic diagram of an example of a planar configuration of a second wiring layer and a third wiring layer shown.

[0104] Fig.40 It is shown Fig.34 Schematic diagram of an example of a planar configuration of a third wiring layer and a fourth wiring layer shown.

[0105] Fig.41 It is used to illustrate Figure 3 A schematic diagram of the path of the input signal of the imaging device is shown.

[0106] Fig.42 It is used to illustrate Figure 3 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0107] Fig.43 It is shown Fig.36 A schematic diagram of a modification of the planar configuration of the second substrate (semiconductor layer) is shown.

[0108] Fig.44 It is shown Fig.43 A schematic diagram showing a planar configuration of a main portion of a first wiring layer and a first substrate together with a pixel circuit.

[0109] Fig.45 It is shown Fig.44 A schematic diagram showing an example of a planar configuration of a second wiring layer together with a first wiring layer.

[0110] Fig.46 It is shown Fig.45 FIG. 1 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with a second wiring layer.

[0111] Fig.47 It is shown Fig.46 FIG. 1 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with a third wiring layer.

[0112] Fig.48 It is shown Fig.35AA schematic diagram of a modification of the planar configuration of the first substrate is shown.

[0113] Fig.49 is shown laminated in Fig.48 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0114] Fig.50 It is shown Fig.49 A schematic diagram showing an example of a planar configuration of a first wiring layer together with a pixel circuit is shown.

[0115] Fig.51 It is shown Fig.50 FIG. 1 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with a first wiring layer.

[0116] Fig.52 It is shown Fig.51 FIG. 1 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with a second wiring layer.

[0117] Fig.53 It is shown Fig.52 FIG. 1 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with a third wiring layer.

[0118] Fig.54 It is shown Fig.48 FIG. 2 is a schematic diagram of another example of the planar configuration of the first substrate shown.

[0119] Fig.55 is shown laminated in Fig.54 Schematic diagram of an example of a planar configuration of a second substrate (semiconductor layer) on a first substrate shown.

[0120] Fig.56 It is shown Fig.55 A schematic diagram showing an example of a planar configuration of a first wiring layer together with a pixel circuit is shown.

[0121] Fig.57 It is shown Fig.56 FIG. 1 is a schematic diagram showing an example of a planar configuration of a second wiring layer together with a first wiring layer.

[0122] Fig.58 It is shown Fig.57 FIG. 1 is a schematic diagram showing an example of a planar configuration of a third wiring layer together with a second wiring layer.

[0123] Fig.59 It is shown Fig.58 FIG. 1 is a schematic diagram showing an example of a planar configuration of a fourth wiring layer together with a third wiring layer.

[0124] Fig.60 It is shown Figure 3A schematic cross-sectional view of another example of the imaging device shown.

[0125] Fig.61 It is used to illustrate Fig.60 A schematic diagram of the path of the input signal of the imaging device is shown.

[0126] Fig.62 It is used to illustrate Fig.60 Schematic diagram of the signal path of the pixel signal of the imaging device shown.

[0127] Fig.63 It is shown Fig.34 A schematic cross-sectional view of another example of the imaging device shown.

[0128] Fig.64 It is shown Fig.32 Schematic diagram of another example of an equivalent circuit shown.

[0129] Fig.65 It is shown Fig.35A A schematic plan view of another example of a pixel separation portion, etc. shown.

[0130] Fig.66 : is a diagram showing an example of a schematic configuration of an imaging system including an imaging apparatus according to the above-described embodiment and its modifications.

[0131] Fig.67 It is shown Fig.66 Schematic diagram of an example of an imaging process for an imaging system shown.

[0132] Fig.68 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0133] Fig.69 1 is an explanatory diagram showing an example of the installation positions of the vehicle exterior information detection unit and the imaging section.

[0134] Fig.70 is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0135] Fig.71 is a block diagram showing an example of the functional configuration of a camera and a CCU. DETAILED DESCRIPTION

[0136] Hereinafter, embodiments of the comparator, the light detection element, and the electronic device will be described with reference to the accompanying drawings. Hereinafter, the main components of the comparator, the light detection element, and the electronic device will be mainly described, but the comparator, the light detection element, and the electronic device may have components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0137] (First Embodiment)

[0138] (Configuration of Imaging Device 1)

[0139] Figure 1 is a block diagram showing an example of a functional configuration of the imaging apparatus according to the first embodiment.

[0140] For example, Figure 1 The imaging device 1 includes an input section 510A, a row driving section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0141] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a pixel sharing unit 539 including a plurality of pixels is a repeating unit, and is repeatedly arranged in an array including a row direction and a column direction. Note that in this specification, for convenience, the row direction may be referred to as the H direction, and the column direction orthogonal to the row direction may be referred to as the V direction. In this embodiment, as Figure 2 As shown, one pixel sharing unit 539 includes eight pixels 541. Each pixel 541 includes a photodiode PD. The pixel sharing unit 539 is a unit that shares one pixel circuit. In other words, one pixel circuit (e.g., Figure 2 By operating the pixel circuit in a time-division manner, the pixel signal of each of the pixels 541 is sequentially read. For example, the pixels 541 are arranged in 2 rows×2 columns. Figure 1 In the pixel array section 540, a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided together with a plurality of pixels 541. The row drive signal line 542 drives the pixel 541 included in each of the plurality of pixel sharing units 539 arranged side by side in the row direction in the pixel array section 540. In the pixel sharing unit 539, each pixel arranged side by side in the row direction is driven. The pixel sharing unit 539 is provided with a plurality of transistors. In order to drive each of the plurality of transistors, a plurality of row drive signal lines 542 are connected to one pixel sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. A pixel signal is read from each of the pixels 541 included in the pixel sharing unit 539 via the vertical signal line (column readout line) 543.

[0142] The row driving section 520 includes, for example, a row address control section (in other words, a row decoder section) that determines the position of a row for driving pixels, and a row driving circuit section that generates a signal for driving the pixels 541 .

[0143] The column signal processing section 550 includes, for example, a load circuit section connected to the vertical signal line 543 and forming a source follower circuit with the pixel sharing unit 539. The column signal processing section 550 may include an amplifier circuit section that amplifies a pixel signal read from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing section 550 may include a noise processing section. In the noise processing section, for example, as a result of photoelectric conversion, a noise level of the system is removed from the signal read from the pixel sharing unit 539.

[0144] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). In the analog-to-digital converter, the signal read from the pixel sharing unit 539 or the above-mentioned analog signal after noise processing is converted into a digital signal. The ADC may include, for example, a comparator unit ( Figure 5 In the comparator section 210, the analog signal to be converted (pixel signal) is compared with the reference signal to be compared. Figure 5 The comparator section 210 is described. In the counter section, the time until the comparison result in the comparator section 210 is inverted is measured. The count value from the counter section is a pixel signal subjected to a correlated double sampling (CDS) process and subjected to AD conversion. The column signal processing section 550 may include a horizontal scanning circuit section that performs control to scan the readout column so as to output the pixel signal.

[0145] The timing control section 530 provides a signal for controlling timing to the row driving section 520 and the column signal processing section 550 based on a reference clock signal and a timing control signal input to the device.

[0146] The image signal processing section 560 is a circuit that performs various types of signal processing on data obtained as a result of photoelectric conversion (in other words, data obtained as a result of imaging operation in the imaging device 1). The image signal processing section 560 includes, for example, an image signal processing circuit section and a data holding section. The image signal processing section 560 may include a processor section.

[0147] An example of the signal processing performed in the image signal processing section 560 is a tone curve correction process that provides a large amount of grayscale when the imaging data after AD conversion is data obtained by imaging a dark object, and reduces the grayscale when the imaging data after AD conversion is data obtained by imaging a bright object. In this case, based on which tone curve it is desired to correct the grayscale of the imaging data, feature data of the tone curve is stored in advance in the data holding section of the image signal processing section 560.

[0148] For example, the input section 510A is used to input the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from the outside of the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal, a horizontal synchronization signal, etc. For example, the characteristic data is stored in the data holding section of the image signal processing section 560. The input section 510A includes, for example, an input terminal 511, an input circuit section 512, an input amplitude changing section 513, an input data conversion circuit section 514, and a power supply section (not shown).

[0149] The input terminal 511 is an external terminal for inputting data. The input circuit section 512 is used to bring the signal input to the input terminal 511 into the imaging device 1. In the input amplitude changing section 513, the amplitude of the signal captured by the input circuit section 512 is changed to an amplitude that can be easily used inside the imaging device 1. In the input data conversion circuit section 514, the arrangement of the data string of the input data is changed. The input data conversion circuit section 514 includes, for example, a serial-to-parallel conversion circuit. In the serial-to-parallel conversion circuit, a serial signal received as input data is converted into a parallel signal. Note that in the input section 510A, the input amplitude changing section 513 and the input data conversion circuit section 514 can be omitted. The power supply section supplies power set to various voltages required inside the imaging device 1 to the imaging device 1 based on the power supplied from the outside to the imaging device 1.

[0150] When the imaging apparatus 1 is connected to an external memory device, the input section 510A may be provided with a memory interface circuit that receives data from the external memory device. Examples of the external memory device include flash memory, SRAM, and DRAM.

[0151] The output section 510B outputs the image data to the outside of the device. The image data is, for example, image data captured by the imaging device 1, image data subjected to signal processing by the image signal processing section 560, etc. The output section 510B includes, for example, an output data conversion circuit section 515, an output amplitude changing section 516, an output circuit section 517, and an output terminal 518.

[0152] For example, the output data conversion circuit section 515 includes a parallel / serial conversion circuit, and in the output data conversion circuit section 515, a parallel signal used inside the imaging device 1 is converted into a serial signal. The output amplitude change section 516 changes the amplitude of the signal used inside the imaging device 1. The signal with the changed amplitude is easily used in an external device connected to the outside of the imaging device 1. The output circuit section 517 is a circuit that outputs data from the inside of the imaging device 1 to the outside of the device, and the wiring outside the imaging device 1 connected to the output terminal 518 is driven by the output circuit section 517. At the output terminal 518, the data is output from the imaging device 1 to the outside of the device. In the output section 510B, the output data conversion circuit section 515 and the output amplitude change section 516 can be omitted.

[0153] When the imaging apparatus 1 is connected to an external memory device, the output section 510B may be provided with a memory interface circuit that outputs data to the external memory device. Examples of the external memory device include flash memory, SRAM, and DRAM.

[0154] (Schematic Configuration of Imaging Device 1)

[0155] Figure 2 and Figure 3 is a diagram showing an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 2 The planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300 is schematically shown, and Figure 3 A cross-sectional configuration of a first substrate 100 , a second substrate 200 , and a third substrate 300 laminated to one another is schematically shown. Figure 3 Corresponding to the Figure 2The cross-sectional configuration taken along the line III-III' shown. The imaging device 1 is an imaging device having a three-dimensional structure formed by bonding three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, a combination of wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and an interlayer insulating film around the wiring is referred to as a wiring layer (100T, 200T, 300T) provided on each substrate (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100, the second substrate 200 and the third substrate 300 are sequentially laminated, and the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T and the semiconductor layer 300S are sequentially arranged along the lamination direction. The specific configurations of the first substrate 100, the second substrate 200 and the third substrate 300 will be described later. Figure 3 The arrow shown indicates the incident direction of the light L on the imaging device 1. In this specification, for the sake of convenience, in the following cross-sectional views, the light incident side in the imaging device 1 may be referred to as "lower", "lower side", and "downward direction", and the side opposite to the light incident side may be referred to as "upper", "upper side", and "upward direction". In addition, in this specification, for the sake of convenience, in a substrate including a semiconductor layer and a wiring layer, one side of the wiring layer may be referred to as a front surface, and one side of the semiconductor layer may be referred to as a rear surface. Note that the description of the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light enters from the rear surface side of the first substrate 100 having a photodiode.

[0156] The pixel array section 540 and the pixel sharing unit 539 included in the pixel array section 540 are configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539. Each of these pixels 541 includes a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TG or TR described later). The second substrate 200 is provided with a pixel circuit included in the pixel sharing unit 539. The pixel circuit reads a pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C, and 541D via a transfer transistor, or resets the photodiode. In addition to such a pixel circuit, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further includes a power supply line 544 extending in the row direction and a portion of the column signal processing unit 550. For example, the third substrate 300 includes an input section 510A, a row driving section 520, a timing control section 530, the remaining portion of the column signal processing section 550, an image signal processing section 560, and an output section 510B. For example, the row driving section 520 is disposed in a region where a portion thereof overlaps with the pixel array section 540 in the lamination direction (hereinafter, simply referred to as the lamination direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driving section 520 is disposed in a region that overlaps with the vicinity of the end portion of the pixel array section 540 in the H direction in the lamination direction ( Figure 2 ). For example, the column signal processing section 550 is disposed in a region partially overlapping with the pixel array section 540 in the lamination direction. More specifically, the column signal processing section 550 is disposed in a region overlapping with the vicinity of the end portion in the V direction of the pixel array section 540 in the lamination direction ( Figure 2 ). Although not shown, the input section 510A and the output section 510B may be provided in a portion other than the third substrate 300, for example, may be provided on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the rear surface (light incident surface) side of the first substrate 100. Note that the pixel circuit provided on the above-mentioned second substrate 200 may also be referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit as another name. In this specification, the term "pixel circuit" is used.

[0157] The first substrate 100 and the second substrate 200 are electrically connected, for example, via a through electrode. The second substrate 200 and the third substrate 300 are electrically connected, for example, via contact portions 201, 202, 301 or 302. The contact portions 201 and 202 are arranged on the second substrate 200, and the contact portions 301 and 302 are arranged on the third substrate 300. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact area 201R provided with a plurality of contact portions 201 and a contact area 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact area 301R provided with a plurality of contact portions 301 and a contact area 302R provided with a plurality of contact portions 302. The contact areas 201R and 301R are arranged between the pixel array portion 540 and the row drive portion 520 in the lamination direction ( Figure 3 ). In other words, the contact regions 201R and 301R are provided, for example, in a region where the row drive section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the lamination direction or in a region near the lamination direction. The contact regions 201R and 301R are provided, for example, at the ends in the H direction of such a region ( Figure 2 In the third substrate 300, for example, the contact region 301R is provided at a portion of the row drive section 520 (specifically, in the H direction ( Figure 2 and Figure 3 ) is at a position where the end of the row driving section 520 on the third substrate 300 overlaps. For example, the contact portions 201 and 301 connect the row driving section 520 provided on the third substrate 300 and the row driving line 542 provided on the second substrate 200. For example, the contact portions 201 and 301 can connect the input section 510A provided on the third substrate 300 to the power supply line 544 and the reference potential line (reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the lamination direction ( Figure 3 ). In other words, the contact regions 202R and 302R are provided, for example, in a region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the lamination direction or in a vicinity thereof. The contact regions 202R and 302R are provided, for example, at the end portions in the V direction of such a region ( Figure 2 In the third substrate 300, for example, the contact region 301R is provided at a portion of the column signal processing section 550 (specifically, in the V direction ( Figure 2 and Figure 3) at a position where the column signal processing section 550 on the third substrate 300 overlaps with the end of the column signal processing section 550 on the second substrate 200. The contact portions 202 and 302 are used, for example, to connect a pixel signal (a signal corresponding to an amount of charge generated as a result of photoelectric conversion in a photodiode) output from each of the plurality of pixel sharing units 539 included in the pixel array section 540 to the column signal processing section 550 provided on the third substrate 300. The pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0158] Figure 3 1 is an example of a cross-sectional view of the imaging device 1 as described above. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are composed of electrodes composed of a conductive material. The conductive material is composed of, for example, a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R are electrically connected by directly bonding the wiring formed as the electrodes.

[0159] The second substrate 200 and the third substrate 300 are connected to each other, and enable a signal to be input and / or output between the second substrate 200 and the third substrate 300 .

[0160] The electrical connection portion electrically connecting the second substrate 200 and the third substrate 300 may be disposed at a desired position. Figure 3 As described above with respect to the contact regions 201R, 202R, 301R, and 302R, the contact region may be provided in a region overlapping with the pixel array section 540 in the lamination direction. In addition, the electrical connection portion may be provided in a region not overlapping with the pixel array section 540 in the lamination direction. Specifically, it may be provided in a region overlapping with a peripheral portion arranged outside the pixel array section 540 in the lamination direction.

[0161] For example, the first substrate 100 and the second substrate 200 are provided with connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 ( Figure 3 The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping with the pixel array section 540) ( Figure 2). For example, the connection hole H1 is arranged outside the pixel array portion 540 in the H direction, and the connection hole H2 is arranged outside the pixel array portion 540 in the V direction. For example, the connection hole H1 reaches the input portion 510A provided in the third substrate 300, and the connection hole H2 reaches the output portion 510B provided in the third substrate 300. The connection holes H1 and H2 may be hollow, and at least a portion thereof may contain a conductive material. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which an electrode formed as the input portion 510A and / or the output portion 510B is connected to a conductive material provided in the connection holes H1 and H2. The conductive material provided in the connection holes H1 and H2 may be embedded in a portion or all of the connection holes H1 and H2, and the conductive material may be formed on the side walls of the connection holes H1 and H2.

[0162] Note that Figure 3 In the embodiment, the input portion 510A and the output portion 510B are disposed on the third substrate 300, but the present invention is not limited thereto. For example, by transmitting the signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T, the input portion 510A and / or the output portion 510B may be disposed on the second substrate 200. Similarly, by transmitting the signal of the second substrate 200 to the first substrate 1000 via the wiring layers 100T and 200T, the input portion 510A and / or the output portion 510B may be disposed on the first substrate 100.

[0163] Figure 4 2 is a schematic cross-sectional view showing the configuration of the pixel sharing unit 539, the column signal processing unit 550 and the pixel signal processing unit 560 according to the first embodiment. The pixel sharing unit 539, the column signal processing unit 550 and the pixel signal processing unit 560 are, for example, respectively arranged on the first substrate 100, the second substrate 200 and the third substrate 300. The first substrate 100 to the third substrate 300 are, for example, silicon substrates and laminated to each other. The first substrate 100 to the third substrate 300 are electrically connected to each other by using a through-hole contact VIA, a through-electrode (through-silicon via (TSV)) and / or a wiring junction (Cu-Cu junction) CCC. The through-hole contact VIA is a contact plug arranged through an interlayer insulating film. The through-electrode TSV is an electrode that penetrates the substrate and electrically connects the semiconductor element to the semiconductor element of another substrate. The wiring junction CCC is formed by directly joining the wiring arranged on each of the first substrate 100 to the third substrate 300 by laminating the substrate.

[0164] For example, the first substrate 100 is provided with components corresponding to the corresponding pixels 541, such as a photodiode PD, a transfer transistor TG, an overflow gate ( Figure 4 not shown) and the floating diffusion FD. Figure 4The solid-state imaging device in is a back-illuminated CIS, and the on-chip lens OCL is arranged on the light receiving surface of the first substrate 100. The transfer transistor TG and the overflow gate are arranged on the surface of the first substrate 100 opposite to the light receiving surface. The transfer transistor TG and the overflow gate are covered by an interlayer insulating film and are electrically connected to a through-hole contact VIA embedded in the interlayer insulating film. For example, the comparator section 210 of the column signal processing section 550 is arranged on the second substrate 200. The column signal processing section 550 is electrically connected to the floating diffusion FD of the first substrate 100 via the through-electrode TSV and the through-hole contact VIA penetrating the second substrate 200. The column signal processing section 550 is also covered by an interlayer insulating film and is electrically connected to the wiring embedded in the interlayer insulating film. A portion of the wiring is exposed on the surface of the interlayer insulating film. For example, the third substrate 300 is provided with a logic circuit after the comparator section 210 of the column signal processing section 550, the pixel signal processing section 560, etc. The logic circuit, the pixel signal processing section 560 and the like are also covered by the interlayer insulating film and are electrically connected to wiring embedded in the interlayer insulating film. Part of the wiring is exposed on the surface of the interlayer insulating film.

[0165] Parts of the wirings of the second substrate 200 and the third substrate 300 are bonded to each other by lamination of the second substrate 200 and the third substrate 300, and the wirings are electrically connected to each other. Thus, a wiring junction CCC is formed.

[0166] Figure 5 is an equivalent circuit diagram showing an example of the configuration of a pixel sharing unit 539 and a comparator section 210. The pixel sharing unit 539 includes a plurality of pixels 541 and one comparator section 210 connected to the plurality of pixels 541. The plurality of pixels 541 are provided on a first substrate 100, and the comparator section 210 is provided on a second substrate 200. The first substrate 100 and the second substrate 200 are electrically connected through through electrodes electrically connected in a wiring junction (Cu-Cu junction) CCC.

[0167] (Configuration of pixel sharing unit 539)

[0168] The pixel sharing unit 539 sequentially outputs pixel signals of a plurality of pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating one comparator unit 210 in a time-division manner. A mode in which one comparator unit 210 is connected to a plurality of pixels 541 and pixel signals of the plurality of pixels 541 are output in a time-division manner through one comparator unit 210 is referred to as "a plurality of pixels 541 share one comparator unit 210". Figure 5 In FIG. 2 , eight pixels 541 share one comparator section 210 , but the number thereof is not particularly limited.

[0169] The pixels 541 have components in common with each other. Hereinafter, in the case where it is not necessary to distinguish components of the plurality of pixels 541A, 541B, 541C, 541D, identification numbers at the end of the reference numbers of the components of the pixels 541A, 541B, 541C, 541D are omitted.

[0170] The pixel 541 includes, for example, a photodiode PD, a transfer transistor TG electrically connected to the photodiode PD, an overflow gate OF electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TG.

[0171] In the photodiode PD (PD1 to PD4), the cathode is electrically connected to the source or drain of the transfer transistor TG and the overflow gate OF, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD is a photoelectric conversion element that photoelectrically converts incident light into a pixel signal and generates a charge corresponding to the amount of light received.

[0172] The transfer transistors TG (TG1 to TG4) are, for example, complementary metal oxide semiconductor (CMOS) transistors. In the transfer transistor TG, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to the drive signal line. The drive signal line is a plurality of row drive signal lines 542 (see Figure 1 The transfer transistor TG transfers the charges generated in the photodiode PD to the floating diffusion FD.

[0173] The floating diffusion FD is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD, and is a charge-voltage conversion device that generates a voltage corresponding to the amount of charge. The floating diffusion FD is shared by a plurality of pixels 541.

[0174] Overflow gates OF (OF1 to OF4) are connected between photodiodes PD and power supply VDD, and a predetermined voltage is applied to the gates. Overflow gates OF allow charges exceeding the saturation charge amount of photodiodes PD to flow to power supply VDD. Overflow gates OF include, for example, n-type transistors.

[0175] (Configuration and Function of Comparator Section 210)

[0176] The comparator section 210 includes a current mirror circuit 210 a as an active load circuit, a differential circuit 210 b , a current source 210 c , and a reset transistor 210 d .

[0177] The current mirror circuit 210a includes p-type transistors Tp1 and Tp2. The source of transistor Tp1 is connected to the power supply VDD, and its drain is connected to the drain of n-type transistor Tn1. The gate of transistor Tp1 and the gate of transistor Tp2 are commonly connected to the drain of transistor Tp1. The source of transistor Tp2 is connected to the power supply VDD, and its drain is connected to the drain of n-type transistor Tn2. The gate of transistor Tp2 and the drain of transistor Tp1 are commonly connected to the drain of transistor Tp1.

[0178] Since the gates of the transistors Tp1 and Tp2 are commonly connected to the drain of the transistor Tp1, the transistors Tp1 and Tp2 constitute a current mirror circuit, and a current corresponding to a predetermined mirror ratio flows through the transistors Tn1 and Tn2. A more detailed configuration of the transistors Tp1 and Tp2 will be described later.

[0179] The differential circuit 210b includes n-type transistors Tn1 and Tn2. The drain of transistor Tn1 is connected to the drain and gate of transistor Tp1. The source of transistor Tn1 and the source of transistor Tn2 are connected to the drain of n-type transistor Tn3. The drain of transistor Tn2 is connected to the drain of transistor Tp2. The source of transistor Tn2 and the drain of transistor Tn3 are connected to the source of transistor Tn1.

[0180] The transistors Tn1 and Tn2 receive a pixel signal and a reference signal from the floating diffusion FD at gates thereof, and output a voltage difference from a node N210 .

[0181] The current source 210c includes an n-type transistor Tn3, and maintains the total current flowing through the transistors Tn1 and Tn2 at a predetermined value. The drain of the transistor Tn3 is commonly connected to the sources of the transistors Tn1 and Tn2, and the source of the transistor Tn3 is connected to the ground GND. A predetermined voltage Vb is applied to the gate of the transistor Tn3.

[0182] The n-type transistor Tn4 is connected between the node N210 and the gate (floating diffusion FD) of the transistor Tn2. The gate of the n-type transistor Tn4 receives the reset signal RST. The n-type transistor Tn4 is used as an AZ transistor and performs an auto-zero operation by electrically connecting the floating diffusion FD and the node N210 before detecting the output signal.

[0183] A negative voltage VRLW is applied as a reverse bias to the transistors Tn1 to Tn4.

[0184] (Transconductance and noise)

[0185] Here, noise reduction is required in the ADC. The noise characteristics of the ADC are determined, for example, by the balance between the transconductance gm of the p-type transistors Tp1 and Tp2 and the transconductance gm of the n-type transistors Tn1 and Tn2. By reducing the transconductance gm of the p-type transistors Tp1 and Tp2 constituting the current mirror circuit 210a, the noise is reduced and the noise characteristics are improved. On the other hand, by increasing the transconductance gm of the n-type transistors Tn1 and Tn2 constituting the differential circuit 210b, the noise is reduced and the noise characteristics are improved. For example, the signal-to-noise ratio (S / N) is improved, and the dynamic range can be expanded. Therefore, the sensor characteristics of the solid-state imaging device (light detection element) according to the present embodiment are improved.

[0186] The transconductance gm changes according to the relationship between the channel length L and the channel width W of the transistor. For example, the transconductance gm decreases as the channel length L increases, and increases as the channel width W increases.

[0187] (Configuration of p-type transistors Tp1 and Tp2)

[0188] Figure 6 is a diagram showing an example of the configuration of p-type transistors Tp1 and Tp2 according to the first embodiment. Figure 6 The upper part shows a plan view. Figure 6 The middle part shows the Figure 6 The cross-sectional view corresponds to a cross-sectional view taken along line BB' of the plan view. Figure 6 The lower part shows the Figure 6 The cross-sectional view corresponds to a cross-sectional view taken along line AA' of the plan view.

[0189] The p-type transistors Tp1 and Tp2 have a channel region CHtp extending in a direction substantially perpendicular to the substrate surface. In addition, the channel region CHtp of the p-type transistors Tp1 and Tp2 has an uneven shape along the channel length direction Dcp. That is, the channel region CHtp of the p-type transistors Tp1 and Tp2 has at least one concave portion (groove or dug) 141 substantially perpendicular to the surface of the substrate along the channel length direction Dcp. Figure 6 In the example shown, three recesses 141 are provided.

[0190] The recess 141 includes two side surfaces Ss1 and Ss2 and a bottom surface Sb1. The side surfaces Ss1 and Ss2 are surfaces substantially perpendicular to the substrate surface. The bottom surface Sb1 is a surface substantially parallel to the substrate surface.

[0191] The effective channel length L (Leff) extends on the side surface Ss1, the bottom surface Sb1, and the side surface Ss2. Therefore, the charges (holes) move sequentially along the side surface Ss1, the bottom surface Sb1, and the side surface Ss2 from the source region S to the drain region D. That is, the holes move along the recess 141 in a direction substantially perpendicular to the substrate surface, a direction substantially horizontal to the substrate surface, and a direction substantially perpendicular to the substrate surface.

[0192] The effective channel length L (Leff) is the length along the recess 141. That is, the channel length Lg can extend a certain distance along the side surfaces Ss1 and Ss2. Therefore, the transconductance gm of the p-type transistors Tp1 and Tp2 can be reduced, and the noise can be reduced. In addition, since the distance in the depth direction of the substrate is used, the channel length L can be extended without increasing the mounting area (gate size) of the transistor. Therefore, pixel miniaturization with less noise characteristic degradation can be achieved.

[0193] like Figure 6 , which shows the channel width W of the p-type transistors Tp1 and Tp2. The channel regions CHtp of the p-type transistors Tp1 and Tp2 do not have a concavo-convex shape along a direction substantially perpendicular to the channel length direction Dcp. That is, the extension of the groove 141 to the channel width W is smaller than the extension of the channel length L.

[0194] In addition, a gate insulating film (gate oxide film) 150 is provided around the hollowed-out portion of the gate electrode Gtp. An insulating film 170 or 180 is provided as a sidewall insulating film on the top of the gate electrode Gtp. An insulating film 160 is provided on the substrate. The insulating film 160 is, for example, a shallow trench isolation (STI).

[0195] (Configuration of n-type transistors Tn1 and Tn2)

[0196] Figure 7 is a diagram showing an example of the configuration of n-type transistors Tn1 and Tn2 according to the first embodiment. Figure 7 The upper part shows a plan view. Figure 7 The lower part shows the Figure 7 The cross-sectional view corresponds to a cross-sectional view taken along line BB' of the plan view. Figure 7 The lower part shows the Figure 7 The cross-sectional view corresponds to a cross-sectional view taken along line AA' of the plan view.

[0197] The n-type transistors Tn1 and Tn2 have a channel region CHtn extending in a direction substantially perpendicular to the surface of the substrate. In addition, the channel region CHtn of the n-type transistors Tn1 and Tn2 has a concave-convex shape along a direction substantially perpendicular to the channel length direction Dcn. That is, the channel region CHtn of the n-type transistors Tn1 and Tn2 has at least one concave portion (groove or hollowed-out portion) 142 substantially perpendicular to the substrate surface along a direction substantially perpendicular to the channel length direction Dcn. Figure 7 In the example shown, three recesses 142 are provided.

[0198] The recess 142 includes two side surfaces Ss3 and Ss4 and a bottom surface Sb2. The side surfaces Ss3 and Ss4 are surfaces substantially perpendicular to the substrate surface. The bottom surface Sb2 is a surface substantially parallel to the substrate surface.

[0199] The effective channel width W (Weff) is the length along the recess 142. That is, the channel width W can extend a certain distance along the side surfaces Ss3 and Ss4. Therefore, the transconductance gm of the n-type transistors Tn1 and Tn2 can be increased, and the noise can be reduced. In addition, since the distance in the depth direction of the substrate is used, the channel width W can be extended without increasing the mounting area (gate size) of the transistor. Therefore, pixel miniaturization with less noise characteristic degradation can be achieved.

[0200] like Figure 7 , which shows the channel length L of the n-type transistors Tn1 and Tn2. The channel regions CHtn of the n-type transistors Tn1 and Tn2 do not have a concavo-convex shape along the channel length direction Dcn. That is, the extension of the concave portion 142 to the channel length L is smaller than the extension of the channel width W.

[0201] In addition, a gate insulating film (gate oxide film) 150 is provided around the hollowed-out portion of the gate electrode Gtn. An insulating film 170 or 180 is provided as a sidewall insulating film on the top of the gate electrode Gtp. An insulating film 160 is provided on the substrate. The insulating film 160 is, for example, a shallow trench isolation (STI).

[0202] In the first embodiment, the thickness Tgp of the gate insulating film 150 of the p-type transistors Tp1 and Tp2 is substantially the same as the thickness Tgn of the gate insulating film 150 of the n-type transistors Tn1 and Tn2 .

[0203] Figure 8 1 is a schematic plan view showing an example of a planar layout of the first substrate 100. The photodiodes PD are separated by element isolation portions deep trench isolation (DTI) penetrating the first substrate 100. Figure 8 , four photodiodes PD are shown, but the present invention is not limited thereto. The photodiode PD is provided in the element formation region RA.

[0204] The element formation region RA is provided between adjacent contact regions RCNT and is a region for forming a semiconductor element such as a transistor. The contact region RCNT is a region for forming a contact such as a TSV.

[0205] The transfer transistor TG is provided on one side of the photodiode PD, and the overflow gate OF is provided on the other side of the photodiode PD.

[0206] The well contact WCNT is a contact provided for applying a well potential to a well diffusion layer (not shown) formed on the first substrate 100 .

[0207] Fig. 9 is a schematic plan view showing an example of the plan layout of the second substrate 200. Note that Fig. 9 Also with Figure 8 A diagram showing a second substrate 200 including transistors Tn1 to Tn4, Tp1, and Tp2 in a manner overlapped with the first substrate 100. The second substrate 200 includes element formation regions RAn and RAp and a contact region RCNT. When the first substrate 100 and the second substrate 200 are laminated, the element formation regions RAn and RAp and the contact region RCNT of the second substrate 200 are arranged to correspond to the element formation region RA and the contact region RCNT of the first substrate 100, respectively. In addition, Fig. 9 In the embodiment, the n-type transistor Tn4 is omitted.

[0208] The n-type transistors Tn1 to Tn4 are formed in the element forming region RAn, and the p-type transistors Tp1 and Tp2 are formed in the element forming region RAp. As described above, the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 are respectively arranged in different element forming regions RAn and RAp. The transistors Tn1 to Tn4, Tp1 and Tp2 are arranged above the photodiode PD of the first substrate 100, and overlap with the photodiode PD when viewed from the surface of the second substrate 200.

[0209] In the second substrate 200 and the first substrate 100, each contact of the contact region RCNT is arranged to correspond to each other. These contact CNTs are composed of, for example, TSVs. For example, the contact CNTs of the first substrate 100 and the contact CNTs of the second substrate 200 are wire-bonded using CCC.

[0210] This planar layout of the first substrate 100 and the second substrate 200 realizes Figure 51 and 2. The pixel sharing unit 539 and the comparator unit 210 are shown in FIG. 1 . The pixel sharing unit 539 is provided on the first substrate 100, and the comparator unit 210 is provided on the second substrate 200 different from the first substrate 100. The first substrate 100 and the second substrate 200 are laminated, and the pixel sharing unit 539 and the comparator unit 210 are electrically connected through a wiring junction CCC between a wiring of the first substrate 100 and a wiring of the second substrate 200. Note that the pixel sharing unit 539 and the comparator unit 210 may be electrically connected through a through electrode penetrating the first substrate 100 or the second substrate 200.

[0211] Here, the channel length direction Dcp of the p-type transistors Tp1 and Tp2 and the channel length direction Dcn of the n-type transistors Tn1 and Tn2 are Fig. 9 That is, Fig. 9 The channel length direction of the transistors Tp1, Tp2, Tn1 and Tn2 shown is Figure 6 and Figure 7 The channel length directions of transistors Tp1, Tp2, Tn1 and Tn2 shown in the plan view are the same. Figure 6 As described above, by providing the recess 141, the effective channel length L (Leff) of the p-type transistors Tp1 and Tp2 can be extended relative to the size on the layout. Figure 7 As described above, by providing the recessed portion 142 , the effective channel width W (Weff) of the n-type transistors Tn1 and Tn2 can be extended with respect to the size on the layout.

[0212] The n-type transistors Tn3 and Tn4 may also be provided with a recess 142. Therefore, the n-type transistors Tn3 and Tn4 may be formed in the same process as the n-type transistors Tn1 and Tn2. However, the recess 142 may not be provided in the n-type transistors Tn3 and Tn4.

[0213] As described above, according to the first embodiment, the n-type transistors Tn1 and Tn2 have a channel region CHtn extending in a direction substantially perpendicular to the substrate surface. Specifically, the channel region CHtn of the n-type transistors Tn1 and Tn2 has a concave-convex shape along a direction substantially perpendicular to the channel length direction Dcn. By using a direction substantially perpendicular to the substrate surface, the channel width W can be extended without considering the mounting area (gate size) of the transistor. Therefore, the transconductance gm of the n-type transistors Tn1 and Tn2 can be increased to reduce noise while suppressing the increase in the mounting area (gate size) of the transistor. In addition, pixel miniaturization (high resolution) with noise characteristic degradation suppressed becomes possible.

[0214] In addition, in the first embodiment, the p-type transistors Tp1 and Tp2 have a channel region CHtp extending in a direction substantially perpendicular to the surface of the substrate. More specifically, the channel region CHtp of the p-type transistors Tp1 and Tp2 has a concave-convex shape along the channel length direction Dcp. By using a direction substantially perpendicular to the substrate surface, the channel length L can be extended without considering the mounting area (gate size) of the transistor. Therefore, the transconductance gm of the p-type transistors Tp1 and Tp2 can be reduced and the noise can be reduced while suppressing the increase in the mounting area (gate size) of the transistor. In addition, pixel miniaturization (high resolution) with suppressed noise characteristic degradation becomes possible.

[0215] Note that either the concavoconvex shape (concave portion 141) of the channel region CHtn of the n-type transistors Tn1 and Tn2 or the concavoconvex shape (concave portion 142) of the channel region CHtp of the p-type transistors Tp1 and Tp2 may be provided. However, by providing the concavoconvex portions 141 and 142, noise characteristics can be further improved.

[0216] The number of the recesses 141 and 142 is not limited to Figure 6 and Figure 7 The transconductance gm can be adjusted by adjusting the number and depth of the recesses 141 and 142 .

[0217] (Modification of First Embodiment)

[0218] Fig.10 1 is a diagram showing an example of the configuration of p-type transistors Tp1 and Tp2 according to a modification of the first embodiment. Modification of the First Embodiment Compared with the first embodiment, the relationship between the thicknesses Tgp and Tgn of the gate insulating film 150 is different.

[0219] The transconductance gm varies according to the thickness of the gate insulating film 150. For example, the transconductance gm decreases as the thickness of the gate insulating film 150 increases.

[0220] Fig.10 The thickness Tgp2 of the gate insulating film 150 of the p-type transistors Tp1 and Tp2 shown is greater than Figure 6 The thickness Tgp of the gate insulating film 150 of the p-type transistors Tp1 and Tp2 is shown.

[0221] The other configuration of the imaging apparatus 1 according to the modification of the first embodiment is similar to the configuration corresponding to the imaging apparatus 1 according to the first embodiment, and therefore a detailed description thereof will be omitted.

[0222] In a modification of the first embodiment, the thickness of the gate insulating film 150 is different between the p-type transistors Tp1 and Tp2 and the n-type transistors Tn1 and Tn2. More specifically, the gate insulating film 150 of the p-type transistors Tp1 and Tp2 is thicker than the gate insulating film 150 of the n-type transistors Tn1 and Tn2. That is, Fig.10 The thickness Tgp2 of the gate insulating film 150 of the p-type transistors Tp1 and Tp2 shown is greater than Figure 7 The thickness Tgn of the gate insulating film 150 of the n-type transistors Tn1 and Tn2 is shown. Therefore, the ratio of the transconductance gm of the p-type transistors Tp1 and Tp2 constituting the current mirror circuit 210a to the transconductance gm of the n-type transistors Tn1 and Tn2 constituting the differential circuit 210b can be reduced.

[0223] In the modification of the first embodiment, by using the thickness of the gate insulating film 150, the size of the transconductance gm can be adjusted regardless of the mounting area (gate size) of the transistor. Therefore, noise can be reduced by reducing the ratio of the transconductance gm of the p-type transistors Tp1 and Tp2 to the transconductance gm of the n-type transistors Tn1 and Tn2 while suppressing the increase in the mounting area (gate size) of the transistor. In addition, pixel miniaturization (high resolution) with suppressed noise characteristic degradation becomes possible.

[0224] As in the modification of the first embodiment, the thickness of the gate insulating film 150 may be different between the p-type transistors Tp1 and Tp2 and the n-type transistors Tn1 and Tn2. In this case, the same effect as in the first embodiment can also be obtained. Note that in the modification of the first embodiment, the recesses 141 and 142 do not necessarily have to be provided. However, by both the configuration of the recesses 141 and 142 and the adjustment of the thickness of the gate insulating film 150, the noise characteristics can be further improved.

[0225] (Second Embodiment)

[0226] Figures 11 to 14 is a plan view showing a configuration example of p-type transistors Tp1 and Tp2. Figures 11 to 14 In FIG. 1 , one of the transistors Tp1 and Tp2 is shown, and the schematic diagram of the other configuration is omitted. The transistors Tp1 and Tp2 may have the same configuration. In addition, the transistors Tp1 and Tp2 may be Figures 11 to 14 A combination of any two of the configurations shown.

[0227] Fig.11 and Fig.12A 45-degree notch substrate W45 is shown. The 45-degree notch substrate W45 is a silicon substrate having a face ((100) crystal plane) with a crystal orientation of (100). Transistors Tp1 and Tp2 are disposed on the 45-degree notch substrate W45 and include a source region S, a drain region D, and a gate electrode Gtp. The channel region CHtp is disposed between the source region S and the drain region D. The gate electrode Gtp covers the bottom surface Sb1 and the side surfaces Ss1 and Ss2 of the recess 141 in the channel region CHtp via a gate insulating film (not shown). The gate electrode Gtp is electrically insulated from the channel region CHtp by the gate insulating film. The bottom surface Sb1 or the side surfaces Ss1 and Ss2 of the recess 141 in the channel region CHtp of the transistors Tp1 and Tp2 are in a plane substantially parallel to the (100) crystal plane of the substrate W45 on the surface of the substrate W45.

[0228] By applying a voltage to the gate electrode Gtp, the bottom surface Sb1 of the recess 141 in the channel region CHtp is reversed with the side surfaces Ss1 and Ss2, and the source region S is conductive with the drain region D. Therefore, the current flows in the channel region CHtp in the D1 direction. The D1 direction is the direction in which the current flows in the transistors Tp1 and Tp2, and is also the channel length direction of the transistors Tp1 and Tp2. The D1 direction is a direction that is approximately perpendicular or approximately parallel to the (100) crystal plane of the substrate W45. That is, the channel length direction of the transistors Tp1 and Tp2 is approximately parallel or approximately perpendicular to the (100) crystal plane (cut plane) of the substrate W45 on the surface of the substrate W45.

[0229] Fig.13 and Fig.14 A 0-degree notch substrate W0 having a plane with a crystal orientation (100) is shown. Transistors Tp1 and Tp2 are disposed on the 0-degree notch substrate W0 and include a source region S, a drain region D, and a gate electrode Gtp. A channel region CHtp is disposed between the source region S and the drain region D. The gate electrode Gtp covers the bottom surface Sb1 and the side surfaces Ss1 and Ss2 of the recess 141 in the channel region CHtp via a gate insulating film (not shown). The gate electrode Gtp is electrically insulated from the channel region CHtp by the gate insulating film. The bottom surface Sb1 or the side surfaces Ss1 and Ss2 of the recess 141 in the channel region CHtp of the transistors Tp1 and Tp2 are in a plane inclined at about 45 degrees or about 135 degrees relative to the (110) crystal plane (notch plane) of the substrate W0 on the surface of the substrate W0.

[0230] By applying a voltage to the gate electrode Gtp, the bottom surface Sb1 of the recess 141 in the channel region CHtp is reversed with the side surfaces Ss1 and Ss2, and the source region S is conductive with the drain region D. Therefore, the current flows in the channel region CHtp in the direction D2. The direction D2 is the direction in which the current flows in the transistors Tp1 and Tp2, and is also the channel length direction of the transistors Tp1 and Tp2. The D2 direction is a direction that is approximately perpendicular or approximately parallel to the (100) crystal plane of the substrate W0. That is, the channel length direction of the transistors Tp1 and Tp2 is about 45 degrees or about 135 degrees relative to the (110) crystal plane (cut plane) of the substrate W45 on the surface of the substrate W0.

[0231] Here, the transconductance gm decreases as the carrier mobility of the transistor decreases. On the other hand, the transconductance gm increases as the carrier mobility of the transistor increases. The mobility of the n-type transistor hardly depends on the direction of the (100) crystal plane or the (110) crystal plane relative to the substrate. On the other hand, the mobility of the p-type transistor changes according to the direction of the (100) crystal plane or the (110) crystal plane relative to the substrate. Therefore, the noise can be reduced by reducing the mobility of the p-type transistors Tp1 and Tp2 to reduce the transconductance gm.

[0232] In the case of a 45 degree notch substrate W45, as Fig.11 or Fig.12 As shown, the channel length direction (D1 direction) of the transistors Tp1 and Tp2 is substantially perpendicular or substantially parallel to the (100) crystal plane (cut plane) of the substrate W45 on the surface F45 of the substrate W45. In the case of a 0-degree notch substrate W0, as shown in FIG. Fig.13 As shown in FIG. 14, the channel length direction (D1 direction) of the transistors Tp1 and Tp2 is inclined at about 45 degrees or about 135 degrees relative to the (110) crystal plane (notch plane) of the substrate W0 on the front surface F0 of the substrate W0. In this case, the carrier mobility is relatively low.

[0233] On the other hand, in the case of a 45-degree notch substrate W45, the channel length direction (D1 direction) of the transistors Tp1 and Tp2 is inclined at about 45 degrees or about 135 degrees relative to the (100) crystal plane (notch plane) of the substrate W45 on the front surface F45 of the substrate W45. In the case of a 0-degree notch substrate W0, the channel length direction (D1 direction) of the transistors Tp1 and Tp2 is approximately perpendicular or approximately parallel to the (110) crystal plane (notch plane) of the substrate W0 on the surface F0 of the substrate W0. In this case, the carrier mobility is relatively high.

[0234] As described above, in the case where the channel length direction is substantially perpendicular or substantially parallel to the (100) crystal plane (cut plane) of the substrate W45, the carrier mobility of the p-type transistors Tp1 and Tp2 is much lower than in the case where the channel length direction is inclined by approximately 45 degrees or approximately 135 degrees relative to the (100) crystal plane (cut plane) of the substrate W45. That is, the transconductance gm of the p-type transistors Tp1 and Tp2 can be reduced.

[0235] By reducing the transconductance gm of the p-type transistors Tp1 and Tp2, noise is reduced and noise characteristics are improved. For example, the signal-to-noise ratio (S / N) is improved, and the dynamic range can be expanded. Therefore, the sensor characteristics of the solid-state imaging device according to the present embodiment are improved.

[0236] In the n-type transistors Tn1 and Tn2, the inclination angle of the bottom surface Sb2 and the side surfaces Ss3 and Ss4 of the recess 142 in the channel region relative to the crystal plane of the substrate hardly changes the transconductance gm of the n-type transistors Tn1 and Tn2. The higher the transconductance gm of the n-type transistors Tn1 and Tn2, the more the noise characteristics are improved. However, the transconductance gm of the n-type transistors Tn1 and Tn2 does not change much according to the inclination angle of the upper surface or side surface of the channel region relative to the crystal plane of the substrate. Therefore, the change of the channel length direction (D1) of the n-type transistors Tn1 and Tn2 relative to the crystal plane of the substrate does not contribute much to the improvement of, for example, the S / N ratio and the dynamic range.

[0237] In this embodiment, based on the above-mentioned understanding, only the channel length direction of the p-type transistors Tp1 and Tp2 is formed into a plane that is approximately parallel to or approximately perpendicular to the (100) crystal plane of the substrate W45. Therefore, the transconductance gm of the p-type transistors Tp1 and Tp2 can be reduced, and the noise characteristics can be effectively improved. Therefore, a high-resolution image with less noise characteristic degradation can be obtained.

[0238] (Third Embodiment)

[0239] Fig.15 is a conceptual diagram showing a configuration example of a solid-state imaging device according to a third embodiment. The second embodiment is similar to the first embodiment in that the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 of the comparator section 210 are arranged on the same substrate. However, in the first embodiment, the photodiode PD is formed on the first substrate 100, and the comparator section 210 is formed on a second substrate 200 that is different from the first substrate 100. On the other hand, in the third embodiment, the comparator section 210 is formed on the same first substrate 100 as the photodiode PD, and is formed to be laminated above the photodiode PD. Note that here, the light receiving surface of the first substrate 100 is represented as "down" in the up and down directions. Therefore, in Fig.15, the +Z direction is the "upward direction".

[0240] Therefore, the connection between the photodiode PD and the comparator section 210 can be made as follows Fig.16 The contact plug PLG is shown configured without CCC. Fig.16 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539 and the comparator section 210 according to the third embodiment. The comparator section 210 is formed on the same first substrate 100 as the photodiode PD. Therefore, a contact plug PLG is formed between the comparator section 210 and the photodiode PD. The contact plug PLG passes through the interlayer insulating film between the comparator section 210 and the photodiode PD to electrically connect them. A plurality of wiring junctions CCC between the substrates 100 and 200 are not formed between the comparator section 210 and the photodiode PD. Therefore, it is advantageous for miniaturization of the photodiode PD and the comparator section 210. In addition, one wiring junction CCC between the first substrate 100 and the second substrate 200 is sufficient to connect from the photodiode PD to the logic circuit (column signal processing section 550) after the comparator section 210. Therefore, the noise characteristics are improved.

[0241] (Fourth Embodiment)

[0242] Fig.17 is a conceptual diagram showing a configuration example of a solid-state imaging device according to a fourth embodiment. The fourth embodiment is different from the first to third embodiments in that the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 of the comparator section 210 are arranged on different substrates. For example, the n-type transistors Tn1 to Tn4 of the comparator section 210 are formed on the same first substrate 100 as the photodiode PD, and are formed in the semiconductor layer above the photodiode PD. On the other hand, the p-type transistors Tp1 and Tp2 of the comparator section 210 are formed on a second substrate 200 different from the first substrate 100.

[0243] Fig.18 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539 and the comparator section 210 according to the fourth embodiment. In the comparator section 210, n-type transistors Tn1 to Tn4 including the differential circuit 210b are formed on the same first substrate 100 as the photodiode PD. The n-type transistors Tn1 to Tn4 are arranged above the photodiode PD. Therefore, a contact plug PLG is formed between the differential circuit 210b of the comparator section 210 and the photodiode PD. The contact plug PLG passes through the interlayer insulating film between the comparator section 210 and the photodiode PD to electrically connect them. A wiring junction CCC between a plurality of substrates 100 and 200 is not formed between the comparator 210 and the photodiode PD. Therefore, it is advantageous for miniaturization of the photodiode PD and the comparator 210.

[0244] On the other hand, in the comparison section 210, the p-type transistors Tp1 and Tp2 constituting the current mirror circuit 210a are formed on the second substrate 200 different from the first substrate 100. Therefore, the differential circuit 210b and the current mirror circuit 210a in the comparator 210 are respectively provided on separate substrates 100 and 200. Two wiring junctions CCC are provided between the current mirror circuit 210a and the differential circuit 210b. That is, a plurality of wiring junctions CCC are used at one interface between the first substrate 100 and the second substrate 200.

[0245] One wiring junction CCC is used for one interface between the second substrate 200 and the third substrate 300 from the photodiode PD to the logic circuit (column signal processing section 550 ) after the comparator 210 .

[0246] As described above, in the fourth embodiment, the p-type transistors Tp1 and Tp2 and the n-type transistors Tn1 to Tn4 of the comparator 210 are formed on separate substrates 100 and 200. Therefore, the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 can be formed in separate semiconductor manufacturing processes. Therefore, the semiconductor manufacturing process can be simplified.

[0247] (Fifth Embodiment)

[0248] Fig.19 is a conceptual diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment. In the fifth embodiment, the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 of the comparator 210 are arranged on the same substrate. However, the n-type transistors Tn1 to Tn4 of the comparator 210 are formed on the first substrate 100 in the same semiconductor manufacturing process as the photodiode PD, the transfer transistor TG, and the overflow gate OF, and are arranged in the same semiconductor layer as the transfer transistor TG and the overflow gate OF. On the other hand, in the comparator 210, the p-type transistors Tp1 and Tp2 constituting the current mirror circuit 210a are formed to be laminated on another semiconductor layer above the photodiode PD, the transfer transistor TG, the overflow gate OF, and the n-type transistors Tn1 to Tn4 (differential circuit 210b).

[0249] Therefore, if Fig. 20 As shown, the connection between the photodiode PD and the n-type transistors Tn1 to Tn4 of the comparator 210 may include common wiring W and contacts (not shown). Fig. 20is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539 and the comparator section 210 according to the fifth embodiment. The comparator 210 is formed on the same first substrate 100 as the photodiode PD. Therefore, a wiring W is formed between the comparator 210 and the photodiode PD. The wiring W electrically connects the comparator 210 and the photodiode PD. A plurality of wiring junctions CCC between the substrates 100 and 200 are not formed between the comparator 210 and the photodiode PD. Therefore, it is advantageous for miniaturization of the photodiode PD and the comparator 210.

[0250] In addition, the length of the wiring W between the floating diffusion FD and the input of the differential circuit 210b is shortened, and the capacity of the wiring is reduced. Therefore, the conversion efficiency of the potential of the floating diffusion FD is improved, and the noise characteristics are improved.

[0251] In the comparator 210, a contact plug PLG is formed between the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2. The contact plug PLG passes through the interlayer insulating film between the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2 to electrically connect them. Note that the wiring junctions CCC between the plurality of substrates 100 and 200 are not formed between the n-type transistors Tn1 to Tn4 and the p-type transistors Tp1 and Tp2. Therefore, it is advantageous for miniaturization of the photodiode PD and the comparator 210.

[0252] (Sixth Embodiment)

[0253] Fig.21 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539 and the comparator section 210 according to the sixth embodiment. In the sixth embodiment, the current mirror circuit 210a includes n-type transistors Tn11 and Tn12, and the differential circuit 210b includes p-type transistors Tp11 and Tp12. In this case, in order to improve the noise characteristics, the transconductance gm of the p-type transistors Tp11 and Tp12 of the differential circuit 210b is preferably large. Note that a voltage VRHW equal to or higher than the power supply VDD is applied to the transistors Tp11 to Tp14 as a reverse bias.

[0254] In the sixth embodiment, by reducing the transconductance gm of the n-type transistors Tn11 and Tn12 constituting the current mirror circuit 210a, the noise is reduced and the noise characteristics are improved. On the other hand, by increasing the transconductance gm of the p-type transistors Tp11 and Tp12 constituting the differential circuit 210b, the noise is reduced and the noise characteristics are improved.

[0255] Fig. 22 is a diagram showing an example of the configuration of p-type transistors Tp11 and Tp12 according to the sixth embodiment. Fig. 22 The upper part shows a plan view. Fig. 22 The lower part shows the Fig. 22 The cross-sectional view corresponds to a cross-sectional view taken along line BB' of the plan view. Fig. 22 The lower part shows the Fig. 22 The cross-sectional view corresponds to a cross-sectional view taken along line AA' of the plan view.

[0256] The p-type transistors Tp11 and Tp12 have a channel region CHtp extending in a direction substantially perpendicular to the surface of the substrate. In addition, the channel region CHtp of the p-type transistors Tp11 and Tp12 has a concave-convex shape along a direction substantially perpendicular to the channel length direction Dcp. That is, Fig. 22 The configuration of the p-type transistors Tp11 and Tp12 shown is similar to Figure 7 The n-type transistors Tn1 and Tn2 shown have substantially the same configuration.

[0257] Fig.23 is a diagram showing an example of the configuration of n-type transistors Tn11 and Tn12 according to the sixth embodiment. Fig.23 The upper part shows a plan view. Fig.23 The lower part shows the Fig.23 The cross-sectional view corresponds to a cross-sectional view taken along line BB' of the plan view. Fig.23 The lower part shows the Fig.23 The cross-sectional view corresponds to a cross-sectional view taken along line AA' of the plan view.

[0258] The n-type transistors Tn11 and Tn12 have a channel region CHtn extending in a direction substantially perpendicular to the surface of the substrate. In addition, the channel region CHtn of the n-type transistors Tn11 and Tn12 has a concave-convex shape along the channel length direction Dcn. That is, Fig.23 The configuration of the n-type transistors Tn11 and Tn12 shown is similar to Figure 6 The configurations of the p-type transistors Tp1 and Tp2 shown are substantially the same.

[0259] In the sixth embodiment, similar to the first embodiment, the configuration and arrangement of the p-type transistors Tp11 and Tp12 and the n-type transistors Tn11 and Tn12 make it possible to improve the noise characteristic (S / N) and achieve pixel miniaturization (high resolution) with suppressed noise characteristic degradation.

[0260] Here, as described in the second embodiment, the mobility of the p-type transistor changes depending on the direction of the (100) crystal plane or the (110) crystal plane relative to the substrate. Therefore, the noise can be reduced by increasing the mobility of the p-type transistors Tp11 and Tp12 constituting the differential circuit 210b to increase the transconductance gm.

[0261] Figure 24 to Figure 27is a plan view showing a configuration example of p-type transistors Tp11 and Tp12. Figure 24 to Figure 27 In FIG. 1 , one of the transistors Tp11 and Tp12 is shown, and the schematic diagram of the other configuration is omitted. The transistors Tp11 and Tp12 may have the same configuration. In addition, the transistors Tp11 and Tp12 may be Figure 24 to Figure 27 A combination of any two of the configurations shown.

[0262] exist Fig.24 and Fig.25 , transistors Tp11 and Tp12 are arranged on a 0-degree notch substrate W0. The bottom surface Sb2 or side surfaces Ss3 and Ss4 of the recess 142 in the channel region CHtp of the transistors Tp11 and Tp12 are in a plane on the surface of the substrate W0 that is approximately parallel to or approximately perpendicular to the (110) crystal plane of the substrate W0. The D1 direction is a direction that is approximately perpendicular to or approximately parallel to the (110) crystal plane of the substrate W0. That is, the channel length direction of the transistors Tp11 and Tp12 is approximately parallel to or approximately perpendicular to the (110) crystal plane (notch surface) of the substrate W0 on the surface of the substrate W0. Therefore, the transconductance gm of the transistors Tp11 and Tp12 becomes relatively large.

[0263] exist Fig.26 and Fig. 27 , transistors Tp11 and Tp12 are arranged on a 45-degree notch substrate W45. The bottom surface Sb2 or the side surfaces Ss3 and Ss4 of the recess 142 in the channel region CHtp of the transistors Tp11 and Tp12 are in a plane inclined at about 45 degrees or about 135 degrees relative to the (100) crystal plane of the substrate W45 on the surface of the substrate W45. The D1 direction is a direction inclined at about 45 degrees or about 135 degrees relative to the (100) crystal plane of the substrate W45. That is, the channel length direction of the transistors Tp11 and Tp12 is a direction inclined at about 45 degrees or about 135 degrees relative to the (100) crystal plane (notch plane) of the substrate W45 on the surface of the substrate W45. Therefore, the transconductance gm of the transistors Tp11 and Tp12 becomes relatively large.

[0264] Therefore, even in the case where the conductivity types of transistors constituting the current mirror circuit 210 a and the differential circuit 210 b are opposite to those of the transistors of the first embodiment, effects similar to those of the second embodiment can be obtained.

[0265] Figures 28 to 30 1 is a diagram showing an embodiment in which the third to fifth embodiments are respectively combined with the sixth embodiment. The conductivity types of transistors constituting the current mirror circuit 210a and the differential circuit 210b of the third to fifth embodiments are reversed. The p-type transistors Tp11 and Tp12 of the differential circuit 210b may have the same configuration as the transistors of the sixth embodiment.

[0266] Therefore, even in the case where the conductivity type of transistors constituting the current mirror circuit 210a and the differential circuit 210b is opposite to that of the transistors in the third to fifth embodiments, effects similar to those in each of the third to fifth embodiments can be obtained.

[0267] Note that the sixth embodiment may also be combined with a modification of the first embodiment. In this case, the gate insulating film 150 of the n-type transistors Tn11 and Tn12 is thicker than the gate insulating film 150 of the p-type transistors Tp11 and Tp12.

[0268] (Seventh Embodiment)

[0269] Fig.31 1 is a schematic cross-sectional view showing the configuration of a pixel sharing unit 539, a column signal processing section 550, and a pixel signal processing section 560 according to a seventh embodiment. The seventh embodiment is different from the first embodiment in that the electrical connection between the first substrate 100 and the second substrate 200 is performed by a wiring junction CCC instead of a through-hole contact VIA.

[0270] As in the seventh embodiment, the electrical connection between the first substrate 100 and the second substrate 200 may be performed by the wiring junction CCC instead of the through-hole contact VIA. In this case, similar effects to those of the first embodiment can also be obtained.

[0271] (Other changes)

[0272] Hereinafter, a solid-state imaging device to which any of the above-described embodiments is applicable will be described. The present embodiment can also be applied to the following solid-state imaging devices.

[0273] Fig.32 5 is an equivalent circuit diagram showing an example of the configuration of the pixel sharing unit 539. The pixel sharing unit 539 includes a plurality of pixels 541 ( Fig.32541A, 541B, 541C, and 541D), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 5433 connected to the pixel circuit 210 are shown. In the following, the comparator section 210 may be considered to be included in the pixel circuit. In addition to the comparator section, the pixel circuit 210 includes, for example, four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switch transistor FD. As described above, the pixel sharing unit 539 sequentially outputs the pixel signals of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel sharing unit 539 to the vertical signal line 543 by operating the one pixel circuit 210 in a time-division manner. A mode in which one pixel circuit 210 is connected to a plurality of pixels 541, and the pixel signals of the plurality of pixels 541 are output by the one pixel circuit 210 in a time-division manner is referred to as "a plurality of pixels 541 share one pixel circuit 210".

[0274] Pixels 541A, 541B, 541C, and 541D have common components. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D, identification number 1 is given to the end of the reference number of the component of pixel 541A, identification number 2 is given to the end of the reference number of the component of pixel 541B, identification number 3 is given to the end of the reference number of the component of pixel 541C, and identification number 4 is given to the end of the reference number of the component of pixel 541D. In the case where it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D, the identification number at the end of the reference number of the components of pixels 541A, 541B, 541C, and 541D is omitted.

[0275] Pixels 541A, 541B, 541C, and 541D include, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. Hereinafter, the transfer transistor TG is also referred to as a transfer transistor TR. In the photodiode PD (PD1, PD2, PD3, or PD4), the cathode is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD photoelectrically converts incident light and generates charges corresponding to the amount of light received. The transfer transistor TR (transfer transistor TR1, TR2, TR3, or TR4) is, for example, an n-type complementary metal oxide semiconductor (CMOS) transistor. In the transfer transistor TR, the drain is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. The drive signal line is a plurality of row drive signal lines 542 (see Figure 1). The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusion FD1, FD2, FD3, or FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding device that temporarily holds the charge transferred from the photodiode PD, and is a charge-voltage conversion device that generates a voltage corresponding to the charge amount.

[0276] Four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel sharing unit 539 are electrically connected to each other, and are electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switch transistor FDG. The drain of the FD conversion gain switch transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switch transistor FDG is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one pixel sharing unit 539 .

[0277] When the transfer transistor TR is turned on, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. The gate of the transfer transistor TR (transfer gate TG) includes, for example, a so-called vertical electrode and is provided from the semiconductor layer (described later) to the floating diffusion FD. Fig.34 The surface of the semiconductor layer 100S in the embodiment extends to a surface to be described later. Fig.34 The depth of the PD shown. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. The reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply line VDD when turned on. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a signal of a voltage corresponding to the level of the charge held in the floating diffusion FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. The amplifier transistor AMP is connected to the load circuit section (see Figure 1) together constitute a source follower. When the selection transistor SEL is turned on, the amplifier transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. For example, the reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are N-type CMOS transistors.

[0278] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion in the floating diffusion FD. Generally, the pixel signal is small when imaging in a dark place. If the capacitance (FD capacitance C) of the floating diffusion FD is large when the charge-voltage conversion is performed based on Q=CV, V becomes smaller when it is converted into a voltage by the amplifier transistor AMP. On the other hand, in a bright place, because the pixel signal becomes larger, the floating diffusion FD cannot receive the charge of the photodiode PD unless the FD capacitance C is large. In addition, the FD capacitance C needs to be large so that V does not become too large (in other words, becomes smaller) when it is converted into a voltage by the amplifier transistor AMP. In view of this, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, so that the total FD capacitance C increases. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the total FD capacitance C decreases. In this way, by turning on and off the FD conversion gain switching transistor FDG, the FD capacitance C can be made variable, and the conversion efficiency can be switched. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0279] Note that a configuration in which the FD conversion gain switch transistor FDG is not provided is also possible. In this case, for example, the pixel circuit 210 includes three transistors, for example, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. For example, the pixel circuit 210 includes at least one of the pixel transistors such as the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switch transistor FDG.

[0280] The selection transistor SEL may be provided between the power supply line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542 (see Figure 1 ). The source of the amplifier transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. Note that, although not shown, the number of pixels 541 that share one pixel circuit 210 may not be four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0281] Fig.33 An example of a connection mode between a plurality of pixel sharing units 539 and a vertical signal line 543 is shown. For example, four pixel sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For ease of description, Fig.33 An example is shown in which four groups each have one pixel sharing unit 539, but the four groups each may include a plurality of pixel sharing units 539. As described above, in the imaging device 1, a plurality of pixel sharing units 539 arranged in the column direction may be divided into a group including one or more pixel sharing units 539. For example, a vertical signal line 543 and a column signal processing circuit 550 are connected to each group, and pixel signals may be read from each group at the same time. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to a plurality of pixel sharing units 539 arranged in the column direction. At this time, pixel signals are sequentially read from a plurality of pixel sharing units 539 connected to one vertical signal line 543 in a time-division manner.

[0282] [Specific Configuration of Imaging Device 1]

[0283] Fig.34 An example of a cross-sectional configuration in a direction perpendicular to the main surfaces of the first substrate 100 , the second substrate 100 , and the third substrate 300 of the imaging apparatus 1 is shown. Fig.34 The positional relationship of the components is schematically shown for ease of understanding and may be different from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200 and the third substrate 300 are laminated in this order. The imaging device 1 also includes a light receiving lens 401 on the rear surface side (light incident surface side) of the first substrate 100. A color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. The light receiving lens 401 is, for example, provided in each of the pixels 541A, 541B, 541C and 541D. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array portion 540 arranged in a central portion and a peripheral portion 540B arranged outside the pixel array portion 540.

[0284] The first substrate 100 includes an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T in order from the light receiving lens 401 side. The semiconductor layer 100S is composed of, for example, a silicon substrate. For example, the semiconductor layer 100S includes a P-well layer 115 in a part of the surface (the surface on the wiring layer 100T side) and its vicinity, and includes an n-type semiconductor region 114 in other regions (regions deeper than the P-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 constitute a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0285] Fig.35A An example of a planar configuration of the first substrate 100 is shown. Fig.35A The planar configuration of the pixel separation portion 117, the photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR of the first substrate 100 is mainly shown. Fig.35A Together with Fig.34 The configuration of the first substrate 100 is described.

[0286] The floating diffusion FD and the VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD includes an n-type semiconductor region provided in the P-well layer 115. The floating diffusion FD (floating diffusion FD1, FD2, FD3, or FD4) of each of the pixels 541A, 541B, 541C, and 541D is provided, for example, close to each other in the central portion ( Fig.35A ). Although the details will be described later, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in the shared unit 539 are electrically connected to each other in the first substrate 100 (more specifically, in the wiring layer 100T) via an electrical connection device (a pad portion 120 described later). In addition, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical device (through an electrode 120E described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switch transistor FDG through the electrical device.

[0287] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is provided separately from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of the V direction of each pixel, and the VSS contact region 118 is arranged at the other end ( Fig.35A ). The VSS contact region 118 includes, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. Therefore, a reference potential is provided to the semiconductor layer 100S.

[0288] The transfer transistor TR is provided on the first substrate 100 together with the photodiode PD, the floating diffusion FD and the VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118 and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C and 541D. The transfer transistor TR is provided on the front surface side (the side opposite to the light incident surface side, the second substrate 200 side) of the semiconductor layer 100S. The transfer transistor TR has a transfer gate TG. The transfer gate TG, for example, includes a horizontal portion TGb facing the surface of the semiconductor layer 100S and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa contacts the horizontal portion TGb, and the other end is provided in the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transmission failure of the pixel signal hardly occurs, and the readout efficiency of the pixel signal can be improved.

[0289] The horizontal portion TGb of the transfer gate TG extends, for example, in the H direction from a position facing the vertical portion TGa toward the center portion of the pixel sharing unit 539 ( Fig.35A ). Therefore, the position of the through electrode (through electrode TGV described later) reaching the transfer gate TG in the H direction can be made close to the position of the through electrodes (through electrodes 120E and 121E described later) connected to the floating diffusion FD and the VSS contact region 118 in the H direction. For example, a plurality of pixel sharing units 539 provided on the first substrate 100 have the same configuration ( Fig.35A ).

[0290] The semiconductor layer 100S is provided with a pixel separation portion 117 that separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed to extend in the normal direction of the semiconductor layer 100S (the direction perpendicular to the surface of the semiconductor layer 100S). The pixel separation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D, and has, for example, a grid-like planar shape ( Fig.35A and Fig.35B). For example, the pixel separation portion 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117, for example, includes a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like is used for the light shielding film 117A. The insulating film 117B is disposed between the light shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is composed of, for example, silicon oxide (SiO). The pixel separation portion 117, for example, has a full trench isolation (FTI) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separation portion 117 is not limited to the FTI structure that penetrates the semiconductor layer 100S. For example, a deep trench isolation (DTI) structure that does not penetrate the semiconductor layer 100S can be used. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a portion of the semiconductor layer 100S.

[0291] For example, in the semiconductor layer 100S, a first pinning region 113 and a second pinning region 116 are provided. The first pinning region 113 is provided near the rear surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on the side surface of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 115 or the n-type semiconductor region 114. For example, the first pinning region 113 and the second pinning region 116 are composed of p-type semiconductor regions.

[0292] The fixed charge film 112 having negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. By the electric field induced by the fixed charge film 112, the first pinning region 113 of the hole accumulation layer is formed at the interface on the light receiving surface (rear surface) side of the semiconductor layer 100S. Therefore, the generation of dark current due to the interface state on the light receiving surface side of the semiconductor layer 100S is suppressed. The fixed charge film 112 is composed of, for example, an insulating film having negative fixed charge. Examples of the material of the insulating film having negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0293] The light shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. The light shielding film 117A may be provided continuously with the light shielding film 117A constituting the pixel separation portion 117. For example, the light shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided at a position facing the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 111 is provided to cover the light shielding film 117A. The insulating film 111 is composed of, for example, silicon oxide.

[0294] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 includes an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124 in order from the semiconductor layer 100S side. The horizontal portion TGb of the transfer gate TG is provided in the wiring layer 100T, for example. The interlayer insulating film 119 is provided on the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is composed of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above, and may be a configuration including wiring and an insulating film.

[0295] Fig.35B The configuration of the pad portions 120 and 121 is shown together with Fig.35A The pad portions 120 and 121 are provided in a selective region on the interlayer insulating film 119. The pad portion 120 is used to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D to each other. For example, in the plan view, for each pixel sharing unit 539 ( Fig.35B ), the pad portion 120 is arranged at the central portion of the pixel sharing unit 539. The pad portion 120 is provided to cross the pixel separation portion 117, and is arranged to overlap at least a portion of each of the floating diffusions FD1, FD2, FD3, and FD4 ( Fig.34 and Fig.35B ). Specifically, the pad portion 120 is formed in a region overlapping at least a portion of the pixel separation portion 117 formed between the multiple photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) of the shared pixel circuit 210 and at least a portion of each of the multiple floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the shared pixel circuit 210 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection through hole 120C for electrically connecting the pad portion 120 and the floating diffusions FD1, FD2, FD3, and FD4. The connection through hole 120C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, by embedding a portion of the pad portion 120 in the connection through hole 120C, the pad portion 120 and the floating diffusions FD1, FD2, FD3, and FD4 are electrically connected.

[0296] The pad portion 121 is used to connect a plurality of VSS contact regions 118 to each other. For example, the VSS contact regions 118 provided in the pixels 541C and 541D of one pixel sharing unit 539 adjacent in the V direction and the VSS contact regions 118 provided in the pixels 541A and 541B of another pixel sharing unit 539 are electrically connected through the pad portion 121. The pad portion 121 is provided, for example, to cross the pixel separation portion 117, and is arranged to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region overlapping with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contacts 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection through hole 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection through hole 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, by embedding a portion of the pad portion 121 in the connection through hole 121C, the pad portion 121 and the VSS contact area 118 are electrically connected. For example, the pad portion 120 and the pad portion 121 of each of the plurality of pixel sharing units 539 arranged in the V direction are arranged at approximately the same position in the H direction ( Fig.35B ).

[0297] By providing the pad portion 120, the number of wirings for connection from each floating diffusion FD to the pixel circuit 210 (e.g., the gate electrode of the amplifier transistor AMP) in the entire chip can be reduced. Similarly, by providing the pad portion 121, the number of wirings for supplying a potential to each VSS contact region 118 in the entire chip can be reduced. Therefore, it is possible to reduce the area of ​​the entire chip, suppress electrical interference between wirings in miniaturized pixels, and / or reduce costs by reducing the number of components, etc.

[0298] The pad portions 120 and 121 may be disposed at desired locations on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 may be disposed in the insulating region 212 of the wiring layer 100T or the semiconductor layer 200S. In the case of being disposed in the wiring layer 100T, the pad portions 120 and 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be directly connected to at least a portion of each of the floating diffusion FD and / or the VSS contact region 118. In addition, connection vias 120C and 121C may be disposed from the floating diffusion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, respectively, and the pad portions 120 and 121 may be disposed at desired locations of the insulating region 2112 of the wiring layer 100T and the semiconductor layer 200S.

[0299] Specifically, in the case where the pad portions 120 and 121 are provided in the wiring layer 100T, the number of wirings connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S can be reduced. Therefore, in the second substrate 200 forming the pixel circuit 210, the area of ​​the insulating region 212 for forming the through wiring connected from the floating diffusion FD to the pixel circuit 210 can be reduced. Therefore, a large area of ​​the second substrate 200 forming the pixel circuit 210 can be ensured. By ensuring the area of ​​the pixel circuit 210, a large pixel transistor can be formed and contribute to image quality improvement by noise reduction and the like.

[0300] In particular, in the case where the FTI structure is used for the pixel separation portion 117, it is preferred to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541. Therefore, by using the configuration of the pad portions 120 and 121, the wiring connecting the first substrate 100 and the second substrate 200 can be greatly reduced.

[0301] In addition, if Fig.35B As shown, for example, a pad portion 120 connected to a plurality of floating diffusions FD and a pad portion 121 connected to a plurality of VSS contacts 118 are alternately arranged in a linear manner in the V direction. In addition, the pad portions 120 and 121 are formed at a position surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusions FD. Therefore, elements other than the floating diffusion FD and the VSS contact region 118 can be freely arranged on the first substrate 100 where a plurality of elements are formed, and the efficiency of the layout of the entire chip can be improved. In addition, the symmetry in the layout of the elements formed in each pixel sharing unit 539 is ensured, and the variation in the characteristics of each pixel 541 can be suppressed.

[0302] The pad portions 120 and 121 are composed of, for example, polysilicon (Poly Si), more specifically, doped polysilicon doped with impurities. The pad portions 120 and 121 are preferably composed of a conductive material with high heat resistance such as polysilicon, tungsten (W), titanium (Ti) or titanium nitride (TiN). Therefore, after the semiconductor layer 200S of the second substrate 200 is bonded to the first substrate 100, the pixel circuit 210 can be formed. Hereinafter, the reason will be described. Note that in the following description, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 and the second substrate 200 is referred to as the first manufacturing method.

[0303] Here, it is also conceivable to form the pixel circuit 210 on the second substrate 200 and then bond it to the first substrate 100 (hereinafter, referred to as the second manufacturing method). In the second manufacturing method, electrodes for electrical connection are pre-formed on each of the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded to each other, the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200 are in contact with each other at the same time. Therefore, an electrical connection is formed between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by adopting the configuration of the imaging device 1 using the second manufacturing method, for example, it can be manufactured using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

[0304] In such a second manufacturing method, when the first substrate 100 and the second substrate 200 are bonded to each other, an alignment error may occur due to the manufacturing equipment used for bonding. In addition, the first substrate 100 and the second substrate 200 have a size of, for example, a diameter of about tens of centimeters, but when the first substrate 100 and the second substrate 200 are bonded to each other, there is a possibility that the extension and contraction of the substrate occurs in the microscopic area of ​​the corresponding parts of the first substrate 100 and the second substrate 200. This extension and contraction of the substrate is caused by a slight deviation in the timing of the contact between the substrates. Due to this extension and contraction of the first substrate 100 and the second substrate 200, an error may occur in the position of the electrode for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200. In the second manufacturing method, even if such an error occurs, it is preferred to take measures to make the electrodes of the first substrate 100 and the second substrate 200 contact each other. Specifically, in view of the above-mentioned error, at least one (preferably, two) of the electrodes of the first substrate 100 and the second substrate 200 is enlarged. Therefore, when the second manufacturing method is used, for example, the size of the electrode formed on the surface of the first substrate 100 or the second substrate 200 (the size in the substrate plane direction) is larger than the size of the internal electrode extending from the inside of the first substrate 100 or the second substrate 200 along the thickness direction to the surface.

[0305] On the other hand, the pad portions 120 and 121 are made of a heat-resistant conductive material so that the above-mentioned first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded to each other. At this time, the second substrate 200 is in a state where a pattern such as an active element and a wiring layer constituting the pixel circuit 210 is not formed. Because the second substrate 200 is in a state before patterning, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded, an error does not occur in the alignment between the pattern of the first substrate 100 and the pattern of the second substrate 200 due to the bonding error. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded. Note that when a pattern is formed on the second substrate, for example, in an exposure device for pattern formation, the pattern is formed while the pattern formed on the first substrate is set as an alignment target. For the above reasons, an error in the bonding position between the first substrate 100 and the second substrate 200 does not cause a problem in manufacturing the imaging device 1 in the first manufacturing method. For similar reasons, an error caused by the extension and contraction of the substrate caused by the second manufacturing method does not cause a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0306] In the first manufacturing method, after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded in this manner, an active element is formed on the second substrate 200. Thereafter, the through electrodes 120E and 121E and the through electrode TGV ( Fig.34 ). When forming the through electrodes 120E, 121E and TGV, for example, the pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure by an exposure device. Since a reduced exposure projection is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error is only a small portion (the inverse of the reduced exposure projection magnification) of the magnitude of the error of the above-mentioned second manufacturing method in the second substrate 200. Therefore, by adopting the configuration of the imaging device 1 using the first manufacturing method, it is easy to align the elements formed on each of the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured.

[0307] The imaging device 1 manufactured using such a first manufacturing method has features different from those of the imaging device manufactured by the second manufacturing method. Specifically, in the imaging device 1 manufactured by the first manufacturing method, for example, the through electrodes 120E, 121E and TGV have a substantially constant thickness (dimension in the substrate plane direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E and TGV have a tapered shape, they have a tapered shape with a constant inclination. In the imaging device 1 including such through electrodes 120E, 121E and TGV, the pixel 541 is easily miniaturized.

[0308] Here, when the imaging device 1 is manufactured by the first manufacturing method, since the active element is formed on the second substrate 200 after the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, the first substrate 100 is also affected by the heating process required to form the active element. Therefore, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120 and 121 provided on the first substrate 100. For example, the pad portions 120 and 121 are preferably composed of a material having a higher melting point (i.e., higher heat resistance) than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance such as doped polysilicon, tungsten, titanium, or titanium nitride is used for the pad portions 120 and 121. Therefore, the imaging device 1 can be manufactured using the above-mentioned first manufacturing method.

[0309] The passivation film 122 is provided on the entire surface of the semiconductor layer 100S to cover the pad portions 120 and 121 ( Fig.34 ). The passivation film 122 is composed of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 via the passivation film 122. The interlayer insulating film 123 is, for example, provided on the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is, for example, composed of a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is provided on the entire main surface of the first substrate 100. The bonding film 124 is, for example, composed of a silicon nitride film.

[0310] For example, the light receiving lens 401 faces the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 interposed therebetween ( Fig.34 ). The light receiving lens 401 is provided, for example, at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0311] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T in order from the first substrate 100 side. The semiconductor layer 200S is composed of a silicon substrate. In the semiconductor layer 200S, a well region 211 is arranged in the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 20 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is, for example, arranged on the front surface side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 so that the rear surface side (semiconductor layer 200S side) of the second substrate 200 faces the front surface side (wiring layer 100T side) of the first substrate 100. That is, the second substrate 200 is bonded to the first substrate 100 in a face-to-back manner.

[0312] Figures 36 to 40 An example of a planar configuration of the second substrate 200 is schematically shown. Fig.36 The configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S is shown. Fig.37 The configuration of each portion of the wiring layer 200T (specifically, a first wiring layer W1 described later), the semiconductor layer 200S connected to the wiring layer 200T, and the first substrate 100 is schematically shown. Figures 38 to 40 An example of a planar configuration of the wiring layer 200T is shown. Figures 36 to 40 Together with Fig.34 The configuration of the second substrate 200 is described. Fig.36 and Fig.37 In the figure, the outer shape of the photodiode PD (the boundary between the pixel separation portion 117 and the photodiode PD) is indicated by a dotted line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 is indicated by a dotted line in the portion overlapping with the gate electrode of each transistor constituting the pixel circuit 210. In the portion overlapping with the gate electrode of the amplifier transistor AMP, the boundary between the semiconductor layer 200S and the element isolation region 213 and the boundary between the element isolation region 213 and the insulating region 213 are set on one side in the channel width direction.

[0313] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element isolation region 213 ( Fig.34 For example, the through electrodes 120E and 121E of the two pixel sharing units 539 connected to the two pixel circuits 210 and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) are arranged in the insulating region 212 between the two pixel circuits 210 adjacent to each other in the H direction ( Fig.37 ).

[0314] The insulating region 212 has a Fig.34 ) is substantially the same thickness. The semiconductor layer 200S is divided by the insulating region 212. The through electrodes 120E and 121E and the through electrode TGV are provided in the insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0315] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E and 121E are connected to the wirings of the wiring layer 200T (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described later). The through electrodes 120E and 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120 and 121 ( Fig.34 ). The through electrode 120E is used to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 through the through electrode 120E. The through electrode 121E is used to electrically connect the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the VSS contact area 118 of the first substrate 100 is electrically connected to the reference potential line VSS of the second substrate 200 through the through electrode 121E.

[0316] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring 200T. The through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transmission gate TG ( Fig.34 ). Such a through electrode TGV is used to electrically connect the transfer gate TG (transfer gates TG1, TG2, TG3, and TG4) of each of the pixels 541A, 541B, 541C, and 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, specifically, the later described Fig.39 That is, the transfer gate TG of the first substrate 100 is electrically connected to the wiring TRG of the second substrate 200 through the through electrode TGV, and transmits a driving signal to each transfer transistor TR (transmission transistors TR1, TR2, TR3, and TR4).

[0317] The insulating region 212 is a region for insulating the through electrodes 120E and 121E and the through electrode TGV that electrically connect the first substrate 100 and the second substrate 200 from the semiconductor layer 200S. For example, the through electrodes 120E and 121E and the through electrodes TGV (through electrodes TGV1, TGV2, TGV3, and TGV4) connected to two pixel circuits 210 are arranged in the insulating region 212 between two pixel circuits 210 (shared unit 539) adjacent to each other in the H direction. The insulating region 212 is set to extend in the V direction, for example ( Fig.36 and Fig.37 Here, by designing the arrangement of the horizontal portion TGb of the transfer gate TG, the through electrode TGV is arranged so that the position of the through electrode TGV in the H direction is close to the positions of the through electrodes 120E and 121E in the H direction compared to the position of the vertical portion TGa ( Fig.35A , Fig.37 ). For example, the through electrode TGV is arranged at approximately the same position as the through electrodes 120E and 121E in the H direction. Therefore, the through electrodes 120E and 121E and the through electrode TGV can be jointly arranged in the insulating region 212 extending in the V direction. As another arrangement example, it is also conceivable to arrange the horizontal portion TGb only in the area overlapping with the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and, for example, the through electrode TGV is arranged at the approximately central portion of each pixel 541 in the H direction and the V direction. At this time, the position of the through electrode TGV in the H direction greatly deviates from the position of the through electrodes 120E and 121E in the H direction. For example, the insulating region 212 is arranged around the through electrode TGV and the through electrodes 120E and 121E to electrically insulate them from the adjacent semiconductor layer 200S. In the case where the position of the through electrode TGV in the H direction and the position of the through electrodes 120E and 121E in the H direction are greatly separated from each other, it is necessary to independently provide an insulating region 212 around each of the through electrodes 120E, 121E, and TGV. Therefore, the semiconductor layer 200S is thinned. In contrast, the layout in which the through electrodes 120E and 121E and the through electrode TGV are jointly arranged in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. Therefore, a large area of ​​the semiconductor element formation region of the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0318] As reference Fig.32As described, the pixel sharing unit 539 has a structure in which the floating diffusion FD provided in each of the plurality of pixels 541 is electrically connected and the plurality of pixels 541 share one pixel circuit 210. Then, the floating diffusion FD is electrically connected to each other through the pad portion 120 provided on the first substrate 100 ( Fig.34 and Fig.35B ). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via a through electrode 120E. As another structural example, it is also conceivable to provide an electrical connection portion between the floating diffusions FD on the second substrate 200. In this case, the pixel sharing unit 539 is provided with four through electrodes respectively connected to the floating diffusions FD1, FD2, FD3 and FD4. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes increases. In contrast, in the structure in which the pad portion 120 is provided on the first substrate 100 ( Fig.34 and Fig.35B ), the number of through electrodes can be reduced, and the insulating region 212 can be reduced. Therefore, a large area of ​​the semiconductor element formation region of the semiconductor layer 200S can be ensured. Therefore, for example, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0319] The element isolation region 213 is arranged on the front surface side of the semiconductor layer 200S. The element isolation region 213 has a shallow trench isolation (STI) structure. In the element isolation region 213, the semiconductor layer 200S is dug out in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and an insulating film is embedded in the dug-out region. The insulating film is composed of silicon oxide, for example. The element isolation region 213 isolates a plurality of transistors constituting the pixel circuit 210 from each other according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (the deep part of the semiconductor layer 200S).

[0320] Here, we will refer to Fig.35A , Fig.35B and Fig.36 A difference between the outer shape of the pixel sharing unit 539 on the first substrate 100 (outer shape in the substrate plane direction) and the outer shape of the pixel sharing unit 539 on the second substrate 200 is described.

[0321] In the imaging device 1, the pixel sharing unit 539 is provided on both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel sharing unit 539 provided on the first substrate 100 is different from the outer shape of the pixel sharing unit 539 provided on the second substrate 200.

[0322] exist Fig.35A and Fig.35B , the outlines of pixels 541A, 541B, 541C, and 541D are indicated by single-dot chain lines, and the outer shape of the pixel sharing unit 539 is indicated by a bold line. For example, the pixel sharing unit 539 of the first substrate 100 includes two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, the pixel sharing unit 539 of the first substrate 100 includes four pixels 541 in adjacent 2 rows × 2 columns, and the pixel sharing unit 539 of the first substrate 100 has a substantially square outer shape. In the pixel array section 540, such pixel sharing units 539 are arranged to be adjacent to each other at two pixel pitches (corresponding to the pitch of the two pixels 541) in the H direction and at two pixel pitches (corresponding to the pitch of the two pixels 541) in the V direction.

[0323] exist Fig.36 and Fig.37 , the outlines of the pixels 541A, 541B, 541C, and 541D are indicated by a single-dot chain line, and the outer shape of the pixel sharing unit 539 is indicated by a bold line. For example, the outer shape of the pixel sharing unit 539 of the second substrate 200 is smaller than the pixel sharing unit 539 of the first substrate 100 in the H direction, and is larger than the pixel sharing unit 539 of the first substrate 100 in the V direction. For example, the pixel sharing unit 539 of the second substrate 200 is formed with a size (area) corresponding to one pixel in the H direction, and is formed with a size corresponding to four pixels in the V direction. That is, the pixel sharing unit 539 of the second substrate 200 is formed with a size corresponding to pixels arranged in adjacent 1 row×4 columns, and the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape.

[0324] For example, in each pixel circuit 210, a selection transistor SEL, an amplification transistor AMP, a reset transistor RST, and an FD conversion gain switching transistor FDG are arranged in this order in the V direction ( Fig.36 ). By setting the outer shape of each pixel circuit 210 in a substantially rectangular shape as described above, the four transistors (select transistor SEL, amplification transistor AMP, reset transistor RST, and FD conversion gain switch transistor FDG) can be arranged in one direction ( Fig.36Therefore, the drain of the amplifier transistor AMP and the drain of the reset transistor RST can be shared by one diffusion region (the diffusion region connected to the power supply line VDD). For example, the formation area of ​​each pixel circuit 210 can be set to be approximately square (see the later described Fig.49 ). In this case, two transistors are arranged in one direction, and it is difficult to share the drain of the amplifier transistor AMP and the drain of the reset transistor RST in one diffusion region. Therefore, by setting the formation area of ​​the pixel circuit 210 to a substantially rectangular shape, the four transistors can be easily arranged close to each other, and the formation area of ​​the pixel circuit 210 can be reduced. That is, the pixel can be miniaturized. In addition, when it is not necessary to reduce the formation area of ​​the pixel circuit 210, the formation area of ​​the amplifier transistor AMP can be increased to suppress noise.

[0325] For example, near the surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switch transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 includes, for example, a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through electrode 121E. The VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switch transistor FDG, and the element isolation region 213 is inserted between the VSS contact region 218 and the source of the FD conversion gain switch transistor FDG ( Fig.36 ).

[0326] Next, we will refer to Fig.35B and Fig.36 The positional relationship between the pixel sharing unit 539 disposed on the first substrate 100 and the pixel sharing unit 539 disposed on the second substrate 200 is described. For example, one of the two pixel sharing units 539 disposed in the V direction on the first substrate 100 (for example, Fig.35B The pixel sharing unit 539 is connected to one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, Fig.36 For example, the other of the two pixel sharing units 539 arranged in the V direction on the first substrate 100 (for example, Fig.35B The pixel sharing unit 539 is connected to the other of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, Fig.36 Pixel sharing unit 539 on the right side of the paper).

[0327] For example, in two pixel sharing units 539 arranged in the H direction of the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to the layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V direction and the H direction. Hereinafter, the effect obtained by this layout will be described.

[0328] In the two pixel sharing units 539 arranged in the V direction of the first substrate 100, each pad portion 120 is arranged at the central portion of the outer shape of the pixel sharing unit 539, that is, at the central portion in the V direction and the H direction of the pixel sharing unit 539 ( Fig.35B ). On the other hand, as described above, because the pixel sharing unit 539 of the second substrate 200 has a substantially rectangular outer shape that is longer in the V direction, for example, the amplifier transistor AMP connected to the pad portion 120 is arranged at a position moved upward from the center of the pixel sharing unit 539 in the V direction to the position on the paper. For example, when the internal layout of two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, the distance between the amplifier transistor AMP of one pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the upper side on the paper of FIG. 35) becomes relatively short. However, the distance between the amplifier transistor AMP of the other pixel sharing unit 539 and the pad portion 120 (for example, the pad portion 120 of the pixel sharing unit 539 on the lower side on the paper of FIG. 35) becomes longer. For this reason, the wiring area required to connect the amplifier transistor AMP and the pad portion 120 increases, and the wiring layout of the pixel sharing unit 539 may become complicated. This may affect the miniaturization of the imaging device 1.

[0329] On the other hand, by reversing the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 at least in the V direction, the distance between the amplifier transistor AMP of the two pixel sharing units 539 and the pad portion 120 can be shortened. Therefore, compared with a configuration in which the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is the same, it is easy to miniaturize the imaging device 1. Note that the planar layout of each of the plurality of pixel sharing units 539 of the second substrate 200 is Fig.36 The range shown is bilaterally symmetrical, but when including the later Fig.37 The layout of the first wiring layer W1 described is bilaterally asymmetrical.

[0330] In addition, preferably, the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 is also reversed in the H direction. The reason will be described below. Fig.37As shown, each of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 is connected to the pad portions 120 and 121 of the first substrate 100. For example, the pad portions 120 and 121 are arranged at the central portion in the H direction of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (arranged between the two pixel sharing units 539 in the H direction). Therefore, by reversing the internal layout of the two pixel sharing units 539 arranged in the H direction of the second substrate 200 in the H direction, the distance between each of the plurality of pixel sharing units 539 of the second substrate 200 and the pad portions 120 and 121 can be reduced. That is, it is easier to miniaturize the imaging device 1.

[0331] In addition, the position of the outline of the pixel sharing unit 539 of the second substrate 200 may not be aligned with the position of any outline of the pixel sharing unit 539 of the first substrate 100. For example, one of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (e.g., Fig.37 In the pixel sharing unit 539, one (eg, Fig.37 The outline of the pixel sharing unit 539 (eg, Fig.35B In addition, the other of the two pixel sharing units 539 arranged in the H direction on the second substrate 200 (for example, Fig.36 In the pixel sharing unit 539 on the right side of the paper, another pixel sharing unit 539 in the V direction (for example, Fig.37 The contour of the lower side on the paper) is arranged on another side (for example, Fig.35B As described above, by arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 to each other, the distance between the amplifying transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0332] In addition, the positions of the contours of the plurality of pixel sharing units 539 of the second substrate 200 may not be aligned. For example, two pixel sharing units 539 arranged in the H direction of the second substrate 200 are arranged so that the positions of the contours in the V direction are moved. Therefore, the distance between the amplifier transistor AMP and the pad portion 120 can be shortened. Therefore, it is easy to miniaturize the imaging device 1.

[0333] Reference Fig.35B and Fig.37The repeated arrangement of the pixel sharing unit 539 in the pixel array section 540 is described. The pixel sharing unit 539 of the first substrate 100 has a size of two pixels 541 in the H direction and a size of two pixels 541 in the V direction ( Fig.35B ). For example, in the pixel array portion 540 of the first substrate 100, the pixel sharing units 539 having a size corresponding to four pixels 541 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (corresponding to the pitch of two pixels 541) and at a pitch of two pixels in the V direction (corresponding to the pitch of two pixels 541). Alternatively, the pixel array portion 540 of the first substrate 100 may be provided with a pair of pixel sharing units 539, wherein the two pixel sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array portion 540 of the first substrate 100, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other at a pitch of two pixels in the H direction (corresponding to the pitch of two pixels 541) and at a pitch of four pixels in the V direction (corresponding to the pitch of four pixels 541). The pixel sharing unit 539 of the second substrate 200 has a size of one pixel 541 in the H direction and a size of four pixels 541 in the V direction ( Fig.37 ). For example, the pixel array portion 540 of the second substrate 200 is provided with a pair of pixel sharing units 539, which include two pixel sharing units 539 having a size corresponding to four pixels 541. The pixel sharing units 539 are arranged to be adjacent to each other in the H direction and are arranged to be offset in the V direction. In the pixel array portion 540 of the second substrate 200, for example, a pair of pixel sharing units 539 are repeatedly arranged adjacent to each other without gaps at a spacing of two pixels in the H direction (corresponding to the spacing of two pixels 541) and a spacing of four pixels in the V direction (corresponding to the spacing of four pixels 541). This repeated arrangement of the pixel sharing units 539 enables the pixel sharing units 539 to be arranged without any gaps. Therefore, it is easy to miniaturize the imaging device 1.

[0334] For example, the amplifier transistor AMP preferably has a three-dimensional structure such as a fin shape ( Fig.34 ). Therefore, the size of the effective gate width is increased, and noise can be suppressed. For example, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switch transistor FDG have a planar structure. The amplifier transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, the reset transistor RST, or the FD conversion gain switch transistor FDG may have a three-dimensional structure.

[0335] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221, for example, contacts the surface of the semiconductor layer 200S and covers the entire surface of the semiconductor layer 200S. The passivation film 221 covers the corresponding gate electrodes of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switch transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. A plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4) are separated by the interlayer insulating film 222. The interlayer insulating film 222 is, for example, composed of silicon oxide.

[0336] In the wiring layer 200T, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 are sequentially provided from the semiconductor layer 200S side, and these layers are insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 is provided with a plurality of connection portions connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 and the lower layer thereof. The connection portion is a portion in which a conductive material is embedded in a connection hole provided in the interlayer insulating film 222. For example, the interlayer insulating film 222 is provided with a connection portion 218V connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the aperture of the connection portion connecting the elements of such a second substrate 200 is different from the aperture of the through electrodes 120E and 121E and the through electrode TGV. Specifically, the aperture of the connection hole connecting the elements of the second substrate 200 is preferably smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV. The reason will be described below. The depth of the connection portion (connection portion 218V, etc.) provided in the wiring layer 200T is shallower than the depth of the through electrodes 120E, 121E and the through electrode TGV. Therefore, compared with the through electrodes 120E and 121E and the through electrode TGV, the connection portion can easily fill the conductive material in the connection hole. By making the aperture of the connection portion smaller than the aperture of the through electrodes 120E and 121E and the through electrode TGV, it is easy to miniaturize the imaging device 1.

[0337] For example, the through electrode 120E is connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switch transistor FDG through the first wiring layer W1 (specifically, the connection hole reaches the source of the FD conversion gain switch transistor FDG). The first wiring layer W1, for example, connects the through electrode 121E and the connection portion 218V, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S.

[0338] Next, we will refer to Figures 38 to 40 The plane configuration of the wiring layer 200T is described. Fig.38 An example of a plane configuration of the first wiring layer W1 and the second wiring layer W2 is shown. Fig.39 An example of a plane configuration of the second wiring layer W2 and the third wiring layer W3 is shown. Fig.40 An example of a plane configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown.

[0339] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL ( Fig.39 ). These traces correspond to the reference Fig.32 A plurality of row drive signal lines 542 are described. The wirings TRG1, TRG2, TRG3, and TRG4 are used to send drive signals to the transmission gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transmission gates TG1, TG2, TG3, and TG4, respectively, via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E. The wiring SELL is used to send the drive signal to the gate of the selection transistor SEL, the wiring RSTL is used to send the drive signal to the gate of the reset transistor RST, and the wiring FDGL is used to send the drive signal to the gate of the FD conversion gain switch transistor FDG. The wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, the reset transistor RST, and the FD conversion gain switch transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0340] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 ( Fig.40 ). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion. The reference potential line VSS is connected to the VSS contact area 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion 218V. In addition, the reference potential line VSS is connected to the VSS contact area 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the selection transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and the connection portion.

[0341] The contact portions 201 and 202 may be disposed at positions overlapping with the pixel array section 540 in a plan view (eg, Figure 3 ), or may be provided in a peripheral portion 540B outside the pixel array section 540 (eg, Fig.34 ). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portions 201 and 202 are composed of, for example, metals such as copper (Cu) and aluminum (Al). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding between the second substrate 200 and the third substrate 300.

[0342] Fig.34 2 shows an example in which the peripheral circuit is disposed in the peripheral portion 540B of the second substrate 200. The peripheral circuit may include a portion of the row driving unit 520, a portion of the column signal processing unit 550, and the like. Figure 3 As shown, the peripheral circuit may not be arranged in the peripheral portion 540B of the second substrate 200 , and the connection holes H1 and H2 may be arranged near the pixel array part 540 .

[0343] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in sequence from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S is composed of a silicon substrate. The circuit is arranged in a portion of the front surface side of the semiconductor layer 300S. Specifically, for example, at least a portion of the input section 510A, the row drive section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560, and the output section 510B are arranged in a portion of the front surface side of the semiconductor layer 300S. The wiring layer 300T arranged between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, a plurality of wiring layers separated by the interlayer insulating film, and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface on the second substrate 200 side), the contact portion 301 contacts the contact portion 201 of the second substrate 200, and the contact portion 302 contacts the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to a circuit (for example, at least one of the input portion 510A, the row driving portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, or the output portion 510B) formed in the semiconductor layer 300S. The contact portions 301 and 302 are made of, for example, a metal such as copper (Cu) and aluminum (Al). For example, the external terminal TA is connected to the input portion 510A via the connection hole H1, and the external terminal TB is connected to the output portion 510B via the connection hole H2.

[0344] Here, features of the imaging apparatus 1 will be described.

[0345] Generally, an imaging device mainly includes a photodiode and a pixel circuit. Here, when the area of ​​the photodiode increases, the charge generated as a result of photoelectric conversion increases, and therefore, the signal-to-noise ratio (S / N ratio) of the pixel signal improves, and the imaging device can output better image data (image information). On the other hand, when the size of the transistor included in the pixel circuit (specifically, the size of the amplifying transistor) increases, the noise generated in the pixel circuit decreases, and therefore, the S / N ratio of the imaging signal improves, and the imaging device can output better image data (image information).

[0346] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor included in the pixel circuit can be reduced. In addition, if the size of the transistor included in the pixel circuit is increased, the area of ​​the photodiode can be reduced.

[0347] In order to solve these problems, for example, the imaging device 1 of the present embodiment uses a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, it is possible to realize as large an area as possible of the photodiode PD and as large a size as possible of the transistor included in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. Therefore, the S / N ratio of the pixel signal can be improved, and the imaging device 1 can output better image data (image information).

[0348] When a structure is implemented in which a plurality of pixels 541 share one pixel circuit 210 and the pixel circuits overlap and are arranged on the photodiode PD, a plurality of wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the plurality of pixels 541. In order to ensure a large area of ​​the semiconductor substrate 200 in which the pixel circuit 210 is formed, for example, a connection wiring in which a plurality of extension wirings are connected to each other and integrated into one may be formed. Similarly, for a plurality of wirings extending from the VSS contact region 118, a connection wiring in which a plurality of extension wirings are connected to each other and integrated into one may be formed.

[0349] For example, when a connection wiring that interconnects a plurality of wirings extending from the floating diffusion FD of each of the plurality of pixels 541 is formed in the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable to reduce the area for forming the transistor included in the pixel circuit 210. Similarly, when a connection wiring that interconnects a plurality of wirings extending from the VSS contact region 118 of each of the plurality of pixels 541 and combines the plurality of wirings into one is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable to reduce the area for forming the transistor included in the pixel circuit 210.

[0350] In order to solve these problems, for example, the imaging device 1 of the present embodiment may have a structure in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD, and a structure in which a connection wiring that connects the floating diffusion FD of each of the plurality of pixels 541 to each other and integrates them into one and a connection wiring that connects the VSS contact areas 118 included in each of the plurality of pixels 541 to each other and integrates them into one is provided on the first substrate 100.

[0351] Here, when the above-mentioned second manufacturing method is used as a manufacturing method for providing a connection wiring that connects the floating diffusion FD of each of the plurality of pixels 541 to each other and integrates them into one and a connection wiring that connects the VSS contact area 118 of each of the plurality of pixels 541 to each other and integrates them into one on the first substrate 100, for example, an imaging device with high quality and high performance can be manufactured using an appropriate process according to the configuration of each of the first substrate 100 and the second substrate 200. In addition, the connection wiring of the first substrate 100 and the second substrate 200 can be formed by an easy process. Specifically, in the case of using the above-mentioned second manufacturing method, an electrode connected to the floating diffusion FD and an electrode connected to the VSS contact area 118 are respectively provided on the surface of the first substrate 100 and the surface of the second substrate 200, which are the bonding boundary surfaces of the first substrate 100 and the second substrate 200. In addition, preferably, when the first substrate 100 and the second substrate 200 are bonded together, even if a positional shift occurs between the electrodes provided on the two substrate surfaces, the electrodes formed on the two substrate surfaces are expanded so that the electrodes formed on the two substrate surfaces are in contact with each other. In this case, it is conceivable that it is difficult to arrange the above-mentioned electrodes in a limited area of ​​each pixel included in the imaging device 1 .

[0352] In order to solve the problem that a large electrode is required at the bonding boundary surface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of the present embodiment can use the above-mentioned first manufacturing method as a manufacturing method in which a plurality of pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged to be superimposed on the photodiode PD. Therefore, it is easy to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality and high-performance imaging device can be manufactured. In addition, a unique structure generated by using this manufacturing method can be provided. That is, the imaging device includes a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are laminated in this order, in other words, it has a structure in which the first substrate 100 and the second substrate 200 are laminated in a face-to-back manner, and through electrodes 120E and 121E penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 from the front surface side of the semiconductor layer 200S of the second substrate 200 and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0353] In a structure in which connection wiring that connects the floating diffusions FD of a plurality of pixels 541 to one another and integrates them into one and connection wiring that connects the VSS contact areas 118 of a plurality of pixels 541 to one another and integrates them into one are provided on a first substrate 100, when the structure and the second substrate 200 are laminated using a first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of a heating treatment required when forming an active element included in the pixel circuit 210 may reach the above-mentioned connection wiring formed on the first substrate 100.

[0354] Therefore, in order to solve the problem that the above-mentioned connection wiring is affected by the heat treatment when the above-mentioned active elements are formed, it is desirable that the imaging device 1 of the present embodiment uses a conductive material having high heat resistance for the connection wiring that connects the floating diffusions FD of the plurality of pixels 541 to each other and integrates them into one and for the connection wiring that connects the VSS contact regions 118 of the plurality of pixels 541 to each other and integrates them into one. Specifically, a material having a higher melting point than that of at least a part of the wiring material included in the wiring layer 200T of the second substrate 200 can be used as the conductive material having high heat resistance.

[0355] As described above, for example, the imaging device 1 of the present embodiment includes: (1) a structure in which the first substrate 100 and the second substrate 200 are laminated in a face-to-back manner (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are laminated in this order); (2) a structure in which the through electrodes 120E and 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrate the semiconductor layer 200S and the wiring layer 100T of the first substrate 100 and reach the surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the connection wiring that connects the floating diffusions FD included in the plurality of pixels 541 to each other and integrates them into one and the connection wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to each other and integrates them into one are made of a conductive material having high heat resistance. Therefore, without providing a large electrode at the interface between the first substrate 100 and the second substrate 200, the first substrate 100 may be provided with connection wiring that connects the floating diffusions FD included in the plurality of pixels 541 to one another and integrates them into one, and connection wiring that connects the VSS contact areas 118 included in the plurality of pixels 541 to one another and integrates them into one.

[0356] [Operation of Imaging Device 1]

[0357] Next, we will refer to Fig.41 and Fig.42 The operation of the imaging device 1 is described. Fig.41 and Fig.42 In the example, arrows representing the path of each signal are added to Figure 3 .exist Fig.41 In FIG. 1 , the paths of input signals input from the outside to the imaging device 1 and the power supply potential and the reference potential are indicated by arrows. Fig.42, a signal path of a pixel signal output from the imaging device 1 to the outside is indicated by an arrow. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input portion 510A is transmitted to the row driving portion 520 of the third substrate 300, and the row driving portion 520 creates a row driving signal. The row driving signal is sent to the second substrate 200 via the contact portions 301 and 201. In addition, the row driving signal reaches each pixel sharing unit 539 of the pixel array portion 540 via the row driving signal line 542 in the wiring layer 200T. Among the row driving signals reaching the pixel sharing unit 539 of the second substrate 200, a driving signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The driving signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven ( Fig.41 ). In addition, the power supply potential and the reference potential provided to the input portion 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are sent to the second substrate 200 via the contact portions 301 and 201, and are provided to the pixel circuit 210 of each pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is further provided to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through electrode 121E. On the other hand, for each pixel sharing unit 539, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is sent to the pixel circuit 210 of the second substrate 200 via the through electrode 120E. A pixel signal based on the pixel signal is sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 202 and 302. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 , and then output to the outside via the output section 510B.

[0358] [Effect]

[0359] In the present embodiment, pixels 541A, 541B, 541C, and 541D (pixel sharing unit 539) and pixel circuit 210 are arranged on different substrates (first substrate 100 and second substrate 200). Therefore, compared with the case where pixels 541A, 541B, 541C, and 541D and pixel circuit 210 are formed on the same substrate, the area of ​​pixels 541A, 541B, 541C, and 541D and pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the transistor noise of pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information). In addition, the imaging device 1 can be miniaturized (in other words, the pixel size is reduced and the imaging device 1 is miniaturized). The imaging device 1 can increase the number of pixels per unit area by reducing the pixel size, and can output high-quality images.

[0360] In addition, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by through electrodes 120E and 121E provided in the insulating region 212. For example, a method of connecting the first substrate 100 and the second substrate 200 by connecting pad electrodes to each other, or a method of connecting the first substrate 100 and the second substrate 200 by through wiring (e.g., through Si through hole (TSV)) penetrating the semiconductor layer can be considered. Compared with this method, by providing the through electrodes 120E and 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, the pixel size can be reduced, and the imaging device 1 can be further miniaturized. In addition, the resolution can be further increased by further miniaturizing the area of ​​each pixel. When it is not necessary to reduce the chip size, the formation area of ​​the pixels 541A, 541B, 541C and 541D and the pixel circuit 210 can be enlarged. Therefore, the amount of pixel signals obtained by photoelectric conversion can be increased, and the noise of the transistors included in the pixel circuit 210 can be reduced. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0361] In addition, in the imaging device 1, the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are provided on different substrates (the second substrate 200 and the third substrate 300). Therefore, compared with the case where the pixel circuit 210 and the column signal processing section 550 and the image signal processing section 560 are formed on the same substrate, the area of ​​the pixel circuit 210 and the area of ​​the column signal processing section 550 and the image signal processing section 560 can be enlarged. Therefore, the noise generated in the column signal processing section 550 can be reduced, and an advanced image processing circuit can be installed by the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0362] In addition, in the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. In addition, the contact portions 201, 202, 301 and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact portions 201, 202, 301 and 302 can be freely arranged without being disturbed by the layout of various wirings provided in the pixel array. Thus, the contact portions 201, 202, 301 and 302 can be used for electrical connection between the second substrate 200 and the third substrate 300. For example, by using the contact portions 201, 202, 301 and 302, the column signal processing section 550 and the image signal processing section 560 have a higher degree of freedom in layout. Therefore, the noise generated in the column signal processing section 550 can be reduced, and an advanced image processing circuit can be installed by the image signal processing section 560. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0363] In addition, in the imaging device 1, the pixel separation portion 117 penetrates the semiconductor layer 100S. Therefore, even in the case where the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) is shortened due to the miniaturization of the area of ​​each pixel, color mixing between the pixels 541A, 541B, 541C, and 541D can be suppressed. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0364] In addition, in the imaging device 1, the pixel circuit 210 is provided for each pixel sharing unit 539. Therefore, compared with the case where the pixel circuit 210 is provided in each pixel 541A, 541B, 541C, and 541D, the formation area of ​​the transistors (amplifier transistor AMP, reset transistor RST, selection transistor SEL, and FD conversion gain switch transistor FDG) constituting the pixel circuit 210 can be enlarged. For example, noise can be suppressed by increasing the formation area of ​​the amplifier transistor AMP. Therefore, the signal-to-noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0365] Furthermore, in the imaging device 1, the pad portion 120 of the floating diffusion FD (floating diffusion FD1, FD2, FD3, and FD4) electrically connecting the four pixels (pixels 541A, 541B, 541C, and 541D) is provided on the first substrate 100. Therefore, compared with the case where such a pad portion 120 is provided on the second substrate 200, the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 can be reduced. Therefore, the insulating region 212 can be made smaller, and the transistor formation region (semiconductor layer 200S) constituting the pixel circuit 210 can be ensured to have a sufficient size. Therefore, the noise of the transistor included in the pixel circuit 210 can be reduced, the signal / noise ratio of the pixel signal can be improved, and the imaging device 1 can output better pixel data (image information).

[0366] Hereinafter, a modification of the imaging device 1 according to the above-described embodiment will be described. In the following modification, the same reference numerals are attached to the same configurations as those of the above-described embodiment.

[0367] <1. Modification 1>

[0368] Figure 43 to Figure 47 A modification of the planar configuration of the imaging apparatus 1 according to the above-described embodiment is shown. Fig.46 The planar configuration near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.36 . Fig.44 The configuration of each portion of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.37 . Fig.45 An example of a plane configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.38 . Fig.46 An example of a plane configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.39 . Fig.47 An example of a plane configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.40 .

[0369] In this amendment, if Fig.44 As shown, among the two pixel sharing units 539 arranged in the H direction on the second substrate 200, the internal layout of one (e.g., the right side on the paper) pixel sharing unit 539 has a configuration that reverses the internal layout of the other (e.g., the left side on the paper) pixel sharing unit 539 only in the H direction. In addition, the deviation between the outline of one pixel sharing unit 539 and the outline of the other pixel sharing unit 539 in the V direction is greater than the deviation described in the above embodiment ( Fig.37 ). In this way, by increasing the deviation in the V direction, the distance between the amplifier transistor AMP of the other pixel sharing unit 539 and the pad portion 120 connected thereto (the pad portion 120 of the other (lower side on the paper) of the two pixel sharing units 539 arranged in the V direction shown in FIG. 35) can be reduced. With this layout, Figure 43 to Figure 47 The modification 1 of the imaging device 1 shown can make the area of ​​the plane layout of the two pixel sharing units 539 arranged in the H direction the same as the area of ​​the pixel sharing unit 539 of the second substrate 200 described in the above embodiment without reversing the plane layout of the two pixel sharing units 539 in the V direction. Note that the plane layout of the pixel sharing unit 539 of the first substrate 100 is different from the plane layout described in the above embodiment ( Fig.35A , Fig.35B ) are the same. Therefore, the imaging device 1 of the present modification can obtain effects similar to those of the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and the present modification.

[0370] <3. Modification 2>

[0371] Figures 48 to 53 A modification of the planar configuration of the imaging apparatus 1 according to the above embodiment is shown. Fig.48 The planar configuration of the first substrate 100 is schematically shown and corresponds to the configuration described in the above embodiment. Fig.35A . Fig.49 The planar configuration near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.36 . Fig.50The configuration of each portion of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.37 . Fig.51 An example of a plane configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.38 . Fig.52 An example of a plane configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.39 . Fig.53 An example of a plane configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.40 .

[0372] In the present modification, the outer shape of each pixel circuit 210 has a substantially square planar shape ( Fig.49 In this respect, the planar configuration of the imaging device 1 of the present modification is different from that of the imaging device 1 described in the above-mentioned embodiment.

[0373] For example, the pixel sharing unit 539 of the first substrate 100 is formed on a pixel region of 2 rows×2 columns and has a substantially square planar shape ( Fig.48 ), as described in the above-mentioned embodiment. For example, in each pixel sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixel 541A and the pixel 541C of one pixel column extend in the H direction from the position overlapping with the vertical portion TGa toward the direction of the center portion of the pixel sharing unit 539 (more specifically, the direction toward the outer edges of the pixels 541A and 541C and the direction toward the center portion of the pixel sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixel 541B and the pixel 541D of another pixel column extend in the H direction from the position overlapping with the vertical portion TGa toward the direction of the outside of the pixel sharing unit 539 (more specifically, the direction toward the outer edges of the pixels 541B and 541D and the direction toward the outside of the pixel sharing unit 539). The pad portion 120 connected to the floating diffusion FD is provided at the center portion of the pixel sharing unit 539 (the center portion of the pixel sharing unit 539 in the H direction and the V direction), and the pad portion 121 connected to the VSS contact region 118 is at least in the H direction (in the V direction). Fig.48 The pixel sharing unit 539 is arranged at the end of the pixel sharing unit 539 (in the H direction and the V direction).

[0374] As another arrangement example, it is also conceivable to set the horizontal portion TGb of the transfer gates TG1, TG2, TG3 and TG4 only in the area facing the vertical portion TGa. In this case, as described in the above embodiment, the semiconductor layer 200S is easily subdivided. Therefore, it is difficult to form a large transistor of the pixel circuit 210. On the other hand, when the horizontal portion TGb of the transfer gates TG1, TG2, TG3 and TG4 extends in the H direction from the position overlapping with the vertical portion TGa, as described in the above example, the width of the semiconductor layer 200S can be increased. Specifically, the positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 in the H direction can be arranged close to the position of the through electrode 120E in the H direction, and the positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 in the H direction can be arranged close to the position of the through electrode 121E in the H direction ( Fig.50 ). Therefore, as shown in the above embodiment, the width of the semiconductor layer 200S extending in the V direction (the size in the H direction) can be increased. Therefore, the size of the transistor of the pixel circuit 210 can be increased, specifically, the size of the amplifier transistor AMP can be increased. Therefore, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0375] For example, the pixel sharing unit 539 of the second substrate 200 has a size in the H direction and the V direction that is substantially the same as that of the pixel sharing unit 539 of the first substrate 100, and is disposed on an area corresponding to, for example, a pixel area of ​​approximately 2 rows×2 columns. For example, in each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction, and the FD conversion gain switch transistor FDG and the reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction. One semiconductor layer 200S in which the selection transistor SEL and the amplifier transistor AMP are disposed and one semiconductor layer 200S in which the FD conversion gain switch transistor FDG and the reset transistor RST are disposed are arranged in the H direction via an insulating region 212. The insulating region 212 extends in the V direction ( Fig.49 ).

[0376] Here, we will refer to Fig.49 and Fig.50 Describe the outer shape of the pixel sharing unit 539 of the second substrate 200. For example, Fig.48 The pixel sharing unit 539 of the first substrate 100 shown is connected to a side ( Fig.50The amplifying transistor AMP and the selecting transistor SEL are arranged on the left side of the paper of FIG. 1 , and the other side ( Fig.50 The outer shape of the shared unit 541 of the second substrate 200 including the amplification transistor AMP, the selection transistor SEL, the FD conversion gain switch transistor FDG and the reset transistor RST is determined by the following four outer edges.

[0377] The first outer edge is one end in the V direction of the semiconductor layer 200S including the selection transistor SEL and the amplification transistor AMP ( Fig.50 The first outer edge is provided at the end of the upper side on the paper of the pixel sharing unit 539. The first outer edge is provided at the amplifying transistor AMP included in the pixel sharing unit 539 and at one side ( Fig.50 More specifically, the first outer edge is set at the center portion of the element isolation region 213 in the V direction between the amplifying transistor AMP and the selecting transistor SEL. The second outer edge is the other end ( Fig.50 The second outer edge is provided between the selection transistor SEL included in the pixel sharing unit 539 and the amplification transistor AMP included in the pixel sharing unit 539, which is connected to the other side (the lower side on the paper) of the pixel sharing unit 539 in the V direction. Fig.50 More specifically, the second outer edge is set at the central portion in the V direction of the element isolation region 213 between the selection transistor SEL and the amplifier transistor AMP. The third outer edge is the other end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switch transistor FDG ( Fig.50 The third outer edge is provided between the FD conversion gain switch transistor FDG included in the pixel sharing unit 539 and the reset transistor RST included in the pixel sharing unit 539, which is connected to the other side (the lower side on the paper) of the pixel sharing unit 539 in the V direction. Fig.50 More specifically, the third outer edge is disposed at the center portion in the V direction of the element isolation region 213 between the FD conversion gain switch transistor FDG and the reset transistor RST. The fourth outer edge is one end in the V direction of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switch transistor FDG ( Fig.50The fourth outer edge is provided between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switch transistor FDG (not shown) included in the pixel sharing unit 539, which is connected to one side (the upper side on the paper of the pixel sharing unit 539) in the V direction. Fig.50 More specifically, the fourth outer edge is disposed at a central portion in the V direction of an element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switch transistor FDG.

[0378] In the outer shape of the pixel sharing unit 539 of the second substrate 200 including such a first outer edge, a second outer edge, a third outer edge, and a fourth outer edge, the third outer edge and the fourth outer edge are arranged to be offset to one side in the V direction relative to the first outer edge and the second outer edge (in other words, offset to one side in the V direction). By using such a layout, both the gate of the amplifier transistor AMP and the source of the FD conversion gain switch transistor FDG can be arranged as close to the pad portion 120 as possible. Therefore, the area of ​​the wiring connecting them is reduced, and the imaging device 1 can be easily miniaturized. Note that the VSS contact area 218 is provided between the semiconductor layer 200S including the selection transistor SEL and the amplifier transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switch transistor FDG. For example, a plurality of pixel circuits 210 have the same arrangement.

[0379] The imaging device 1 including such a second substrate 200 can also obtain effects similar to those described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and the present modification.

[0380] <4. Modification 3>

[0381] Figure 54 to Figure 59 A modification of the planar configuration of the imaging apparatus 1 according to the above embodiment is shown. Fig.54 The planar configuration of the first substrate 100 is schematically shown and corresponds to the configuration described in the above embodiment. Fig.35B . Fig.55 The planar configuration near the surface of the semiconductor layer 200S of the second substrate 200 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.36 . Fig.56 The configuration of each portion of the first wiring layer W1, the semiconductor layer 200S connected to the first wiring layer W1, and the first substrate 100 is schematically shown, and corresponds to the configuration described in the above embodiment. Fig.37 . Fig.57An example of a plane configuration of the first wiring layer W1 and the second wiring layer W2 is shown, and corresponds to the example described in the above embodiment. Fig.38 . Fig.58 An example of a plane configuration of the second wiring layer W2 and the third wiring layer W3 is shown, and corresponds to the example described in the above embodiment. Fig.39 . Fig.59 An example of a plane configuration of the third wiring layer W3 and the fourth wiring layer W4 is shown, and corresponds to the example described in the above embodiment. Fig.40 .

[0382] In the present modification, the semiconductor layer 200S of the second substrate 200 extends in the H direction ( Fig.56 ). That is, it basically corresponds to the Fig.49 The planar configuration of the imaging apparatus 1 shown is a configuration rotated by 90 degrees.

[0383] For example, the pixel sharing unit 539 of the first substrate 100 is formed on a pixel region of 2 rows×2 columns and has a substantially square planar shape ( Fig.54 ), as described in the above embodiment. For example, in each pixel sharing unit 539, the transfer gates TG1 and TG2 of the pixel 541A and the pixel 541B of one pixel row extend in the V direction toward the central portion of the pixel sharing unit 539, and the transfer gates TG3 and TG4 of the pixel 541C and the pixel 541D of another pixel row extend in the V direction in the outer direction of the pixel sharing unit 539. The pad portion 120 connected to the floating diffusion FD is provided at the central portion of the pixel sharing unit 539, and the pad portion 121 connected to the VSS contact region 118 is at least extended in the V direction (in the V direction). Fig.54 In the V direction and H direction of the transmission gates TG1 and TG2, the through electrodes TGV1 and TGV2 are located at the end of the pixel sharing unit 539. At this time, the positions of the through electrodes TGV1 and TGV2 in the V direction are close to the position of the through electrode 120E in the V direction, and the positions of the through electrodes TGV3 and TGV4 in the V direction are close to the position of the through electrode 121E in the V direction ( Fig.56 ). Therefore, for reasons similar to those described in the above embodiment, the width of the semiconductor layer 200S extending in the H direction (the dimension in the V direction) can be increased. Therefore, the size of the amplifier transistor AMP can be increased, and noise can be suppressed.

[0384] In each pixel circuit 210, the selection transistor SEL and the amplifier transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged at adjacent positions in the V direction with the selection transistor SEL and the insulating region 212 interposed therebetween ( Fig.55). The FD conversion gain switch transistor FDG and the reset transistor RST are arranged side by side in the H direction. The VSS contact region 218 is arranged in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction ( Fig.58 ), and the fourth wiring layer W4 extends in the V direction ( Fig.59 ).

[0385] The imaging device 1 including such a second substrate 200 can also obtain effects similar to those described in the above embodiment. The arrangement of the pixel sharing unit 539 of the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification. For example, the semiconductor layer 200S described in the above embodiment and modification 1 may extend in the H direction.

[0386] <5. Modification 4>

[0387] Fig.60 A modification of the cross-sectional configuration of the imaging apparatus 1 according to the above-described embodiment is schematically shown. Fig.60 Corresponding to the above-described embodiment Figure 3 In the present modification, in addition to the contact portions 201, 202, 301 and 302, the imaging device 1 includes contact portions 203, 204, 303 and 304 at a position facing the central portion of the pixel array section 540. In this respect, the imaging device 1 of the present modification is different from the imaging device 1 described in the above embodiment.

[0388] The contact portions 203 and 204 are provided on the second substrate 200, and the bonding surface with the third substrate 300 is exposed. The contact portions 303 and 304 are provided on the third substrate 300 and exposed on the bonding surface with the second substrate 200. The contact portion 203 contacts the contact portion 303, and the contact portion 204 contacts the contact portion 304. That is, in the imaging device 1, in addition to the contact portions 201, 202, 301, and 302, the second substrate 200 and the third substrate 300 are connected by the contact portions 203, 204, 303, and 304.

[0389] Next, we will refer to Fig.61 and Fig.62 The operation of the imaging device 1 is described. Fig.61 In FIG. 1 , the paths of input signals input from the outside to the imaging device 1 and the power supply potential and the reference potential are indicated by arrows. Fig.62, the signal path of the pixel signal output from the imaging device 1 to the outside is indicated by an arrow. For example, the input signal input to the imaging device 1 via the input portion 510A is transmitted to the row drive portion 520 of the third substrate 300, and the row drive portion 520 creates a row drive signal. The row drive signal is sent to the second substrate 200 through the contact portions 303 and 203. In addition, the row drive signal reaches each pixel sharing unit 539 of the pixel array portion 540 via the row drive signal line 542 in the wiring layer 200T. Among the row drive signals reaching the pixel sharing unit 539 of the second substrate 200, the drive signal other than the transmission gate TG is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The drive signal of the transmission gate TG is input to the transmission gates TG1, TG2, TG3 and TG4 of the first substrate 100 via the through electrode TGV, and the pixels 541A, 541B, 541C and 541D are driven. In addition, the power supply potential and the reference potential supplied to the input portion 510A (input terminal 511) of the third substrate 300 from the outside of the imaging device 1 are transmitted to the second substrate 200 via the contact portions 303 and 203, and are supplied to the pixel circuit 210 of each pixel sharing unit 539 via the wiring in the wiring layer 200T. The reference potential is further supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-electrode 121E. On the other hand, for each pixel sharing unit 539, the pixel signal photoelectrically converted by the pixels 541A, 541B, 541C, and 541D of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200. A pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact portions 204 and 304. The pixel signal is processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300 , and then output to the outside via the output section 510B.

[0390] The imaging device 1 including such contact portions 203, 204, 303 and 304 can also obtain effects similar to those described in the above embodiments. The position, number, etc. of the contact portions can be changed according to the design of the circuit, etc. of the third substrate 300 to which the wiring is connected via the contact portions 303 and 304.

[0391] <6. Modification 5>

[0392] Fig.63 A modification of the cross-sectional configuration of the imaging apparatus 1 according to the above-described embodiment is shown. Fig.63 Corresponding to the above embodiment described Fig.34In the present modification, the transfer transistor TR having a planar structure is provided on the first substrate 100. In this respect, the imaging device 1 of the present modification is different from the imaging device 1 described in the above embodiment.

[0393] In the transfer transistor TR, the transfer gate TG is configured only by the horizontal portion TGb. In other words, the transfer gate TG does not have the vertical portion TGa, and is disposed to face the semiconductor layer 100S.

[0394] The imaging device 1 including the transfer transistor TR having such a planar structure can also obtain effects similar to those described in the above examples. In addition, by providing the planar transfer gate TG on the first substrate 100, the photodiode PD is formed closer to the surface of the semiconductor layer 100S, thereby increasing the saturation signal amount (Qs), as compared with the case where the vertical transfer gate TG is provided on the first substrate 100. In addition, it can be considered that the method of forming the planar transfer gate TG on the first substrate 100 has a smaller number of manufacturing processes than the method of forming the vertical transfer gate TG on the first substrate 100, and the photodiode PD is less likely to be adversely affected by the manufacturing process.

[0395] <7. Modification 6>

[0396] Fig.64 A modification of the pixel circuit of the imaging device 1 according to the above-described embodiment is shown. Fig.64 Corresponding to the above embodiment described Fig.32 In the present modification, the pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by a plurality of pixels. In this respect, the imaging device 1 of the present modification is different from the imaging device 1 described in the above embodiment.

[0397] The imaging device 1 of this modification is the same as the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (the first substrate 100 and the second substrate 200). Therefore, the imaging device 1 according to this modification can also obtain effects similar to those described in the above embodiment.

[0398] <8. Amendment 7>

[0399] Fig.65FIG. 2 shows a modification of the planar configuration of the pixel separation portion 117 described in the above embodiment. A gap may be provided in the pixel separation portion 117 around the pixels 541A, 541B, 541C, and 541D. That is, the pixel separation portion 117 may not surround the entire periphery of the pixels 541A, 541B, 541C, and 541D. For example, a gap in the pixel separation portion 117 may be provided near the pad portions 120 and 121 (see FIG. 2 ). Fig.35B ).

[0400] In the above-described embodiment, an example has been described in which the pixel separation portion 117 has the FTI structure that penetrates the semiconductor layer 100S (see Fig.34 ), but the pixel separation portion 117 may have a configuration other than the FTI structure. For example, the pixel separation portion 117 may not be provided to completely penetrate the semiconductor layer 100S, and may have a so-called deep trench isolation (DTI) structure.

[0401] <9. Application Examples>

[0402] Fig.66 An example of a schematic configuration of an imaging system 7 including the imaging apparatus 1 according to the above-described embodiment and its modifications is shown.

[0403] The imaging system 7 is, for example, an electronic device such as an imaging apparatus (such as a digital still camera or a video camera) or a portable terminal device (such as a smart phone or a tablet terminal). For example, the imaging system 7 includes the imaging apparatus 1 according to the above-mentioned embodiment and its modification, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, the operation section 247, and the power supply section 248. In the imaging system 7, the imaging apparatus 1 according to the above-mentioned embodiment and its modification, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, the operation section 247, and the power supply section 248 are connected to each other via a bus 249.

[0404] The imaging device 1 according to the above-described embodiment and its modification outputs image data according to incident light. The DSP circuit 243 is a signal processing circuit that processes a signal (image data) output from the imaging device 1 according to the above-described embodiment and its modification. The frame memory 244 temporarily holds the image data processed by the DSP circuit 243 in units of frames. For example, the display section 245 includes a panel-type display device such as a liquid crystal panel or an organic electroluminescent (EL) panel, and displays a moving image or a still image captured by the imaging device 1 according to the above-described embodiment and its modification. The storage section 246 records the image data of the moving image or the still image captured by the imaging device 1 according to the above-described embodiment and its modification in a recording medium such as a semiconductor memory or a hard disk. The operation section 247 issues operation commands for various functions of the imaging system 7 according to the user's operation. The power supply section 248 appropriately supplies various power sources used as operation power sources of the imaging device 1, the DSP circuit 243, the frame memory 244, the display section 245, the storage section 246, and the operation section 247 according to the above-described embodiment and its modification to these supply targets.

[0405] Next, the imaging process in the imaging system 7 will be described.

[0406] Fig.67 An example of a flowchart of an imaging operation in the imaging system 7 is shown. The user instructs to start imaging by operating the operating unit 247 (step S101). Then, the operating unit 247 sends an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) performs imaging in a prescribed imaging mode (step S103).

[0407] The imaging device 1 outputs the image data obtained by imaging to the DSP circuit 243. Here, the image data is data of all pixels of the pixel signal generated based on the charge temporarily held in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (for example, noise reduction processing, etc.) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 causes the frame memory 244 to hold the image data subjected to the predetermined signal processing, and the frame memory 244 causes the storage section 246 to store the image data (step S105). In this way, imaging in the imaging system 7 is performed.

[0408] In the present application example, the imaging device 1 according to the above-described embodiment and its modifications is applied to the imaging system 7. Therefore, since the imaging device 1 can be miniaturized or high-definition, a miniaturized or high-definition imaging system 7 can be provided.

[0409] <10. Application Examples>

[0410] [Application Example 1]

[0411] The technology according to the present disclosure (the present technology) can be applied to various electronic devices. For example, the technology of the present disclosure can be implemented in the form of a device installed on any kind of mobile object, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobile body, an airplane, a drone, a ship, or a robot.

[0412] Fig.68 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology of the present disclosure is applied.

[0413] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.68 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0414] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0415] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a rear light, a brake light, a turn indicator, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a mobile device as a substitute for a key may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, a power window device, a light, etc. of the vehicle.

[0416] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0417] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0418] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0419] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0420] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0421] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the outside vehicle information detection unit 12030.

[0422] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.68 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0423] Fig.69 12031 is a diagram illustrating an example of the installation position of the imaging unit 12031.

[0424] exist Fig.69 In the figure, vehicle 12100 includes imaging units 12101, 12102, 12103, 12104 and 12105 as imaging unit 12031.

[0425] The imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and the upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the upper portion of the windshield in the interior of the vehicle mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the side surfaces of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The front images obtained by the imaging units 12101 and 12105 are mainly used to detect front vehicles, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0426] Notice, Fig.69An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0427] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0428] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting a three-dimensional object that exists on the driving path of the vehicle 12100 and travels at a prescribed speed (e.g., equal to or greater than 0 km / hour) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance to keep in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, cooperative control for automatic driving that allows the vehicle to automatically travel without relying on the driver's operation, etc. can be performed.

[0429] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is higher than or equal to the set value and therefore there is a possibility of collision, the microcomputer 12051 can output a warning to the driver via the audio speaker 12061 or the display unit 12062, and perform forced deceleration or avoidance steering via the driving system control unit 12010 to perform driving assistance for collision avoidance.

[0430] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. Such recognition of pedestrians is performed, for example, by a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and thereby identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0431] An example of a mobile body control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, the imaging device 1 of the above embodiment and its modification can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a high-definition captured image with little noise can be obtained, and therefore, high-precision control can be performed using the captured image in the mobile body control system.

[0432] [Application Example 2]

[0433] Fig.70 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0434] Fig.70 The figure shows a state in which a surgeon (doctor) 11131 performs surgery on a patient 11132 on a bed 11133 by using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy treatment tool 11112, a support arm device 11120 supporting the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are installed.

[0435] The endoscope 11100 includes a lens barrel 11101 and a camera 11102 connected to the proximal end of the lens barrel 11101, and the lens barrel 11101 has a region of a predetermined length from its distal end to be inserted into a body cavity of a patient 11132. In the illustrated example, the endoscope 11100 is shown as a rigid endoscope having a rigid lens barrel 11101. However, the endoscope 11100 may be additionally included as a flexible endoscope having a flexible lens barrel.

[0436] The lens barrel 11101 has an opening at its distal end, and the objective lens is assembled in the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the front end of the lens barrel 11101 by the light guide extending inside the lens barrel 11101, and irradiated toward the observation object in the body cavity of the patient 11132 via the objective lens. Note that the endoscope 11100 can be either a straight-view endoscope, an oblique-view endoscope, or a side-view endoscope.

[0437] The optical system and the imaging element are arranged inside the camera 11102 so that the reflected light (observation light) from the observation target is focused on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as raw data.

[0438] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102 and, for example, performs various image processing for displaying an image based on the image signal, such as development processing (demosaic processing), on the image signal.

[0439] The display device 11202 displays an image thereon based on an image signal under the control of the CCU 11201 , wherein image processing is performed on the image signal by the CCU 11201 .

[0440] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and provides the endoscope 11100 with irradiation light for photographing the operation area.

[0441] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various information and input instructions to the endoscopic surgery system 11000 through the input device 11204. For example, the user inputs instructions for changing the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0442] The treatment instrument control device 11205 controls the drive of the energy treatment instrument 11112 for removing tissue, cutting, sealing blood vessels, etc. In order to ensure the field of view of the endoscope 11100 and the working space of the surgeon, the pneumoperitoneum device 11206 supplies gas to the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms (such as text, images or graphics).

[0443] Note that the light source device 11203 that provides irradiation light when imaging the surgical area to the endoscope 11100 may include a white light source, which includes, for example, an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing can be controlled with high precision for each color (each wavelength), the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the observation target with laser light from each RGB laser light source in a time-division manner, and controlling the drive of the imaging element of the camera 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained even if a color filter is not provided for the imaging element.

[0444] In addition, the drive of the light source device 11203 can be controlled so as to change the intensity of the output light at predetermined time intervals. By controlling the drive of the imaging element of the camera 11102 in synchronization with the timing of the light intensity change to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0445] In addition, the light source device 11203 can be configured to provide light of a prescribed wavelength band for special light observation. In special light observation, for example, by utilizing the wavelength dependence of the absorption of light by biological tissue to irradiate light of a narrower band than the irradiation light (i.e., white light) during normal observation, narrow-band light observation (narrow-band light observation) is performed to image prescribed tissues such as blood vessels in the surface layer of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation in which an image is obtained from fluorescence generated by irradiation with excitation light can also be performed. In fluorescence observation, it is possible to observe fluorescence from biological tissue by irradiating excitation light to biological tissue (autofluorescence observation), or to obtain a fluorescence image by locally injecting a reagent such as indocyanine green (ICG) into the biological tissue and irradiating the biological tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for special light observation as described above.

[0446] Fig.71 It is shown Fig.71 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0447] The camera head 11102 includes a lens unit 11401, an imaging section 11402, a driving section 11403, a communication section 11404, and a camera control section 11405. In addition, the CCU 111201 includes, as its functions, a communication section 11411, an image processing section 11412, and a control section 11413. The camera head 11102 and the CCU 11201 are connected by a transmission cable 11400 for communication with each other.

[0448] The lens unit 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0449] The imaging unit 11402 includes an imaging element. The number of imaging elements included in the imaging unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B may be generated by the corresponding imaging elements, and a color image may be obtained by combining the generated image signals. Alternatively, the imaging unit 11402 may include a pair of imaging elements for acquiring a right-eye image signal and a left-eye image signal corresponding to a three-dimensional (3D) display. In the case of a 3D display, the surgeon 11131 can more accurately grasp the depth of the living body tissue within the surgical area. Note that in the case where the imaging unit 11402 is a multi-board type, a plurality of lens unit 11401 systems are provided corresponding to a single imaging element.

[0450] In addition, the imaging portion 11402 may not necessarily be provided on the camera head 11102. For example, the imaging portion 11402 may be provided immediately behind the objective lens in the interior of the lens barrel 11101.

[0451] The driving section 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera control section 11405. Therefore, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0452] The communication section 11404 includes a communication device for sending and receiving various information to and from the CCU 11201. The communication section 11404 transmits the image signal acquired from the imaging section 11402 to the CCU 11201 as raw data through the transmission cable 11400.

[0453] Furthermore, the communication section 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and supplies the control signal to the camera control section 11405. The control signal includes, for example, information on imaging conditions, such as information specifying a frame rate for capturing an image, information specifying an exposure value at the time of imaging, and / or information specifying a magnification and a focus for capturing an image.

[0454] Note that imaging conditions such as frame rate, exposure value, magnification, or focus may be specified by a user or may be automatically set based on an acquired image signal by the control section 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are incorporated in the endoscope 11100.

[0455] The camera control unit 11405 controls the driving of the camera 11102 based on the control signal from the CCU 111201 received through the communication unit 11404 .

[0456] The communication section 11411 includes a communication device for sending and receiving various information to and from the camera 11102. The communication section 11411 receives an image signal transmitted thereto from the camera 11102 through the transmission cable 11400.

[0457] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0458] The image processing unit 11412 performs various image processing on the image signal in the raw data form sent thereto from the camera 11102 .

[0459] The control section 11413 performs various controls related to image capture of the operation area, etc. of the endoscope 11100 and display of a captured image obtained by the image capture of the operation area, etc. For example, the control section 11413 creates a control signal for controlling the driving of the camera head 11102 .

[0460] In addition, the control unit 11413 controls the display device 11202 to display the captured image of the surgical area, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 can use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can identify surgical instruments such as forceps, specific living areas, bleeding, and mist when using the energy treatment instrument 11112 by detecting the shape, color, etc. of the edge of the object body contained in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the recognition result to display various surgical support information in a manner overlapping with the image of the surgical area. By overlapping the display of the surgical support information and prompting the surgeon 11131, the burden of the surgeon 11131 can be reduced and the surgeon 11131 can reliably perform the operation.

[0461] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable prepared for communication of electric signals, an optical fiber prepared for optical communication, or a composite cable prepared for both electric communication and optical communication.

[0462] Here, in the example shown, communication is performed by wire using the transmission cable 11400, but communication between the camera 11102 and the CCU 11201 may be performed wirelessly.

[0463] An example of an endoscopic surgical system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be appropriately applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100 in the above configuration. By applying the technology according to the present disclosure to the imaging unit 11402, the imaging unit 11402 can be reduced in size or high in definition, so that an endoscope 11100 having a small size or high in definition can be provided.

[0464] Although the present disclosure has been described with reference to the above-mentioned embodiments, modifications, application examples, and application examples thereof, the present disclosure is not limited to the embodiments, etc., and various modifications may be made. Note that the effects described in this specification are only examples. The effects of the present disclosure are not limited to the effects described herein. The present disclosure may have effects other than the effects described herein.

[0465] Note that the present technology can have the following configurations.

[0466] (1) A comparator that compares a signal with a reference signal and outputs a comparison result, the comparator comprising:

[0467] a differential circuit that outputs a differential voltage between the signal and a reference signal; and

[0468] An active load circuit is electrically connected to the differential circuit, wherein:

[0469] The differential circuit includes a first transistor and a second transistor disposed on a surface of the substrate; and

[0470] The first transistor and the second transistor have a channel region extending in a direction substantially perpendicular to a surface of the substrate.

[0471] (2) The comparator according to (1), wherein the channel regions of the first transistor and the second transistor have a concavo-convex shape along a direction substantially perpendicular to a channel length direction.

[0472] (3) The comparator according to (2), wherein the channel regions of the first transistor and the second transistor do not have a concavo-convex shape along a channel length direction.

[0473] (4) The comparator according to any one of (1) to (3), wherein:

[0474] The active load circuit includes a third transistor and a fourth transistor disposed on a surface of the substrate, and

[0475] The channel regions of the third transistor and the fourth transistor have a concavo-convex shape along the channel length direction.

[0476] (5) The comparator according to any one of (1) to (4), wherein:

[0477] The active load circuit includes a third transistor and a fourth transistor disposed on a surface of the substrate, and

[0478] The gate insulating films of the third transistor and the fourth transistor are thicker than the gate insulating films of the first transistor and the fourth transistor.

[0479] (6) The comparator according to any one of (1) to (5), wherein:

[0480] The active load circuit includes a third transistor and a fourth transistor disposed on a surface of the substrate, the first transistor and the second transistor are n-type transistors, and

[0481] The third transistor and the fourth transistor are p-type transistors.

[0482] (7) The comparator according to (6), wherein the channel length directions of the third transistor and the fourth transistor are substantially perpendicular or substantially parallel to the (100) crystal plane of the substrate.

[0483] (8) A comparator according to (6), wherein:

[0484] The substrate is a 45-degree notch substrate, and

[0485] The channel length directions of the third transistor and the fourth transistor are substantially perpendicular or substantially parallel to the notch plane on the surface of the substrate.

[0486] (9) A comparator according to (6), wherein:

[0487] The substrate is a 0 degree notch substrate, and

[0488] The channel length directions of the third transistor and the fourth transistor are directions inclined at about 45 degrees or about 135 degrees with respect to the notch plane on the surface of the substrate.

[0489] (10) The comparator according to any one of (1) to (5), wherein:

[0490] The active load circuit includes a third transistor and a fourth transistor disposed on a surface of the substrate, the first transistor and the second transistor are p-type transistors, and

[0491] The third transistor and the fourth transistor are n-type transistors.

[0492] (11) The comparator according to (10), wherein a channel length direction of the first transistor and the second transistor is substantially perpendicular or substantially parallel to a (110) crystal plane of the substrate.

[0493] (12) A comparator according to (10), wherein:

[0494] The substrate is a 45-degree notch substrate, and

[0495] The channel length directions of the first transistor and the second transistor are directions inclined at about 45 degrees or about 135 degrees with respect to the notch plane on the surface of the substrate.

[0496] (13) A comparator according to (10), wherein:

[0497] The substrate is a 0 degree notch substrate, and

[0498] The channel length directions of the first transistor and the second transistor are substantially perpendicular or substantially parallel to the notch plane on the surface of the substrate.

[0499] (14) A light detection element comprising:

[0500] a pixel portion including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; and

[0501] a comparator, comparing the pixel signal with a reference signal and outputting a comparison result,

[0502] The comparator includes:

[0503] a differential circuit that outputs a differential voltage between a pixel signal and a reference signal; and

[0504] An active load circuit is electrically connected to the differential circuit, wherein:

[0505] The differential circuit includes a first transistor and a second transistor disposed on a surface of the substrate; and

[0506] The first transistor and the second transistor have a channel region extending in a direction substantially perpendicular to a surface of the substrate.

[0507] (15) The light detection element according to (14), wherein:

[0508] The pixel portion is disposed on the first substrate.

[0509] The comparator is disposed on a second substrate different from the first substrate,

[0510] laminating a first substrate and a second substrate, and

[0511] The pixel portion and the comparator are electrically connected through a through electrode provided on the first substrate or the second substrate or through a wiring junction between a wiring of the first substrate and a wiring of the second substrate.

[0512] (16) The light detection element according to (14), wherein:

[0513] The pixel portion and the comparator are arranged on the same first substrate,

[0514] The comparator is disposed above the pixel portion of the first substrate, and

[0515] The pixel portion and the comparator are electrically connected through a contact plug provided in an interlayer insulating film between the pixel portion and the comparator.

[0516] (17) The light detection element according to (14), wherein:

[0517] The differential circuit is arranged on the first substrate.

[0518] The active load circuit is disposed on a second substrate different from the first substrate,

[0519] laminating a first substrate and a second substrate, and

[0520] The differential circuit and the active load circuit are electrically connected by bonding the wiring of the first substrate and the wiring of the second substrate.

[0521] (18) The light detection element according to (17), wherein:

[0522] The pixel portion and the differential circuit are arranged on the same first substrate;

[0523] A differential circuit is disposed over a pixel portion of the first substrate; and

[0524] The pixel portion and the differential circuit are electrically connected via a contact plug provided in an interlayer insulating film between the pixel portion and the differential circuit.

[0525] (19) The light detection element according to (14), wherein:

[0526] The pixel portion and the comparator are arranged on the same first substrate;

[0527] The differential circuit is provided in the same layer as the transistor of the pixel portion;

[0528] The active load circuit is disposed above the pixel portion of the first substrate, and

[0529] The differential circuit and the active load circuit are electrically connected via a contact plug provided in an interlayer insulating film between the differential circuit and the active load circuit.

[0530] (20) An electronic device comprising the light detection element according to any one of (14) to (19).

[0531] The various aspects of the present disclosure are not limited to the above-mentioned embodiments, but include various modifications that can be thought of by those skilled in the art, and the effects of the present disclosure are not limited to the above-mentioned contents. That is, various additions, modifications, and partial deletions may be made without departing from the concept and spirit of the present disclosure obtained from the contents defined in the claims and their equivalents.

[0532] Reference Mark List

[0533] 100 First Substrate

[0534] 200 Second substrate

[0535] 300 Third substrate

[0536] 210 Comparator

[0537] 539 pixel sharing unit

[0538] 210a Current Mirror Circuit

[0539] 210b differential circuit

[0540] 210c Current Source

[0541] Tp1, Tp2 p-type transistor

[0542] Tn1 to Tn4 n-type transistors

[0543] PD Photodiode

[0544] FD floating diffusion

[0545] TR transfer transistor

[0546] OF overflow gate

[0547] CCC wiring knot

[0548] VIA through-hole contact

[0549] PLG contact plug

[0550] W0 0 degree notch base plate

[0551] W45 45 degree notch base plate

[0552] CHtp channel region

[0553] Gtp gate electrode

[0554] D1, D2 channel length direction

[0555] CHtp, CHtn channel regions.

Claims

1. A comparator, which compares a signal with a reference signal and outputs a comparison result, the comparator comprising: A differential circuit outputs a differential voltage between the signal and the reference signal; as well as an active load circuit electrically connected to the differential circuit, wherein: The differential circuit includes a first transistor and a second transistor disposed on a surface of a substrate; and The first transistor and the second transistor have channel regions extending in a direction substantially perpendicular to the surface of the substrate.

2. The comparator according to claim 1, wherein: The channel regions of the first transistor and the second transistor have a concavo-convex shape along a direction substantially perpendicular to a channel length direction.

3. The comparator according to claim 2, wherein: The channel regions of the first transistor and the second transistor do not have a concavo-convex shape along the channel length direction.

4. The comparator according to claim 1, wherein: The active load circuit includes a third transistor and a fourth transistor disposed on the surface of the substrate, and The channel regions of the third transistor and the fourth transistor have a concavo-convex shape along a channel length direction.

5. The comparator according to claim 1, wherein: The active load circuit includes a third transistor and a fourth transistor disposed on the surface of the substrate, and The gate insulating films of the third transistor and the fourth transistor are thicker than the gate insulating films of the first transistor and the fourth transistor.

6. The comparator according to claim 1, wherein: The active load circuit includes a third transistor and a fourth transistor disposed on the surface of the substrate, The first transistor and the second transistor are n-type transistors, and The third transistor and the fourth transistor are p-type transistors.

7. The comparator according to claim 6, wherein: The channel length directions of the third transistor and the fourth transistor are substantially perpendicular or substantially parallel to the (100) crystal plane of the substrate.

8. The comparator according to claim 6, wherein: The substrate is a 45-degree notch substrate, and Channel length directions of the third transistor and the fourth transistor are substantially perpendicular or substantially parallel to a notch plane on the surface of the substrate.

9. The comparator according to claim 6, wherein: The substrate is a 0 degree notch substrate, and The channel length directions of the third transistor and the fourth transistor are directions inclined at about 45 degrees or about 135 degrees with respect to the notch plane on the surface of the substrate.

10. The comparator according to claim 1, wherein: The active load circuit includes a third transistor and a fourth transistor disposed on the surface of the substrate, The first transistor and the second transistor are p-type transistors, and The third transistor and the fourth transistor are n-type transistors.

11. The comparator according to claim 10, wherein: The channel length directions of the first transistor and the second transistor are substantially perpendicular or substantially parallel to the (110) crystal plane of the substrate.

12. The comparator according to claim 10, wherein: The substrate is a 45-degree notch substrate, and The channel length directions of the first transistor and the second transistor are directions inclined at about 45 degrees or about 135 degrees with respect to a notch plane on the surface of the substrate.

13. The comparator according to claim 10, wherein: The substrate is a 0 degree notch substrate, and Channel length directions of the first transistor and the second transistor are substantially perpendicular or substantially parallel to a notch plane on the surface of the substrate.

14. A light detection element, comprising: A pixel portion including a photoelectric conversion element that photoelectrically converts incident light into a pixel signal; as well as a comparator, comparing the pixel signal with a reference signal and outputting a comparison result, The comparator comprises: a differential circuit, outputting a differential voltage between the pixel signal and the reference signal; and an active load circuit electrically connected to the differential circuit, wherein: The differential circuit includes a first transistor and a second transistor disposed on a surface of a substrate; and The first transistor and the second transistor have channel regions extending in a direction substantially perpendicular to the surface of the substrate.

15. The light detecting element according to claim 14, wherein The pixel portion is disposed on the first substrate, The comparator is disposed on a second substrate different from the first substrate, laminating the first substrate and the second substrate, and The pixel portion and the comparator are electrically connected through a through electrode provided on the first substrate or the second substrate or through a wiring junction between a wiring of the first substrate and a wiring of the second substrate.

16. The light detecting element according to claim 14, wherein The pixel portion and the comparator are arranged on the same first substrate, The comparator is provided over the pixel portion of the first substrate, and the pixel portion and the comparator are electrically connected through a contact plug provided in an interlayer insulating film between the pixel portion and the comparator.

17. The light detecting element according to claim 14, wherein The differential circuit is arranged on the first substrate. The active load circuit is disposed on a second substrate different from the first substrate, laminating the first substrate and the second substrate, and The differential circuit and the active load circuit are electrically connected by bonding a wiring of the first substrate and a wiring of the second substrate.

18. The light detecting element according to claim 17, wherein The pixel portion and the differential circuit are arranged on the same first substrate; The differential circuit is disposed above the pixel portion of the first substrate; and The pixel portion and the differential circuit are electrically connected via a contact plug provided in an interlayer insulating film between the pixel portion and the differential circuit.

19. The light detecting element according to claim 14, wherein The pixel portion and the comparator are arranged on the same first substrate; The differential circuit is provided in the same layer as the transistor of the pixel portion; The active load circuit is disposed above the pixel portion of the first substrate; and The differential circuit and the active load circuit are electrically connected via a contact plug provided in an interlayer insulating film between the differential circuit and the active load circuit.

20. An electronic device comprising the light detecting element according to claim 14.

Images