Multi-gate hybrid channel field effect transistor
By introducing additional semiconductor channel layers into the FET structure and forming a fin-shaped structure, the problem of limited increase in effective transistor width in the prior art is solved, and the current gain and performance improvement is achieved.
Patent Information
- Application Number
- CN202380050759.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2022-06-29
- Filing Date
- 2023-06-26
- Publication Date
- 2025-02-18
AI Technical Summary
The existing FET structures are limited by the bottom channel layer efficiency when increasing the effective transistor width, resulting in a decrease in current.
By introducing at least one additional semiconductor channel layer into the FET structure and positioning it within the gap between the first and second stacks, a fin-like structure is formed to increase the effective transistor width.
Current gain is achieved and performance of integrated devices is improved, especially in three-door fork-sheet devices.
Smart Images
Figure CN119487991A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a field effect transistor (FET) and a method for manufacturing the FET. The present invention provides a multi-gate hybrid channel FET structure. The FET structure can be used to manufacture integrated devices such as nanosheet devices or forksheet devices. Background Art
[0002] Integrated devices including FET structures can improve device performance by increasing the effective transistor width. This can be achieved by using a stack of multiple semiconductor channel layers to form the FET structure. The effective transistor width depends on the channel width and channel height of each channel layer, and on the total number of channel layers used.
[0003] Therefore, one way to increase the effective transistor width is to increase the number of channel layers. However, this number is limited by the efficiency of the bottom channel layer. Since the voltage on the lower channel layers decreases, the current along these layers is observed to decrease. Summary of the Invention
[0004] The present invention aims to increase the effective transistor width in FET structures and / or integrated devices in various ways. For example, the present invention aims to achieve a better effective transistor width in a three-gate prong wafer-like device. Thus, the present invention aims to improve device performance.
[0005] This is achieved by the measures of the invention described in the independent claim. Advantageous implementations are defined in the dependent claims.
[0006] A first aspect of the present invention provides a FET structure for a nanosheet device, the FET structure comprising: a substrate layer; a first layer stack and a second layer stack, arranged side by side on the substrate layer, wherein the first layer stack and the second layer stack each include one or more semiconductor channel layers and one or more gate layers, the one or more semiconductor channel layers and the one or more gate layers being stacked in an alternating manner along a first direction perpendicular to the surface of the substrate layer, wherein the respective surfaces of the semiconductor channel layers and the gate layers are parallel to the surface of the substrate layer; at least a first additional semiconductor channel layer and a second additional semiconductor channel layer, the first additional semiconductor channel layer being arranged next to the first layer stack and the second additional semiconductor channel layer being arranged next to the second layer stack, wherein the respective surfaces of the first additional semiconductor channel layer and the second additional semiconductor channel layer are parallel to each other and perpendicular to the surface of the substrate layer; a dielectric wall arranged on the substrate layer between the first layer stack and the first additional semiconductor channel layer on one side and the second layer stack and the second additional semiconductor channel layer on the other side.
[0007] The first additional semiconductor channel layer and the second additional semiconductor channel layer may each be a fin-shaped structure extending in a first direction, for example, each may be a vertical fin. For example, each additional semiconductor channel layer has a high aspect ratio, that is, the ratio of the extension of each additional semiconductor channel layer to the first direction (layer length / height) to the extension of each additional semiconductor channel layer to the second direction perpendicular to the first direction (layer thickness). The additional semiconductor channel layer can increase the effective transistor width in each layer stack. For example, the possible total width gain can be 2*n*Vp, where n is the number of semiconductor channel layers in the layer stack, and Vp is the spacing of these channel layers in the layer stack, which are stacked in the first direction (wherein the gate layer is arranged between these channel layers). The additional semiconductor channel layer can be arranged in a gap between the first layer stack and the second layer stack, the gap being large enough so that the space occupied by the additional semiconductor channel layer can be ignored. The FET structure of the first aspect can provide current gain and can improve the device performance of the integrated device.
[0008] In an implementation of the first aspect, the first additional semiconductor channel layer adjoins the first layer stack; and / or the second additional semiconductor channel layer adjoins the second layer stack.
[0009] Therefore, the space occupied between the two layer stacks is minimal.
[0010] In an implementation of the first aspect, the FET structure further includes: a third additional semiconductor channel layer, arranged next to the first layer stack and located on the other side of the first layer stack, the other side being not the side where the first additional semiconductor channel layer is located; a fourth additional semiconductor channel layer, arranged next to the second layer stack and located on the other side of the second layer stack, the other side being not the side where the second additional semiconductor channel layer is located; wherein the dielectric wall is arranged between the first layer stack, the first additional semiconductor channel layer and the third additional semiconductor channel layer on one side and the second layer stack, the second additional semiconductor channel layer and the fourth additional semiconductor channel layer on the other side.
[0011] This can further increase the effective transistor channel width, thereby increasing the current gain.
[0012] In an implementation of the first aspect, the third additional semiconductor channel layer adjoins the first layer stack; and / or the fourth additional semiconductor channel layer adjoins the second layer stack.
[0013] In this way, a compact FET structure can be achieved.
[0014] In an implementation of the first aspect, each additional semiconductor channel layer is spaced apart from the layer stack and arranged next to the layer stack.
[0015] In an implementation of the first aspect, the first layer stack and the first additional semiconductor channel layer form an n-type FET (n-FET); and / or the second layer stack and the second additional semiconductor channel layer form a p-type FET (p-FET).
[0016] In an implementation of the first aspect, each additional semiconductor channel layer arranged next to the first layer stack is made of n-type silicon-based semiconductor material; and / or each additional semiconductor channel layer arranged next to the second layer stack is made of p-type silicon-based semiconductor material.
[0017] In an implementation of the first aspect, each additional semiconductor channel layer includes one or more portions made of silicon and one or more portions made of silicon germanium.
[0018] Due to the high mobility of silicon germanium, the heterostructure of silicon and silicon germanium with an additional semiconductor channel layer can generate more current gain.
[0019] In an implementation of the first aspect, the one or more portions made of silicon of each additional semiconductor channel layer are respectively arranged next to the one or more semiconductor channel layers of the layer stack, the additional semiconductor channel layers being arranged next to the layer stack.
[0020] In an implementation of the first aspect, the one or more gate layers of the first layer stack are made of an n-type work function metal; and the one or more gate layers of the second layer stack are made of a p-type work function metal.
[0021] In one implementation of the first aspect, the FET structure further includes: a first gate all around (GAA) structure surrounding the first layer stack and each additional semiconductor channel layer arranged next to the first layer stack, wherein the one or more gate layers of the first layer stack are formed integrally with the first GAA structure; and / or a second GAA structure surrounding the second layer stack and each additional semiconductor channel layer arranged next to the second layer stack, wherein the one or more gate layers of the second layer stack are formed integrally with the second GAA structure.
[0022] This GAA structure is conducive to the manufacture of integrated devices, for example, nanosheet devices or forksheet devices using the FET structure of the first aspect.
[0023] In an implementation of the first aspect, the FET structure further includes a dielectric material arranged on the substrate layer and surrounding the first layer stack, the second layer stack, each additional semiconductor channel layer, each GAA structure and the dielectric wall.
[0024] In an implementation of the first aspect, the first layer stack, each additional semiconductor channel layer arranged next to the first layer stack, and the first GAA structure form an n-FET structure; the second layer stack, each additional semiconductor channel layer arranged next to the second layer stack, and the second GAA structure form a p-FET structure.
[0025] A second aspect of the present invention provides a nanosheet device comprising a FET structure according to the first aspect or any implementation thereof.
[0026] Due to the FET structure of the first aspect included in the integrated device, the integrated device can have improved device performance.
[0027] A third aspect of the present invention provides a method for manufacturing a FET structure of a nanosheet device, the method comprising: forming a substrate layer; forming a first layer stack and a second layer stack side by side on the substrate layer; wherein the first layer stack and the second layer stack each include one or more semiconductor channel layers and one or more gate layers, and the one or more semiconductor channel layers and the one or more gate layers are stacked in an alternating manner along a first direction perpendicular to the surface of the substrate layer; wherein the corresponding surfaces of the semiconductor channel layers and the gate layers are parallel to the surface of the substrate layer; forming at least a first additional semiconductor channel layer next to the first layer stack and forming a second additional semiconductor channel layer next to the second layer stack, wherein the corresponding surfaces of the first additional semiconductor channel layer and the second additional semiconductor channel layer are parallel to each other and perpendicular to the surface of the substrate layer; forming a dielectric wall on the substrate layer between the first layer stack and the first additional semiconductor channel layer on one side and the second layer stack and the second additional semiconductor channel layer on the other side.
[0028] The method of the third aspect may have an implementation according to the implementation of the FET structure of the first aspect. Specifically, each implementation of the method may form an implementation of the FET structure. Therefore, the method described in the third aspect and its possible implementations achieves the same advantages as the FET structure described in the first aspect and its corresponding implementations. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] The following description of specific embodiments will illustrate the above aspects and their implementation methods in conjunction with the accompanying drawings. In the drawings:
[0030] Figure 1 The FET structure provided by the present invention is shown.
[0031] Figure 2 Various examples of FET structures provided by the present invention are shown.
[0032] Figure 3 A first exemplary process for fabricating a FET structure provided by the present invention is shown.
[0033] Figure 4 A second exemplary process for fabricating a FET structure provided by the present invention is shown.
[0034] Figure 5 A third exemplary process for fabricating a FET structure provided by the present invention is shown.
[0035] Figure 6 A fourth exemplary process for fabricating a FET structure provided by the present invention is shown.
[0036] Figure 7 A fifth exemplary process for fabricating a FET structure provided by the present invention is shown.
[0037] Figure 8 A sixth exemplary process for fabricating a FET structure provided by the present invention is shown.
[0038] Figure 9 The general method provided by the present invention for fabricating a FET structure is shown. DETAILED DESCRIPTION
[0039] Figure 1 The FET structure 100 provided by the present invention is shown. The FET structure 100 can be used as a basis for building an integrated device. The integrated device can be a nanosheet device, a fork-sheet device, or a complementary FET device, etc.
[0040] The FET structure 100 includes a substrate layer 101, which may be a semiconductor substrate layer, such as a silicon-based layer or a silicon layer. The substrate layer 101 may be disposed on or provided by a thick substrate or a wafer.
[0041] The FET structure 100 further includes a first layer stack 102 and a second layer stack 103, which are arranged side by side on the substrate layer 101. Thus, the first layer stack 102 is separated from the second layer stack 103 by a distance (along the second direction). Therefore, the first layer stack 102 is spaced apart from the second layer stack 103, and / or a gap is formed between the first layer stack 102 and the second layer stack 103.
[0042] Both the first layer stack 102 and the second layer stack 103 include one or more semiconductor channel layers 104 (e.g., silicon layers) and one or more gate layers 105 (e.g., metal layers and dielectric layers) stacked in an alternating manner along a first direction, wherein the first direction is perpendicular to the surface of the substrate layer 101 and the second direction (it should be noted that if the layers 104 and 105 are grown, for example, by epitaxial growth, the first direction may also be referred to as the stacking direction or growth direction). The respective surfaces of the semiconductor channel layers 104 and the gate layers 105 are parallel to the surface of the substrate layer 101 and are parallel to each other.
[0043] The FET structure 100 further includes at least a first additional semiconductor channel layer 106 (e.g., a silicon layer) arranged next to the first layer stack 102 and at least a second additional semiconductor channel layer 107 (e.g., a silicon layer) arranged next to the second layer stack 103. Respective surfaces of the first additional semiconductor channel layer 106 and the second additional semiconductor channel layer 107 are parallel to each other and perpendicular to the surface of the substrate layer 101. Therefore, the additional semiconductor channel layers 106, 107 can form a fin-like structure, which extends in a first direction as shown in the figure and can have a layer thickness measured in a second direction.
[0044] The FET structure 100 further includes a dielectric wall 108 (e.g., made of silicon oxide) disposed on the substrate layer 101. The dielectric wall 108 is located between the first layer stack 102 and the first additional semiconductor channel layer 106 on one side of the dielectric wall 108 and the second layer stack 103 and the second additional semiconductor channel layer 107 on the other side of the dielectric wall 108. Thus, the dielectric wall 108 is disposed between the first layer stack 102 and the second layer stack 103, for example, in the gap between the two layer stacks 102, 103.
[0045] Typically, the first layer stack 102 and the first additional semiconductor channel layer 106 of the FET structure 100 of the present invention may form an n-FET, while the second layer stack 103 and the second additional semiconductor channel layer 107 may form a p-FET. Figure 2. In this case, one or more gate layers 105 of the first layer stack 102 can be made of an n-type work function metal 105a, while one or more gate layers 105 of the second layer stack 103 can be made of a p-type work function metal 105b. In addition, the semiconductor channel layer 104 of the first layer stack 102 can be an undoped or p-type channel layer 104a, while the semiconductor channel layer 104 of the second layer stack 103 can be an undoped or n-type channel layer 105b. In addition, the first additional semiconductor channel layer 106 arranged next to the first layer stack 102 can be made of an undoped or p-type semiconductor material, and the second additional semiconductor channel layer 107 arranged next to the second layer stack 103 can be made of an undoped or n-type semiconductor material. Conventional semiconductor materials, such as silicon-based or III-V, and conventional dopants for these semiconductor materials can be used to obtain the above-mentioned n-type and p-type FETs, respectively.
[0046] Figure 2 Different examples of the FET structure 100 provided by the present invention are shown. Figure 2 In each example, as described above, an n-FET is formed using the first layer stack 102 and the first additional semiconductor channel layer 106 , and a p-FET is formed using the second layer stack 103 and the second additional semiconductor channel layer 107 .
[0047] exist Figure 2 In the example of FIG. 1 a, the first additional semiconductor channel layer 106 adjoins the first layer stack 102 and the second additional semiconductor channel layer 107 adjoins the second layer stack 103. For example, the dielectric wall 108 is formed of a dielectric material completely surrounding the layer stacks 102, 103 and the additional semiconductor channel layers 106, 107.
[0048] exist Figure 2 In the example of FIG. 1 b, the first additional semiconductor channel layer 106 does not abut the first layer stack 102 (but is separated from the first layer stack 102), and the second additional semiconductor channel layer 107 does not abut the second layer stack 103 (but is separated from the second layer stack 103). For example, the dielectric wall 108 is again formed of a dielectric material surrounding the layer stacks 102, 103 and the additional semiconductor channel layers 106, 107.
[0049] exist Figure 2In the example of FIG. 3 , the first additional semiconductor channel layer 106 and the second additional semiconductor channel layer 107 each include one or more portions made of a first semiconductor material (e.g., silicon) and one or more portions made of a second semiconductor material (e.g., silicon germanium). These different portions and semiconductor materials can be arranged alternately along the first direction. For example, a portion of the first semiconductor material of each additional semiconductor channel layer 106, 107 can be arranged next to one or more semiconductor channel layers 104 of the layer stacks 102, 103, respectively, and the additional semiconductor channel layers 106, 107 are arranged next to the layer stacks 102, 103. A portion of the second semiconductor material of each additional semiconductor channel layer 106, 107 can be arranged next to one or more gate layers 105 of the layer stacks 102, 103, respectively, and the additional semiconductor channel layers 106, 107 are arranged next to the layer stacks 102, 103. For example, the dielectric wall 108 is again formed by the dielectric material surrounding the layer stacks 102, 103 and the additional semiconductor channel layers 106, 107.
[0050] exist Figure 2 In the example of d, the FET structure 100 further includes a third additional semiconductor channel layer 201, which is arranged next to the first layer stack 102 and is located on the other side of the first layer stack 102, which is not the side where the first additional semiconductor channel layer 106 is located. In addition, the FET structure 100 includes a fourth additional semiconductor channel layer 202, which is arranged next to the second layer stack 102 and is located on the other side of the second layer stack 102, which is not the side where the second additional semiconductor channel layer 107 is located. The dielectric wall 108 is arranged between the first layer stack 102, the first additional semiconductor channel layer 106 and the third additional semiconductor channel layer 201 located on one side of the dielectric wall 108 and the second layer stack 103, the second additional semiconductor channel layer 107 and the fourth additional semiconductor channel layer 202 located on the other side of the dielectric wall 108. The dielectric wall 108 can be formed of a dielectric material (e.g., oxide) surrounding the layer stacks 102, 103 and the additional semiconductor channel layers 106, 107. In addition, in Figure 2 d, all additional semiconductor channel layers 106, 107, 201, 202 are shown by way of example as not adjoining the layer stacks 102, 103 and being arranged next to the layer stacks 102, 103. However, each additional semiconductor channel layer 106, 107, 201, 202 can also adjoin the laser stack 102, 203 individually (i.e. independently of the others) and be arranged next to the layer stack 102, 203. That is, each layer stack 102, 103 can have no, one, or two adjacent additional semiconductor channel layers 106, 107, 201, 202. Figure 2 The same is true for the FET structure 100 of c.
[0051] Figure 3 A first exemplary process for manufacturing a FET structure 100 according to the present invention is shown. In this case, the FET structure 100 comprises one additional semiconductor layer 106, 107 (fin) per layer stack 102, 103, wherein each additional semiconductor layer 106, 107 is adjacent to the layer stack 102, 103 and is arranged next to the layer stack 102, 103. Thus, Figure 3 The process can be used to form Figure 2 a FET structure 100.
[0052] Figure 3 Figure a shows that a first layer stack 102 and a second layer stack 103 are initially manufactured on a substrate layer 101. For example, each layer stack 102, 103 can be epitaxially grown on the substrate layer 101. Thereby, a gap can be formed between the first layer stack 102 and the second layer stack 103. However, it is also possible to grow a larger layer stack and then separate the larger layer stack into the first layer stack 102 and the second layer stack 103, for example by etching trenches. This can be done by using a hard mask 302, as shown in the figure. It should be noted that for the first layer stack 102 and the second layer stack 103, the semiconductor channel layer 104 can be the same, that is, have the same semiconductor material (for example, silicon). However, as Figure 3 As shown by different shading in FIG, they may be n-type channel layer 104a and p-type channel layer 104b, respectively. This can be achieved by different doping profiles of semiconductor materials.
[0053] It should be noted that at this point in the process (i.e. Figure 3 As shown in FIG. 1 ), each layer stack 102 and 103 is an intermediate layer stack because each layer stack 102 and 103 includes a semiconductor channel layer 104 (e.g., made of silicon) and a semiconductor dummy gate layer 301 (e.g., made of silicon germanium) instead of Figure 1 and 2 The gate layer 105 is shown. However, for simplicity, the present invention relates to the first layer stack 102 and the second layer stack 103 regardless of whether the gate layer 105 or the dummy gate layer 301 is present.
[0054] Figure 3 Figure a also shows that a first additional semiconductor channel layer 106 and a second additional semiconductor channel layer 107 can be grown laterally, for example by lateral epitaxy, onto the sidewalls of the first layer stack 102 and the second layer stack 103. This is possible because there is a gap between the layer stacks 102, 103.
[0055] Figure 3b shows that a dielectric protection layer 303 may then be inserted between the two layer stacks 102, 103, in particular, into the gap separating the two layer stacks 102, 103. For example, the dielectric protection layer 303 may be formed by dielectric deposition.
[0056] Figure 3 c shows that the semiconductor dummy gate layer 301 can then be replaced by the gate layer 104 (e.g., metal). This can be achieved by selectively etching the dummy gate layer 301 (e.g., made of silicon germanium) and then depositing a gate material (e.g., a metal material) to form the gate layer 105. In the deposition step, different metal materials can be used to form different gate layers 105a, 105b for the two layer stacks 102, 103, for example, using an n-type work function metal for the first layer stack 102 and a p-type work function metal for the second layer stack 103. The dielectric protection layer 303 is also removed, and (not shown) finally, the dielectric wall 108 can be filled into the space between the two layer stacks 102, 103 formed by removing the dielectric protection layer 303. The dielectric protection layer 303 can also be retained to form the dielectric wall 108.
[0057] Figure 4 A second exemplary process for manufacturing a FET structure 100 according to the present invention is shown. In this case, the FET structure 100 includes one additional semiconductor layer 106, 107 (e.g., a fin) per layer stack 102, 103, wherein each additional semiconductor layer 106, 107 does not adjoin the layer stack 102, 103 and is arranged next to the layer stack 102, 103. Thus, Figure 4 The process can be used to form Figure 2 b FET structure 100.
[0058] Figure 4 The process is similar to Figure 3 The process shown, however, Figure 4 In a, it starts with the arrangement of a dielectric protection layer 303 between the two layer stacks 102 , 103 .
[0059] exist Figure 4 In FIG. 5 , the dielectric protection layer 303 is removed, and the first additional semiconductor channel layer 106 and the second semiconductor channel layer 107 are formed, for example, by lateral epitaxy. It should be noted that the lateral epitaxy can be performed directly on the material of the semiconductor dummy gate layer 301 (for example, silicon germanium), and the semiconductor dummy gate layer 301 can extend beyond the channel layer 104 into the gap between the layer stacks 102 and 103, so that the additional semiconductor channel layers 106 and 107 do not adjoin the layer stacks 102 and 103 (in particular, do not adjoin the channel layer 104) at a later time, and are arranged next to the layer stacks 102 and 103.
[0060] exist Figure 4In FIG. 3 , the gate layer 104 is formed by replacing the semiconductor dummy gate layer 301 with at least one metal material. A dielectric wall 108 may be filled into the space between the two layer stacks 102 and 103 .
[0061] Figure 5 A third exemplary process for manufacturing a FET structure 100 according to the present invention is shown. In this case, the FET structure 100 includes one additional semiconductor layer 106, 107 (e.g., a fin) per layer stack 102, 103, wherein each additional semiconductor layer 106, 107 does not adjoin the layer stack 102, 103 and is arranged next to the layer stack 102, 103. Thus, Figure 5 The process can be used to form Figure 2 b FET structure 100.
[0062] exist Figure 5 In Figure a, a larger layer stack including a semiconductor channel layer 104 (e.g., silicon) and a semiconductor dummy gate layer 301 (e.g., silicon germanium) is grown on a substrate layer 101 (e.g., silicon). In addition, a dielectric layer 503 and spacer layers 501 and 502 are arranged on top of the larger layer stack.
[0063] Figure 5 b shows that the previously grown larger layer stack is then etched using spacer layers 501 and 502 to obtain respectively narrower first layer stack 102, second layer stack 103 and a third layer stack arranged between the first layer stack 102 and the second layer stack 103. This can be done by any trench etching procedure.
[0064] Figure 5 c shows that dielectric spacers 505 are then formed on the side surfaces of the three layer stacks, specifically on the side surfaces of the first layer stack 102 and the second layer stack 103 .
[0065] exist Figure 5 In d, the remaining free space between the dielectric spacers 505 is filled with semiconductor material, which forms the first additional semiconductor channel layer 106 and the second additional semiconductor channel layer 107. Planarization may then be performed.
[0066] exist Figure 5 In FIG. 5 , the third layer stack located between the first layer stack 102 and the second layer stack 103 is removed, for example by etching. The created space is filled with a dielectric material, which forms a dielectric wall 108 .
[0067] exist Figure 5 In step f, a sacrificial release process is performed to selectively remove the semiconductor dummy gate layer 301 .
[0068] exist Figure 5g, a gate layer 105 is formed. Specifically, as shown in the figure, a gate layer 105a made of an n-type work function metal and a gate layer 105b made of a p-type work function metal 105b can be formed for the first layer stack 102 and the second layer stack 105b, respectively. It should be noted that the one or more gate layers 105a of the first layer stack 102 and the one or more gate layers 105b of the second layer stack 103 can be formed by being integrally formed with the first GAA structure and the second GAA structure, respectively. These GAA structures can be formed around the first layer stack 102 and the first semiconductor channel layer 106 arranged next to the first layer stack 102, and around the second layer stack 103 and the second additional semiconductor channel layer 107 arranged next to the second layer stack 103, respectively. In this way, the first layer stack 102, the first additional semiconductor channel layer 106, and the first GAA structure can form an n-FET structure. Similarly, the second layer stack 103, the second additional semiconductor channel layer 107, and the second GAA structure can form a p-FET structure.
[0069] exist Figure 5 In FIG. 1 , a dielectric material 504 is arranged on the substrate layer 101 , wherein the dielectric material 504 surrounds the first layer stack 102 , the second layer stack 103 , each additional semiconductor channel layer 106 , 107 , and the dielectric wall 108 , and optionally surrounds each GAA structure.
[0070] Figure 6 A fourth exemplary process for manufacturing a FET structure 100 according to the present invention is shown. In this case, the FET structure 100 includes two additional semiconductor layers 106, 201, 107, 202 (e.g., fins) per layer stack 102, 103, wherein each additional semiconductor layer 106, 107, 201, 202 does not adjoin the layer stack 102, 103 (specifically, does not adjoin the semiconductor channel layer 104 thereof) and is arranged next to the layer stack 102, 103. Thus, Figure 6 The process can be used to form Figure 2 d FET structure 100.
[0071] Process similar to Figure 5 The main difference is that in this fourth exemplary process, Figure 6 D additionally forms a third additional semiconductor layer 201 and a fourth additional semiconductor layer 202. To this end, Figure 6 In b, additional spaces are etched on the outer sides of the layer stacks 102 , 103 , respectively, at locations where the third additional semiconductor channel layer 201 and the fourth additional semiconductor channel layer 202 are subsequently formed.
[0072] For example, without providing a dielectric layer (with Figure 5 e) but by Figure 6 h forms the surrounding dielectric material 504 integrally with the dielectric wall 108. Figure 6 The process is also applicable.
[0073] Figure 7 A fifth exemplary process for manufacturing a FET structure 100 according to the present invention is shown. In this case, the FET structure 100 includes one additional semiconductor layer 106, 107 (e.g., a fin) per layer stack 102, 103, wherein each additional semiconductor layer 106, 107 is not adjacent to the layer stack 102, 103, is arranged next to the layer stack 102, 103, and includes a portion of a different semiconductor material. Thus, Figure 7 The process can be used to form Figure 2 c FET structure 100.
[0074] exist Figure 7 In a, a layer stack of a semiconductor channel layer 104 and a semiconductor dummy gate layer 301 is formed on a substrate layer 101. Furthermore, a dielectric layer 503 and spacer layers 701, 702 and 703 are formed on top of the layer stack.
[0075] exist Figure 7 In b, the spacer layer 702 is selectively removed, for example, by selective etching.
[0076] exist Figure 7 In c, the gap created by removing the spacer layer 702 is used to etch a trench into the layer stack.
[0077] exist Figure 7 In d, these etched trenches are filled with dielectric material 704. Planarization may then be performed.
[0078] exist Figure 7 In e, the outermost sides of the middle FET structure are shown removed.
[0079] exist Figure 7 In step f, the semiconductor dummy gate layer 301 (eg made of silicon germanium) is selectively removed in the first layer stack 102 and the second layer stack 103 , for example by selective etching.
[0080] exist Figure 7 In g, the dielectric material 704 is selectively removed. Thus, the first additional semiconductor layer 106 and the second additional semiconductor channel layer 107 are formed by free placement (as a fin-shaped structure extending from the substrate layer 101 along the first direction). It should be noted that since the first additional semiconductor layer 106 and the second additional semiconductor channel layer 107 are formed by free placement (as a fin-shaped structure extending from the substrate layer 101 along the first direction), the first additional semiconductor layer 106 and the second additional semiconductor channel layer 107 are formed by free placement. Figure 7In step f), the selective removal of the semiconductor dummy gate layer 301 is not performed, so the additional semiconductor channel layers 106 and 107 respectively include different portions of different semiconductor materials (eg, the silicon-based channel layer 104 and the silicon-germanium-based dummy gate layer 301 ).
[0081] exist Figure 7 In FIG. 1 , dielectric material 504 is filled between and surrounds the layer stacks 102 and 103 and essentially forms a dielectric wall 108 between the layer stacks 102 and 103 .
[0082] Figure 8 A sixth exemplary process provided by the present invention for fabricating a FET structure 100 is shown. In this case, a FET 100 structure having only one layer of stack 102 may be implemented.
[0083] exist Figure 8 In a, the substrate layer 101 is provided with two trenches formed by using a hard mask dielectric material 503.
[0084] Then, dielectric material 503 is also formed on Figure 8 The sidewalls of the etched trench in b are etched. This can be done by dielectric deposition or thermal oxidation.
[0085] exist Figure 8 In c, the surface of the trench bottom is free of dielectric material 503. This is achieved, for example, by selective etching.
[0086] exist Figure 8 In step d, a first layer stack 102 and a second layer stack 103 (including a semiconductor channel layer 104 and a semiconductor dummy gate layer 301 in this case) are grown.
[0087] exist Figure 8 In e, flattening is performed.
[0088] exist Figure 8 In FIG. 5 , one of the layer stacks 102 and 103 can be removed, in this case the second layer stack 103 .
[0089] exist Figure 8 In g, the remaining layer stack 102 is sacrificially etched to remove the dummy gate layer 301 .
[0090] exist Figure 8 In FIG. 3 , the gate layer 104 is formed at the location where the sacrificial etching has occurred to remove the dummy gate layer 301 .
[0091] Figure 9 The method for manufacturing the FET structure 100 provided by the present invention (specifically Figure 1 A general method for a FET structure 100).
[0092] Method 900 includes step 901 of forming a substrate layer 101 and step 902 of forming a first layer stack 102 and a second layer stack 103 side by side on the substrate layer 101. The first layer stack and the second layer stack 103 respectively include one or more semiconductor channel layers 104 and one or more gate layers 105, and the one or more semiconductor channel layers 104 and the one or more gate layers 105 are stacked in an alternating direction along a first direction perpendicular to the surface of the substrate layer 101. In addition, the respective surfaces of the semiconductor channel layers 104 and the gate layers 105 are parallel to the surface of the substrate layer 101.
[0093] The method 900 further includes step 903 of forming at least a first additional semiconductor channel layer 106 adjacent to the first layer stack 102 and a second additional semiconductor channel layer 107 adjacent to the second layer stack 103. Respective surfaces of the first additional semiconductor channel layer 106 and the second additional semiconductor channel layer 107 are parallel to each other and perpendicular to the surface of the substrate layer 101. The method 900 further includes step 904 of forming a dielectric wall 108 on the substrate layer 101 between the first layer stack 102 and the first additional semiconductor channel layer 106 located on one side of the dielectric wall 108 and the second layer stack 103 and the second additional semiconductor channel layer 107 located on the other side of the dielectric wall 108.
[0094] In short, Figure 1 and Figure 2 The FET structure 100 is shown, and Figures 3 to 9 The exemplary process flow and method shown enables an increase in effective transistor width, and accordingly, may enable integrated devices (having the FET structure 100 ) with improved device performance.
[0095] The invention has been described with reference to various embodiments as examples and implementations. However, those skilled in the art will be able to understand and implement other variations when implementing the claimed subject matter, based on a study of the drawings, the present disclosure, and the independent claims. In the claims and the specification, the word "comprising" does not exclude other elements or steps, and "a" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. The enumeration of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.
Claims
1. A field-effect transistor (FET) structure (100) for a nanosheet device, characterized in that: The FET structure (100) comprises: A substrate layer (101); A first layer stack (102) and a second layer stack (103) are arranged side by side on the substrate layer (101), The first layer stack (102) and the second layer stack (103) each include one or more semiconductor channel layers (104) and one or more gate layers (105), and the one or more semiconductor channel layers (104) and the one or more gate layers (105) are stacked in an alternating manner along a first direction perpendicular to the surface of the substrate layer (101), Wherein, the corresponding surfaces of the semiconductor channel layer (104) and the gate layer (105) are parallel to the surface of the substrate layer (101); at least a first additional semiconductor channel layer (106) and a second additional semiconductor channel layer (107), the first additional semiconductor channel layer (106) being arranged next to the first layer stack (102), the second additional semiconductor channel layer (107) being arranged next to the second layer stack (103), Wherein, respective surfaces of the first additional semiconductor channel layer (106) and the second additional semiconductor channel layer (107) are parallel to each other and perpendicular to the surface of the substrate layer (101); A dielectric wall (108) is arranged on the substrate layer (101) between the first layer stack (102) and the first additional semiconductor channel layer (106) on one side and the second layer stack (103) and the second additional semiconductor channel layer (107) on the other side.
2. The FET structure (100) according to claim 1, characterized in that: The first additional semiconductor channel layer (106) adjoins the first layer stack (102); and / or The second additional semiconductor channel layer (107) adjoins the second layer stack (103).
3. The FET structure (100) according to claim 1 or 2, characterized in that: Also includes: A third additional semiconductor channel layer (201) is arranged beside the first layer stack (102) and is located on another side of the first layer stack (102), the other side not being the side where the first additional semiconductor channel layer (106) is located; a fourth additional semiconductor channel layer (202) arranged beside the second layer stack (103) and located on another side of the second layer stack (103), the other side not being the side where the second additional semiconductor channel layer (107) is located; The dielectric wall (108) is arranged between the first layer stack (102), the first additional semiconductor channel layer (106) and the third additional semiconductor channel layer (201) on one side and the second layer stack (103), the second additional semiconductor channel layer (107) and the fourth additional semiconductor channel layer (202) on the other side.
4. The FET structure (100) according to claim 3, characterized in that: The third additional semiconductor channel layer (201) adjoins the first layer stack (102); and / or The fourth additional semiconductor channel layer (202) adjoins the second layer stack (103).
5. The FET structure (100) according to claim 1 or 3, characterized in that: Each additional semiconductor channel layer (106, 107, 201, 202) is spaced apart from the layer stack (102, 103) and is arranged next to the layer stack (102, 103).
6. The FET structure (100) according to any one of claims 1 to 5, characterized in that: The first layer stack (102) and the first additional semiconductor channel layer (106) form an n-FET; and / or The second layer stack (103) and the second additional semiconductor channel layer (107) form a p-FET.
7. The FET structure (100) according to any one of claims 1 to 6, characterized in that: Each additional semiconductor channel layer (106, 201) arranged beside the first layer stack (102) is made of an n-type silicon-based semiconductor material; and / or Each additional semiconductor channel layer (107, 202) arranged beside the second layer stack (103) is made of a p-type silicon-based semiconductor material.
8. The FET structure (100) according to claim 7, characterized in that: Each additional semiconductor channel layer (106, 107, 201, 202) includes one or more portions made of silicon and one or more portions made of silicon germanium.
9. The FET structure (100) according to claim 8, characterized in that: The one or more parts made of silicon of each additional semiconductor channel layer (106, 107, 201, 202) are arranged next to the one or more semiconductor channel layers (104) of the layer stack (102, 103), respectively, and the additional semiconductor channel layer (106, 107, 201, 202) is arranged next to the layer stack (102, 103).
10. The FET structure (100) according to any one of claims 1 to 9, characterized in that: The one or more gate layers (105, 105a) of the first layer stack (102) are made of an n-type work function metal; The one or more gate layers (105, 105b) of the second layer stack (103) are made of a p-type work function metal.
11. The FET structure (100) according to any one of claims 1 to 10, characterized in that: Also includes: a first gate all around (GAA) structure surrounding the first layer stack (102) and each additional semiconductor channel layer (106, 201) arranged next to the first layer stack (102), wherein the one or more gate layers (105, 105a) of the first layer stack (102) are formed integrally with the first GAA structure; and / or A second GAA structure surrounds the second layer stack (103) and each additional semiconductor channel layer (107, 202) arranged next to the second layer stack (103), wherein the one or more gate layers (105, 105b) of the second layer stack (103) are formed integrally with the second GAA structure.
12. The FET structure (100) according to claim 11, characterized in that Also includes: A dielectric material is arranged on the substrate layer (101) and surrounds the first layer stack (102), the second layer stack (103), each additional semiconductor channel layer (106, 107, 201, 202), each GAA structure and the dielectric wall (108).
13. The FET structure (100) according to claim 11 or 12, characterized in that: The first layer stack (102), each additional semiconductor channel layer (106, 201) arranged beside the first layer stack (102), and the first GAA structure form an n-FET structure; The second layer stack (103), each additional semiconductor channel layer (107, 202) arranged beside the second layer stack (107), and the second GAA structure form a p-FET structure.
14. A nanosheet device, characterized in that: Comprising a FET structure (100) according to any one of claims 1 to 13.
15. A method (900) for manufacturing a FET structure (100) for a nanosheet device, characterized in that: The method (900) comprises: forming (901) a substrate layer (101); forming (902) a first layer stack (102) and a second layer stack (103) side by side on the substrate layer (101); The first layer stack (102) and the second layer stack (103) each include one or more semiconductor channel layers (104) and one or more gate layers (105), and the one or more semiconductor channel layers (104) and the one or more gate layers (105) are stacked in an alternating manner along a first direction perpendicular to the surface of the substrate layer (101); Wherein, the corresponding surfaces of the semiconductor channel layer (104) and the gate layer (105) are parallel to the surface of the substrate layer (101); forming (903) at least a first additional semiconductor channel layer (106) next to the first layer stack (102), forming (903) a second additional semiconductor channel layer (107) next to the second layer stack (103), Wherein, respective surfaces of the first additional semiconductor channel layer (106) and the second additional semiconductor channel layer (107) are parallel to each other and perpendicular to the surface of the substrate layer (101); A dielectric wall (108) is formed (904) on the substrate layer (101) between the first layer stack (102) and the first additional semiconductor channel layer (106) on one side and the second layer stack (103) and the second additional semiconductor channel layer (107) on the other side.