Frequency detection pixel

Abstract

The present disclosure relates to a pixel (PIX2) comprising a first node (202), a second node (200) configured to receive a first DC potential (Vdd2), and a plurality of acquisition channels (CH1, CH2), each acquisition channel comprising: a photodiode (PD1, PD2) adapted to detect radiation (SIGL) in a first wavelength range; a capacitive element (Cc1, Cc2) coupling the photodiode to the first node (202); and resistive elements (R1, R2) that couple the first terminals (K1, K2) of the photodiodes (PD1, PD2) to the second node (200).

Description

Technical Field

[0001] The present description relates generally to electronic circuits, such as integrated electronic circuits, and more particularly to a pixel for detecting a frequency of an optical signal received by the pixel. Background Art

[0002] Many known integrated circuits include at least one known pixel for detecting or measuring the frequency of an optical signal received by the pixel. Such circuits or pixels are used, for example, with frequency detection methods such as frequency modulated continuous wave (FMCW).

[0003] However, these known pixels and circuits for detecting the frequency of a received light signal have their disadvantages.

[0004] For example, the photoelectric conversion that takes place in these pixels in order to obtain a photocurrent at the frequency of the received signal is disturbed by photon noise, and the useful part of the obtained photocurrent, or the useful signal, is buried in the noisy part of this photocurrent.

[0005] For example, when these frequency detection pixels are used to detect the frequency of infrared signals and are further arranged in a pixel array for detecting visible light, these frequency detection pixels replace pixels for visible light detection. This has an adverse effect on the quality of the two-dimensional image obtained with the visible light detection pixels. Summary of the invention

[0006] There is a need to overcome some or all of the disadvantages of known circuits and / or pixels for detecting the frequency of an optical signal, for example on the basis of an FMCW type method.

[0007] One embodiment overcomes some or all of the disadvantages of known circuits and / or pixels for detecting the frequency of an optical signal, for example on the basis of an FMCW type method.

[0008] One embodiment provides a pixel comprising a first node, a second node configured to receive a first DC potential, and a plurality of acquisition channels, each acquisition channel comprising:

[0009] a photodiode adapted to detect radiation within a first wavelength range;

[0010] a capacitive element coupling the photodiode to the first node; and

[0011] a resistive element coupling the first terminal of the photodiode to the second node;

[0012] Among them, the pixel also includes:

[0013] a switch coupling the first node to a node configured to receive a second DC potential; and

[0014] The control circuit is configured to control the switch to be in an off state during the acquisition phase to make the first node float.

[0015] According to one embodiment, in each channel the capacitive element has one electrode connected to the first node and another electrode connected to the photodiode, eg to the first terminal of the photodiode.

[0016] According to one embodiment, in each channel, the photodiode is a non-pinned photodiode.

[0017] According to one embodiment, the pixel comprises a sensing circuit having an input coupled, preferably connected, to the first node.

[0018] According to one embodiment, the sensing circuit is configured to provide a binary signal in a first state if the voltage on the first node is above a threshold, and to provide a binary signal in a second state if the voltage on the first node is below a threshold, the threshold being determined, for example, at least in part, by the first potential.

[0019] According to one embodiment, a pixel comprises a sensing circuit having an input coupled, eg connected, to a first terminal of a photodiode of one of the channels of the pixel.

[0020] According to one embodiment, the sensing circuit is configured to provide a binary signal in a first state if the voltage on the first node is above a threshold, and to provide a binary signal in a second state if the voltage on the first node is below a threshold, the threshold being at least partially determined by the first potential.

[0021] According to one embodiment, a pixel comprises a sensing circuit having an input connected to a second node, the sensing circuit being configured to supply a first potential to the second node.

[0022] According to one embodiment, the sensing circuit is further configured to convert the current on its input terminal into a voltage and provide a binary signal in a first state if the voltage is above a threshold and to provide a binary signal in a second state if the voltage is below a threshold, the threshold being determined, for example, at least in part, by the first potential.

[0023] According to one embodiment:

[0024] The pixel comprises a first semiconductor region doped with a first type of conductivity, adapted to detect radiation in a second range of wavelengths, such as visible, and extending from a first face intended to receive radiation in the first wavelength range and in the second wavelength range;

[0025] The photodiodes for each channel include:

[0026] a second semiconductor region doped with the first conductivity type, corresponding to the first terminal of the photodiode and extending from a second face parallel to the first face, and

[0027] - a third semiconductor region doped with the second conductivity type and sandwiched between the first region and the second region;

[0028] The pixel includes a vertical transfer gate extending from the second face to the first region, the transfer gate electrically isolating the photodiodes of the channel from each other and contacting each second region.

[0029] According to one embodiment, the vertical transfer gate includes a conductive core and an insulating sheath, the conductive core corresponding to a first node of the pixel.

[0030] According to one embodiment, the pixel further comprises:

[0031] Additional sensing circuitry and circuitry configured to:

[0032] selectively coupling and decoupling a first electrode of a photodiode of each channel from a second node; and

[0033] A first electrode of the photodiode of each channel is selectively coupled and decoupled from additional sensing circuitry.

[0034] One embodiment provides a sensor comprising a plurality of pixels as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0036] Figure 1 An example pixel for detecting the frequency of a light signal is shown;

[0037] Figure 2 An example embodiment of a pixel for detecting the frequency of a light signal is shown;

[0038] Figure 3 An example alternative implementation of a pixel for detecting the frequency of a light signal is shown;

[0039] Figure 4 Shows Figure 3 An example alternative implementation of a portion of a pixel is shown;

[0040] Figure 5 A three-dimensional partial cross-sectional view showing an example embodiment of a pixel for detecting a frequency of an optical signal and for acquiring another optical signal;

[0041] Figure 6Shows Figure 5 a partial top view of the pixel shown; and

[0042] Figure 7 schematically and at least partially in circuit form Figure 5 and Figure 6 Pixels shown. DETAILED DESCRIPTION

[0043] Similar features have been designated by similar reference numerals in the various drawings. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0044] For the sake of clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, various known circuits, systems, and applications in which one or more frequency detection pixels may be provided have not been described in detail, because the embodiments and variations described herein are compatible with these known circuits, systems, and applications.

[0045] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate elements except conductors, and when referring to two elements being coupled together, this means the two elements may be connected or they may be coupled via one or more other elements.

[0046] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers, such as terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as terms "above", "below", "higher", "lower", etc., or orientation qualifiers, such as "horizontal", "vertical", etc., reference is made to the orientation shown in the accompanying drawings.

[0047] Unless otherwise indicated, the expressions "about," "approximately," "substantially," and "approximately" mean within 10%, and preferably within 5%.

[0048] Figure 1 An exemplary pixel PIX1 for detecting the frequency of the light signal SIGL is shown.

[0049] The pixel PIX1 comprises a photodiode PD. The photodiode PD is a non-pinned photodiode, or, in other words, is not a pinned photodiode.

[0050] The photodiode PD has its cathode K coupled to a node 100, which is configured to receive a bias potential Vdd. More specifically, the pixel PIX1 includes a resistive element R coupling the cathode K of the photodiode PD to the node 100. The anode of the photodiode PD is coupled (e.g., connected) to a node 102 configured to receive a reference potential Vss. The potential Vdd is, for example, positive. The potential Vdd is greater than the potential Vss.

[0051] The pixel PIX1 further comprises a sensing circuit LECT1. The circuit LECT1 has an input coupled, preferably connected, to the cathode K of the photodiode PD.

[0052] In operation, the photodiode PD of the pixel PIX1 receives a light signal SIGL and converts it into a photocurrent Iph. This current Iph is converted by the resistive element R into a voltage Vph available at the cathode K of the photodiode PD. The circuit LECT1 receives the voltage Vph and provides a binary output signal OUT1. The circuit LECT1 is configured such that when the voltage Vph is above a threshold, for example equal to a DC voltage present at the cathode K of the photodiode PD, the signal OUT1 is in a first binary state, and when the voltage Vph is below the threshold, the signal OUT1 is in a second binary state.

[0053] Since the photocurrent evolves with the same frequency as the signal SIGL, the voltage Vph comprises an AC component at the frequency of the signal, and the OUT1 signal is then a periodic binary signal at the frequency of the signal SIGL.

[0054] However, the above operation does not take into account the photon noise in the photodiode PD. This photon noise causes a noise component in the photocurrent Iph, which in turn causes a noise component in the voltage Vph. This noise in the voltage Vph causes unnecessary switching of the signal OUT1, which then no longer oscillates at the frequency that the pixel PIX1 is intended to detect or measure.

[0055] A pixel is proposed, which comprises a plurality of acquisition channels, each of which comprises a standard (or non-pinned) photodiode. The photodiodes of the pixel are connected to each other by a capacitive coupling element. Each photodiode of the pixel supplies a signal having a useful component at the frequency of the light signal received by the pixel. Since the photon noise in each photodiode of the pixel is different, the coupling capacitance allows averaging of the photon noise, with the result that the noise component in the signal supplied by the photodiode of the pixel is reduced relative to the useful component of the signal.

[0056] Figure 2 An example embodiment of a pixel PIX2 for detecting the frequency of a light signal SIGL is shown.

[0057] The pixel PIX2 comprises a node 200 configured to receive a bias potential Vdd2. Figure 2 In the example shown, the potential Vdd2 is received by the node 200. As in the pixel PIX1, the potential Vdd2 is a DC potential.

[0058] The pixel PIX2 further comprises a node 202 .

[0059] The pixel PIX2 includes N acquisition channels CHi, where N is an integer greater than or equal to 2, and i is an integer index ranging from 1 to N. Figure 2 In the example shown, the pixel PIX2 comprises N=2 acquisition channels CH1 and CH2.

[0060] Each channel CHi includes a photodiode PDi. Figure 2 In the example shown, channel CH1 includes photodiode PD1 and channel CH2 includes photodiode PD2 .

[0061] Each photodiode PDi is a non-pinned photodiode.

[0062] Each channel CHi also includes a resistive element, such as a resistor, Ri. Figure 2 In the example shown, channel CH1 includes element R1 and channel CH2 includes element R2 .

[0063] In each channel CHi, the cathode Ki ( Figure 2 K1 and K2 in the channel are coupled to the node 200 through the resistance element Ri of the channel CHi. Figure 2 In the example shown, in each channel CHi, the element Ri has one terminal connected to the cathode Ki of the photodiode PDi and another terminal connected to the node 200 .

[0064] In each channel CHi, the anode of the photodiode PDi is coupled (eg connected) to a node 201 configured to receive a reference potential Vss. The potential Vss is a DC potential. The potential Vdd2 is, for example, positive. The potential Vdd2 is greater than the potential Vss.

[0065] Each channel CHi also includes a capacitive element, such as a capacitor Cci. Figure 2 In the example shown, channel CH1 includes element Cc1 and channel CH2 includes element Cc2 .

[0066] In each channel CHi, a capacitive element Cci couples the cathode Ki of the photodiode PDi to the node 202 of the pixel PIX2. For example, in each channel CHi, the element Cci has one terminal (or electrode) connected to the cathode Ki of the photodiode PDi in the channel CHi, and another terminal (or electrode) connected to the node 202. Preferably, the elements Cci all have substantially equal capacitance values, such as equal capacitance values.

[0067] In the pixel PIX2, when the signal SIGL is received by the photodiode PDi of the pixel PIX2, each photodiode PDi supplies a signal converted into a voltage Vphi ( Figure 2 The photocurrent Iphi( Figure 2 In each channel PDi, the photocurrent Iphi and the corresponding voltage Vphi each include useful components that are similar or identical in all channels CHi, and noise components that are different in each channel CHi. This is because the photodiodes PDi are subjected to the same incident signal SIGL, but the photon noise varies from one photodiode to another.

[0068] Furthermore, when the node 202 is kept floating, the capacitive element Cci coupling the photodiodes PDi together generates a common inertia on all voltages Vphi by capacitive coupling. As a result, similar components (i.e., useful signals) in all channels CHi are retained, while the noise components are reduced. In other words, the capacitive element Cci implements an averaging function that tends to reduce the noise components of the channels CHi and reduces their voltages Vphi to their average value, which corresponds to the useful signal at the frequency of the signal SIGL.

[0069] According to one embodiment, the pixel PIX2 comprises a circuit for resetting the node 202 to a reset potential Vrst. The reset circuit is configured to set the node 202 to the potential Vrst before the acquisition phase, or the frequency detection phase, and then to float the node 202 during the acquisition phase. For example, the potential Vrst is selected so that when the node 202 floats, the voltage V on the node 202 can follow the variation of the useful component of the voltage Vphi without clipping. For example, in Figure 2 In the embodiment, potential Vrst may be selected to be substantially equal to (eg, equal to) an average of potentials Vdd2 and Vss.

[0070] The reset circuit comprises a switch IT1, for example a MOS (Metal Oxide Semiconductor) transistor. The switch IT1 couples the node 202 to a node 204 configured to receive a potential Vrst at least during a reset phase before the frequency detection phase. By way of example, the switch IT1 comprises a conduction terminal coupled, preferably connected to the node 202, and another conduction terminal coupled, preferably connected to the node 204. The switch IT1 is controlled by a signal RST. The signal RST is provided, for example, by a control circuit of the pixel PIX2, which is, for example, part of the pixel PIX2 or part of a more complex circuit or system including the pixel PIX2.

[0071] The pixel PIX2 comprises a sensing circuit LECT2. The circuit LECT2 is configured to provide a binary signal OUT2 at the frequency of the signal SIGL as a function of a signal (voltage or current) present at a node of the pixel PIX2. More specifically, the circuit LECT2 has an input coupled or connected to a node of the pixel PIX2 at which a signal at the frequency of the signal SIGL is available and an output configured to deliver the signal OUT2.

[0072] For example, when the input signal to the circuit LECT2 is above a threshold, the signal OUT2 is a binary signal in a first binary state, and when the input signal to the circuit LECT2 is below the threshold, the signal OUT2 is a binary signal in a second binary state. By way of example, the value of the threshold is determined by the DC component of the signal at the input of the circuit LECT2, so that the signal OUT2 is at the frequency of the signal SIGL.

[0073] exist Figure 2 In the embodiment shown, the circuit LECT2 has its input coupled, preferably connected, to the node 202. By way of example, in Figure 2 In the example shown, the circuit LECT2 comprises a comparator COMP having an input connected to an input of the circuit LECT2 and an output connected to an output of the circuit LECT2 , the output of the comparator COMP delivering a signal OUT2 .

[0074] Although in Figure 2 In the example shown, the number N of channels CHi is equal to 2, but a person skilled in the art will be able to provide a pixel PIX2 in which the number N of channels CHi is strictly greater than two.

[0075] Figure 3 An example alternative implementation of a pixel PIX3 for detecting the frequency of a light signal is shown.

[0076] Pixel PIX3 has many common features with pixel PIX2, and only the differences between these two pixels are highlighted here.

[0077] exist Figure 3 In the example shown, the pixel PIX3 comprises N=2 channels CHi.

[0078] The pixel PIX3 comprises a sensing circuit LECT3 in place of the circuit LECT2 of the pixel PIX2. Like the circuit LECT2, the circuit LECT3 is configured to deliver a binary signal OUT3 at the frequency of the signal SIGL as a function of a signal (voltage or current) present at a node of the pixel PIX3. More specifically, the circuit LECT3 has an input coupled or connected to a node of the pixel PIX3 at which a signal at the frequency of the signal SIGL is available, and an output configured to deliver the signal OUT3.

[0079] For example, when the signal at the input of the circuit LECT3 is above a threshold, the signal OUT3 is a binary signal in a first binary state, and when the signal at the input of the circuit LECT3 is below the threshold, the signal OUT3 is a binary signal in a second binary state. By way of example, the value of the threshold is determined by the DC component of the signal at the input of the circuit LECT3, so that the signal OUT3 is at the frequency of the signal SIGL.

[0080] and Figure 2 In contrast to the embodiment shown, the circuit LECT2 of the pixel PIX2 has its input coupled, preferably connected to the node 202, Figure 3 In the alternative embodiment shown, the circuit LECT3 of the pixel PIX3 has its input coupled, preferably connected, to the node 200 .

[0081] Therefore, in Figure 3 In the alternative embodiment shown, the circuit LECT3 is further configured, compared to the circuit LECT2 , to supply a DC bias potential to the node 200 , or, in other words, to impose a DC potential of the node 200 .

[0082] In addition, Figure 3 In the alternative embodiment shown, the input of the circuit LECT3 receives the sum of the photocurrents Iphi supplied to the node 200 by the photodiodes PDi of the channels CHi of the pixels PIX3. The circuit LECT3 then compares the total current I it receives with a threshold value to determine the state of the signal OUT3. More specifically, the signal OUT3 is in a first binary state if the current I is above the threshold value, and in a second binary state if the current I is below the threshold value. By way of example, the current threshold value is determined by the DC component of the current I, so that the signal OUT3 is at the frequency of the signal SIGL.

[0083] More specifically, in Figure 3 In the example shown, the circuit LECT3 performs a conversion of the current I received at its input into a voltage VI which is then compared with a voltage threshold to determine the state of the signal OUT3. By way of example, the value of this voltage threshold is determined by the DC component of the voltage VI so that the signal OUT3 is at the frequency of the signal SIGL.

[0084] According to one embodiment, Figure 3 As shown, the circuit LECT3 includes a resistance element, such as a resistor Res, and a MOS transistor T connected in series between an input terminal of the circuit LECT3 and a node 300 configured to receive a bias potential Vdd3. The transistor T and the resistance element Res are connected to each other at a node 302. The transistor T is connected between the input terminal of the circuit 33 and the node 302, and the resistance element Res is connected between the node 302 and the node 300. For example, the transistor T has one conduction terminal connected to the node 302 and another conduction terminal connected to the input terminal of the circuit 33. For example, the resistance element Res has one terminal connected to the node 302 and another terminal connected to the node 300.

[0085] The transistor T is controlled by a DC potential Vdc applied to its gate so as to impose a DC bias potential on the node 200, or in other words, so that the node 200 receives this DC bias potential. In other words, the transistor T is cascoded and receives the cascode voltage Vdc on its gate.

[0086] The resistive element Res is configured to convert a current I received by the input of the circuit LECT3 into a voltage VI which is available at a node 302 in this example.

[0087] In this embodiment, the circuit LECT3 further comprises a circuit COMP, for example a comparator, which is configured to compare the voltage V1 with a threshold value and to provide a signal OUT3 based on the result of this comparison. For example, the circuit COMP has an input coupled, preferably connected to the node 302, and an output coupled, preferably connected to an output of the circuit LECT3 at which the signal OUT3 is available.

[0088] Figure 4 Shows Figure 3 An example of an alternative implementation of a portion of the pixel PIX3 is shown, and more specifically an example of an alternative implementation of the circuit LECT3.

[0089] In this alternative, the circuit LECT3 comprises an operational amplifier AOP. The amplifier AOP has one input 404 coupled, preferably connected, to an input of the circuit LECT3, and another input 406 coupled, preferably connected, to a node 400 configured to receive a bias potential Vdd4. The output of the amplifier AOP is connected to a node 402 of the circuit LECT3. A resistor Rlect is connected between the input 404 of the amplifier AOP and the node 402 (the output of the amplifier AOP). The amplifier AOP is installed as an adder with a resistor Ri of the channel CHi of the pixel PIX3 (see Figure 3 The amplifier AOP also enables imposing a bias potential on a node 200 to which the input of the circuit LECT3 is coupled, preferably connected (see Figure 3 ). The amplifier AOP allows the sum of the currents Iphi in the channels CHi of the pixel PIX3 , ie the currents I received by the inputs of the circuit LECT3 , to be converted into a voltage VI available at the node 402 .

[0090] In this alternative embodiment, as in Figure 3 , the circuit LECT3 further comprises a circuit COMP, for example a comparator, which is configured to compare the voltage V1 with a threshold value and to provide a signal OUT3 based on the result of this comparison. For example, the circuit COMP has an input terminal coupled, preferably connected to the node 402, and an output terminal coupled, preferably connected to an output terminal of the circuit LECT3 at which the signal OUT3 is available.

[0091] Embodiments and alternatives of a pixel having a plurality of channels CHi in each of which a photodiode PDi and a capacitive element Cci coupling an electrode of the photodiode to a node 202 of the pixel are provided have been described. From the description of these embodiments and alternatives, a person skilled in the art will be able to implement such a pixel. In particular, a person skilled in the art will be able to provide other embodiments of the circuits LECT2 and LECT3 than those given by way of example.

[0092] An embodiment of the pixel PIX2 which a person skilled in the art will know how to adapt to the pixel PIX3 will now be described. This embodiment is particularly suitable and advantageous when the pixel PIX2 is intended to be implemented in a pixel array of a sensor configured to detect light signal frequencies (e.g. infrared) and to acquire a two-dimensional image of a scene. Figure 5 , Figure 6 and Figure 7 An example of such an implementation is described.

[0093] Figure 5An example three-dimensional partial cross-sectional view of a pixel PIX2 for detecting a frequency of an optical signal (eg, infrared) and for acquiring another optical signal (eg, visible light) is shown. Figure 5 Taken from Figure 6 The cross section AA is shown, which shows a partial top view of the pixel PIX2.

[0094] In these Figure 5 and Figure 6 In the drawings, the circuit LECT2, the resistor Ri and the switch IT1 are not shown to avoid overloading the drawings. In these drawings, the number N of channels CHi of the pixel PIX2 is equal to 4, but a person skilled in the art will know how to use Figure 5 and Figure 6 The description is adapted to pixels including any number N of channels greater than or equal to 2.

[0095] The pixel PIX2 includes a portion of the silicon substrate, the thickness (or height) of which is 500 ( Figure 5 The bottom surface in) and surface 502 ( Figure 5 ), surface 502 is Figure 6 Plane 500 is the face of pixel PIX2 that is intended to receive light, i.e., light signals of a frequency that pixel PIX2 will detect (e.g., infrared), and light signals that pixel PIX2 will integrate (e.g., visible), e.g., to obtain corresponding image pixels of a two-dimensional image of the scene.

[0096] The silicon substrate portion of the pixel PIX2 is laterally delimited by an isolation structure 506 extending through the entire thickness of the substrate, ie the isolation structure 506 extends from the surface 502 to the surface 500. Preferably, the structure 506 completely surrounds the semiconductor substrate portion of the pixel PIX2.

[0097] Structure 506 is, for example, a capacitive deep trench insulation (CDTI). In this case, structure 506 includes an insulating sheath ( Figure 5 and Figure 6 A conductive material core (not shown) covered Figure 5 and Figure 6 ), the insulating sheath insulates the conductive core from the silicon of the substrate portion of the pixel PIX2.

[0098] As an alternative example, structure 506 is a deep trench insulation (DTI). Preferably, in this alternative example, the layer doped with the first type of conductivity ( Figure 5 and Figure 6 Not shown), (in Figure 5 and Figure 6In the example shown in FIG. 5 , type P) completely covers the side wings of structure 506 .

[0099] The pixel PIX2 includes a semiconductor region 508 doped with a second conductivity type. Figure 5 and Figure 6 In the example shown, it is of type N. Region 508 is, for example, part of a layer extending from face 500 in thickness. In other words, region 508 extends from face 500. Region 508 is laterally bounded by structure 506, with which region 508 is in contact. Region 508 has, for example, a substantially constant thickness, which is measured in a direction orthogonal to faces 500 and 502 of pixel PIX2. Region 508 is configured to implement a pinned photodiode.

[0100] In this embodiment, each channel CHi ( Figure 5 and Figure 6 The photodiode PDi (not cited in Figure 5 and Figure 6 PD1, PD2, PD3 and PD4 in FIG. 5 include a semiconductor region 510 ( Figure 5 ).

[0101] In each photodiode PDi, region 510 is preferably more heavily doped than region 508, or in other words, the doping level of each region 510 is greater than the doping level of region 508. In this example, region 510 is therefore more heavily doped N-type (N+) than region 508.

[0102] For each photodiode PDi, region 510 corresponds in this example to the cathode Ki ( Figure 5 and Figure 6 K1, K2, K3 and K4 in it).

[0103] Each region 510 extends from the face 502 of the pixel PIX2. Preferably, the regions 510 all have the same thickness. For example, each region 510 corresponds to a portion of a doped layer of the second conductivity type having a face merging with the face 502.

[0104] In this embodiment, the photodiode PDi of each channel CHi further comprises a doped semiconductor region 512 of a first conductivity type, in this example a P type. Figure 5 In FIG. 5 , only the region 512 of the photodiodes PD3 and PD4 is visible.

[0105] For each photodiode PDi, region 512 corresponds in this example to the anode of the photodiode PDi. Figure 5 and Figure 6Not shown in FIG. 5 , the pixel PIX2 includes means configured to apply a potential Vss to the region 512 .

[0106] By way of example, when structure 506 is of DTI type bordered by a doping layer of the same type as region 512, pixel PIX2 comprises a doping region of the same type as region 512, which is flush with surface 502 and in contact with this doping layer, so that by applying a potential Vss to this region, the potential Vss is also applied to region 512.

[0107] As an alternative example, when structure 506 is of CDTI type, pixel PIX2 includes a device configured to apply a bias potential to the conductive core of structure 506 so that a doped layer of the same conductive type as region 512 is formed along the wall of structure 506, and pixel PIX2 also includes a doped region of the same type as region 512, which is flush with surface 502 and in contact with the doped layer, so that by applying a potential Vss to this region, the potential Vss is also applied to region 512.

[0108] In each photodiode PDi, region 512 is sandwiched between region 508 and region 510 of the photodiode PDi. In other words, in each photodiode PDi, region 512 extends in thickness from region 508 of the photodiode PDi to region 510. In yet other words, in each photodiode PDi, region 512 has one face in contact with one face of region 508, and an opposite face in contact with region 510 of the photodiode PDi.

[0109] Preferably, all regions 512 have the same thickness. For example, each region 512 corresponds to a portion of a doped layer of the first conductivity type that rests on and contacts region 508.

[0110] Pixel PIX2 also includes a vertical transfer gate VEGA. Gate VEGA extends vertically from face 502 of pixel PIX2 to region 508 and preferably penetrates into region 508 only over a portion of the thickness of region 508. Gate VEGA electrically isolates photodiodes PDi from each other. Gate VEGA contacts each of regions 512. Gate VEGA includes a dielectric sheath ( Figure 5 and Figure 6 The conductive core (not shown) is covered Figure 5 and Figure 6 ), the insulating sheath electrically insulates the conductive core from the silicon bordering the gate electrode VEGA.

[0111] The conductive core of the gate VEGA corresponds in this embodiment to the node 202 of the pixel PIX2. Thus, advantageously, in this embodiment, the capacitive element Cci ( Figure 5 and Figure 6The Cc1, Cc2, Cc3 and Cc4 in FIG. 1 are implemented by the gate VEGA, and more specifically, by the conductive core 202 of the gate VEGA (which corresponds to the first electrode of the capacitive element Cci), the insulating sheath of the gate VEGA (which corresponds to the insulating layer of the capacitive element), and by the region 510 of the corresponding photodiode PDi (which corresponds to the second electrode of the capacitive element Cci). The capacitive element Cci is Figure 5 and Figure 6 It is schematically shown in FIG.

[0112] Therefore, in Figure 5 and Figure 6 In the pixel PIX2 shown, when:

[0113] - light, for example visible light, is received by the face 500 of the pixel PIX2,

[0114] the potential of the conductive core of the gate VEGA has been initialized to a value such that the gate VEGA is blocked, i.e. the photogenerated charges in the pinned photodiode 508 cannot be transferred to the region 510,

[0115] - The conductive core of the gate VEGA remains floating, and

[0116] - surface 500 also receives an optical signal SIGL, such as an infrared signal,

[0117] Therefore, the pixel PIX2 integrates the light (eg, visible light) received in the region 508, and at the same time, the light signal SIGL (eg, infrared) is converted into a corresponding photocurrent Iphi (in Figure 5 and Figure 6 2. Pixel PIX2 implements a photon noise reduction function in the photodiodes PDi due to the presence of a capacitive element Cci coupling each photodiode PDi to the floating node 202. The sensing circuit LECT2 of the pixel PIX2 (in Figure 5 and Figure 6 (not shown) the signal can then be read out at node 202 at the frequency of signal SIGL.

[0118] After a phase at the frequency of the detection signal SIGL, during which light (e.g., visible light) has been converted into photogenerated charges in the pinned photodiode 508, the accumulated charges in the region 508 can be read by applying a potential to the gate VEGA, turning it on. The accumulated charges are then transferred to the region 510, where they can be read by an additional dedicated sensing circuit.

[0119] During this phase of reading the photogenerated charge, although Figure 5 and Figure 6Not shown in FIG. 1 , region 510 is connected to node 200 ( Figure 2 ) are electrically isolated, whereas they are coupled to the node 200 by this same circuit during the phase of detecting the frequency of the optical signal SIGL.

[0120] Furthermore, during the phase of reading the charge accumulated in the region 508, the circuit configured to selectively couple each of the regions 510 to and decouple each of the regions 510 from the node 200 is also configured to couple each of the regions 510 to the sense node of the pixel PIX2, whereas the circuit is configured not to couple these regions 510 to the sense node during the frequency detection phase. An additional sense circuit configured to read the charge transferred to the sense node is connected to the sense node.

[0121] In other words, despite Figure 5 and Figure 6 Not shown, pixel PIX2 includes a circuit configured to selectively couple and decouple a region 510 of the photodiode PDi to and from the node 200, such as a corresponding resistor Ri connected to the node 200, and to selectively couple and decouple the region 510 to and from the detection node.

[0122] Now it will be relative to Figure 7 An example embodiment of pixel PIX2 is described in detail in which sensing circuits and circuits are configured to selectively couple and decouple region 510 of photodiode PDi to and from node 200 and to selectively couple and decouple region 510 to and from a detection node.

[0123] Figure 7 schematically and at least partially in circuit form Figure 5 and Figure 6 Pixel PIX2 is shown.

[0124] exist Figure 7 In FIG. 2 , the conductive core corresponding to the gate VEGA of the node 202 is coupled to the node 204 through the switch IT1 .

[0125] The pixel PIX2 comprises a circuit LECT2, the input of which is connected to the node 202 and the output of which provides the signal OUT2.

[0126] The pixel PIX2 comprises a detection node SN, and an additional sensing circuit LECTSUP connected to the node SN. By way of example, the circuit LECTSUP comprises an initialization switch INIT coupling the node SN to the node SN of the reset potential Vinit, a MOS transistor SF having its gate connected to the node SN and its drain connected to the bias potential Vsf, and a read switch RD connecting the source of the transistor SF to the read conductor Vx. The operation of such a sensing circuit (e.g., referred to as circuit 3T) is well known to those skilled in the art. In addition, those skilled in the art will be able to provide other examples of implementation of the circuit LECTSUP.

[0127] The pixel PIX2 further includes a circuit SEL configured to selectively couple the regions 510 of each of the photodiodes PDi to and decouple them from the node 200, and to selectively couple the regions 510 to and decouple them from the node SN. More specifically, during the phase of transferring photogenerated charges from the region 508 to the region 510 and during the phase of reading the transferred charges, the circuit SEL is configured to electrically couple each region 510 to the node SN through the circuit SEL, and the circuit SEL electrically decouples each region 510 from the node 200, and during the phase of detecting the frequency of the signal SIGL, the circuit SEL is configured to electrically couple each region 510 to the node 200 and to electrically decouple the regions 510 from the node SN.

[0128] By way of example, for each channel CHi ( Figure 7 , CH1, CH2, CH3 and CH4 in the circuit SEL, the circuit SEL includes a first switch coupling the region 510 of the photodiode PDi of this channel to the node 200, the first switch is, for example, connected in series with the resistor Ri of this channel CHi between the photodiode PDi of this channel CHi and the node 200, for example, connected between this photodiode PDi and this resistor Ri. In addition, by way of example, for each channel CHi, the circuit SEL includes a second switch coupling the region 510 of this channel CHi to the node SN. The first switch and the second switch of the circuit SEL are, for example, controlled so that the first switch is turned off when the second switch is turned on, and so that the second switch is turned off when the first switch is turned on.

[0129] A person skilled in the art will be able to provide other implementations of the circuit SEL, for example using a multiplexer.

[0130] During the phase of resetting the potential of node 202, before the phase of detecting the frequency of signal SIGL, switch IT1 is opened by signal RST and node 202 is then set to potential Vrst of node 204. Switch IT1 is then turned off, leaving node 202 floating. During this reset phase, circuit SEL preferably couples region 510 to node 200 and decouples region 510 from node SN.

[0131] In conjunction with the pinned photodiode 508 ( Figure 5 ), the circuit SEL couples the region 510 to the node 200 and decouples the region 510 from the node SN. The circuit LECT2 then provides a signal OUT2 at the frequency of the signal SIGL.

[0132] In removing the photogenerated charges from region 508 ( Figure 5 ) is transferred to region 510 in a subsequent stage, circuit SEL couples region 510 to node SN and decouples region 510 from node 200. Node SN is then initialized to initialization potential Vinit by circuit LECTSUP. For example, node SN is initialized to potential Vinit by opening switch INIT, and then switch INIT is turned off so that potential Vinit is stored on node SN. Next, charge transfer to node SN is implemented. For this purpose, switch IT1 is opened so that potential Vrst is applied to node 202 (conductive core of gate VEGA). Then the value of potential Vrst is selected so that gate VEGA is opened, and this value of potential Vrst is different from the value of potential Vrst during the stage of resetting node 202 before the frequency detection stage. More particularly, during the transfer stage, the value of potential Vrst is selected so that the gate is in an open state, and during the stage of resetting node 202, the value of potential Vrst is selected so that gate VEGA remains blocked throughout the entire frequency detection stage. When the gate VEGA is set in the open state, the charge is transferred from the region 508 to the node SN. The end of the charge transfer is caused by setting the gate VEGA in the off state. For example, switching the gate VEGA to the blocking state to terminate the charge transfer is implemented by switching the potential Vrst to a value that switches the gate VEGA to the blocking state. Then, at the end of the transfer phase, the switch IT1 is switched to the blocking state.

[0133] Thus, the transfer phase successively includes resetting the node SN, switching the gate VEGA to the open state, and then switching the gate VEGA to the off state. Preferably, throughout the transfer phase, the circuit SEL maintains the region 510 coupled to the node SN and the region 510 decoupled from the node 200 .

[0134] After the transfer phase, circuit SEL maintains region 510 coupled to node SN and decouples region 510 from node 200 during a phase of reading these transferred charges. Circuit LECTSUP then reads the photogenerated charges that have been transferred in region 510. Figure 7 For the example circuit shown, LECTSUP, this read phase includes switching the switch RD to the open state.

[0135] By way of example, during the transfer phase, between the initialization of the region 510 (i.e., the node SN) at the potential Vinit and the transfer of the charge to the node SN, a phase for reading the initialization potential of the region 510 (i.e., the node SN) may be provided, for example, in order to implement Correlated Double Sampling (CDS). For example, the reading of the node SN, and more particularly the reading of the initialization potential of the node SN, is implemented by switching the switch RD to the open state.

[0136] By way of example, between the end of the phase of reading the transferred charges and the beginning of a simultaneous phase of integrating the light and detecting the frequency of the signal SIGL, the region 508 is emptied of the photogenerated charges located therein. To this end, the gate VEGA is switched to the open state and the potential Vinit is applied to the region 510, while the circuit SEL couples the region 510 to the node SN and decouples the region 510 from the node 200. Figure 7 In the example circuit LECTSUP shown, this involves setting potential Vrst to a value suitable for causing gate VEGA to open when switch INIT is opened, and simultaneously switching switch INIT to an open state so that as gate VEGA is opened, potential Vinit is applied to region 510 and therefore to region 508.

[0137] Although already relative to Figure 7 An example is described in which circuit LECT2 is connected to node 202, in another example not shown, this circuit LECT2 is coupled to node 202 via a switch so that, during the phase of transferring charge from region 508 to region 510 and the phase of reading the transferred charge, this switch is turned to the off state to electrically decouple circuit LECT2 from node 202.

[0138] Relative to Figures 5 to 7 An advantage of the described pixel is that, in a pixel array comprising a plurality of such pixels, when the pixel implements a frequency detection function, the resolution of a two-dimensional image captured by the pixel array is not affected, since this pixel simultaneously implements an integration of the visible light it receives, while performing frequency detection.

[0139] Relative to Figures 5 to 7Another advantage of the described pixel is that the capacitive element is integrated directly into the pixel, taking advantage of the presence of a transfer gate VEGA which is used to transfer the photogenerated charges during the integration of the light corresponding to the acquisition of a two-dimensional image.

[0140] although Figures 5 to 7 A pixel PIX2 is described in which the sensing circuit LECT2 of the pixel is connected to the node 202, but a person skilled in the art will be able to adapt this description to the case of a pixel PIX2 in which the sensing circuit LECT2 of the pixel is, for example, selectively coupled or connected to one of the regions 510 of the photodiode PDi, and to the case of a pixel PIX3 in which the sensing circuit LECT3 of the pixel is connected to the node 200.

[0141] Compared with the circuit LECT2, the circuit LECT3 has the advantage that in these circuits the Figure 5 , Figure 6 and Figure 7 When the pixel is implemented, its bias potential Vdd3 ( Figure 3 ) or Vdd4( Figure 4 ) can be higher than the potential Vdd2. In fact, when the circuit LECT2 is as relative to Figure 5 , Figure 6 and Figure 7 When connected to the node 202 of the pixel, i.e. to the conductive core of the gate VEGA, the threshold of the circuit LECT2, for example its comparator COMP, is determined so that the signal OUT3 is at the frequency of the signal SIGL and, moreover, the gate VEGA is in a blocking state, in which case this threshold can be zero, or even negative. This is not the case for the circuit LECT3 connected to the node 200.

[0142] Although not shown in any of the drawings, one embodiment provides a sensor including a plurality of pixels PIX2 or PIX3. For example, the sensor includes a pixel array. For example, some of the pixels in the array correspond to pixels PIX2 or PIX3, while other pixels in the array correspond to pixels similar to pixels PIX2 and PIX3. These other pixels preferably have the same configuration as the gate VEGA of the pixel PIX2 or PIX3, so as to have the same pinned photodiode and node SN capacitance characteristics as the pixel PIX2 or PIX3 (although this is not necessary). In addition, these other pixels may not have circuits LECT2 and LECT3. These other pixels preferably include a circuit SEL so as to have the same capacitance characteristics on the node SN (although this is not necessary). Preferably, all pixels of the array have the same size in a top view, which facilitates the implementation of the pixel array, and in addition, reduces the dispersion between pixels. Such sensors can then measure the frequency of the signal SIGL, preferably in the infrared range, and in addition, obtain a two-dimensional image, such as a color image, by integrating light (e.g., visible light) into the pinned photodiodes 508 of all pixels of the array. Preferably, when the sensor is configured to acquire a two-dimensional, color image of a scene, pixels PIX2 and PIX3 are configured to integrate blue light, which penetrates less deeply into the silicon than red and green light.

[0143] In the above described embodiments and alternatives, during the phase of detecting the frequency of the signal SIGL, the node 202 remains floating after being reset to the potential Vrst, or in other words, no potential is applied to the node 202 during the frequency detection phase.

[0144] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and those skilled in the art will readily conceive of other variations.

[0145] In particular, the above has been relative to Figures 2 to 7 Example embodiments and alternatives are described in which, in each channel CHi, the capacitive element Cci of this channel CHi couples the cathode Ki of the photodiode PDi of this channel to the node 202, for example corresponding to an example in which the DC potential at the node 200 is greater than the potential Vss at the node 201. In other examples, in which the DC potential on the node 200 is lower than the potential Vss, the photodiode PDi of each channel is connected in a manner opposite to that described with respect to the figures, its anode then being on one side of the resistor Ri and its cathode being on one side of the node 201, and the element Cci then coupling the anode of the photodiode PDi to the node 202. Referring back to Figures 5 to 7 , which means inverting all conductivity types.

[0146] More generally, those skilled in the art will be able to adapt the described example in which element Cci couples the cathode of photodiode PDi to node 202 to an example in which element Cci couples the anode of photodiode PDi to node 202 .

[0147] Finally, the actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided herein. In particular, with respect to the values ​​of the various DC potentials described above, those skilled in the art will be able to select these values ​​from the descriptions made above to obtain the described operations.

Claims

1. A pixel comprising a first node (202), a second node (200) configured to receive a first DC potential, and a plurality of acquisition channels (CH1, CH2), each acquisition channel comprising: a photodiode (PD1, PD2) adapted to detect radiation in a first wavelength range (SIGL); a capacitive element (Cc1, Cc2) coupling the photodiode to the first node (202); as well as a resistive element (R1, R2) coupling a first terminal (K1, K2) of the photodiode (PD1, PD2) to the second node (200), Wherein, the pixel further includes: a switch (IT1) coupling the first node (202) to a node (204) configured to receive a second DC potential (Vrst); and A control circuit is configured to control the switch (IT1) to be in an off state during an acquisition phase to allow the first node (202) to float.

2. The pixel according to claim 1, wherein: In each channel (CH1, CH2), the capacitive element (Cc1, Cc2) has one electrode connected to the first node and another electrode connected to the photodiode (PD1, PD2), for example to the first terminal (K1, K2) of the photodiode (PD1, PD2).

3. The pixel according to claim 1, wherein: In each channel (CH1, CH2), the photodiode (PD1, PD2) is a non-pinned photodiode.

4. The pixel according to claim 1, wherein: The pixel (PIX2) comprises a sensing circuit (LECT2) having an input coupled, preferably connected, to the first node (202).

5. The pixel according to claim 4, wherein: The sensing circuit (LECT2) is configured to provide a binary signal (OUT2) in a first state if the voltage (V) on the first node (202) is above a threshold value, and to provide the binary signal (OUT2) in a second state if the voltage (V) on the first node (202) is below the threshold value, the threshold value being determined, for example, at least in part, by the first potential.

6. The pixel according to claim 1, wherein: The pixel (PIX2) comprises a sensing circuit (LECT2) having an input coupled, for example connected, to a first terminal (K1, K2) of a photodiode (PD1, PD2) of one of the channels (CH1, CH2) of the pixel.

7. The pixel according to claim 6, wherein: The sensing circuit (LECT2) is configured to provide a binary signal (OUT2) in a first state if the voltage (V) on the first node (202) is above a threshold value, and to provide the binary signal (OUT2) in a second state if the voltage (V) on the first node (202) is below the threshold value, the threshold value being determined, for example, at least in part, by the first potential.

8. The pixel according to claim 1, wherein: The pixel (PIX3) comprises a sensing circuit (LECT3) having an input connected to the second node (200), the sensing circuit being configured to supply the first potential to the second node.

9. The pixel according to claim 8, wherein: The sensing circuit (LECT3) is further configured to convert the current (I) on its input terminal into a voltage (VI) and to provide a binary signal (OUT3) in a first state if the voltage is above a threshold value and to provide the binary signal (OUT3) in a second state if the voltage is below the threshold value, the threshold value being determined, for example, at least in part, by the first potential.

10. The pixel of claim 1, wherein: The pixel comprises a first semiconductor region (508) doped with a first type of conductivity, suitable for detecting radiation in a second wavelength range, such as visible, and extending from a first face (500) intended to receive radiation in the first wavelength range and in the second wavelength range; The photodiode (PD1, PD2) of each channel (CH1, CH2) includes: a second semiconductor region (510) doped with the first type of conductivity, corresponding to a first terminal of the photodiode (PD1, PD2) and extending from a second face (502) parallel to the first face, and - a third semiconductor region (512) doped with the second type of conductivity and sandwiched between the first region (508) and the second region (510); The pixel includes a vertical transfer gate (VEGA) extending from the second face (502) to the first region (508), the transfer gate electrically isolating the photodiodes (PD1, PD2) of the channels (CH1, CH2) from each other and contacting each second region (512).

11. The pixel according to claim 10, wherein: The vertical transfer gate (VEGA) includes a conductive core and an insulating sheath, the conductive core corresponding to a first node (202) of the pixel.

12. The pixel according to claim 10, wherein: The pixel also includes: Additional sensing circuit (LECTSUP) and circuit (SEL), the circuit (SEL) being configured to: selectively coupling and decoupling a first electrode (510, K1, K2) of a photodiode (PD1, PD2) of each channel from the second node (200); and A first electrode (510, K1, K2) of the photodiode (PD1, PD2) of each channel is selectively coupled and decoupled from the additional sensing circuit (LECTSUP).

13. A sensor comprising a plurality of pixels according to claim 1.

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