Flash memory controller based on FPGA

Abstract

The invention relates to the technical field of flash memory controllers, and discloses a flash memory controller based on an FPGA (Field Programmable Gate Array), which comprises a register block module, and a master controller configures the register block module through a control interface module; the command type caching module is used for caching operation command types; the plurality of state machine modules are used for receiving operation command types of the corresponding flash memories from the command type cache module and sending power consumption requests to the power consumption control module; the single-channel state machine module receives an operation command type from the state machine module and obtains a specific storage address of a specific operation command from the register block module; and the waveform control state machine module is used for specifically receiving a specific storage address and an operation command type of the operation command from the single-channel state machine module, and generating an interface signal time sequence and interface signal specific data content in the process of executing the specific operation command on the flash memory. The controller can be conveniently transplanted in the FPGA, the flexibility of the system is improved, and a flash memory storage system can be quickly built.

Description

Technical Field

[0001] The present application relates to the technical field of flash memory controllers, and in particular to a flash memory controller based on FPGA. Background Art

[0002] Nand-flash memory has the advantages of large capacity, fast rewriting speed, and reasonable price. The solid-state drive (SSD) composed of it has been used in many devices and has become the most commonly used high-speed and large-capacity storage unit. The present invention proposes to use a field programmable gate array (FPGA) to implement a Nand-flash controller, which has good portability, improves the flexibility of the system, and can quickly and conveniently build a Nand-flash storage system. Summary of the invention

[0003] The purpose of this application is to provide an FPGA-based flash memory controller that can be easily transplanted in FPGA devices, greatly improving the flexibility of the system and enabling rapid construction of a Nand-flash storage system.

[0004] The present application discloses a flash memory controller based on FPGA, comprising:

[0005] A control interface module, the control interface module is coupled to a main control;

[0006] A register group module, the register group module is coupled to the control interface module, and the master configures the register group module through the control interface module;

[0007] A command type cache module, the command type cache module is coupled to the master control and is used to cache the operation command type of the master control to perform operations on the flash memory;

[0008] A plurality of state machine modules, each of which is coupled to the command type cache module and is respectively used to receive an operation command type corresponding to the flash memory from the command type cache module and send a power consumption request to the power consumption control module, and in response to the power consumption control module having allocated power consumption, the state machine module outputs the operation command type to the single-channel state machine module;

[0009] The power consumption control module is coupled to each state machine module and is used to receive the power consumption request sent by the state machine module and allocate power consumption to the state machine module;

[0010] The single-channel state machine module is connected to the register group module and the multiple state machine modules, and the single-channel state machine module receives the operation command type from the state machine module and obtains the specific storage address of the specific operation command from the register group module;

[0011] A waveform control state machine module, used for receiving a specific storage address of an operation command and a type of the operation command from the single-channel state machine module, and generating an interface signal timing and specific data content of the interface signal in the process of executing the specific operation command on the flash memory;

[0012] An interface module, the interface module is coupled to the waveform control state machine module and is used to perform data interaction with the flash memory;

[0013] A write data cache module, the write data cache module is coupled to the multiple state machine modules and the single-channel state machine module and is used to cache the data that the master is going to write to the flash memory;

[0014] a read data cache module, the read data cache module being coupled to the waveform state machine module and configured to cache data read from the flash memory; and

[0015] A state cache module is coupled to the waveform state machine module and is used to store the state of the flash memory feedback.

[0016] In a preferred example, the command type cache module includes: a high priority command cache unit and a low priority command cache unit, and the read command of the flash memory is cached to the high priority command cache unit; the low priority command cache unit has a self-protection mechanism that is not interrupted by the command in the high priority command cache unit.

[0017] In a preferred example, when the operation command type belongs to a write command, the state machine module jumps to send a data acquisition request to the write data cache module according to the write command, and in response to receiving a reply from the write data cache module, jumps to send a power consumption request to the power consumption control module; the state machine module executes a command to read the NAND status after the write data is completed.

[0018] In a preferred example, when the operation command type belongs to a write command, the single-channel state machine module receives the write command from the state machine module and obtains the specific storage address of the write command from the register group module, sends the write command and address information to the waveform control state machine module, sends write data to the waveform control state machine module, the write data waiting time ends and executes the next operation command; the single-channel state machine module receives and executes a command to read the NAND state from the state machine module.

[0019] In a preferred example, when the operation command type belongs to a write command, the process of the waveform control state machine module executing the write command includes:

[0020] Writing a command to the interface module: acquiring a write command from the command cache RAM inside the waveform control state machine module, and sending the write command, row address, and column address to the interface module;

[0021] Writing data to the interface module: generating waveform information before writing to the flash memory, generating waveform information for writing to the flash memory, and generating waveform information after writing to the flash memory;

[0022] Read NAND status: Generate waveform information before reading flash memory, generate waveform information during reading flash memory, and generate waveform information after reading flash memory.

[0023] In a preferred example, the register group module includes:

[0024] The first register is used to configure the hardware information of the current flash memory;

[0025] The second register is used to configure the status information of the flash memory to be polled using different commands;

[0026] The third register is used to configure the waiting time after the flash memory is reset;

[0027] The fourth and fifth registers are used to configure the waiting time after the read operation of different types of flash memory;

[0028] The sixth register is used to configure the waiting time after the flash multi-plane read operation;

[0029] The seventh register is used to configure the waiting time after the fast read operation of the flash memory part page;

[0030] The eighth register is used to configure the waiting time after the flash cache read operation;

[0031] The ninth register is used to configure the waiting time after writing to the flash memory;

[0032] The tenth register is used to configure the waiting time after the multi-plane write operation to the flash memory;

[0033] The eleventh register is used to configure the waiting time after writing to the flash cache;

[0034] The twelfth register is used to configure the waiting time after the flash memory erase operation;

[0035] The thirteenth register is used to configure the waiting time for the flash memory polling status operation;

[0036] The fourteenth register is used to configure the interval and maximum number of polling times for the flash memory polling status operation;

[0037] The fifteenth register is used to configure the waiting time for the flash write suspend and erase suspend operations;

[0038] The sixteenth register is used to configure automatic initiation of certain command operations on the flash memory;

[0039] The seventeenth register is used to configure the specific address where the flash memory read, write, and erase command information is stored in the RAM;

[0040] The eighteenth register is used to configure the specific address where the flash memory polling status command information is stored in the RAM;

[0041] The nineteenth register is used to store the timing information of the CE / CLE / ALE signals for configuring the flash command operation at a specific address in the RAM;

[0042] The 20th register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data input operation and store it at a specific address in the RAM;

[0043] The twenty-first register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data output operation and store it at a specific address in the RAM.

[0044] In a preferred example, the control interface module includes: a read address interface, a write address interface, a read data interface, a write data interface, a write response interface, a configuration write register group interface, and a configuration read register group interface.

[0045] In the implementation mode of the present application, a controller for Nand-flash memory is implemented by using FPGA to access Nand-flash memory. The controller can be easily transplanted in FPGA devices, greatly improving the flexibility of the system and enabling the rapid construction of Nand-flash storage system.

[0046] The specification of the present application records a large number of technical features, which are distributed in various technical solutions. If all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of the present application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should all be regarded as having been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be regarded as having been recorded because it is technically infeasible, and the solution of A+B+C+E should be regarded as having been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the structure of a flash memory controller based on FPGA in one embodiment of the present application.

[0048] Figure 2 It is a schematic diagram of the operation process of the LUN state machine module according to one embodiment of the present application.

[0049] Figure 3 It is a schematic diagram of the operation process of a single-channel state machine module according to one embodiment of the present application.

[0050] Figure 4 It is a schematic diagram of the operation process of the waveform control state machine module in one embodiment of the present application.

[0051] Figure 5 It is a waveform diagram in an external interface module according to one embodiment of the present application. DETAILED DESCRIPTION

[0052] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0053] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0054] The first embodiment of the present application relates to a flash memory controller based on FPGA, whose structure is as follows Figure 1As shown, the FPGA-based flash memory controller includes a control interface module 101, a register group module 102, a command type cache module 103, multiple LUN state machine modules 104.1-104.N, a power consumption control module 105, a single channel state machine module 106, a waveform control state machine module 107, an external interface module 108, a write data cache module 110, a read data cache module 111 and a state cache module 112. Among them, the external interface module 108 is coupled to the Nand-flash memory 109, and the control interface module 101 is coupled to the main control (not shown in the figure). The register group module 102 is coupled to the control interface module 101, and the main control configures the register group module 102 through the control interface module 101. The command type cache module 103 is coupled to the main control and is used to cache the operation command type of the main control to perform operations on the flash memory.

[0055] In one embodiment, the register file module 102 includes:

[0056] The first register is used to configure the hardware information of the current flash memory, such as the number of LUNs controlled by each CE pin, LUN ID, row / column address bit width, etc.

[0057] The second register is used to configure the status information of the flash memory to be polled using different commands such as 78h or 77h;

[0058] The third register is used to configure the waiting time after the flash memory is reset;

[0059] The fourth and fifth registers are used to configure the waiting time after the read operation of different types of flash memory, such as the waiting time after the read operation of Nand-flash memory of SLC / TLC / MLC / QLC type;

[0060] The sixth register is used to configure the waiting time after the flash multi-plane read operation;

[0061] The seventh register is used to configure the waiting time after the fast read operation of the flash memory part page;

[0062] The eighth register is used to configure the waiting time after the flash cache read operation;

[0063] The ninth register is used to configure the waiting time after writing to the flash memory;

[0064] The tenth register is used to configure the waiting time after the multi-plane write operation to the flash memory;

[0065] The eleventh register is used to configure the waiting time after writing to the flash cache;

[0066] The twelfth register is used to configure the waiting time after the flash memory erase operation;

[0067] The thirteenth register is used to configure the waiting time for the flash memory polling status operation;

[0068] The fourteenth register is used to configure the interval and maximum number of polling times for the flash memory polling status operation;

[0069] The fifteenth register is used to configure the waiting time for the flash write suspend and erase suspend operations;

[0070] The sixteenth register is used to configure automatic initiation of certain command operations on the flash memory;

[0071] The seventeenth register is used to configure the specific address where the flash memory read, write, and erase command information is stored in the RAM;

[0072] The eighteenth register is used to configure the specific address where the flash memory polling status command information is stored in the RAM;

[0073] The nineteenth register is used to store the timing information of the CE / CLE / ALE signals for configuring the flash command operation at a specific address in the RAM;

[0074] The 20th register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data input operation and store it at a specific address in the RAM;

[0075] The twenty-first register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data output operation and store it at a specific address in the RAM.

[0076] In one embodiment, the control interface module includes: a read address interface, a write address interface, a read data interface, a write data interface, a write response interface, a configuration write register group interface, and a configuration read register group interface.

[0077] The plurality of LUN state machine modules 104.1-104.N are each coupled to the command type cache module 103 and are respectively used to receive the operation command type of the corresponding flash memory from the command type cache module 103 and send a power consumption request to the power consumption control module 105. The power consumption control module 105 is coupled to each of the LUN state machine modules 104.1-104.N and is used to receive the power consumption request sent by the state machine module and allocate power consumption to the state machine module. In response to the power consumption control module 105 having allocated power consumption, the plurality of LUN state machine modules 104.1-104.N output the operation command type to the single channel state machine module 106.

[0078] The single channel state machine module 106 is connected to the register group module 102 and the plurality of LUN state machine modules 104 . 1 ˜ 104 .N. In addition, the single channel state machine module 106 receives the operation command type from the LUN state machine modules 104 . 1 ˜ 104 .N and obtains the specific storage address of the specific operation command from the register group module 102 .

[0079] The waveform control state machine module 107 is coupled to the single-channel state machine module 106, and is used to receive the specific storage address and operation command type of the operation command from the single-channel state machine module 106, and generate the interface signal timing and specific data content of the interface signal in the process of executing the specific operation command on the flash memory.

[0080] The external interface module 108 is coupled to the waveform control state machine module 107 and is used to interact with the flash memory. The write data cache module 110 is coupled to the multiple LUN state machine modules 104.1-104.N and the single channel state machine module 106 and is used to cache the data that the master wants to write to the flash memory. The read data cache module 111 is coupled to the waveform state machine module 107 and is used to cache the data read from the flash memory. The state cache module 112 is coupled to the waveform state machine module 107 and is used to store the state of the flash memory feedback.

[0081] The input end of the command type cache module 103 uses a standard AXI4 interface. The output end of the read data cache module 111 uses a user-defined interface. The input end of the write data cache module 110 uses a user-defined interface. The output end of the status cache module 113 uses a standard AXI4 interface.

[0082] Furthermore, the interfaces of the control interface module 101 include: an AXI4 read address interface, an AXI4 write address interface, an AXI4 read data interface, an AXI4 write data interface, an AXI4 write response interface, a configuration write register group interface, and a configuration read register group interface.

[0083] In one embodiment, the command type cache module includes: a high priority command cache unit and a low priority command cache unit, and the read command of the flash memory is cached in the high priority command cache unit. If it is necessary to ensure that N commands in the low priority command cache unit are not interrupted by the commands in the high priority command cache unit, then the command self-protection mechanism in the low priority command cache unit can be enabled. Furthermore, the interface of the command type cache module 102 includes: an AXI4 read address interface, an AXI4 write address interface, an AXI4 read data interface, an AXI4 write data interface, an AXI4 write response interface, a Nand-flash high priority command, a Nand-flash high priority command valid signal, a Nand-flash low priority command, and a Nand-flash low priority command valid signal.

[0084] Furthermore, the interfaces of the LUN state machine modules 104.1 to 104.N include: a custom command output after Nand-flash command conversion, a custom command valid signal after Nand-flash command conversion, a RAM base address for caching Nand-flash command types, and a power consumption control interface.

[0085] Furthermore, the interface of the single channel state machine module 106 includes: a Nand-flash data write request interface, a Nand-flash data write valid signal, a Nand-flash data read valid signal, and a RAM base address for caching Nand-flash command types.

[0086] Furthermore, the interfaces of the waveform control state machine module 107 include: a RAM interface of a write cache Nand-flash command type, a RAM interface of a write cache Nand-flash interface signal timing, a Nand-flash status information return interface, a read Nand-flash data return interface, a write Nand-flash data input interface, and Nand-flash memory interface signal timing information.

[0087] Furthermore, the interface of the external interface module 108 includes: Nand-flash memory chip select signal, address enable signal, command enable signal, data input and output signal, data synchronization reference signal, and read data enable signal.

[0088] In one embodiment, when the operation command type belongs to a write command, the LUN state machine module jumps to send a data acquisition request to the write data cache module according to the write command, and in response to receiving a reply from the write data cache module, jumps to send a power consumption request to the power consumption control module. The LUN state machine module executes a command to read the NAND state after writing the data.

[0089] In one embodiment, when the operation command type belongs to a write command, the single-channel state machine module receives the write command from the LUN state machine module and obtains the specific storage address of the write command from the register group module, and sequentially performs the following operations: sending the write command and address information to the waveform control state machine module, sending the write data to the waveform control state machine module, the write data waiting time ends and the next operation command is executed. In addition, the single-channel state machine module receives and executes a command to read the NAND state from the state machine module.

[0090] In one embodiment, when the operation command type is a write command, the process of the waveform control state machine module executing the write command includes the following:

[0091] Write command to the interface module: Get the write command from the command cache RAM inside the waveform control state machine module, and send the write command, row address (Row), and column address (Column) to the interface module;

[0092] Writing data to the interface module: generating waveform information before writing to the flash memory, generating waveform information when writing to the flash memory, and generating waveform information after writing to the flash memory;

[0093] Read NAND status: Generate waveform information before reading flash memory, generate waveform information during reading flash memory, and generate waveform information after reading flash memory.

[0094] Each module in the FPGA-based Nand-flash controller of the present invention is implemented inside the FPGA. The controller supports ONFI protocol, is compatible with Nand-flash memories of different manufacturers and models, and has broad application prospects.

[0095] In order to better understand the technical solution of the present application, the following is an explanation in conjunction with a specific write Nand-flash operation command. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0096] like Figure 1 As shown, during system initialization, the control interface module initializes the register group in the register group module and initializes the information in the RAM through the standard AXI4 protocol.

[0097] During the operation of the system, different Nand-flash operation command types (such as read type, write type, general type, etc.) are sent to the command type cache module through the standardized AXI4 protocol. The command type cache module contains a high-priority command cache FIFO and a low-priority command cache FIFO. According to the application operation requirements, the command of the high-priority command FIFO can interrupt the command in the low-priority command FIFO to achieve the best effect of application operation. Of course, if the N commands in the low-priority FIFO do not want to be interrupted by the commands in the high-priority command FIFO, the self-protection mechanism of the commands in the low-priority command FIFO can be enabled. That is, when the autom_start field value of the command in the low-priority command cache FIFO is 1, the subsequent commands in the low-priority command cache FIFO will not be interrupted by the commands in the high-priority cache FIFO; until the autom_end field value of the command in the low-priority command cache FIFO is 1, the commands in the high-priority cache FIFO can continue to execute.

[0098] LUN_N state machine module operation process reference Figure 2As shown. The LUN_N state machine module receives the Nand-flash write command type belonging to the current LUN number, and further starts the internal state machine according to the Nand-flash write command type to perform state jump. After the LUN_N state machine is started, it further sends a request to the write data module to obtain data. After waiting for the data response, it jumps to the next state and sends a request to the power consumption control module to request a certain amount of power consumption to execute this LUN_N state machine. If the request is not responded to, it means that the power consumption control module detects that the current system power consumption has reached the power consumption setting upper limit, and the LUN_N state machine will remain in this state, waiting for the response of the power consumption control module. When the power consumption control module responds to the power consumption request issued by the LUN_N state machine, it jumps to the next state, outputs the specific storage address of the write command type to the single-channel state machine module and starts the data write operation. After the data is transmitted to the Nand-flash interface, it jumps to the next state and waits for the data write time. The data write time is obtained by the configuration of the register group. Further, it jumps to the next state and waits for the Nand-flash state to be no longer busy. Further, jump to the next state to release the requested power consumption amount.

[0099] Single-channel state machine module operation process reference Figure 3 As shown, the single-channel state machine module receives the specific storage address information of the write command type, determines that this command belongs to the write Nand-flash operation command, and further starts the internal state machine and jumps between the states of write command (80h), write address (Column address and Row address), send data, and write command (10h).

[0100] Waveform control state machine operation process reference Figure 4 As shown, after receiving the information generated by the single-channel state machine module in different states, the waveform control state machine starts the internal state machine, reads the specific waveform information in the waveform control state machine cache RAM, and sends it to the external interface module.

[0101] The external interface module writes to the Nand-flash memory according to the input waveform information. Figure 5 .

[0102] It should be noted that in the application documents of this patent, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one" do not exclude the existence of other identical elements in the process, method, article or device including the elements. In the application documents of this patent, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, which includes two situations: performing the action only according to the element, and performing the action according to the element and other elements. Expressions such as multiple, multiple, and multiple include 2, 2 times, 2 kinds, and more than 2, more than 2 times, and more than 2 kinds.

[0103] The term "coupled to" and its derivatives may be used herein. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements are in indirect contact with each other, but still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements referred to as being coupled to each other.

[0104] This specification includes combinations of the various embodiments described herein. Individual references to an embodiment (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0105] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0106] In some cases, the actions or steps recorded in this specification may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A flash memory controller based on FPGA, characterized in that: include: A control interface module, the control interface module is coupled to a main control; A register group module, the register group module is coupled to the control interface module, and the master configures the register group module through the control interface module; A command type cache module, the command type cache module is coupled to the master control and is used to cache the operation command type of the master control to perform operations on the flash memory; A plurality of state machine modules, each of which is coupled to the command type cache module and is respectively used to receive an operation command type corresponding to the flash memory from the command type cache module and send a power consumption request to the power consumption control module, and in response to the power consumption control module having allocated power consumption, the state machine module outputs the operation command type to the single-channel state machine module; The power consumption control module is coupled to each state machine module and is used to receive the power consumption request sent by the state machine module and allocate power consumption to the state machine module; The single-channel state machine module is connected to the register group module and the multiple state machine modules, and the single-channel state machine module receives the operation command type from the state machine module and obtains the specific storage address of the specific operation command from the register group module; A waveform control state machine module, used for receiving a specific storage address of an operation command and a type of the operation command from the single-channel state machine module, and generating an interface signal timing and specific data content of the interface signal in the process of executing the specific operation command on the flash memory; An interface module, the interface module is coupled to the waveform control state machine module and is used to perform data interaction with the flash memory; A write data cache module, the write data cache module is coupled to the multiple state machine modules and the single-channel state machine module and is used to cache the data that the master is going to write to the flash memory; a read data cache module, the read data cache module being coupled to the waveform state machine module and used for caching data read from the flash memory; as well as A state cache module is coupled to the waveform state machine module and is used to store the state of the flash memory feedback.

2. The FPGA-based flash memory controller according to claim 1, wherein: The command type cache module includes: a high priority command cache unit and a low priority command cache unit, and the read command of the flash memory is cached in the high priority command cache unit; the low priority command cache unit has a self-protection mechanism that is not interrupted by the command in the high priority command cache unit.

3. The FPGA-based flash memory controller according to claim 1, wherein: When the operation command type belongs to a write command, the state machine module jumps to send a data acquisition request to the write data cache module according to the write command, and in response to receiving a reply from the write data cache module, jumps to send a power consumption request to the power consumption control module; The state machine module executes a command to read the NAND state after writing the data.

4. The FPGA-based flash memory controller according to claim 3, wherein: When the operation command type belongs to a write command, the single-channel state machine module receives the write command from the state machine module and obtains the specific storage address of the write command from the register group module, sends the write command and address information to the waveform control state machine module, sends write data to the waveform control state machine module, the write data waiting time ends and executes the next operation command; the single-channel state machine module receives and executes the command to read the NAND state from the state machine module.

5. The FPGA-based flash memory controller according to claim 4, wherein: When the operation command type belongs to a write command, the process of the waveform control state machine module executing the write command includes: Writing a command to the interface module: acquiring a write command from the command cache RAM inside the waveform control state machine module, and sending the write command, row address, and column address to the interface module; Writing data to the interface module: generating waveform information before writing to the flash memory, generating waveform information for writing to the flash memory, and generating waveform information after writing to the flash memory; Read NAND status: Generate waveform information before reading flash memory, generate waveform information during reading flash memory, and generate waveform information after reading flash memory.

6. The FPGA-based flash memory controller according to claim 1, wherein: The register group module comprises: The first register is used to configure the hardware information of the current flash memory; The second register is used to configure the status information of the flash memory to be polled using different commands; The third register is used to configure the waiting time after the flash memory is reset; The fourth and fifth registers are used to configure the waiting time after the read operation of different types of flash memory; The sixth register is used to configure the waiting time after the flash multi-plane read operation; The seventh register is used to configure the waiting time after the fast read operation of the flash memory part page; The eighth register is used to configure the waiting time after the flash cache read operation; The ninth register is used to configure the waiting time after writing to the flash memory; The tenth register is used to configure the waiting time after the multi-plane write operation to the flash memory; The eleventh register is used to configure the waiting time after writing to the flash cache; The twelfth register is used to configure the waiting time after the flash memory erase operation; The thirteenth register is used to configure the waiting time for the flash memory polling status operation; The fourteenth register is used to configure the interval and maximum number of polling times for the flash memory polling status operation; The fifteenth register is used to configure the waiting time for the flash write suspend and erase suspend operations; The sixteenth register is used to configure automatic initiation of certain command operations on the flash memory; The seventeenth register is used to configure the specific address where the flash memory read, write, and erase command information is stored in the RAM; The eighteenth register is used to configure the specific address where the flash memory polling status command information is stored in the RAM; The nineteenth register is used to store the timing information of the CE / CLE / ALE signals for configuring the flash command operation at a specific address in the RAM; The 20th register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data input operation and store it at a specific address in the RAM; The twenty-first register is used to configure the timing information of the CE / CLE / ALE signals for the flash memory data output operation and store it at a specific address in the RAM.

7. The FPGA-based flash memory controller according to claim 1, wherein: The control interface module includes: a read address interface, a write address interface, a read data interface, a write data interface, a write response interface, a configuration write register group interface and a configuration read register group interface.

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